Gate preparation method of radio frequency GaN HEMT device
By depositing a thick dielectric layer on the second dielectric layer of the radio frequency GaN HEMT device and eliminating step difference using CMP, the photoresist and anti-reflective coating stacking problems caused by step difference in the gate area in the prior art are solved, and strict control of the gate line width and good etching morphology are achieved.
Patent Information
- Application Number
- CN202411630668.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-02-25
AI Technical Summary
In the gate process of existing RF GaN HEMT devices, due to the existence of ohmic metal and dielectric layers, a higher step difference will be formed in the gate area, resulting in photoresist and anti-reflective coating stacking, affecting the gate lithography and etching process, and it is difficult to achieve strict control of the gate line width.
A thick dielectric layer is deposited above the second dielectric layer, and the step difference is eliminated by chemical mechanical polishing (CMP), the gate etching morphology is improved, and the gate line width is achieved.
By eliminating the step difference, the gate etching morphology is improved, and the CD and OVL with high requirements are achieved, which ensures strict control of the gate line width and solves the problem of photoresist and anti-reflective coating accumulation.
Smart Images
Figure CN119521745A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a gate of a radio frequency GaN HEMT device. Background Art
[0002] The various advantages of GaN materials enable GaN-based devices to have good stability when working in extremely harsh environments such as high temperature radiation. GaN materials have a high saturation electron velocity, and GaN-based devices can have both large current output capabilities and high frequency characteristics, allowing GaN-based high electron mobility transistors (HEMTs) to have both high frequency characteristics and high power characteristics.
[0003] In order to give full play to the high-frequency characteristics of RF GaN devices, it is necessary to reduce the influence of gate-source capacitance Cgs, so its gate line width needs to be strictly controlled. Figures 1 to 4 As shown, due to the presence of ohmic metal (OHM) and gate dielectric, a higher step difference will be formed in the gate region, and photoresist (PR) and anti-reflective coating (Barc) will accumulate in the gate region, which is extremely unfavorable to the gate lithography and etching process. Summary of the invention
[0004] In order to solve the problems existing in the above-mentioned prior art, the present invention provides a gate preparation method of a radio frequency GaN HEMT device, which is used to improve the gate etching morphology and achieve strict control of the gate line width.
[0005] The present invention provides a method for preparing a gate of a radio frequency GaN HEMT device, comprising the following steps:
[0006] Step 1, providing a semiconductor structure, wherein the semiconductor structure includes, from bottom to top, a substrate, a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a first dielectric layer, a source-drain electrode, and a second dielectric layer;
[0007] Step 2: depositing a thick dielectric layer on the second dielectric layer, and performing a planarization process on the thick dielectric layer;
[0008] Step 3: forming an anti-reflective coating and a photoresist layer on the surface of the thick dielectric layer, and patterning the photoresist layer to form a gate opening region;
[0009] Step 4: etching the thick dielectric layer, the second dielectric layer and the first dielectric layer in sequence to form a gate groove;
[0010] Step 5: removing the thick dielectric layer;
[0011] Step six: depositing gate metal in the gate groove, and then forming a gate electrode through a lift-off process.
[0012] Preferably, the substrate in step one is a silicon substrate.
[0013] Preferably, the buffer layer in step one is a GaN buffer layer.
[0014] Preferably, in step one, the source-drain electrodes are formed by etching the first dielectric layer and then filling the source-drain electrodes with metal.
[0015] Preferably, the source-drain electrode metal is a Ti / Al / Ti / TiN stack.
[0016] Preferably, in step one, the second dielectric layer is deposited on the first dielectric layer and the source-drain electrode.
[0017] Preferably, the planarization treatment in step 2 is a chemical mechanical polishing process.
[0018] Preferably, the method for removing the thick dielectric in step 5 is wet etching.
[0019] Preferably, the gate metal in step six is one or a combination of Ni, Pt, Al, Au, and Ti.
[0020] After the second dielectric layer is formed, the present invention grows another thick dielectric layer on the surface thereof, then eliminates the step difference by CMP, then performs gate photolithography and etching, and finally removes the thick dielectric layer on the surface, thereby solving the problem that after the source / drain is completed and the gate dielectric layer is grown, a large step difference is left in the middle, which is not conducive to the photoresist and the anti-reflective coating to evenly cover the surface, effectively improving the gate etching morphology, being able to achieve higher requirements for CD and OVL, and realizing strict control of the gate line width. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0022] Figure 1-Figure 4 A schematic diagram showing a process of making a gate of a prior art RF GaN device;
[0023] Figure 5 A flow chart showing a method for preparing a gate of a radio frequency GaN HEMT device according to an embodiment of the present invention;
[0024] Figure 6-Figure 10 Shown are structural schematic diagrams of various steps in a method for preparing a gate of a radio frequency GaN HEMT device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.
[0026] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0027] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".
[0028] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0029] At present, the gate process manufacturing method of the RF GaN device includes: providing a GaN HEMT substrate structure, which includes a substrate, a buffer layer, a GaN channel layer, an AlGaN barrier layer, a first dielectric layer, a source-drain electrode, and a second dielectric layer covering it; depositing an anti-reflection coating (Barc) and a photoresist (PR); exposing and developing the photoresist to obtain a photolithography pattern; and etching the second dielectric layer and the first dielectric layer in sequence to form a gate groove. Among them, due to the presence of the ohmic metal and the dielectric layer, a higher step difference will be formed in the gate area, and the photoresist and the anti-reflection coating (Barc) will accumulate in the gate area, resulting in an uneven surface, resulting in a deviation in the photolithography alignment, resulting in abnormal exposure morphology, resulting in abnormal etching morphology, and being unfavorable for gate metal filling and electrical parameters. Therefore, the present invention proposes a new gate process method. The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.
[0030] Figure 5 A flow chart showing a method for preparing a gate of a radio frequency GaN HEMT device according to an embodiment of the present invention; Figure 6-Figure 10 The schematic diagram of the structure of each step of the gate preparation method of the RF GaN HEMT device according to the embodiment of the present invention is shown. Figure 5 As shown, the gate preparation method of the RF GaN HEMT device of the embodiment of the present invention includes the following steps:
[0031] Step 1: Figure 6As shown, a semiconductor structure is provided, which includes, from bottom to top, a substrate, a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a first dielectric layer, a source-drain electrode, and a second dielectric layer.
[0032] The material of the substrate can be Si, SiC, SiGe, GeAs, InAs, InP or other III-V or II-VI compound semiconductors. In the embodiment of the present invention, the substrate is a silicon substrate, and the buffer layer is a GaN buffer layer. Figure 6 As shown, the substrate, buffer layer, GaN channel layer, AlN insertion layer, AlGaN barrier layer, first dielectric layer (ILD-1), source / drain electrodes (S / D) and second dielectric layer (ILD-2) are sequentially stacked, and a two-dimensional electron gas channel (2DEG) is formed between the GaN channel layer and the AlGaN barrier layer (not shown in the figure).
[0033] The source / drain electrode (S / D) is formed by etching the first dielectric layer and then filling the source / drain electrode metal. The source / drain electrode metal is a Ti / Al / Ti / TiN stack. The metal layers Ti / Al / Ti / TIN are deposited in sequence by magnetron sputtering. Of course, other suitable methods may also be used.
[0034] A first dielectric layer (ILD-1) is deposited on the AlGaN barrier layer by a chemical vapor deposition process (e.g., a low pressure chemical vapor deposition process (LPCVD) or a plasma assisted chemical vapor deposition process (PECVD)), and a second dielectric layer (ILD-2) is deposited on the first dielectric layer (ILD-1) and the source / drain electrodes (S / D). Of course, other suitable methods may also be used.
[0035] In addition, the 2DEG must be shut off and isolated between each HEMT through isolation technology to prevent signal interference between devices. In order to achieve isolation between HEMT devices, the existing technology mainly uses two methods: plasma etching (RIE) or ion beam implantation. In an optional method, the isolation area is isolated by local ion implantation, and the implanted element is Ar, and of course it can also be F, N or B.
[0036] Step 2: Figure 7 As shown, a thick dielectric layer is deposited on the second dielectric layer, and the thick dielectric layer is planarized.
[0037] A thick dielectric layer (ILD-3) is deposited on the second dielectric layer (ILD-2) by sputtering or atomic layer deposition. Of course, other suitable methods may also be used. In the embodiment of the present invention, the thick dielectric layer (ILD-3) covers the semiconductor structure in step one, and the thick dielectric layer is planarized by chemical mechanical polishing. In the embodiment of the present invention, a thick dielectric layer (ILD-3) is grown on the surface again, and then the step difference is eliminated by CMP, which is beneficial to the subsequent etching of the gate.
[0038] Step 3: Figure 8 As shown, an anti-reflection coating and a photoresist layer are formed on the surface of the thick dielectric layer, and the photoresist layer is patterned to form a gate opening region.
[0039] In the embodiment of the present invention, the gate etching pattern region is defined on the dielectric layer using the photolithography technology, including processes such as photoresist coating, exposure, and development, which will not be described in detail here.
[0040] Step 4: Fig. 9 As shown, the thick dielectric layer, the second dielectric layer and the first dielectric layer are sequentially etched to form a gate groove.
[0041] In the embodiment of the present invention, etching can be performed by dry etching or wet etching. Exemplarily, the dry etching process includes but is not limited to reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation or any combination of these methods.
[0042] Step 5: Fig.10 As shown, the thick dielectric layer is removed.
[0043] In the embodiment of the present invention, a wet etching process is used to remove the thick dielectric layer (ILD-3).
[0044] contrast Figure 4 and Fig.10 Obviously, the method of the embodiment of the present invention has a good effect and effectively solves the problem that after the source / drain is completed and the gate dielectric layer is grown, a large step difference will be left in the middle, which is not conducive to the smooth coverage of the surface by the photoresist and the anti-reflective coating. The gate etching morphology is good.
[0045] Step 6: Deposit gate metal in the gate trench, and then form a gate electrode through a lift-off process.
[0046] In the embodiment of the present invention, the gate metal is one or more of Ni, Pt, Al, Au, and Ti. The gate metal is deposited by magnetron sputtering. Of course, other suitable methods may also be used. The stripping process refers to stripping the deposited gate metal except for the gate pattern area.
[0047] In summary, after the second dielectric layer is formed, the embodiment of the present invention grows another thick dielectric layer on its surface, then eliminates the step difference through CMP, then performs gate photolithography and etching, and finally removes the thick dielectric layer on the surface, which effectively improves the gate etching morphology, can achieve higher requirements for CD and OVL, and achieves strict control of the gate line width. The problem that after the source / drain is completed and the gate dielectric layer is grown, a large step difference will be left in the middle, which is not conducive to the photoresist and anti-reflective coating to smoothly cover the surface is solved.
[0048] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for preparing a gate of a radio frequency GaN HEMT device, characterized in that: The following steps are involved: Step 1, providing a semiconductor structure, wherein the semiconductor structure includes, from bottom to top, a substrate, a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a first dielectric layer, a source-drain electrode, and a second dielectric layer; Step 2: depositing a thick dielectric layer on the second dielectric layer, and performing a planarization process on the thick dielectric layer; Step 3: forming an anti-reflective coating and a photoresist layer on the surface of the thick dielectric layer, and patterning the photoresist layer to form a gate opening region; Step 4: etching the thick dielectric layer, the second dielectric layer and the first dielectric layer in sequence to form a gate groove; Step 5: removing the thick dielectric layer; Step six: depositing gate metal in the gate groove, and then forming a gate electrode through a lift-off process.
2. The method for preparing a gate of a RF GaN HEMT device according to claim 1, characterized in that: The substrate in step 1 is a silicon substrate.
3. The method for preparing a gate of a RF GaN HEMT device according to claim 1, characterized in that: The buffer layer in step 1 is a GaN buffer layer.
4. The method for preparing a gate of a RF GaN HEMT device according to claim 1, characterized in that: In step one, the source-drain electrodes are formed by etching the first dielectric layer and then filling the source-drain electrodes with metal.
5. The method for preparing a gate of a radio frequency GaN HEMT device according to claim 4, characterized in that: The source-drain electrode metal is a Ti / Al / Ti / TiN stack.
6. The method for preparing a gate of a radio frequency GaN HEMT device according to claim 1, characterized in that: In step one, the second dielectric layer is deposited on the first dielectric layer and the source-drain electrode.
7. The method for preparing a gate of a radio frequency GaN HEMT device according to claim 1, characterized in that: The planarization process in step 2 is a chemical mechanical polishing process.
8. The method for preparing a gate of a radio frequency GaN HEMT device according to claim 1, characterized in that: The method for removing the thick dielectric in step 5 is wet etching.
9. The method for preparing a gate of a radio frequency GaN HEMT device according to claim 1, characterized in that: The gate metal in step six is one or a combination of Ni, Pt, Al, Au, and Ti.