Semiconductor device and method of forming the same

Abstract

A semiconductor device and a forming method thereof, the method comprising: providing a plurality of groups of to-be-processed wafers, the to-be-processed wafers comprising a substrate and a device structure formed on the substrate, wherein gaps are formed between the device structures; sequentially processing the to-be-processed wafers based on an order of parameter groups in a preset parameter set to form a deposition layer on the to-be-processed wafers, the deposition layer completely covering the gaps; the parameter set comprises a plurality of parameter groups, one parameter group corresponding to one group of to-be-processed wafers, and different parameter groups corresponding to different states of a deposition device; and forming a sacrificial layer on the deposition layer. The scheme can improve the yield of the semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and particularly relate to a semiconductor device and a forming method thereof. BACKGROUND

[0002] In the forming process of a semiconductor device, it is required to form uneven device structures on a substrate, so that there are gaps with different sizes between the device structures on the surface of the substrate. At this time, a deposition process is usually used to fill in the gaps and further completely cover the device structures, so as to protect and isolate the device structures.

[0003] However, the yield of the semiconductor device needs to be improved in the existing process. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device and a forming method thereof, so as to improve the yield of the semiconductor device.

[0005] To solve the above problems, embodiments of the present application provide a forming method of a semiconductor device, comprising:

[0006] A plurality of groups of to-be-processed wafers are provided, the to-be-processed wafers comprising a substrate and device structures formed on the substrate, wherein gaps are formed between the device structures;

[0007] Based on the order of a parameter group in a preset parameter set, the to-be-processed wafers are processed in sequence to form a deposition layer completely covering the gaps on the to-be-processed wafers; the parameter set comprises a plurality of parameter groups, one parameter group corresponding to one group of to-be-processed wafers, and different parameter groups corresponding to different states of a deposition device;

[0008] A sacrificial layer is formed on the deposition layer.

[0009] Optionally, the parameter groups in the parameter set are executed in cycles, and the device cleaning process is executed once every cycle of the parameter groups.

[0010] Optionally, in the step of forming the deposition layer completely covering the gaps on the to-be-processed wafers, a deposition process is used to form the deposition layer; wherein the parameter group at least comprises a reaction gas flow.

[0011] In the parameter set, the reaction gas flow gradually increases in sequence with the order of the parameter groups.

[0012] Optionally, in the step of forming the deposition layer completely covering the gaps on the to-be-processed wafers, a deposition process is used to form the deposition layer; wherein the parameter group at least comprises a bias power.

[0013] In the parameter set, the bias power is sequentially increased with the order of the parameter group.

[0014] Optionally, in the step of forming the deposition layer completely covering the gap on the wafer to be processed, the deposition process is used to form the deposition layer; wherein the parameter group at least includes deposition time.

[0015] In the parameter set, the deposition time is sequentially increased with the order of the parameter group.

[0016] Optionally, the number of parameter groups in the parameter set is 4-20.

[0017] Optionally, in the deposition process, the reaction gas is SIH4, in the parameter group, the side flow of the reaction gas is 6-15 Sccm, the top flow of the reaction gas is 6-15 Sccm, the bias power is 1200-2000 W, and the deposition time is 110-200 S.

[0018] Optionally, after the step of forming the deposition layer completely covering the gap on the wafer to be processed, and before the step of forming the sacrificial layer on the deposition layer, the method further comprises:

[0019] forming a supplementary deposition layer on the deposition layer;

[0020] The step of forming the sacrificial layer on the deposition layer specifically comprises forming the sacrificial layer on the supplementary deposition layer.

[0021] Optionally, the device structure comprises a gate structure protruding from a substrate, and source-drain structures located on both sides of the gate structure, wherein the source-drain structures are located in the substrate, and between adjacent device structures, an isolation structure is further included for isolating the device structures.

[0022] The embodiment of the present application further provides a semiconductor device formed by the forming method of the semiconductor device.

[0023] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0024] The embodiment of the present application provides a semiconductor device and a forming method thereof, and the forming method comprises the following steps: providing a plurality of groups of to-be-processed wafers, the to-be-processed wafers comprising a substrate and a device structure formed on the substrate, wherein a gap is formed between the device structures; sequentially processing the to-be-processed wafers based on the sequence of a parameter group in a preset parameter set, so as to form a deposition layer on the to-be-processed wafers, the deposition layer completely covering the gap; the parameter set comprises a plurality of parameter groups, one parameter group corresponds to one group of to-be-processed wafers, and different parameter groups correspond to different states of a deposition device; and a sacrifice layer is formed on the deposition layer.

[0025] It can be seen that, in the method provided by the embodiment of the present application, a plurality of parameter groups are arranged in the parameter set, and different parameter groups correspond to different states of the deposition device, and meanwhile, one parameter group corresponds to one group of to-be-processed wafers, so that the adjustment of the parameter can be realized once after processing one group of to-be-processed wafers, so as to adapt to the state change of the deposition device, thereby ensuring the surface quality of the deposition layer of each to-be-processed wafer and improving the yield of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the provided drawings.

[0027] Figures 1 to 3 It is a structure schematic diagram corresponding to each step in a forming method of a semiconductor device.

[0028] Figures 4 to 7 It is a structure schematic diagram corresponding to each step in a forming method of a semiconductor device in an embodiment of the present application.

[0029] Figure 8 It is a structure schematic diagram corresponding to each step in a forming method of a semiconductor device in another embodiment of the present application. DETAILED DESCRIPTION

[0030] As described in the background, the yield of the semiconductor device formed by the prior art needs to be improved.

[0031] Next, in combination with an existing forming method of a semiconductor device, the reason for this problem will be analyzed.

[0032] Reference Figures 1 to 3 , Figures 1 to 3 It is a structure schematic diagram corresponding to each step in a forming method of a semiconductor device.

[0033] Reference Figure 1A plurality of wafers to be processed are provided, the wafers to be processed including substrates 1 and device structures 2 (shown by the dashed line box) formed on the substrates, wherein gaps (the area indicated by the arrow L) are formed between the device structures.

[0034] Referring to Figure 2 A deposition layer 3 completely covering the gaps is formed on the wafers to be processed.

[0035] Referring to Figure 3 A sacrificial layer 4 is formed on the deposition layer.

[0036] However, the inventors found that the yield of the semiconductor devices is not high in the above process flow. Through further observation and analysis, it is considered that the quality of the surface morphology of the deposition layer 3 in the semiconductor devices presents a certain regularity, i.e. the quality of the surface morphology of the deposition layer will decrease to a certain extent every certain number of wafers, thereby affecting the yield of the semiconductor devices. After analysis, the inventors consider that this is because, during the deposition process, the equipment cleaning process is performed once every preset number of wafers, so that the equipment is in a relatively ideal state, and the deposition layer formed thereafter exhibits good surface morphology quality. However, after processing a certain number of wafers, the state of the equipment changes, thereby causing the quality of the surface morphology of the deposition layer of the remaining wafers to decrease, which affects the yield of the semiconductor devices.

[0037] For example, in the production process of a wafer with a line width (i.e. the width of the gate) greater than 40 nm, the wafers with low yield exhibit poor surface morphology of the outer ring area of the deposition layer. After a batch of 25 wafers are continuously processed, the wafers with low yield exhibit the following regularity: the wafers exhibiting the above problem are essentially the 2nd and 3rd wafers every 3 wafers, wherein the yield of the 2nd wafer decreases by about 6%, and the yield of the 3rd wafer decreases by about 15%. Meanwhile, SEM (Scanning Electron Microscope) analysis shows that the outer ring area of the deposition layer exhibits a bridging problem between the device structures due to the failure of the deposition layer to completely cover the device structures.

[0038] However, in the wafer processing flow, the time consumed for performing the equipment cleaning process once is too much, which makes the scheme of performing the equipment cleaning process too frequently to ensure the quality of the wafers impractical.

[0039] Therefore, the embodiment of the present application provides a semiconductor device and a forming method thereof.

[0040] It can be seen that, in the method provided by the embodiment of the present application, a plurality of parameter groups are arranged in a parameter set, and different parameter groups correspond to different states of a deposition device, and one parameter group corresponds to one group of to-be-processed wafers, so that the adjustment of parameters can be realized once after processing one group of to-be-processed wafers to adapt to the state change of the deposition device, thereby ensuring the surface quality of the deposition layer of each to-be-processed wafer and improving the yield of the semiconductor device.

[0041] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0042] Figures 4 to 7 The structure diagram corresponding to each step in the embodiment of the forming method of the semiconductor device.

[0043] Reference Figure 4 A plurality of groups of to-be-processed wafers are provided, the to-be-processed wafers include a substrate 100 and a device structure 200 (shown in a dashed box) formed on the substrate, and a gap (shown by an arrow L in the figure) is formed between the device structures.

[0044] The to-be-processed wafers can be understood as wafers in a semi-finished product, which are used to provide a process basis for the formation of semiconductor devices, and the corresponding device structures can be formed thereon, and the gap L between the device structures is to be covered by subsequent processes.

[0045] In the embodiment, the substrate 100 can be silicon. In other embodiments, the material of the substrate 100 can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and other semiconductor materials, and the substrate 100 can also be a silicon substrate on an insulator or a germanium substrate on an insulator, and other types of substrates.

[0046] The substrate 100 can be formed with a device structure 200, which can be a device structure of an active device, such as a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, an inductor, or the like. It can be understood that, on a wafer to be processed, the number of device structures is usually multiple, and to ensure electrical isolation and interference between the device structures, the device structures are usually spatially isolated, so that gaps are formed between the device structures for spatial isolation of the device structures.

[0047] In a specific example, the device structure is a MOS device structure, wherein the device structure 200 can include a gate structure 201 protruding from the substrate, and source / drain structures 202 located on both sides of the gate structure 201, wherein the source / drain structures 202 can be located in the substrate, and between adjacent device structures, isolation structures 300 for isolating device structures are further included in the substrate.

[0048] The size of the gap between different device structures on the wafer is different based on the layout design of the wafer. When some device structures are close to each other, the corresponding gap size is small, and when some device structures are far away from each other, the corresponding gap size is large. It can be understood that the larger the gap, the more difficult the filling, and the higher the requirement for the deposition process.

[0049] In the embodiment of the present application, the yield problem of semiconductor devices is solved by providing multiple groups of wafers to be processed to ensure the yield of multiple groups of wafers to be processed at the same time. One group of wafers to be processed is a wafer to be processed processed by a deposition device at a time, and the number of wafers to be processed in one group of wafers to be processed can be one or more, such as 2, 3, or 4, etc.

[0050] Reference Figure 5 Based on the order of the parameter groups in the preset parameter set, the wafers to be processed are processed in sequence to form a deposition layer 400 on the wafers to be processed, which completely covers the gaps.

[0051] The parameter set includes multiple parameter groups, one parameter group corresponds to one group of wafers to be processed, and different parameter groups correspond to different states of the deposition device.

[0052] By setting multiple parameter groups in the parameter set and making different parameter groups correspond to different states of the deposition device, the adjustment of the parameters can be realized once a group of wafers to be processed is processed, so as to adapt to the state change of the deposition device and ensure the surface quality of the subsequent group of wafers to be processed.

[0053] The order of the parameter groups in the parameter set is preset, corresponding to different states of the deposition device, thus, in the embodiment of the present application, the to-be-processed wafers need to be processed in sequence based on the order of the parameter groups in the preset parameter set. Moreover, the parameter set can be preconfigured in the deposition device, so that the deposition device directly implements continuous and uninterrupted processing of the to-be-processed wafers based on the parameter set.

[0054] The parameter set corresponds to the process of the deposition device from after performing a cleaning process to before the next cleaning process, and the parameter groups in the parameter set are executed in cycles, and the device cleaning process is performed once per cycle of the parameter groups.

[0055] The deposition layer can be silicon oxide, and in some optional examples, the deposition layer can also be silicon nitride, silicon oxynitride, etc.

[0056] In an optional example, the formation process of the deposition layer can adopt a deposition process, for example, HDP (high-density plasma chemical vapor deposition). HDP deposition process has good filling capacity, better film deposition characteristics and higher yield, so as to quickly and efficiently form the deposition layer covering the gap.

[0057] In an optional example, the parameter group corresponding to the deposition process at least includes a reaction gas flow, and in the parameter set, the reaction gas flow is sequentially increased in the order of the parameter groups. This is because, corresponding to a plurality of to-be-processed wafers, the probability of the occurrence of the deposition recess is greater and greater as the processing flow goes on. By adjusting the reaction gas flow to be greater and greater, the reaction gas in the deposition device is more and more, and the corresponding deposition reaction is also more and more, so as to reduce the probability of the occurrence of the deposition recess in the to-be-processed wafers in the subsequent process. In a specific example, the reaction gas can be SIH4, and the reaction gas flow can include a top flow (SIH4 TOP) and a side flow (SIH4 side). The side flow of the reaction gas can be 6-15 Sccm, and the top flow of the reaction gas can be 6-15 Sccm. The specific parameters of the reaction gas flow can be selected in the range while ensuring the corresponding change trend.

[0058] In a specific optional example, in the parameter set, the side flow of the reaction gas of each parameter group can be 6 Sccm, 8 Sccm, 10 Sccm, 12 Sccm and 14 Sccm in sequence, and the top flow of the reaction gas of each parameter group can be 6 Sccm, 8 Sccm, 10 Sccm, 12 Sccm and 14 Sccm in sequence. In a specific optional example, in the parameter set, the side flow of the reaction gas of each parameter group can be 6 Sccm, 8 Sccm, 10 Sccm, 12 Sccm and 14 Sccm in sequence, and the top flow of the reaction gas of each parameter group can be 6 Sccm, 8 Sccm, 10 Sccm, 12 Sccm and 14 Sccm in sequence.

[0059] In a further optional example, the parameter set corresponding to the deposition process at least includes a bias power, and in the parameter set, the bias power is sequentially increased along with the order of the parameter set. This is because, corresponding to a plurality of groups of to-be-processed wafers, the probability of the occurrence of the corresponding deposition recess is greater and greater as the process flow goes further, and by adjusting the bias power to be greater and greater, the deposition reaction in the deposition device is also more and more sufficient, thereby reducing the probability of the occurrence of the deposition recess of the to-be-processed wafer processed in the subsequent process. In a specific example, the bias power can be 1200-2000 W, and the specific parameters of the corresponding bias power can be selected within the range while ensuring the corresponding change trend.

[0060] In a specific optional example, in the parameter set, the bias power of each parameter set can be 1200 W, 1400 W, 1600 W, 1800 W and 2000 W in turn.

[0061] In a further optional example, the parameter set corresponding to the deposition process at least includes a deposition time, and in the parameter set, the deposition time is sequentially increased along with the order of the parameter set. This is because, corresponding to a plurality of groups of to-be-processed wafers, the probability of the occurrence of the corresponding deposition recess is greater and greater as the process flow goes further, and by adjusting the deposition time to be greater and greater, the deposition reaction in the deposition device is also more and more sufficient, thereby reducing the probability of the occurrence of the deposition recess of the to-be-processed wafer processed in the subsequent process. In a specific example, the deposition time can be 110-200 S, and the specific parameters of the corresponding deposition time can be selected within the range while ensuring the corresponding change trend.

[0062] In a specific optional example, in the parameter set, the deposition time of each parameter set can be 110 S, 130 S, 150 S, 170 S and 190 S in turn.

[0063] It can be understood that, based on the embodiments of the present application, the parameters can be adjusted based on the state of the equipment, thereby maximizing the processing quality of the to-be-processed wafers, and the number of times of processing the to-be-processed wafers between the adjacent equipment cleaning processes in the embodiments of the present application can also be increased, and accordingly, the number of parameter sets in the parameter set can also be increased. In a specific example, the number of parameter sets in the parameter set can be 4-20, for example, can be 4, 8, 12 or 16, which is not limited in the present application.

[0064] In a specific example, the reaction gas can further include O2 and PH3.

[0065] The flow rate of O2 can be 40-80 Sccm, and in the parameter set, the flow rate of O2 of each parameter group can be 40 Sccm, 50 Sccm, 60 Sccm, 70 Sccm and 80 Sccm in sequence, which is not limited in the present application.

[0066] The top flow rate of PH3 can be 1.5-3 Sccm, and the side flow rate can be 1.5-3 Sccm. The corresponding parameter setting can be selected in the above manner, which is not limited in the present application.

[0067] Reference Figure 6 A sacrificial layer 500 is formed on the deposition layer.

[0068] The sacrificial layer is used to further protect and isolate the device structure, wherein the sacrificial layer has a flat surface. The sacrificial layer can be formed by a deposition process, and specifically, the deposition process can be PETEOS (plasma enhanced tetraethyl orthosilicate layer deposition), and correspondingly, the material of the sacrificial layer can be one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0069] Specifically, to form a flat surface of the sacrificial layer, the process of forming the sacrificial layer can include:

[0070] A sacrificial material layer is formed on the deposition layer, and the thickness of the sacrificial material layer is greater than the thickness of the sacrificial layer; the sacrificial material layer with the excess thickness is ground to form the sacrificial layer.

[0071] The sacrificial material layer provides a process basis for forming the sacrificial layer. Correspondingly, the material of the sacrificial material layer is the same as that of the sacrificial layer.

[0072] It can be understood that based on the surface of the wafer to be processed having a device structure, the corresponding surface topography is uneven, and the deposition layer formed based thereon is generally not completely flat, and the sacrificial material layer formed thereon is also not completely flat.

[0073] Therefore, in the embodiment of the present application, the thickness of the sacrificial material layer formed first is greater than the thickness of the sacrificial layer formed subsequently, so that part of the thickness of the sacrificial material layer can be removed based on the grinding process to form the sacrificial layer with a flat surface.

[0074] The excess thickness refers to the difference between the preset thickness of the sacrificial layer and the thickness of the formed sacrificial material layer. Based on the characteristics of the grinding process, a flat surface can be formed, and the embodiment of the present application can utilize the grinding process to form the sacrificial layer with a flat surface.

[0075] It can be seen that in the method provided by the embodiment of the present application, a plurality of parameter groups are set in the parameter set, and different parameter groups correspond to different states of the deposition equipment, and at the same time, one parameter group corresponds to one group of wafers to be processed, so that the adjustment of parameters can be realized once after processing one group of wafers to be processed, to adapt to the state change of the deposition equipment, thereby ensuring the surface quality of the deposition layer of each wafer to be processed, and improving the yield of the semiconductor device.

[0076] It should be noted that the embodiment of the present application can achieve good filling even for gaps with a size greater than 40 nm.

[0077] It can be understood that in the HDP deposition process, the long film rate is relatively slow, about 1800-4000 A / min, and accordingly, the wafer processing speed is relatively slow, and the WPH (wafer per hour) is relatively small. In the process of producing a film thickness of about 5000 A, the WPH is usually less than 3, and the embodiment of the present application can increase the WPH and improve the wafer processing speed.

[0078] In a further embodiment of the present application, a supplementary deposition layer is further formed on the deposition layer to further protect and isolate the device structure and improve the yield of the device structure. Specifically, in the embodiment of the present application, after the step of forming the deposition layer that completely covers the gap on the wafer to be processed, further comprising:

[0079] Reference Figure 7 a supplementary deposition layer 600 is formed on the deposition layer;

[0080] The supplementary deposition layer may, for example, be silicon oxide, and by further forming the supplementary deposition layer, defects such as recesses that may occur in the deposition layer formation process can be corrected. The material of the supplementary deposition layer may, for example, be one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0081] Specifically, the supplementary deposition layer may, for example, be formed by a deposition process, such as HARP TEOS (high aspect ratio polyethylene oxide layer deposition). HARP TEOS has excellent filling capacity and also has extensibility, so that whether the gap is large or small, good and sufficient filling can be achieved.

[0082] Correspondingly, in the example of forming the supplementary deposition layer, the step of forming a sacrificial layer on the deposition layer, specifically, with reference to Figure 8 a sacrificial layer 500 is formed on the supplementary deposition layer 600.

[0083] In another embodiment of the present application, a semiconductor device is also provided, which is formed based on the forming method of the semiconductor device provided in the foregoing embodiment, wherein referring to Figure 8 , the semiconductor device comprises:

[0084] a substrate 100, and a device structure formed on the substrate, wherein a gap (indicated by arrow L in the figure) is formed between the device structures.

[0085] In the embodiment, the substrate 100 can be silicon. In other embodiments, the material of the substrate 100 can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other semiconductor materials, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0086] The device structure formed on the substrate 100 can be a device structure of an active device, such as a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, or an inductor, etc. It can be understood that the number of device structures is usually multiple, and in order to ensure the electrical isolation and interference between the device structures, the device structures are usually spatially isolated, so that a gap is formed between the device structures for spatial isolation of the device structures.

[0087] In a specific example, the device structure is a MOS device structure, wherein the device structure can include a gate structure 201 protruding from the substrate, and source / drain structures 202 located on both sides of the gate structure 201, wherein the source / drain structures 202 can be located in the substrate, and between adjacent device structures, an isolation structure 300 for isolating the device structures is also included.

[0088] The size of the gap between different device structures is different based on the layout design of the wafer, and when some device structures are closer, the corresponding gap size is smaller, and when some device structures are farther apart, the corresponding gap size is larger. It can be understood that the larger the gap, the more difficult the corresponding filling, and the higher the requirement for the deposition process.

[0089] The semiconductor device further comprises a deposition layer 400 completely covering the gap, which can be silicon oxide, and in some optional examples, the deposition layer can also be silicon nitride, silicon oxynitride, etc.

[0090] The deposition layer 400 can further include a sacrificial layer 500, and the material of the sacrificial layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0091] In some optional examples, the deposition layer can further include a supplemental deposition layer 600. The material of the supplemental deposition layer can be one or more of silicon oxide, silicon nitride, silicon oxynitride, etc. Specifically, the supplemental deposition layer is located between the deposition layer and the sacrificial layer.

[0092] It should be noted that each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiment.

[0093] Although the embodiments of the present application are disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a semiconductor device, characterized by, The application relates to a method for forming a semiconductor device. The method comprises the following steps: providing a plurality of groups of to-be-processed wafers, the to-be-processed wafers comprising substrates and device structures formed on the substrates, wherein gaps are formed between the device structures; processing the to-be-processed wafers in sequence based on the sequence of parameter groups in a preset parameter set, so as to form a deposition layer on the to-be-processed wafers, the deposition layer completely covering the gaps; the parameter set comprises a plurality of parameter groups, one parameter group corresponding to one group of to-be-processed wafers, and different parameter groups corresponding to different states of a deposition device; forming a sacrificial layer on the deposition layer; wherein the parameter groups in the parameter set are executed in cycles, and in the step of forming the deposition layer on the to-be-processed wafers, the deposition layer is formed by using a deposition process, and one or more of the following conditions are met: the parameter group at least comprises a reaction gas flow, in the parameter set, the reaction gas flow is sequentially increased along the sequence of the parameter groups; the parameter group at least comprises a bias power, in the parameter set, the bias power is sequentially increased along the sequence of the parameter groups; 2. The method for forming a semiconductor device according to Claim 1, wherein the parameter group at least comprises a deposition time, in the parameter set, the deposition time is sequentially increased along the sequence of the parameter groups.

3. The method of forming a semiconductor device according to Claim 2, wherein The parameter group is executed in cycles, and a device cleaning process is executed once per cycle.

4. The method for forming a semiconductor device according to Claim 1, wherein The number of parameter groups in the parameter set is 4-20.

5. The method for forming a semiconductor device according to Claim 1, wherein In the deposition process, the reaction gas is SIH4, in the parameter group, the side flow of the reaction gas is 6-15 Sccm, the top flow of the reaction gas is 6-15 Sccm, the bias power is 1200-2000 W, and the deposition time is 110-200 S. After the step of forming the deposition layer on the to-be-processed wafers, before the step of forming the sacrificial layer on the deposition layer, the method further comprises the following steps: forming a supplementary deposition layer on the deposition layer; 6. The method for forming a semiconductor device according to Claim 1, wherein the step of forming the sacrificial layer on the deposition layer is specifically forming the sacrificial layer on the supplementary deposition layer.

7. A semiconductor device, characterized by comprising: The device structure comprises a gate structure protruding from the substrate, source-drain structures located on both sides of the gate structure, wherein the source-drain structures are located in the substrate, and between adjacent device structures, an isolation structure is further arranged for isolating the device structures. The method is used for forming the semiconductor device.

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