Manufacturing method of field effect transistor and field effect transistor
By forming a dummy gate structure in the semiconductor substrate of the field effect transistor and removing the dummy gate structure to form a light doped region and gate structure, the problem of heat treatment during LDD ion implantation is solved, and the device performance is improved.
Patent Information
- Application Number
- CN202411524364.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-25
AI Technical Summary
Existing field effect transistors are susceptible to heat treatment by other processes during LDD ion implantation, resulting in degradation of device performance.
A dummy gate structure is formed in the semiconductor substrate, and a light doped region is formed in the well region after removing the dummy gate structure, and a gate structure is formed over the well region to reduce the impact of heat treatment on LDD ion implantation.
It effectively reduces the impact of other processes on LDD ion implantation, improves the performance of field effect transistors, and saves the mask required for LDD ion implantation.
Smart Images
Figure CN119521755A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a field effect transistor and a field effect transistor. Background Art
[0002] In the application process of integrated circuits, the performance of various devices will be affected by the order in which the layers of materials are formed, especially field-effect transistors, because the different formation times of the layers of materials affect the electrical performance of the device.
[0003] In current field effect transistors, especially for short channel devices, LDD (Lightly Doped Drain) ion implantation is usually performed in the early stage of the process to form a lightly doped region. However, this will be affected by the annealing itself and the subsequent heat treatment in other processes, thereby affecting the performance of the device. Summary of the invention
[0004] The main technical problem solved by the present invention is to provide a method for manufacturing a field effect transistor and a field effect transistor, which can effectively reduce the influence of other processes on LDD ion implantation, thereby improving the performance of the device.
[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a method for manufacturing a field effect transistor, comprising: providing a semiconductor base, the semiconductor base comprising a substrate and a dielectric layer arranged on the substrate, wherein a well region is arranged in the substrate, and a dummy gate structure is formed in the dielectric layer, and the dummy gate structure corresponds to the well region; removing the dummy gate structure, forming a lightly doped region in the well region, and forming a gate structure above the well region.
[0006] In one embodiment of the present application, the well region includes a first well region and a second well region, the lightly doped region includes a first lightly doped region and a second lightly doped region, the pseudo gate structure includes a first pseudo gate structure and a second pseudo gate structure, and the gate structure includes a first gate structure and a second gate structure; the removing of the pseudo gate structure, forming a lightly doped region in the well region, and forming a gate structure above the well region, includes: removing the first pseudo gate structure corresponding to the first well region, forming a first lightly doped region in the first well region, and forming a first gate structure above the first well region; removing the second pseudo gate structure corresponding to the second well region, forming a second lightly doped region in the second well region, and forming a second gate structure above the second well region.
[0007] In one embodiment of the present application, the first lightly doped region includes a first sub-lightly doped region and a second sub-lightly doped region; the first dummy gate structure corresponding to the first well region is removed to form a first lightly doped region in the first well region, and a first gate structure is formed on the first well region, including: removing a portion of the dielectric layer corresponding to the first well region, and removing the first dummy gate structure to form a first groove; performing ion implantation at a preset angle in the exposed first well region to respectively form a first sub-lightly doped region and a second sub-lightly doped region in the first well region on both sides of the bottom of the first groove; and forming the first gate structure in the first groove.
[0008] In one embodiment of the present application, the first gate structure includes: a first metal gate filling layer, a first metal covering layer and a first work function adjustment layer; the forming of the first gate structure in the first groove includes: forming the first metal covering layer in the first groove, and forming the first work function adjustment layer on the first metal covering layer; forming the first metal gate filling layer on the first work function adjustment layer.
[0009] In one embodiment of the present application, the second lightly doped region includes a third sub-lightly doped region and a fourth sub-lightly doped region; the second pseudo gate structure corresponding to the second well region is removed to form a second lightly doped region in the second well region, and a second gate structure is formed on the second well region, including: removing a portion of the dielectric layer corresponding to the second well region, and removing the second pseudo gate structure to form a second groove; performing ion implantation at a preset angle in the exposed second well region to respectively form a third sub-lightly doped region and a fourth sub-lightly doped region in the second well region on both sides of the bottom of the second groove; and forming the second gate structure in the second groove.
[0010] In one embodiment of the present application, the second gate structure includes: a second metal gate filling layer, a second metal covering layer and a second work function adjustment layer; the forming of the second gate structure in the second groove includes: forming the second metal covering layer in the second groove, and forming the second work function adjustment layer on the second metal covering layer; forming the second metal gate filling layer on the second work function adjustment layer.
[0011] In one embodiment of the present application, a source region and a drain region are further provided in the well region; the source region contacts the lightly doped region corresponding to the source region, and the drain region contacts the lightly doped region corresponding to the drain region.
[0012] In one embodiment of the present application, it also includes: forming an interlayer dielectric layer, and forming connecting pillars in the interlayer dielectric layer, the connecting pillars including a first gate connecting pillar and a second gate connecting pillar; wherein the first gate connecting pillar corresponds to connecting the first gate structure, and the second gate structure corresponds to connecting the second gate structure.
[0013] In one embodiment of the present application, providing a semiconductor base includes: providing a substrate and forming a first dielectric layer on the substrate; forming the first pseudo gate structure in the first dielectric layer corresponding to the first well region, and forming the second pseudo gate structure in the first dielectric layer corresponding to the second well region; forming a second dielectric layer to cover the first pseudo gate structure and the second pseudo gate structure, wherein the first dielectric layer and the second dielectric layer constitute the dielectric layer.
[0014] In one embodiment of the present application, before forming the first dummy gate structure and the second dummy gate structure, it also includes: performing ion implantation in the substrate to form the first well region and the second well region, wherein the first doping region and the second doping region have opposite doping types.
[0015] In one embodiment of the present application, the method further includes: forming an isolation structure in the substrate, wherein the first well region is divided from the second well region by the isolation structure.
[0016] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a field effect transistor, including: a semiconductor base, the semiconductor base includes a substrate, a dielectric layer arranged on the substrate, wherein a well region is arranged in the substrate; a gate structure, arranged on the substrate and located in the dielectric layer; a lightly doped region, arranged in the well region, and at least part of the lightly doped region is located under the isolation side wall of the gate structure.
[0017] In one embodiment of the present application, the well region includes a first well region and a second well region, the gate structure includes a first gate structure and a second gate structure, and the lightly doped region includes a first lightly doped region and a second lightly doped region; the first gate structure is located above the first well region, and the first lightly doped region is formed in the first well region; the second gate structure is located above the second well region, and the second lightly doped region is formed in the second well region; wherein the work function of the second gate structure is different from the work function of the first gate structure.
[0018] In one embodiment of the present application, the first lightly doped region includes a first sub-lightly doped region and a second sub-lightly doped region; a source region and a drain region are also formed in the first well region, the source region is located in the first well region on one side of the first gate structure, and the drain region is located in the first well region on the other side of the first gate structure; the first sub-lightly doped region is in contact with the source region, and at least a portion of the first sub-lightly doped region is located under the isolation sidewall of the first gate structure; the second sub-lightly doped region is in contact with the drain region, and at least a portion of the second sub-lightly doped region is located under the isolation sidewall of the first gate structure.
[0019] In one embodiment of the present application, the first gate structure includes: a first metal capping layer formed in the first well region; a first work function adjustment layer formed on the first metal capping layer; and a first metal gate filling layer formed on the first work function adjustment layer.
[0020] In one embodiment of the present application, the second lightly doped region includes a third sub-lightly doped region and a fourth sub-lightly doped region; a source region and a drain region are also formed in the second well region, the source region is located in the second well region on one side of the second gate structure, and the drain region is located in the second well region on the other side of the second gate structure; the third sub-lightly doped region is in contact with the source region, and at least a portion of the third sub-lightly doped region is located under the isolation sidewall of the second gate structure; the fourth sub-lightly doped region is in contact with the drain region, and at least a portion of the fourth sub-lightly doped region is located under the isolation sidewall of the second gate structure.
[0021] In one embodiment of the present application, the second gate structure includes: a second metal capping layer formed in the second well region; a second work function adjustment layer formed on the second metal capping layer; and a second metal gate filling layer formed on the second work function adjustment layer.
[0022] In one embodiment of the present application, the first metal gate filling layer in the first gate structure is a first type metal gate, the second metal gate filling layer in the second gate structure is a second type metal gate, and the first type metal gate is different from the second type metal gate.
[0023] In one embodiment of the present application, it also includes: an interlayer dielectric layer, and a connecting column is formed in the interlayer dielectric layer, and the connecting column includes a first gate connecting column and a second gate connecting column; wherein the first gate connecting column corresponds to connecting the first gate structure, and the second gate structure corresponds to connecting the second gate structure.
[0024] Different from the prior art, the manufacturing method of the field effect transistor provided in the present application includes: providing a semiconductor substrate, the semiconductor substrate including a substrate and a dielectric layer arranged on the substrate, wherein a well region is arranged in the substrate, and a dummy gate structure is formed in the dielectric layer, and the dummy gate structure corresponds to the well region; removing the dummy gate structure, forming a lightly doped region in the well region, and forming a gate structure on the well region; that is, in the present application, on the basis of a semiconductor substrate with a dummy gate structure, the dummy gate structure is first removed, and then a lightly doped region is formed in the well region, and then a gate structure is formed on the well region, which reduces the influence of heat treatment of other processes on LDD ion implantation and saves the mask required for LDD ion implantation, that is, it can effectively reduce the influence of other processes on the lightly doped region formed by LDD ion implantation, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:
[0026] Figure 1 This is a flow chart of an embodiment of a method for manufacturing a field effect transistor in the present application;
[0027] Figure 2 It is a structural schematic diagram of an embodiment of a semiconductor substrate in the present application;
[0028] Figure 3 is a structural schematic diagram of an embodiment of the present application in which the first dummy gate structure is removed;
[0029] Figure 4 is a structural schematic diagram of an embodiment of forming a first lightly doped region in the present application;
[0030] Figure 5 is a structural schematic diagram of an embodiment of forming a first gate structure in the present application;
[0031] Figure 6 is a structural schematic diagram of an embodiment of the present application in which the second dummy gate structure is removed;
[0032] Figure 7 is a structural schematic diagram of an embodiment of forming a second lightly doped region in the present application;
[0033] Figure 8 is a structural schematic diagram of an embodiment of forming a second gate structure in the present application;
[0034] Fig. 9It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer and a connecting column in the present application.
[0035] In the accompanying drawings, a substrate 100, an isolation structure 101, a well region 110, a first well region 111, a second well region 112, a first lightly doped region 121, a first sub-lightly doped region 1211, a second sub-lightly doped region 1212, a second lightly doped region 122, a third sub-lightly doped region 1221, a fourth sub-lightly doped region 1222, a source region S, a drain region D, a dielectric layer 200, a first dielectric layer 210, a second dielectric layer 220, an oxide layer 230, a gate dielectric layer 240, a first dummy gate structure 310, and a second Pseudo gate structure 320, isolation sidewall 330, gate structure 400, first gate structure 410, first metal covering layer 4101, first work function adjustment layer 4102, first metal gate filling layer 4103, second gate structure 420, second metal covering layer 4201, second work function adjustment layer 4202, second metal gate filling layer 4203, first groove 201, second groove 202, interlayer dielectric layer 500, first gate connecting column 510, second gate connecting column 520. DETAILED DESCRIPTION
[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0037] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.
[0038] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0039] The present application is described in detail below with reference to the accompanying drawings and embodiments.
[0040] In order to weaken the hot carrier injection effect, existing field effect transistors generally use LDD ion implantation, that is, before the MOS sidewall is formed, a lightly doped ion implantation process is added, and after the sidewall is formed, the source and drain lightly doped ion implantation process is still performed, and a certain wide band lightly doped region is formed between the drain and the channel, thereby reducing the peak electric field near the drain, achieving the purpose of weakening the hot carrier injection effect; in the current manufacturing scheme for field effect transistors, LDD ions are usually implanted into the silicon substrate in the early stage of manufacturing. However, LDD ion implantation in the early stage of manufacturing will not only be affected by its own annealing treatment, but also by the subsequent heat treatment of other processes, thereby affecting the performance of the device.
[0041] Therefore, a method for manufacturing a field effect transistor is provided, which can effectively reduce the influence of other processes on LDD ion implantation, thereby improving the performance of the device.
[0042] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a field effect transistor in the present application.
[0043] like Figure 1 As shown, the method for manufacturing the field effect transistor of the present application comprises the following steps:
[0044] S10, providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a dielectric layer arranged on the substrate, wherein a well region is arranged in the substrate, and a dummy gate structure is formed in the dielectric layer, and the dummy gate structure corresponds to the well region.
[0045] Among them, the substrate is any suitable substrate known in semiconductor devices, the dielectric layer refers to any suitable dielectric layer known in semiconductor devices, the well region refers to the doped region formed by ion implantation into the substrate, and the pseudo gate structure refers to the gate structure corresponding to polysilicon doping, which is usually used for replacement in the last gate process.
[0046] Specifically, a substrate is provided, and a dielectric layer is formed on the substrate, wherein a well region is formed in the substrate, a dummy gate structure is formed in the dielectric layer, and the dummy gate structure corresponds to the well region.
[0047] S20, removing the dummy gate structure, forming a lightly doped region in the well region, and forming a gate structure on the well region.
[0048] The lightly doped region refers to the lightly doped region formed by ion implantation into the well region using the LDD ion implantation process; the gate structure refers to the metal gate structure corresponding to the metal gate material filled therein.
[0049] Specifically, after determining the semiconductor substrate, the dummy gate structure in the semiconductor substrate is removed, and then LDD ion implantation is performed in the well region corresponding to the removed area to form a lightly doped region, and the well region is filled with a metal gate material to form a gate structure.
[0050] In the present application, on the basis of a semiconductor substrate with a dummy gate structure, the dummy gate structure is first removed, and then a lightly doped region is formed in the well region, and then a gate structure is formed above the well region, thereby reducing the impact of heat treatment of other processes on the LDD ion implantation and saving the mask required for the LDD ion implantation, which can effectively reduce the impact of other processes on the lightly doped region formed by the LDD ion implantation, thereby improving the performance of the device.
[0051] The following is described in conjunction with the accompanying drawings, and the operation flow of step S10 is as follows:
[0052] A substrate 100 is provided, and a dielectric layer 200 is formed on the substrate 100, and a well region 110 is provided in the substrate 100, and a dummy gate structure is formed in the dielectric layer 200, and the dummy gate structure corresponds to the well region 110. It is necessary to remove the dummy gate structure 300, and then perform LDD ion implantation on the substrate from the removed area to form a lightly doped region in the well region 110, and form a gate structure 400 on the well region 110.
[0053] In some embodiments, isolation spacers 330 are formed on both sides of the dummy gate structure.
[0054] In some embodiments, the well region 110 can be divided into a first well region 111 and a second well region 112, the lightly doped region can be divided into a first lightly doped region and a second lightly doped region, the dummy gate structure can be divided into a first dummy gate structure and a second dummy gate structure, and the gate structure can be divided into a first gate structure and a second gate structure.
[0055] See also Figure 2 , Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application.
[0056] like Figure 2As shown, a substrate 100 is provided, and a first dielectric layer 210 is formed on the substrate 100. A first dummy gate structure 310 is formed in the first dielectric layer 210 corresponding to the first well region 111, and a second dummy gate structure 320 is formed in the first dielectric layer 210 corresponding to the second well region 112. The second dielectric layer 220 is formed to cover the first dummy gate structure 310 and the second dummy gate structure 320, wherein the first dielectric layer 210 and the second dielectric layer 220 constitute the dielectric layer 200, and isolation spacers 330 are provided on both sides of the first dummy gate structure 310, and isolation spacers 330 are also formed on both sides of the second dummy gate structure 320.
[0057] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).
[0058] In some embodiments, a first well region 111 and a second well region 112 are formed in the substrate 100 , and the first well region 111 and the second well region 112 may be formed by ion implantation in advance in the substrate, and the doping types of the first well region and the second well region are opposite.
[0059] In some embodiments, an isolation structure 101 is also formed in the substrate 100, which may be a shallow trench isolation structure. The first well region 111 is divided from the second well region 112 by the isolation structure 101, and the isolation structure may be formed by pre-forming a groove in the substrate and filling it with an isolation material.
[0060] In some embodiments, an active region S and a drain region D are also formed in the substrate 100, that is, each well region has a corresponding source and drain, wherein the source is arranged in the well region on one side of the dummy gate structure, and the drain is arranged in the well region on the other side of the dummy gate structure.
[0061] Next, the dummy gate structure is removed. Since the dummy gate structure can be divided into a first dummy gate structure 310 and a second dummy gate structure 320, and the work functions of the first gate structure and the second gate structure subsequently formed are different, the first dummy gate structure 310 can be removed first to form the corresponding first gate structure, and then the second dummy gate structure 320 can be removed to form the corresponding second gate structure.
[0062] That is, the first dummy gate structure is removed first.
[0063] See also Figure 3 , Figure 3 It is a structural diagram of an embodiment of the present application in which the first dummy gate structure is removed.
[0064] like Figure 3 As shown, in Figure 2 On the basis of the above, etching is performed from the dielectric layer 200 toward the substrate to expose the first dummy gate structure, and then the first dummy gate structure 310 is removed to form the first groove 201. In some embodiments, an oxide layer 230 is further present at the bottom of the first groove 201.
[0065] Then, LDD ion doping is performed to form a first lightly doped region, wherein the first lightly doped region includes a first sub-lightly doped region and a second sub-lightly doped region.
[0066] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a first lightly doped region in the present application.
[0067] like Figure 4 As shown, in Figure 3 On the basis of this, LDD ion implantation is performed on the first well region 111 from the first groove 201 to form a first lightly doped region 121, wherein the first lightly doped region 121 includes a first sub-lightly doped region 1211 and a second sub-lightly doped region 1212, that is, a first sub-lightly doped region 1211 and a second sub-lightly doped region 1212 are formed respectively.
[0068] In some embodiments, it is necessary to perform LDD ion implantation on the first well region 111 from the first groove 201 at a preset angle so that the first sub-lightly doped region 1211 contacts the source region S in the first well region 111, and the second sub-lightly doped region 1212 contacts the drain region D in the first well region 111; wherein the preset angle may be an inclination angle from the top on one side of the first groove to the bottom on the other side of the first groove.
[0069] A first gate structure is then formed in the first groove.
[0070] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of forming a first gate structure in the present application.
[0071] like Figure 5 As shown, in Figure 4On the basis of the present invention, a first metal covering layer 4101 is formed in the first groove, and the first metal covering layer 4101 is etched to retain the first metal covering layer 4101 in the first groove; and a first work function adjustment layer 4102 is formed on the first metal covering layer 4101, and the first work function adjustment layer 4102 is also etched to retain the first work function adjustment layer 4102 in the first groove, and a metal gate material is filled on the first work function adjustment layer 4102 to form a first metal gate filling layer 4103, that is, the first metal gate filling layer 4103 is formed in the first groove, and chemical mechanical polishing is performed to make the surface of the dielectric layer flat, that is, the first dielectric layer is removed, for example, the dielectric layer is flush with the first metal gate filling layer 4103, and the first metal covering layer 4101, the first work function adjustment layer 4102 and the first metal gate filling layer 4103 are used as the first gate structure 410, and the isolation sidewalls 330 are also retained on both sides of the first gate structure 410.
[0072] In some embodiments, a gate dielectric layer 240 may be further included, and the gate dielectric layer 240 is disposed between the first gate structure 410 and the substrate 100 ; further, an oxide layer 230 may be disposed between the gate dielectric layer 240 and the substrate 100 .
[0073] In some embodiments, the first metal covering layer 4101 is disposed between the gate dielectric layer and the first work function adjustment layer 4102. The first metal covering layer 4101 may include a first sub-metal covering layer and a second sub-metal covering layer. The first sub-metal covering layer is located in the central region of the first gate structure, and the second sub-metal covering layer is located on at least one side of the first sub-metal covering layer. For example, the second sub-metal covering layer is located on the side of the first sub-metal covering layer close to the drain, or the second sub-metal covering layer is located on both sides of the first sub-metal covering layer close to the drain and the source. The material of the second sub-metal covering layer is different from that of the first sub-metal covering layer, and the work function of the second sub-metal covering layer is different from that of the first sub-metal covering layer. Specifically, when the first gate structure is a gate structure of a P-type transistor, the work function of the second sub-metal covering layer is lower than the work function of the first sub-metal covering layer; when the first gate structure is a gate structure of an N-type transistor, the work function of the second sub-metal covering layer is higher than the work function of the first sub-metal covering layer.
[0074] In other embodiments, the material of the first sub-metal covering layer and the second sub-metal covering layer may be the same, that is, the work functions of the first sub-metal covering layer and the second sub-metal covering layer are the same, for example, the material of the first sub-metal covering layer and the second sub-metal covering layer are both TiN; in addition, the material of the first work function adjustment layer corresponding to the gate structure of a P-type crystal is different from the material of the first work function adjustment layer corresponding to the gate structure of an N-type transistor.
[0075] In some embodiments, the first work function adjustment layer 4102 includes a first sub-work function adjustment layer, a second sub-work function adjustment layer, and a third sub-work function adjustment layer; that is, the first sub-work function adjustment layer, the second sub-work function adjustment layer, and the third sub-work function adjustment layer are sequentially formed in the first groove; taking the first gate structure as a gate structure of a P-type transistor as an example, the material of the first sub-work function adjustment layer can be TaN, the material of the second sub-work function adjustment layer can be TiN, and the material of the third sub-work function adjustment layer can be TaN. In other embodiments, the first work function adjustment layer 4102 can also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlN. In some embodiments, the material of the first metal gate filling layer is Al. In other embodiments, the first metal gate filling layer 4103 can also be set to other low-resistance metal materials.
[0076] If the first gate structure is the gate structure of an N-type transistor as an example, the material of the first sub-work function adjustment layer can be TaN, the material of the second sub-work function adjustment layer can be TiAl, and the material of the third sub-work function adjustment layer can be TiN / Ti. In other embodiments, the first work function adjustment layer 4102 can also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlC.
[0077] As described above, in some embodiments, the second sub-metal covering layer is finally formed on the same layer as the first sub-metal covering layer. In other embodiments, the second sub-metal covering layer may also be formed on any layer between the gate dielectric layer and the first metal gate filling layer through other process steps, for example, on the same layer as a layer in the first work function adjustment layer 4102, as long as the second sub-metal covering layer is provided on both sides of the first gate structure 410, especially close to the drain side, so that the work function of the first gate structure 410 and the drain overlap is changed.
[0078] The second dummy gate structure is then removed.
[0079] See also Figure 6 , Figure 6 It is a structural diagram of an embodiment of the present application in which the second dummy gate structure is removed.
[0080] like Figure 6 As shown, in Figure 5 On the basis of the above, the second dummy gate structure 320 is removed to form the second groove 202. In some embodiments, an oxide layer 230 is further present at the bottom of the second groove 202.
[0081] Then, LDD ion implantation is performed to form a second lightly doped region, wherein the second lightly doped region includes a third sub-lightly doped region and a fourth sub-lightly doped region.
[0082] Its reference Figure 7 , Figure 7 It is a structural schematic diagram of an embodiment of forming a second lightly doped region in the present application.
[0083] like Figure 7 As shown, in Figure 6 On the basis of this, LDD ion implantation is performed on the second well region 112 from the second groove 202 to form a second lightly doped region 122, and the second lightly doped region 122 includes a third sub-lightly doped region 1221 and a fourth sub-lightly doped region 1222, that is, a third sub-lightly doped region 1221 and a fourth sub-lightly doped region 1222 are formed respectively.
[0084] In some embodiments, it is necessary to perform LDD ion implantation on the second well region 112 from the second groove 202 at a preset angle so that the third sub-lightly doped region 1221 contacts the source region S in the second well region 112, and the fourth sub-lightly doped region 1222 contacts the drain region D in the second well region 112; wherein the preset angle can be an inclination angle from the top of one side of the second groove to the bottom of the other side of the first groove.
[0085] A second gate structure is then formed in the second groove.
[0086] See also Figure 8 , Figure 8 It is a structural schematic diagram of an embodiment of forming a second gate structure in the present application.
[0087] like Figure 8 As shown, in Figure 7 On the basis of the present invention, a second metal covering layer 4201 is formed in the second groove, and the second metal covering layer 4201 is etched to retain the second metal covering layer 4201 in the second groove; and a second work function adjustment layer 4202 is formed on the second metal covering layer 4201, and the second work function adjustment layer 4202 is also etched to retain the second work function adjustment layer 4202 in the second groove, and a metal gate material is filled on the second work function adjustment layer 4202 to form a second metal gate filling layer 4203, that is, a second metal gate filling layer 4203 is formed in the second groove, and chemical mechanical polishing is performed to make the surface of the dielectric layer flat, for example, the dielectric layer is flush with the second metal gate filling layer 4203; the second metal covering layer 4201, the second work function adjustment layer 4202 and the second metal gate filling layer 4203 are used as the second gate structure 420, and isolation sidewalls 330 are also retained on both sides of the second gate structure 420.
[0088] In some embodiments, a gate dielectric layer may be further included, and the gate dielectric layer is disposed between the second gate structure 420 and the substrate 100 ; further, an oxide layer 230 may be disposed between the gate dielectric layer and the substrate 100 .
[0089] In some embodiments, the second metal covering layer 4201 is disposed between the gate dielectric layer and the second work function adjustment layer 4202, and the second metal covering layer 4201 may include a third sub-metal covering layer and a fourth sub-metal covering layer, wherein the third sub-metal covering layer is located in the central region of the second gate structure, and the fourth sub-metal covering layer is located on at least one side of the third sub-metal covering layer, for example, the fourth sub-metal covering layer is located on the side of the third sub-metal covering layer close to the drain, or the fourth sub-metal covering layer is located on both sides of the third sub-metal covering layer close to the drain and the source. The material of the fourth sub-metal covering layer is different from that of the third sub-metal covering layer, and the work function of the fourth sub-metal covering layer is different from that of the third sub-metal covering layer. Specifically, when the second gate structure is a gate structure of a P-type transistor, the work function of the fourth sub-metal covering layer is lower than the work function of the third sub-metal covering layer; when the second gate structure is a gate structure of an N-type transistor, the work function of the fourth sub-metal covering layer is higher than the work function of the third sub-metal covering layer.
[0090] In other embodiments, the material of the third sub-metal covering layer and the fourth sub-metal covering layer may be the same, that is, the work function of the third sub-metal covering layer and the fourth sub-metal covering layer is the same, for example, the material of the third sub-metal covering layer and the fourth sub-metal covering layer are both TiN; in addition, the material of the second work function adjustment layer corresponding to the gate structure of the second gate structure being an N-type crystal is different from the material of the second work function adjustment layer corresponding to the gate structure of the second gate structure being a P-type transistor.
[0091] In some embodiments, the second work function adjustment layer 4202 includes a fourth sub-work function adjustment layer, a fifth sub-work function adjustment layer, and a sixth sub-work function adjustment layer; that is, the fourth sub-work function adjustment layer, the fifth sub-work function adjustment layer, and the sixth sub-work function adjustment layer are sequentially formed in the second groove, and the second gate structure is an N-type transistor gate structure as an example, wherein the material of the fourth sub-work function adjustment layer can be TaN, the material of the fifth sub-work function adjustment layer can be TiAl, and the material of the sixth sub-work function adjustment layer can be TiN / Ti. In other embodiments, the second work function adjustment layer 4202 can also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlC. In some embodiments, the material of the second metal gate filling layer is Al, and in other embodiments, the second metal gate filling layer 4203 can also be set to other low-resistance metal materials.
[0092] If the second gate structure is a gate structure of a P-type transistor as an example, the material of the fourth sub-work function adjustment layer can be TaN, the material of the fifth sub-work function adjustment layer can be TiN, and the material of the sixth sub-work function adjustment layer can be TaN. In other embodiments, the second work function adjustment layer 4102 can also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlN.
[0093] As described above, in some embodiments, the fourth sub-metal covering layer is finally formed on the same layer as the third sub-metal covering layer. In other embodiments, the fourth sub-metal covering layer may also be formed on any layer between the gate dielectric layer and the second metal gate filling layer 4203 through other process steps, for example, it may be arranged on the same layer as a layer in the second work function adjustment layer 4202, as long as the fourth sub-metal covering layer is arranged on both sides of the second gate structure 420, especially close to the drain side, so that the work function of the second gate structure 420 and the drain overlap is changed.
[0094] Furthermore, an interlayer dielectric layer and a connecting column may be formed.
[0095] See also Fig. 9 , Fig. 9 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer and a connecting column in the present application.
[0096] like Fig. 9 As shown, in Figure 8 On the basis of, an interlayer dielectric layer 500 is formed, and connecting pillars are formed in the interlayer dielectric layer, the connecting pillars including a first gate connecting pillar 510 and a second gate connecting pillar 520, wherein the first gate connecting pillar 510 is correspondingly connected to the first gate structure 410 to lead out the first gate structure 410, and the second gate connecting pillar 520 is correspondingly connected to the second gate structure 420 to lead out the second gate structure 420.
[0097] In some embodiments, the connection pillars may further include a first source / drain connection pillar and a second source / drain connection pillar, which are respectively connected to the corresponding source region S and drain region D, thereby respectively leading out the source region S and drain region D.
[0098] In the present embodiment, on the basis of a semiconductor substrate having a dummy gate structure, the dummy gate structure is first removed, and then a lightly doped region is formed in the well region, and then a gate structure is formed above the well region, thereby reducing the influence of heat treatment of other processes on the LDD ion implantation and saving the photomask required for the LDD ion implantation, which can effectively reduce the influence of other processes on the lightly doped region formed by the LDD ion implantation, thereby improving the performance of the device.
[0099] The present application also provides a field effect transistor, see Figure 2-Figure 9 .
[0100] Specifically, the field effect transistor includes a semiconductor body, which includes a substrate 100 and a dielectric layer 200 arranged on the substrate, wherein a well region 110 is arranged in the substrate 100; it also includes a gate structure 400, which is arranged on the substrate and located in the dielectric layer 200; the well region 110 also includes a lightly doped region, and at least part of the lightly doped region is located under the isolation sidewall 330 of the gate structure 400.
[0101] In some embodiments, the lightly doped region is formed by performing LDD ion implantation on the well region at a preset angle after removing the dummy gate structure in the semiconductor substrate. Therefore, at least part of the lightly doped region is located under the isolation sidewall of the gate structure 400 .
[0102] In this embodiment, the lightly doped region is disposed in the well region, and at least a portion of the lightly doped region is located under the isolation sidewall of the gate structure, thereby reducing the peak electric field near the drain and achieving the purpose of weakening the hot carrier injection effect.
[0103] In some embodiments, see Fig. 9 , the well region includes a first well region 111 and a second well region 112, the gate structure includes a first gate structure 410 and a second gate structure 420, and the lightly doped region includes a first lightly doped region 121 and a second lightly doped region 122; the first gate structure 410 is located on the first well region 111, and the first lightly doped region 121 is formed in the first well region 111; the second gate structure 420 is located on the second well region 112, and the second lightly doped region 122 is formed in the second well region 112; wherein the work function of the second gate structure 420 is different from the work function of the first gate structure 410.
[0104] In some embodiments, see Fig. 9 The first lightly doped region 121 includes a first sub-lightly doped region 1211 and a second sub-lightly doped region 1212; a source region S and a drain region D are also formed in the first well region 111, the source region S is located in the first well region 111 on one side of the first gate structure 410, and the drain region D is located in the first well region 111 on the other side of the first gate structure 410; the first sub-lightly doped region 1211 is in contact with the source region S, and at least a portion of the first sub-lightly doped region 1211 is located under the isolation sidewall 330 of the first gate structure 410; the second sub-lightly doped region 1212 is in contact with the drain region D, and at least a portion of the second sub-lightly doped region 1212 is located under the isolation sidewall 330 of the first gate structure 410.
[0105] In some embodiments, see Fig. 9The first gate structure 410 includes: a first metal capping layer 4101 formed in the first well region 111 ; a first work function adjustment layer 4102 formed on the first metal capping layer 4101 ; and a first metal gate filling layer 4103 formed on the first work function adjustment layer 4102 .
[0106] In some embodiments, the second lightly doped region 122 includes a third sub-lightly doped region 1221 and a fourth sub-lightly doped region 1222; a source region S and a drain region D are also formed in the second well region 112, the source region S is located in the second well region 112 on one side of the second gate structure 420, and the drain region D is located in the second well region 112 on the other side of the second gate structure 420; the third sub-lightly doped region 1221 is in contact with the source region S, and at least a portion of the third sub-lightly doped region 1221 is located under the isolation sidewall of the second gate structure 420; the fourth sub-lightly doped region 1222 is in contact with the drain region D, and at least a portion of the fourth sub-lightly doped region 1222 is located under the isolation sidewall of the second gate structure 420.
[0107] In some embodiments, the second gate structure 420 includes: a second metal capping layer 4201 formed in the second well region 112 ; a second work function adjustment layer 4202 formed on the second metal capping layer 4201 ; and a second metal gate filling layer 4203 formed on the second work function adjustment layer 4202 .
[0108] In some embodiments, the first metal gate filling layer 4103 in the first gate structure 410 is a first type metal gate, and the second metal gate filling layer 4203 in the second gate structure 420 is a second type metal gate, and the first type metal gate is different from the second type metal gate.
[0109] In some embodiments, it also includes: an interlayer dielectric layer 500, and connecting pillars are formed in the interlayer dielectric layer 500, and the connecting pillars include a first gate connecting pillar 510 and a second gate connecting pillar 520; wherein the first gate connecting pillar 510 corresponds to connecting the first gate structure 410, and the second gate connecting pillar 520 corresponds to connecting the second gate structure 420.
[0110] In some embodiments, the semiconductor body includes: a substrate 100 ; a first dielectric layer 210 formed on the substrate 100 ; and a second dielectric layer 220 formed on the first dielectric layer 210 , wherein the first dielectric layer 210 and the second dielectric layer 220 constitute a dielectric layer 200 .
[0111] In some embodiments, the method further includes: an isolation structure 101 formed in the substrate 100 , wherein the first well region 111 is divided from the second well region 112 by the isolation structure 101 .
[0112] In this embodiment, a lightly doped region is formed in the well region of the substrate, and at least a portion of the lightly doped region is located under the isolation sidewall of the gate structure, and then a gate structure is formed on the well region, thereby reducing the peak electric field near the drain and achieving the purpose of weakening the hot carrier injection effect.
[0113] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A method for manufacturing a field effect transistor, characterized in that: include: A semiconductor substrate is provided, the semiconductor substrate comprising a substrate and a dielectric layer disposed on the substrate, wherein a well region is disposed in the substrate, and a dummy gate structure is formed in the dielectric layer, and the dummy gate structure corresponds to the well region; The dummy gate structure is removed, a lightly doped region is formed in the well region, and a gate structure is formed on the well region.
2. The method according to claim 1, characterized in that The well region includes a first well region and a second well region, the lightly doped region includes a first lightly doped region and a second lightly doped region, the dummy gate structure includes a first dummy gate structure and a second dummy gate structure, and the gate structure includes a first gate structure and a second gate structure; The removing of the dummy gate structure, forming a lightly doped region in the well region, and forming a gate structure on the well region comprises: removing the first dummy gate structure corresponding to the first well region, forming a first lightly doped region in the first well region, and forming a first gate structure on the first well region; removing the second dummy gate structure corresponding to the second well region, forming a second lightly doped region in the second well region, and forming a second gate structure on the second well region; The work function of the second gate structure is different from the work function of the first gate structure.
3. The method according to claim 2, characterized in that The first lightly doped region includes a first sub-lightly doped region and a second sub-lightly doped region; The removing of the first dummy gate structure corresponding to the first well region, forming a first lightly doped region in the first well region, and forming a first gate structure on the first well region comprises: removing a portion of the dielectric layer corresponding to the first well region and removing the first dummy gate structure to form a first groove; Performing ion implantation at a preset angle in the exposed first well region to respectively form a first sub-lightly doped region and a second sub-lightly doped region in the first well region at both sides of the bottom of the first groove; The first gate structure is formed in the first groove.
4. The method according to claim 3, characterized in that The first gate structure includes: a first metal gate filling layer, a first metal capping layer and a first work function adjustment layer; The forming of a first gate structure in the first groove comprises: forming the first metal capping layer in the first groove, and forming the first work function adjustment layer on the first metal capping layer; The first metal gate filling layer is formed on the first work function adjustment layer.
5. The method according to claim 2, characterized in that: The second lightly doped region includes a third sub-lightly doped region and a fourth sub-lightly doped region; The removing the second dummy gate structure corresponding to the second well region, forming a second lightly doped region in the second well region, and forming a second gate structure on the second well region, comprises: removing a portion of the dielectric layer corresponding to the second well region and removing the second dummy gate structure to form a second groove; Performing ion implantation at a preset angle in the exposed second well region to respectively form a third sub-lightly doped region and a fourth sub-lightly doped region in the second well region at both sides of the bottom of the second groove; The second gate structure is formed in the second groove.
6. The method according to claim 5, characterized in that The second gate structure includes: a second metal gate filling layer, a second metal capping layer, and a second work function adjustment layer; The forming the second gate structure in the second groove includes: forming the second metal capping layer in the second groove, and forming the second work function adjusting layer on the second metal capping layer; The second metal gate filling layer is formed on the second work function adjusting layer.
7. The method according to claim 1, characterized in that The well region is also provided with a source region and a drain region; The source region contacts the lightly doped region corresponding to the source region, and the drain region contacts the lightly doped region corresponding to the drain region.
8. The method according to claim 2, characterized in that: Also includes: Forming an interlayer dielectric layer, and forming connecting pillars in the interlayer dielectric layer, wherein the connecting pillars include a first gate connecting pillar and a second gate connecting pillar; The first gate connection column is correspondingly connected to the first gate structure, and the second gate structure is correspondingly connected to the second gate structure.
9. The method according to claim 2, characterized in that: The semiconductor substrate is provided, comprising: Providing a substrate, and forming a first dielectric layer on the substrate; forming the first dummy gate structure in the first dielectric layer corresponding to the first well region, and forming the second dummy gate structure in the first dielectric layer corresponding to the second well region; A second dielectric layer is formed to cover the first dummy gate structure and the second dummy gate structure, wherein the first dielectric layer and the second dielectric layer constitute the dielectric layer.
10. The method according to claim 9, characterized in that Before forming the first dummy gate structure and the second dummy gate structure, the method further includes: Ion implantation is performed in the substrate to form the first well region and the second well region, wherein the first well region and the second well region have opposite doping types.
11. The method according to claim 9, characterized in that Also includes: An isolation structure is formed in the substrate, wherein the first well region is divided from the second well region by the isolation structure.
12. A field effect transistor, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a substrate and a dielectric layer disposed on the substrate, wherein a well region is disposed in the substrate; A gate structure, disposed on the substrate and located in the dielectric layer; The lightly doped region is arranged in the well region, and at least a portion of the lightly doped region is located under the isolation sidewall of the gate structure.
13. The field effect transistor according to claim 12, characterized in that: The well region includes a first well region and a second well region, the gate structure includes a first gate structure and a second gate structure, and the lightly doped region includes a first lightly doped region and a second lightly doped region; The first gate structure is located on the first well region, and the first lightly doped region is formed in the first well region; The second gate structure is located on the second well region, and the second lightly doped region is formed in the second well region; The work function of the second gate structure is different from the work function of the first gate structure.
14. The field effect transistor according to claim 13, characterized in that: The first lightly doped region includes a first sub-lightly doped region and a second sub-lightly doped region; A source region and a drain region are also formed in the first well region, the source region is located in the first well region on one side of the first gate structure, and the drain region is located in the first well region on the other side of the first gate structure; The first sub-lightly doped region contacts the source region, and at least a portion of the first sub-lightly doped region is located under the isolation sidewall of the first gate structure; the second sub-lightly doped region contacts the drain region, and at least a portion of the second sub-lightly doped region is located under the isolation sidewall of the first gate structure.
15. The field effect transistor according to claim 14, characterized in that: The first gate structure comprises: a first metal capping layer formed in the first well region; a first work function adjustment layer, formed on the first metal capping layer; A first metal gate filling layer is formed on the first work function adjustment layer.
16. The field effect transistor according to claim 13, characterized in that: The second lightly doped region includes a third sub-lightly doped region and a fourth sub-lightly doped region; A source region and a drain region are also formed in the second well region, the source region is located in the second well region on one side of the second gate structure, and the drain region is located in the second well region on the other side of the second gate structure; The third sub-lightly doped region contacts the source region, and at least a portion of the third sub-lightly doped region is located under the isolation sidewall of the second gate structure; the fourth sub-lightly doped region contacts the drain region, and at least a portion of the fourth sub-lightly doped region is located under the isolation sidewall of the second gate structure.
17. The field effect transistor according to claim 16, characterized in that: The second gate structure comprises: a second metal capping layer formed in the second well region; a second work function adjustment layer, formed on the second metal capping layer; A second metal gate filling layer is formed on the second work function adjusting layer.
18. The field effect transistor according to claim 13, characterized in that: The first metal gate filling layer in the first gate structure is a first type metal gate, the second metal gate filling layer in the second gate structure is a second type metal gate, and the first type metal gate is different from the second type metal gate.
19. The field effect transistor according to claim 13, characterized in that: Also includes: An interlayer dielectric layer, wherein connecting pillars are formed in the interlayer dielectric layer, and the connecting pillars include a first gate connecting pillar and a second gate connecting pillar; The first gate connection column is correspondingly connected to the first gate structure, and the second gate structure is correspondingly connected to the second gate structure.