64results about How to "Mask saving" patented technology

The invention provides a structure and manufacturing method of an array colored film integrated type liquid crystal display panel. The method includes the steps that a color-shielding layer (30) is manufactured on a first protection layer (25), the portions, located above a grid (21) and a source / drain electrode (24), of the color-shielding layer (30) are removed through a wet etching process, and then a second protection layer (40) covering the color-shielding layer (30) and the first protection layer (25) is deposited; a pixel electrode (50) is formed on the second protection layer (40) and penetrates through a via hole (45) of the second protection layer (40) and the first protection layer (25) to be in contact with the source / drain electrode (24); then the region where the color-shielding layer (30) is removed through the wet etching process is filled with black matrix materials, a black matrix (60) and a spacer (70) located on the black matrix (60) and integrated with the black matrix (60) are manufactured at the same time through a slit mask, the aperture opening ratio can be increased, bubbles are avoided, meanwhile the mask is saved, and the production cost is lowered.

The invention disclose a touch control panel and a fabrication method thereof, which belong to the technical field of display and can be used for improving the production efficiency of the touch control panel and reducing the production cost of the control panel. The touch control panel comprises a substrate and also comprises a touch control electrode and a black matrix, wherein the touch control electrode is arranged on the substrate, and the black matrix is arranged on the touch control electrode, has same patterns with the touch control electrode, and is completely coincided with the touch control electrode. The touch control panel can be applicable for display devices with the touch control panel, such as a liquid crystal display television, a liquid crystal displayer, a mobile phone and a tablet computer.

The present invention provides a manufacture method of a Color Filter On Array liquid crystal display panel and a structure thereof. The method comprises: manufacturing a color resist layer (30) on a first protective layer (25), and removing the color resist layer (30) in an area above the gate (21) and the source / the drain (24), and deposing a second protective layer (40) covering the color resist layer (30) and the first protective layer (25); the pixel electrode (50) is formed on the second protective layer (40), and contacts with the source / the drain (24) through a via hole (45) penetrating the second protective layer (40) and the first protective layer (25); and then, filling black matrix material in the area of which the color resist layer (30) is removed, and employing a slit diffraction mask to manufacture a black matrix (60) and spacers (70) on the black matrix (60).

The invention discloses a manufacturing method of a super junction device. The method comprises the following steps: the step 1, forming a gate structure which is a trench gate, filling a gate trenchwith a polysilicon gate in the forming process of the trench gate, then carrying out first planarization to enable the surface of a first epitaxial layer with the trench gate to be a flat surface, andenabling the width of the gate trench at the leading-out position of the gate structure to meet the requirement of forming a contact hole; and the step 2, forming a super junction in the first epitaxial layer with the flat surface on which the trench gate is formed, wherein in the forming process of the super junction, a second epitaxial layer is adopted to fill the super junction trench, and then secondary planarization is performed, so that the surface of the first epitaxial layer with the super junction is a flat surface. According to the invention, the full-flat process can be realized, the trench gate process can be conveniently arranged before the super junction forming process, and the thermal process after the super junction is formed can be reduced, so that the mutual diffusion of impurities of the super junction is reduced, the device performance is improved, a photomask can be saved, and the process cost is reduced.

The invention discloses a method for manufacturing a polysilicon active layer-containing thin film transistor, a manufacturing method thereof and an array substrate. The method comprises the following steps of: depositing an amorphous silicon layer on a substrate; patterning the amorphous silicon layer; forming an active layer which comprises a source region, a drain region and a channel region; forming a gate insulating layer and a gate electrode on the upper part of the channel region; depositing an induced metal layer on the substrate on which the gate electrode is formed; doping impurities into the source region and the drain region in an ion injection way, wherein part of the induced metal is bombarded into the source region and the drain region when ions are injected; removing the induced metal layer; performing heat treatment on the doped active layer, so that impurities are activated, and the active layer is subjected to metal-induced crystallization and metal-induced lateral crystallization under the action of the induced metal; and forming a source electrode and a drain electrode. By the method, the preparation time for a polysilicon thin film transistor (TFT) can be shortened; and the manufacturing cost of the polysilicon TFT can be reduced.

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the steps: step 1, filling a gate electrode trench with a polysilicon gate and carrying out first planarization to form a gate electrode structure; step 2, etching back the polysilicon gate and forming a sealing layer in a top recess formed by back etching; and step 3, filling the super junction trench with a second epitaxial layer and carrying out secondary planarization to form a super junction. According to the invention, a full-flat process can be realized, the trench gate processcan be conveniently arranged before the super junction forming process, and the thermal process after the super junction is formed can be reduced, so that the mutual diffusion of impurities of the super junction is reduced, the device performance is improved, a photomask can be saved, and the process cost is reduced; and doping and external expansion of the polysilicon gate can be prevented, a gate oxide layer can be protected, and the product quality and reliability can be improved.

The invention provides a display panel. The display panel comprises thin film transistors arranged in an array mode. The source electrodes and the drain electrodes of the thin film transistors comprise electrode layers, and the electrode layers of the source electrodes or the drain electrodes extend to pixel opening areas and can serve as pixel electrodes. Dielectric layers used for arranging thepixel electrodes are reduced. Compared with the prior art, the display panel has the advantages that photomask manufacturing procedures can be reduced, and cost is reduced.

The invention discloses a deep trench isolation technical method. The method comprises that a silicon oxide layer and a silicon nitride layer are formed in the surface of a semiconductor substrate successively; a photoresist is defined to etch the silicon oxide layer and the silicon nitride layer, an area to form a deep trench is opened, and the trench of certain depth is formed by etching downwards; a linear oxide layer is formed in the trench, and polycrystalline silicon is filled; polycrystalline silicon is etched back; a furnace tube is oxide to form a silicon oxide layer; the silicon oxide layer and the silicon nitride layer are removed; epitaxial growth is carried out; the silicon oxide layer is formed; polycrystalline silicon is filled; the polycrystalline silicon in the epitaxial surface and the deep trench are etched back; and the silicon oxide layer in the epitaxial surface is removed by etching. According to the technical method, part depth of trench is formed before epitaxial deposition technology, the subsequent trench is formed by using the characteristic of selective growth of the epitaxial deposition technology, the difficulty of dry etching is reduced, challenge totrench pore-filling is reduced, and a zero-layer mask can be omitted.

The invention relates to a fluid dynamic bearing system having a stationary bearing component and a moving bearing component, that are separated from one another by a bearing gap filled with a bearing fluid. There are two radial bearing regions separated from one another and marked by radial bearing grooves. A separator region having a larger bearing gap width is disposed between the radial bearing regions. The radial bearing grooves of the two radial bearing regions have inner ends facing each other and outer ends facing away from each other. At least the outer ends of the radial bearing grooves are connected to each other by connecting grooves. According to the invention, wear zones provided especially for this purpose are disposed adjoining the connecting grooves, so as to prevent material wear at other regions of the bearing.

A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.

The invention discloses a voltage detection circuit on IO. The voltage detection circuit on IO includes a PMOS transistor serial structure which is formed through serial connection of a plurality of PMOS transistors in a diode connection mode, wherein the PMOS transistor serial structure is connected between an input signal and a first node; the source electrode of the first PMOS transistor is connected with the input signal, and the grid electrode of the first PMOS transistor is connected with the first node; a first resistor and a second resistor are connected in series between the drain electrode of the first PMOS transistor and the ground, and the connection point between the first resistor and the second resistor is the second node which outputs a detection signal; a third resistor isconnected between the first node and the source electrode of the second PMOS transistor, and the drain electrode of the second PMOS transistor is connected with the power supply voltage, and the gridelectrode of the second PMOS transistor is connected with the second node, and the source electrode of the second PMOS transistor is a third node; and each PMOS transistor utilizes the transistor technological structure taking the working voltage as the power supply voltage. The voltage detection circuit on IO is implemented by using the transistor technological structure of the power supply voltage, and does not need Zeners so as to save one layer of photomask to save the cost.

Disclosed is a method for manufacturing a thin film transistor, and a thin film transistor, relating to the technical field of liquid crystal display. The method comprises steps of: forming a buffer layer, an active layer, a gate insulator layer, and a gate electrode layer successively on a glass substrate and patterning these layers; forming an inter-layer dielectric layer on the buffer layer, the active layer, and the gate electrode layer and patterning the inter-layer dielectric layer; forming a source and a drain on the inter-layer dielectric layer, enabling the source and the drain to come into contact with the active layer, and patterning the source and the drain; forming a passivation layer and an organic photoresist layer successively on the inter-layer dielectric layer, the source, and the drain, and patterning the organic photoresist layer; dry-etching the passivation layer by using the organic photoresist layer as a mask, so as to form a hole on the passivation layer; and forming an organic light-emitting device by means of the hole on the passivation layer. The method saves a mask, requires simple techniques, and saves manufacturing costs. Besides, the developer is not able to come into direct contact with exposed aluminum of the source and the drain resulted from etching of the passivation layer. The method thus achieves the aim of improving product characteristics.

A touch display panel structure, a method for forming the touch display panel structure, and a touch display device are provided. The touch display panel structure includes: a substrate, scan lines each including a plurality of scan line segments, touch electrode lines each disposed at an interval between adjacent scan line segments; a first dielectric layer and data lines; a second dielectric layer and a first interconnection structure; a first via hole through the first dielectric layer and the second dielectric layer; a third dielectric layer a common electrode layer; a second via hole through the first dielectric layer and the second dielectric layer; and a plurality of third via holes through the third dielectric layer, wherein each touch electrode is connected to a touch electrode line via the second via hole and the third via hole.