Semiconductor device and forming method thereof

Abstract

Techniques described herein include forming respective (different) types of metal silicide layers of a p-type source / drain region and an n-type source / drain region for a nanostructured transistor of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source / drain region of a first nanostructured transistor (e.g., such that the p-type metal silicide layer is not formed over an n-type source / drain region), and an n-type metal silicide layer (which may be selective or non-selective) may be formed over the n-type source / drain region of the second nanostructured transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region and a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for the p-type source / drain region and the n-type source / drain region. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] As semiconductor device manufacturing advances and technology process nodes decrease in size, transistors may be affected by short channel effects (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement, among other examples. In addition, for smaller technology nodes, as the gate length of the transistor decreases, source / drain (S / D) electron tunneling increases, which increases the off current for the transistor (the current flowing through the channel of the transistor when the transistor is in the off configuration). Silicon (Si) / silicon germanium (SiGe) nanostructure transistors such as nanowires, nanosheets, nanoribbons, nanotubes, multi-bridge channels, and all-around gate (GAA) devices are potential candidate transistors to overcome short channel effects at smaller technology nodes. Nanostructure transistors are effective structures that can experience reduced SCE and enhanced carrier mobility relative to other types of transistors. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructure channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructure channel layers; forming a gate structure wrapping each of the plurality of nanostructure channel layers; forming a p-type metal silicide layer on the p-type source / drain region; and after forming the p-type metal silicide layer on the p-type source / drain region, forming an n-type metal silicide layer on the n-type source / drain region.

[0004] Some other embodiments of the present application provide a semiconductor device, comprising: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructured channel layers; a p-type source / drain region adjacent to the plurality of nanostructured channel layers; an n-type source / drain region adjacent to the plurality of nanostructured channel layers; a first metal silicide layer located on the p-type source / drain region and on the n-type source / drain region, wherein the first metal silicide layer comprises a first metal type; and a second metal silicide layer located on the first metal silicide layer above the p-type source / drain region and the n-type source / drain region, wherein the second metal silicide layer comprises a second metal type different from the first metal type.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructured channel layers; forming a gate structure wrapping each of the plurality of nanostructured channel layers; forming a masking layer on the p-type source / drain region; forming a first metal silicide layer on the n-type source / drain region when the masking layer protects the p-type source / drain region, wherein the first metal silicide layer comprises an n-type metal silicide; after forming the first metal silicide layer, removing the masking layer from the p-type source / drain region; and after removing the masking layer, forming a second metal silicide layer on the p-type source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a diagram of an exemplary semiconductor device described herein.

[0009] Figure 3A and Figure 3B is a diagram of an exemplary embodiment of a fin formation process described herein.

[0010] Figure 4A and Figure 4B is a diagram of an exemplary embodiment of a shallow trench isolation (STI) process described herein.

[0011] Figure 5 and Figure 6 is a diagram of an exemplary dummy gate structure formation process described herein.

[0012] FIG. 7A to FIG. 7D is a diagram of an exemplary embodiment of a source / drain recess formation process and an internal spacer formation process described herein.

[0013] Figure 8 is a diagram of an exemplary embodiment of a source / drain region formation process described herein.

[0014] Fig. 9 is a diagram of an exemplary embodiment of a process for forming an interlayer dielectric layer as described herein.

[0015] FIG. 10A to FIG. 10C is a diagram of an exemplary embodiment of a replacement gate process described herein.

[0016] FIG. 11A to FIG. 11I are diagrams of exemplary embodiments of forming semiconductor devices described herein.

[0017] FIG. 12A to FIG. 12L are diagrams of exemplary embodiments of forming semiconductor devices described herein.

[0018] FIG. 13A to FIG. 13H are diagrams of exemplary embodiments of forming semiconductor devices described herein.

[0019] FIG. 14A to FIG. 14L are diagrams of exemplary embodiments of forming semiconductor devices described herein.

[0020] Fig.15 is a diagram of exemplary components of one or more devices described herein.

[0021] Figures 16 to 18 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein. DETAILED DESCRIPTION

[0022] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0024] Before forming source / drain contacts (e.g., source / drain contacts) above the source / drain regions, a metal silicide layer can be formed on the top surface of the source / drain region (e.g., epitaxial region) of the nanostructure transistor. The metal silicide layer can be included so that a low contact resistance can be achieved between the source / drain region and the source / drain contact by adjusting the Schottky barrier height. The top surface of the source / drain region for the metal silicide can be prepared using a pre-cleaning process (e.g., epitaxial pre-cleaning process, silicide pre-cleaning process) to remove residual oxides and other contaminants. After the pre-cleaning process, a metal layer is formed above the source / drain region, and the wafer is subjected to a high temperature annealing, which causes the metal to react with the silicon to form a metal silicide layer.

[0025] The source / drain regions of the nanostructure transistor included in the semiconductor device can be doped with different types of dopants. For example, the source / drain regions of the first nanostructure transistor can be doped with p-type materials, and the source / drain regions of the second nanostructure transistor can be doped with n-type materials. Therefore, if the same type of metal silicide layer is used for two types of source / drain regions (e.g., p-type source / drain regions and n-type source / drain regions), the inherent hot ion barrier of the metal silicide layer used for the source / drain region will take precedence over either the n-type source / drain region or the p-type source / drain region, rather than both of them. This may result in different hot ion barrier characteristics for the n-type source / drain region and the p-type source / drain region, which may produce an increased contact resistance for a particular type of source / drain region.

[0026] As an example, an n-type metal silicide layer formed over the n-type source / drain regions of the first nanostructure transistor may provide a low n-type Schottky barrier height (φ ) at the junction between the n-type metal silicide layer and the n-type source / drain regions. Bn -Conduction band edge (E C ) and the Fermi level (E F ) between the n-type source / drain regions) and thus provide a low contact resistance (e.g., because the junction acts as an ohmic junction). However, the same n-type metal silicide layer over the p-type source / drain regions of the second nanostructure transistor can provide a p-type high Schottky barrier height (Φ) at the junction between the n-type metal silicide layer and the p-type source / drain regions. Bp -Valence band edge (E V ) and the Fermi level (E F ) and thus provide a high contact resistance because the junction acts as a rectifier junction (e.g., a pn junction or a diode).

[0027] Some embodiments described herein provide semiconductor manufacturing techniques and related semiconductor structures for selective double silicide formation in semiconductor devices. The techniques described herein include forming metal silicide layers of corresponding (different) types for p-type source / drain regions and n-type source / drain regions of nanostructure transistors for semiconductor devices in a selective manner that reduces process complexity. For example, a p-type metal silicide layer can be selectively formed above the p-type source / drain region of the first nanostructure transistor (e.g., so that the p-type metal silicide layer is not formed above the n-type source / drain region), and an n-type metal silicide layer can be formed above the n-type source / drain region of the second nanostructure transistor (this can be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region and a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for the p-type source / drain region and the n-type source / drain region.

[0028] Some of the selective double silicide formation techniques described herein are capable of forming a p-type metal silicide layer and an n-type metal silicide layer in situ because the operations for forming the p-type metal silicide layer and the n-type metal silicide layer are performed under the same vacuum (e.g., without breaking the vacuum between the p-type metal silicide layer formation operation and the n-type metal silicide layer formation operation). This enables the double silicide formation operation to be performed with only a single pre-cleaning operation before the p-type metal silicide layer formation operation (e.g., instead of performing a second pre-cleaning operation between the p-type metal silicide layer formation operation and the n-type metal silicide layer formation operation, a second pre-cleaning operation will be performed to clean the n-type source / drain region due to breaking the vacuum between the operations). This reduces process complexity and reduces the likelihood of dielectric damage and critical dimension increase. In addition, this enables the vacuum to be maintained so that a metal barrier layer for the p-type metal silicide layer and the n-type metal silicide layer can be formed in the same operation, which further reduces process complexity. Furthermore, the selective double silicide formation technique described herein enables precise and independent thickness control to form the p-type metal silicide layer and the n-type metal silicide layer to an optimal thickness.

[0029] Figure 1 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1As shown in , the exemplary environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among other examples.

[0030] The deposition tool 102 is a semiconductor processing tool including a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma enhanced CVD (PECVD) tool, a high density plasma CVD (HDP-CVD) tool, a sub-atmospheric pressure CVD (SACVD) tool, a low pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the deposition tool 102 includes an epitaxial tool configured to form a layer and / or region of a device by epitaxial growth. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0031] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme UV (EUV) source, etc.), an x-ray source, an electron beam (e-beam) source, etc. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0032] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0033] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, etc. In some embodiments, the etching tool 108 includes a chamber that can be filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 etches one or more portions of the substrate using plasma etching or plasma-assisted etching, which may involve using an ionized gas to isotropically or directionally etch one or more portions. In some embodiments, the etching tool 108 includes a plasma-based asher to remove photoresist material and / or another material.

[0034] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing individual layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that polishes or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 may polish or planarize the surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free grinding polishing). The planarization tool 110 may utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and level any irregular topography of the semiconductor device, making the semiconductor device flat or flat.

[0035] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion thereof with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0036] The wafer / die transporter 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead lift transport (OHT) system, an automatic material handling system (AMHS), and / or a device configured to transport substrates and / or semiconductor devices between semiconductor processing tools 102-112, to transport substrates and / or semiconductor devices between processing chambers of the same semiconductor processing tool, and / or to transport substrates and / or semiconductor devices to other locations (such as wafer racks, storage chambers, etc.) and from other locations. In some embodiments, the wafer / die transporter 114 can be a programmed device configured to travel a specific path and / or can be semi-automatically or automatically operated. In some embodiments, the exemplary environment 100 includes multiple wafer / die transporters 114.

[0037] For example, the wafer / die transporter 114 may be included in a cluster tool or another type of tool including multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between multiple processing chambers, between a processing chamber and a buffer, between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or between a processing chamber and a transport carrier (e.g., a front opening unified box (FOUP)), among other examples. In some embodiments, the wafer / die transporter 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In these embodiments, the wafer / die transport tool 114 is configured to transport substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the processing chambers and / or between processing operations in the deposition tool 102, as described herein.

[0038] As described herein, semiconductor processing tools 102-112 may perform a combination of operations to form one or more portions of a nanostructure transistor. In some embodiments, the combination of operations includes: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructure channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructure channel layers; forming a gate structure encapsulating each of the plurality of nanostructure channel layers; forming a p-type metal silicide layer on the p-type source / drain region; and / or forming an n-type metal silicide layer on the n-type source / drain region after forming the p-type metal silicide layer on the p-type source / drain region, as well as other examples.

[0039] In some embodiments, a combination of operations includes: forming a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructured channel layers; forming a gate structure wrapping each of the plurality of nanostructured channel layers; forming a masking layer on the p-type source / drain region; forming a first metal silicide layer on the n-type source / drain region when the masking layer protects the p-type source / drain region, wherein the first metal silicide layer comprises an n-type metal silicide; after forming the first metal silicide layer, removing the masking layer from the p-type source / drain region; and / or forming a second metal silicide layer on the p-type source / drain region after removing the masking layer, as well as other examples.

[0040] In some embodiments, a combination of operations includes: forming a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructured channel layers; forming a gate structure wrapping each of the plurality of nanostructured channel layers; forming a first metal silicide layer on the p-type source / drain region and on the n-type source / drain region, wherein the first metal silicide layer comprises a first metal type; and / or forming a second metal silicide layer on the first metal silicide layer above the p-type source / drain region and the n-type source / drain region, wherein the second metal silicide layer comprises a second metal type different from the first metal type, as well as other examples.

[0041] In some embodiments, the combination of operations includes combining Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6 , FIG. 7A to FIG. 7D , Figure 8 , Fig. 9 , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11I , FIG. 12A to FIG. 12L , FIG. 13A to FIG. 13H , FIG. 14A to FIG. 14L , Fig.16 , Fig.17 and / or Fig.18 One or more operations described in one or more of the embodiments, and other examples.

[0042] Figure 1 The number and arrangement of the devices shown in the figure are provided as one or more examples. In practice, there may be Figure 1 Additional devices, fewer devices, different devices, or differently arranged devices than those shown in . In addition, Figure 1 Two or more of the devices shown in FIG. 1 may be implemented in a single device, or Figure 1 A single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, a device group (eg, one or more devices) of the example environment 100 may implement one or more functions described as being implemented by another device group of the example environment 100.

[0043] Figure 2 is a diagram of an exemplary semiconductor device 200 described herein. The semiconductor device 200 includes one or more transistors. The one or more transistors may include nanostructured transistors, such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. The semiconductor device 200 may include Figure 2 One or more additional devices, structures and / or layers not shown in the drawings. For example, the semiconductor device 200 may include a Figure 2 Additional layers and / or dies on layers above and / or below the portion of the semiconductor device 200 shown in FIG. Additionally or alternatively, in the embodiment including the embodiment of FIG. Figure 2 One or more additional semiconductor structures and / or semiconductor devices are formed in the same layer of an electronic device or integrated circuit (IC) of the semiconductor device 200 shown in FIG. FIG. 3A to FIG. 12B One or more of Figure 2 1 and 2 are schematic cross-sectional views of various portions of semiconductor device 200 shown in FIG. 1 , and correspond to various processing stages for forming a nanostructure transistor of semiconductor device 200 .

[0044] The semiconductor device 200 includes a semiconductor substrate 205. The semiconductor substrate 205 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SIC) substrate, or another type of semiconductor substrate. The semiconductor substrate 205 may include various layers, including a conductive or insulating layer formed on the semiconductor substrate. The semiconductor substrate 205 may include a compound semiconductor and / or an alloy semiconductor. The semiconductor substrate 205 may include various doping configurations to meet one or more design parameters. For example, different doping profiles (e.g., n-well, p-well) may be formed on the semiconductor substrate 205 in an area designed for different device types (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistor, n-type metal oxide semiconductor (NMOS) nanostructure transistor). Suitable doping may include ion implantation and / or diffusion processes of dopants. Additionally, the semiconductor substrate 205 may include an epitaxial layer (epi layer) that may be strained for performance enhancement, and / or may have other suitable enhancement features. The semiconductor substrate 205 may include a portion of a semiconductor wafer on which other semiconductor devices are formed.

[0045] The mesa region 210 is included on (and / or extends on) the semiconductor substrate 205. The mesa region 210 provides a structure on which nanostructures of the semiconductor device 200 are formed, such as a nanostructure channel, a nanostructure gate portion of each of the nanostructure channels, and / or a sacrificial nanostructure, as well as other examples. In some embodiments, one or more mesa regions 210 are formed in and / or by a fin structure (e.g., a silicon fin structure) formed in the semiconductor substrate 205. The mesa region 210 can include the same material as the semiconductor substrate 205 and be formed by the semiconductor substrate 205. In some embodiments, the mesa region 210 is doped to form different types of nanostructure transistors, such as a p-type nanostructure transistor and / or an n-type nanostructure transistor. In some embodiments, the mesa region 210 includes a silicon (Si) material or another elemental semiconductor material such as germanium (Ge). In some embodiments, the mesa region 210 includes an alloy semiconductor material such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof.

[0046] The mesa region 210 is manufactured by suitable semiconductor process techniques, such as masking, photolithography and / or etching processes, among other examples. As an example, a fin structure can be formed by etching away a portion of the semiconductor substrate 205 to form a groove in the semiconductor substrate 205. The groove can then be filled with a recessed or etched-back isolation material to form a shallow trench isolation (STI) region 215 above the semiconductor substrate 205 and between the fin structures. Source / drain grooves can be formed in the fin structure, which allows the mesa region 210 to be formed between the source / drain grooves. However, other manufacturing techniques for the STI region 215 and / or for the mesa region 210 can be used.

[0047] The STI regions 215 may electrically isolate adjacent fin structures and may provide a layer on which other layers and / or structures of the semiconductor device 200 are formed. The STI regions 215 may include a dielectric material such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. The STI region 215 may include a multi-layer structure, for example, with one or more liner layers.

[0048] The semiconductor device 200 includes a plurality of nanostructure channels 220 extending between and electrically coupled to source / drain regions 225. The source / drain regions may be referred to as sources or drains, individually or collectively depending on the context. The nanostructure channels 220 are arranged in a direction approximately perpendicular to the semiconductor substrate 205. In other words, the nanostructure channels 220 are arranged or stacked vertically above the semiconductor substrate 205.

[0049] The nanostructure channel 220 includes a silicon-based nanostructure (e.g., a nanosheet or a nanowire, among other examples) used as a semiconductor channel of a nanostructure transistor of the semiconductor device 200. In some embodiments, the nanostructure channel 220 may include silicon germanium (SiGe) or another silicon-based material. The source / drain region 225 includes silicon (Si) with one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge, among other examples), an n-type material (e.g., phosphorus (P) or arsenic (As), among other examples), and / or another type of dopant. Thus, the semiconductor device 200 may include: a p-type metal oxide semiconductor (PMOS) nanostructure transistor including a p-type source / drain region; an n-type metal oxide semiconductor (NMOS) nanostructure transistor including an n-type source / drain region; and / or other types of nanostructure transistors.

[0050] In some embodiments, the buffer region 230 is included below the source / drain region 225, between the source / drain region 225 and the fin structure above the semiconductor substrate 205. The buffer region 230 can provide isolation between the source / drain region 225 and the adjacent mesa region 210. The buffer region 230 can be included to reduce, minimize, and / or prevent electrons from traversing into the mesa region 210 (e.g., instead of traversing the nanostructure channel 220, thereby reducing current leakage), and / or the buffer region 230 can be included to reduce, minimize, and / or prevent dopants from the source / drain region 225 into the mesa region 210 (which reduces short channel effects).

[0051] A capping layer 235 may be included above and / or on the source / drain regions 225. The capping layer 235 may include silicon, silicon germanium, doped silicon, doped silicon germanium, and / or another material. The capping layer 235 may be included to reduce dopant diffusion and protect the source / drain regions 225 during semiconductor processing operations for the semiconductor device 200 prior to contact formation. Additionally, the capping layer 235 may facilitate metal-semiconductor (e.g., silicide) alloy formation.

[0052] At least a subset of the nanostructure channels 220 extends through one or more gate structures 240. The gate structure 240 may be formed of one or more metal materials, one or more high dielectric constant (high-k) materials, and / or one or more other types of materials. In some embodiments, a dummy gate structure (e.g., a polysilicon (PO) gate structure or another type of gate structure) is formed in the location of the gate structure 240 (e.g., before its formation) so that one or more other layers and / or structures of the semiconductor device 200 may be formed before the gate structure 240 is formed. This reduces and / or prevents damage to the gate structure 240 that would otherwise be caused by the formation of one or more layers and / or structures. A replacement gate process (RGP) is then performed to remove the dummy gate structure and replace the dummy gate structure with the gate structure 240 (e.g., a replacement gate structure).

[0053] like Figure 2 As further shown in FIG. 2 , portions of gate structures 240 are formed between pairs of nanostructure channels 220 in an alternating vertical arrangement. In other words, semiconductor device 200 includes one or more vertical stacks of alternating nanostructure channels 220 and portions of gate structures 240, such as Figure 2 In this manner, gate structure 240 wraps around the associated nanostructure channel 220 on multiple sides of the nanostructure channel 220, which increases control over the nanostructure channel 220, increases the drive current of the nanostructure transistor for the semiconductor device 200, and reduces the short channel effect (SCE) of the nanostructure transistor for the semiconductor device 200.

[0054] Some source / drain regions 225 and gate structures 240 may be shared between two or more nanoscale transistors of semiconductor device 200. In these embodiments, one or more source / drain regions 225 and gate structures 240 may be connected or coupled to multiple nanostructure channels 220, such as Figure 2 This enables multiple nanostructure channels 220 to be controlled by a single gate structure 240 and source / drain region 225 pair.

[0055] An internal spacer (InSP) 245 may be included between the source / drain region 225 and an adjacent gate structure 240. In particular, the internal spacer 245 may be included between the source / drain region 225 and a portion of the gate structure 240 that wraps around the plurality of nanostructure channels 220. The internal spacer 245 is included on an end portion of the portion of the gate structure 240 that wraps around the plurality of nanostructure channels 220. The internal spacer 245 is included in a cavity formed between end portions of adjacent nanostructure channels 220. The internal spacer 245 is included to reduce parasitic capacitance and to protect the source / drain region 225 from etching during a nanosheet release operation to remove sacrificial nanosheets between the nanostructure channels 220. The internal spacer 245 includes silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SICN), silicon oxycarbonitride (SiOCN), and / or another dielectric material.

[0056] The semiconductor device 200 may also include an interlayer dielectric (ILD) layer 250 above the STI region 215. The ILD layer 250 may be referred to as an ILD0 layer. The ILD layer 250 surrounds the gate structure 240 to provide electrical isolation and / or insulation between the gate structure 240 and / or the source / drain region 225, as well as other examples. Conductive structures such as contacts and / or interconnects may be formed through the ILD layer 250 to the source / drain region 225 and the gate structure 240 to provide control of the source / drain region 225 and the gate structure 240.

[0057] As noted above, Figure 2 Provided as an example. Other examples may be related to Figure 2 The content described is different.

[0058] Figure 3A and Figure 3B is a diagram of an exemplary embodiment 300 of a fin formation process described herein. The exemplary embodiment 300 includes an example of forming a fin structure for a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include Figure 3Aand Figure 3B One or more additional devices, structures and / or layers not shown in the figure. The semiconductor device 200 may include a Figure 3A and Figure 3B Additional layers and / or dies on layers above and / or below the portion of semiconductor device 200 shown in FIG. Additionally or alternatively, one or more additional semiconductor structures and / or semiconductor devices may be formed in the same layer of an electronic device including semiconductor device 200 .

[0059] Figure 3A 1 shows a perspective view of the semiconductor device 200 and a cross-sectional view along line AA in the perspective view. Figure 3A As shown in , processing of the semiconductor device 200 is performed in conjunction with the semiconductor substrate 205. A layer stack 305 is formed on the semiconductor substrate 205. The layer stack 305 can be referred to as a superlattice. In some embodiments, before forming the layer stack 305, one or more operations are performed in conjunction with the semiconductor substrate 205. For example, an anti-punch-through (APT) implant operation can be performed. The APT implant operation can be performed in one or more regions of the semiconductor substrate 205 on which the nanostructure channel 220 will be formed. The APT implant operation is performed, for example, to reduce and / or prevent punch-through or undesired diffusion into the semiconductor substrate 205.

[0060] The layer stack 305 includes a plurality of alternating layers arranged in a direction approximately perpendicular to the semiconductor substrate 205. For example, the layer stack 305 includes vertically alternating layers of a first layer 310 and a second layer 315 above the semiconductor substrate 205. Figure 3A The number of first layers 310 and the number of second layers 315 shown in are examples, and other numbers of first layers 310 and second layers 315 are within the scope of the presently disclosed embodiments. In some embodiments, the first layer 310 and the second layer 315 are formed to different thicknesses. For example, the second layer 315 can be formed to a thickness greater than the thickness of the first layer 310. In some embodiments, the first layer 310 (or a subset thereof) is formed to a thickness in the range of about 4 nanometers to about 7 nanometers. In some embodiments, the second layer 315 (or a subset thereof) is formed to a thickness in the range of about 8 nanometers to about 12 nanometers. However, other values ​​for the thickness of the first layer 310 and for the thickness of the second layer 315 are within the scope of the presently disclosed embodiments.

[0061] The first layer 310 includes a first material composition, and the second layer 315 includes a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. As an example, the first layer 310 may include silicon germanium (SiGe), and the second layer 315 may include silicon (Si). In some embodiments, the first material composition and the second material composition have different oxidation rates and / or etching selectivities.

[0062] As described herein, the second layer 315 may be processed to form a nanostructure channel 220 for a subsequently formed nanostructure transistor of the semiconductor device 200. The first layer 310 is a sacrificial nanostructure that is ultimately removed and is used to define a vertical distance between adjacent nanostructure channels 220 for a subsequently formed gate structure 240 of the semiconductor device 200. Therefore, the first layer 310 is referred to herein as a sacrificial layer, and the second layer 315 may be referred to as a channel layer.

[0063] The deposition tool 102 deposits and / or grows alternating layers of the layer stack 305 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 205. For example, the deposition tool 102 grows the alternating layers by epitaxial growth. However, other processes may be used to form the alternating layers of the layer stack 305. The epitaxial growth of the alternating layers of the layer stack 305 may be implemented by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or another suitable epitaxial growth process. In some embodiments, the epitaxially grown layers such as the second layer 315 include the same material as the material of the semiconductor substrate 205. In some embodiments, the first layer 310 and / or the second layer 315 include a material different from the material of the semiconductor substrate 205. As described above, in some embodiments, the first layer 310 includes an epitaxially grown silicon germanium (SiGe) layer, and the second layer 315 includes an epitaxially grown silicon (Si) layer. Alternatively, the first layer 310 and / or the second layer 315 may include: other materials, such as germanium (Ge); compound semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (IAs), indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP); and / or combinations thereof. The material of the first layer 310 and / or the material of the second layer 315 may be selected based on providing different oxidation characteristics, different etching selectivity characteristics, and / or other different characteristics.

[0064] like Figure 3A As further shown in , the deposition tool 102 can form one or more additional layers above and / or on the layer stack 305. For example, a hard mask (HM) layer 320 can be formed above and / or on the layer stack 305 (e.g., on the topmost second layer 315 of the layer stack 305). As another example, a capping layer 325 can be formed above and / or on the hard mask layer 320. As another example, another hard mask layer including an oxide layer 330 and a nitride layer 335 can be formed above and / or on the capping layer 325. One or more hard mask (HM) layers 320, 330, and 335 can be used to form one or more structures of the semiconductor device 200. The oxide layer 330 can be used as an adhesion layer between the layer stack 305 and the nitride layer 335, and can be used as an etch stop layer for etching the nitride layer 335. The one or more hard mask layers 320, 330, and 335 can include silicon germanium (SiGe), silicon nitride (Si x N y ), silicon oxide (SiO x ) and / or another material. The capping layer 325 may include silicon (Si) and / or another material. In some embodiments, the capping layer 325 is formed of the same material as the semiconductor substrate 205. In some embodiments, one or more additional layers are thermally grown, deposited by CVD, PVD, ALD, and / or formed using another deposition technique.

[0065] Figure 3B 2 shows a perspective view of the semiconductor device 200 and a cross-sectional view along line AA. Figure 3B As shown in , the layer stack 305 and the semiconductor substrate 205 are etched to remove portions of the layer stack 305 and portions of the semiconductor substrate 205. The portion 340 of the layer stack 305 and the mesa region 210 (also referred to as a silicon mesa or mesa portion) remaining after the etching operation is referred to as a fin structure 345 above the semiconductor substrate 205 of the semiconductor device 200. The fin structure 345 includes a portion 340 of the layer stack 305 located above and / or on the mesa region 210 formed in and / or on the semiconductor substrate 205. The fin structure 345 can be formed by any suitable semiconductor processing technology. For example, the deposition tool 102, the exposure tool 104, the development tool 106, and / or the etching tool 108 can use one or more lithography processes including double patterning or multiple patterning processes to form the fin structure 345. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct lithography process. For example, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers may be formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer may then be removed, and the remaining spacers may then be used to pattern the fin structure.

[0066] In some embodiments, deposition tool 102 forms a photoresist layer above and / or on the hard mask layer including oxide layer 330 and nitride layer 335, exposure tool 104 exposes the photoresist layer to radiation (e.g., deep ultraviolet (UV) radiation, extreme UV (EUV) radiation), performs a post-exposure bake process (e.g., to remove residual solvent from the photoresist layer), and development tool 106 develops the photoresist layer to form a masking element (or pattern) in the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process is used to perform patterning of the photoresist layer to form the masking element. The masking element can then be used to protect portions of semiconductor substrate 205 and portions of layer stack 305 during an etching operation, so that portions of semiconductor substrate 205 and portions of layer stack 305 remain unetched to form fin structure 345. The unprotected portions of the substrate and the unprotected portions of the layer stack 305 are etched (e.g., by etching tool 108) to form trenches in semiconductor substrate 205. The etching tool may etch the unprotected portions of the substrate and the unprotected portions of the layer stack 305 using dry etching techniques (eg, reactive ion etching), wet etching techniques, and / or combinations thereof.

[0067] In some embodiments, another fin formation technique is used to form the fin structure 345. For example, the fin region can be defined (e.g., by a mask or isolation region), and the portion 340 can be epitaxially grown in the form of the fin structure 345. In some embodiments, forming the fin structure 345 includes a trimming process to reduce the width of the fin structure 345. The trimming process can include wet and / or dry etching processes, among other examples.

[0068] like Figure 3B As further shown in FIG. 2 , the fin structures 345 may be formed into different types of nanostructure transistors for the semiconductor device 200. In particular, a first subset of fin structures 345a may be formed for a p-type nanostructure transistor (e.g., a p-type metal oxide semiconductor (PMOS) nanostructure transistor), and a second subset of fin structures 345b may be formed for an n-type nanostructure transistor (e.g., an n-type metal oxide semiconductor (NMOS) nanostructure transistor). The second subset of fin structures 345b may be doped with a p-type dopant (e.g., boron (B) and / or germanium (Ge), among other examples), and the first subset of fin structures 345a may be doped with an n-type dopant (e.g., phosphorus (P) and / or arsenic (As), among other examples). Additionally or alternatively, a p-type source / drain region may be subsequently formed for the p-type nanostructure transistor including the first subset of fin structures 345a, and an n-type source / drain region may be subsequently formed for the n-type nanostructure transistor including the second subset of fin structures 345b.

[0069] The first subset of fin structures 345a (e.g., PMOS fin structures) and the second subset of fin structures 345b (e.g., NMOS fin structures) can be formed to include similar characteristics and / or different characteristics. For example, the first subset of fin structures 345a can be formed to a first height and the second subset of fin structures 345b can be formed to a second height, wherein the first height and the second height are different heights. As another example, the first subset of fin structures 345a can be formed to a first width and the second subset of fin structures 345b can be formed to a second width, wherein the first width and the second width are different widths. Figure 3B In the example shown in , the second width of the second fin structure subset 345b (eg, for NMOS nanostructure transistors) is greater relative to the first width of the first fin structure subset 345b (eg, for PMOS nanostructure transistors). However, other examples are within the scope of the disclosed embodiments.

[0070] As noted above, Figure 3A and Figure 3B Provided as an example. Other examples may be related to Figure 3A and Figure 3B The exemplary embodiment 300 may include a combination of Figure 3A and Figure 3B Additional operations, fewer operations, different operations, and / or a different order of operations than those described.

[0071] Figure 4A and Figure 4B is a diagram of an exemplary embodiment 400 of an STI formation process described herein. The exemplary embodiment 400 includes an example of forming an STI region 215 between fin structures 345 for a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include Figure 4A and / or Figure 4B One or more additional devices, structures and / or layers not shown in the figure. The semiconductor device 200 may include a Figure 4A and Figure 4B In some embodiments, the operations described in conjunction with exemplary embodiment 400 are performed in conjunction with the semiconductor device 200. Figure 3A and Figure 3B The described process is then carried out.

[0072] Figure 4A 2 shows a perspective view of the semiconductor device 200 and a cross-sectional view along line AA. Figure 4AAs shown in FIG. 1 , a liner 405 and a dielectric layer 410 are formed between (e.g., between) the fin structures 345 over the semiconductor substrate 205. The deposition tool 102 may deposit the liner 405 and the dielectric layer 410 in the trenches over the semiconductor substrate 205 and between the fin structures 345. The deposition tool 102 may form the dielectric layer 410 such that a height of a top surface of the dielectric layer 410 and a height of a top surface of the nitride layer 335 are approximately the same height.

[0073] Optionally, the deposition tool 102 may form the dielectric layer 410 such that the height of the top surface of the dielectric layer 410 is greater relative to the height of the top surface of the nitride layer 335, such as Figure 4A . In this way, the trenches between the fin structures 345 are overfilled with the dielectric layer 410 to ensure that the trenches are completely filled with the dielectric layer 410. Subsequently, the planarization tool 110 may perform a planarization or polishing operation (e.g., a CMP operation) to planarize the dielectric layer 410. The nitride layer 335 of the hard mask layer may be used as a CMP stop layer in the operation. In other words, the planarization tool 110 planarizes the dielectric layer 410 until the nitride layer 335 of the hard mask layer is reached. Therefore, after the operation, the height of the top surface of the dielectric layer 410 and the height of the top surface of the nitride layer 335 are approximately equal.

[0074] The deposition tool 102 may use a conformal deposition technique to deposit the liner 405. The deposition tool 102 may use a CVD technique (e.g., a flowable CVD (FCVD) technique or another CVD technique), a PVD technique, an ALD technique, and / or another deposition technique to deposit the dielectric layer. In some embodiments, after depositing the liner 405, the semiconductor device 200 is annealed, for example, to improve the quality of the liner 405.

[0075] The liner 405 and the dielectric layer 410 each include a dielectric material such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material. In some embodiments, the dielectric layer 410 may include a multi-layer structure, for example, with one or more liner layers.

[0076] Figure 4B 2 shows a perspective view of the semiconductor device 200 and a cross-sectional view along line AA. Figure 4BAs shown in , an etch-back operation is performed to remove a portion of the liner 405 and a portion of the dielectric layer 410 to form the STI region 215. The etching tool 108 can etch the liner 405 and the dielectric layer 410 in the etch-back operation to form the STI region 215. The etching tool 108 etches the liner 405 and the dielectric layer 410 based on the hard mask layer (e.g., the hard mask layer including the oxide layer 330 and the nitride layer 335). The etching tool 108 etches the liner 405 and the dielectric layer 410 so that the height of the STI region 215 is less than the bottom of the portion 340 of the layer stack 305 or is about the same height as the bottom of the portion 340 of the layer stack 305. Therefore, the portion 340 of the layer stack 305 extends above the STI region 215. In some embodiments, the liner 405 and the dielectric layer 410 are etched so that the height of the STI region 215 is less than the height of the top surface of the mesa region 210.

[0077] In some embodiments, the etching tool 108 uses a dry etching technique to etch the liner 405 and the dielectric layer 410. Ammonia (NH3), hydrofluoric acid (HF), and / or another etchant may be used. The plasma-based dry etching technique may produce a reaction between the etchant and the material of the liner 405 and the dielectric layer 410, including:

[0078] SiO2+4HF→SiF4+2H2O

[0079] The silicon dioxide (SiO2) of the liner 405 and the dielectric layer 410 reacts with the hydrofluoric acid to form byproducts including silicon tetrafluoride (SiF4) and water (H2O). The silicon tetrafluoride is further decomposed by the hydrofluoric acid and ammonia to form ammonium fluorosilicate ((NH4)2SiF6) byproduct:

[0080] SiF4+2HF+2NH3→(NH4)2SiF6

[0081] The ammonium fluorosilicate byproduct is removed from the process chamber of the etch tool 108. After the ammonium fluorosilicate is removed, the ammonium fluorosilicate is sublimated to components of ammonium tetrafluoride and hydrofluoric acid using a post-process temperature in the range of about 100 degrees Celsius to about 250 degrees Celsius.

[0082] In some embodiments, the etching tool 108 etches the liner 405 and the dielectric layer 410 so that the height of the STI region 215 between the first subset of fin structures 345a (e.g., for a PMOS nanostructure transistor) is greater relative to the height of the STI region 215 between the second subset of fin structures 345b (e.g., for an NMOS nanostructure transistor). This occurs primarily due to the greater width of the fin structure 345b relative to the width of the fin structure 345a. In addition, this causes the top surface of the STI region 215 between the fin structure 345a and the fin structure 345b to be tilted or skewed (e.g., tilted downward from the fin structure 345a to the fin structure 345b, as shown in FIG. 1 ). Figure 4B 405 and the dielectric layer 410). Due to the van der Waals forces between the etchant and the surfaces of the liner 405 and the dielectric layer 410, the etchant used to etch the liner 405 and the dielectric layer 410 first undergoes physical adsorption (e.g., physical bonding to the liner 405 and the dielectric layer 410). The etchant is captured by the dipole motion force. The etchant then attaches to the dangling bonds of the liner 405 and the dielectric layer 410, and chemical adsorption begins. Here, chemical adsorption of the etchant on the surface of the liner 405 and the dielectric layer 410 produces etching of the liner 405 and the dielectric layer 410. The greater width of the trench between the second fin structure subset 345a provides a larger surface area for chemical adsorption to occur, which produces a greater etching rate between the second fin structure subset 345b. The greater etching rate makes the height of the STI region 215 between the second fin structure subset 345b smaller relative to the height of the STI region 215 between the first fin structure subset 345a.

[0083] As noted above, Figure 4A and Figure 4B Provided as an example. Other examples may be related to Figure 4A and Figure 4B The exemplary embodiment 400 may include a combination of Figure 4A and Figure 4B Additional operations, fewer operations, different operations, and / or a different order of operations than those described.

[0084] Figure 5 is a diagram of an exemplary embodiment 500 of a dummy gate formation process described herein. The exemplary embodiment 500 includes an example of forming a dummy gate structure for a semiconductor device 200 or a portion thereof. The semiconductor device 200 may include Figure 5 One or more additional devices, structures and / or layers not shown in the figure. The semiconductor device 200 may include a Figure 5In some embodiments, the operations described in conjunction with exemplary embodiment 500 are performed in conjunction with the semiconductor device 200. FIG. 3A to FIG. 4B The described process is then carried out.

[0085] Figure 5 FIG. 2 shows a perspective view of a semiconductor device 200. Figure 5 As shown in , a dummy gate structure 505 (also referred to as a dummy gate stack or temporary gate structure) is formed over the fin structure 345. The dummy gate structure 505 is a sacrificial structure that will be replaced by a replacement gate structure or replacement gate stack (e.g., gate structure 240) at a subsequent processing stage for the semiconductor device 200. The portion of the fin structure 345 that is located below the dummy gate structure 505 can be referred to as a channel region. The dummy gate structure 505 can also define a source / drain (S / D) region of the fin structure 345, such as a region of the fin structure 345 that is adjacent to the channel region and located on opposite sides of the channel region.

[0086] The dummy gate structure 505 may include a gate electrode layer 510, a hard mask layer 515 located above and / or on the gate electrode layer 510, and a spacer layer 520 located on opposite sides of the gate electrode layer 510 and on opposite sides of the hard mask layer 515. The dummy gate structure 505 may be formed on a gate dielectric layer 525 between the topmost second layer 315 and the dummy gate structure 505. The gate electrode layer 510 includes polycrystalline silicon (polysilicon or PO) or another material. The hard mask layer 515 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or another material) and a nitride layer formed above the oxide layer (e.g., a pad nitride layer that may include silicon nitride such as Si3N4 or another material). The spacer layer 520 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable material. The gate dielectric layer 525 may include silicon oxide (e.g., SiO x , such as SiO2), silicon nitride (e.g., Si x N y , such as Si3N4), high-K dielectric material and / or another suitable material.

[0087] The layers of the dummy gate structure 505 can be formed using various semiconductor processing techniques, such as deposition (e.g., by deposition tool 102), patterning (e.g., by exposure tool 104 and development tool 106), and / or etching (e.g., by etching tool 108), among other examples. Examples include CVD, PVD, ALD, thermal oxidation, e-beam evaporation, photolithography, e-beam lithography, photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), dry etching (e.g., reactive ion etching), and / or wet etching, among other examples.

[0088] In some embodiments, the gate dielectric layer 525 is conformally deposited on the semiconductor device 200 and then selectively removed from a portion (e.g., source / drain region) of the semiconductor device 200. Then, the gate electrode layer 510 is deposited on the remaining portion of the gate dielectric layer 525. Then, the hard mask layer 515 is deposited on the gate electrode layer 510. The spacer layer 520 can be conformally deposited in a manner similar to the gate dielectric layer 525, and etched back so that the spacer layer 520 remains on the sidewall of the dummy gate structure 505. In some embodiments, the spacer layer 520 includes multiple types of spacer layers. For example, the spacer layer 520 can include a sealing spacer layer formed on the sidewall of the dummy gate structure 505 and a block spacer layer formed on the sealing spacer layer. The sealing spacer layer and the block spacer layer can be formed of similar materials or different materials. In some embodiments, the block spacer layer is formed without a plasma surface treatment for the sealing spacer layer. In some embodiments, the bulk spacer layer is formed to a greater thickness relative to the thickness of the encapsulation spacer layer. In some embodiments, the gate dielectric layer 525 is omitted from the dummy gate structure formation process and is instead formed in a replacement gate process.

[0089] Figure 5 Reference cross sections used in subsequent figures described herein are shown. Cross section AA is located in an xz plane (referred to as a y-cut) across the fin structure 345 in the source / drain region of the semiconductor device 200. Cross section BB is located in a yz plane (referred to as an x-cut) perpendicular to cross section AA and across the dummy gate structure 505 in the source / drain region of the semiconductor device 200. Cross section CC is located in an xz plane parallel to cross section AA and perpendicular to cross section BB and along the dummy gate structure 505. For clarity, subsequent figures refer to these reference cross sections. In some figures, for ease of depiction of the figures, some reference numerals of components or parts shown therein may be omitted to avoid obscuring other components or parts.

[0090] As noted above, Figure 5 Provided as an example. Other examples may be related to Figure 5 The exemplary embodiment 500 may include a combination of Figure 5 Additional operations, fewer operations, different operations, and / or a different order of operations than those described.

[0091] Figure 6 is a diagram of an exemplary implementation 600 of a semiconductor device 200 described herein. Figure 6 Including along Figure 5 The cross-sectional views of the cross-sectional planes AA, BB and CC. Figure 6 As shown in cross-sectional planes BB and CC in FIG. 1 , a dummy gate structure 505 is formed on the fin structure 345. Figure 6 As shown in cross-sectional plane CC in FIG. 3 , portions of the gate dielectric layer 525 and portions of the gate electrode layer 510 are formed in recesses formed over the fin structure 345 due to the removal of the hard mask layer 320 .

[0092] As noted above, Figure 6 Provided as an example. Other examples may be related to Figure 6 The exemplary embodiment 600 may include a combination of Figure 6 Additional operations, fewer operations, different operations, and / or a different order of operations than those described.

[0093] FIG. 7A to FIG. 7D is a diagram of an exemplary embodiment 700 of a source / drain recess formation process and an internal spacer formation process described herein. The exemplary embodiment 700 includes an example of forming source / drain recesses and internal spacers 245 for the semiconductor device 200. FIG. 7A to FIG. 7D is from Figure 5 The multiple viewing angles shown in FIG. 1 include Figure 5 The perspective of the cross-sectional plane AA in Figure 5 The viewing angle of the cross-sectional plane BB in Figure 5 In some embodiments, the operations described in conjunction with exemplary embodiment 700 are combined with Figures 3A to 6 The described process is then carried out.

[0094] like Fig. 7AAs shown in the cross-sectional plane AA and the cross-sectional plane BB in FIG. 1 , in the etching operation, a source / drain recess 705 is formed in the portion 340 of the fin structure 345. The source / drain recess 705 is formed to provide a space where the source / drain region 225 will be formed on the opposite side of the dummy gate structure 505. The etching operation can be performed by the etching tool 108 and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique.

[0095] In some embodiments, the source / drain recess 705 also extends into a portion of the mesa region 210 of the fin structure 345. In these embodiments, the source / drain recess 705 can penetrate into a well portion (e.g., a p-well, an n-well) of the fin structure 345. In an embodiment in which the semiconductor substrate 205 includes a silicon (Si) material having a (100) orientation, a (111) face is formed at the bottom of the source / drain recess 705, so that a V-shaped or triangular cross-section is formed at the bottom of the source / drain recess 705. In some embodiments, a wet etch using tetramethylammonium hydroxide (TMAH) and / or a chemical dry etch using hydrochloric acid (HCl) is used to form the V-shaped profile. However, the cross-section at the bottom of the source / drain recess 705 may include other shapes, such as a circle or a semicircle, as well as other examples.

[0096] like Fig. 7A As shown in cross-sectional plane BB and cross-sectional plane CC in FIG. 5 , after the etching operation to form the source / drain recesses 705, a portion of the first layer 310 and a portion of the second layer 315 of the layer stack 305 remain below the dummy gate structure 505. The portion of the second layer 315 located below the dummy gate structure 505 forms a nanostructure channel 220 of the nanostructure transistor of the semiconductor device 200. The nanostructure channel 220 extends between adjacent source / drain recesses 705.

[0097] like Figure 7BAs shown in cross-sectional plane BB in FIG. 1 , during the etching operation, the first layer 310 is laterally etched (e.g., in a direction approximately parallel to the length of the first layer 310) to form a cavity 710 between portions of the nanostructure channel 220. In particular, the etching tool 108 laterally etches the ends of the first layer 310 located below the dummy gate structure 505 through the source / drain recesses 705 to form the cavity 710 between the ends of the nanostructure channel 220. In an embodiment where the first layer 310 is silicon germanium (SiGe) and the second layer 315 is silicon (Si), the etching tool 108 can selectively etch the first layer 310 using a wet etchant such as a mixed solution including hydrogen peroxide (H2O2), acetic acid (CH3COOH) and / or hydrogen fluoride (HF), followed by cleaning with water (H2O). The mixed solution and water can be provided into the source / drain recesses 705 to etch the first layer 310 from the source / drain recesses 705. In some embodiments, etching by the mixed solution and cleaning by water are repeated about 10 to about 20 times. In some embodiments, the etching time by the mixed solution is in the range of from about 1 minute to about 2 minutes. The mixed solution can be used at a temperature in the range of about 60° C. to about 90° C. However, other values ​​of the parameters for the etching operation are within the scope of the disclosed embodiments.

[0098] The cavity 710 can be formed into an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or into another shape. In some embodiments, the depth of one or more of the cavities 710 (e.g., the size of the cavity extending from the source / drain recess 705 to the first layer 310) is in the range of about 0.5 nanometers to about 5 nanometers. In some embodiments, the depth of one or more of the cavities 710 is in the range of about 1 nanometer to about 3 nanometers. However, other values ​​for the depth of the cavity 710 are within the scope of the disclosed embodiments. In some embodiments, the etching tool 108 forms the cavity 710 to a length (e.g., the size of the cavity extending from the nanostructure channel 220 below the first layer 310 to another nanostructure channel 220 above the first layer 310) so that the cavity 710 partially extends into the side of the nanostructure channel 220 (e.g., so that the width or length of the cavity 710 is greater than the thickness of the first layer 310). In this way, the internal spacer formed in the cavity 710 can extend into the portion of the end of the nanostructure channel 220.

[0099] like Figure 7CAs shown in the cross-sectional plane AA and the cross-sectional plane BB in FIG. 7 , an insulating layer 715 is conformally deposited along the bottom and sidewalls of the source / drain recess 705. The insulating layer 715 further extends along the spacer layer 520. The deposition tool 102 can deposit the insulating layer 715 using a CVD technique, a PVD technique, and an ALD technique or / and another deposition technique. The insulating layer 715 includes silicon nitride (Si x N y ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SICN), silicon oxycarbon nitride (SiOCN), and / or another dielectric material. The insulating layer 715 may include a material different from that of the spacer layer 520 .

[0100] The deposition tool 102 forms the insulating layer 715 to a thickness sufficient to fill the cavity 710 between the nanostructure channels 220 with the insulating layer 715. For example, the insulating layer 715 can be formed to a thickness in a range of about 1 nanometer to about 10 nanometers. As another example, the insulating layer 715 can be formed to a thickness in a range of about 2 nanometers to about 5 nanometers. However, other values ​​for the thickness of the insulating layer 715 are within the scope of the disclosed embodiments.

[0101] like Fig.7D As shown in the cross-sectional plane AA in FIG. 7 and in the cross-sectional plane BB in FIG. 7 , the insulating layer 715 is partially removed such that the remaining portion of the insulating layer 715 corresponds to the internal spacer 245 in the cavity 710 . The etching tool 108 may perform an etching operation to partially remove the insulating layer 715 .

[0102] In some embodiments, the etching operation can cause the surface of the internal spacer 245 facing the source / drain recess 705 to be curved or concave. The depth of the recess in the internal spacer 245 can be in the range of about 0.2 nanometers to about 3 nanometers. As another example, the depth of the recess in the internal spacer 245 can be in the range of about 0.5 nanometers to about 2 nanometers. As another example, the depth of the recess in the internal spacer 245 can be in the range of less than about 0.5 nanometers. In some embodiments, the surface of the internal spacer 245 facing the source / drain recess 705 is approximately flat, so that the surface of the internal spacer 245 and the surface of the end of the nanostructure channel 220 are approximately flat and flush.

[0103] As noted above, FIG. 7A to FIG. 7D Provided as an example. Other examples may be related to FIG. 7A to FIG. 7D The exemplary embodiment 700 may include a FIG. 7A to FIG. 7D Additional operations, fewer operations, different operations, and / or a different order of operations than those described.

[0104] Figure 8 is a diagram of an exemplary embodiment 800 of a source / drain region formation process described herein. Exemplary embodiment 800 includes an example of forming source / drain regions 225 in source / drain recesses 705 for semiconductor device 200. In particular, exemplary embodiment 800 includes an example of forming p-type source / drain regions 225a for a PMOS nanostructure transistor (e.g., a PMOS field effect transistor (PFET)) of semiconductor device 200 and n-type source / drain regions 225b for an NMOS nanostructure transistor (e.g., an NMOS field effect transistor (NFET)) of semiconductor device 200.

[0105] Figure 8 is from Figure 5 The multiple viewing angles shown in FIG. 1 include Figure 5 The perspective of the cross-sectional plane AA in Figure 5 The viewing angle of the cross-sectional plane BB in Figure 5 In some embodiments, the operations described in conjunction with exemplary embodiment 800 are combined with FIG. 3A to FIG. 7D The described process is then carried out.

[0106] like Figure 8 , the source / drain recess 705 is filled with one or more layers to form the source / drain region 225 in the source / drain recess 705. For example, the deposition tool 102 may deposit the buffer region 230 at the bottom of the source / drain recess 705, the deposition tool 102 may deposit the source / drain region 225 on the buffer region 230, and the deposition tool 102 may deposit a contact etch stop layer (CESL) 805 on the source / drain region 225. In some embodiments, before forming the CESL 805, a capping layer 235 (not shown) is deposited on the source / drain region 225.

[0107] The buffer region 230 may include silicon (Si), silicon doped with boron (SiB) or another dopant, and / or another material. The buffer region 230 may be included to reduce, minimize, and / or prevent dopants from migrating from the source / drain region 225 into the mesa region 210 and / or current from the source / drain region 225 into the mesa region 210, which may otherwise cause short channel effects in the semiconductor device 200. Therefore, the buffer region 230 may improve the performance of the semiconductor device 200 and / or improve the yield of the semiconductor device 200. In some embodiments, the buffer region 230 is omitted from one or more of the source / drain regions 225.

[0108] The source / drain region 225 may include one or more layers of epitaxially grown material. For example, the deposition tool 102 may epitaxially grow a first layer (referred to as L1) of the source / drain region 225 above the buffer region 230, and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 225 above the first layer. The p-type source / drain region 225a may include a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe)) doped with a p-type dopant, such as boron (B) (e.g., boron-doped silicon (SiB) and / or boron-doped silicon germanium (SiGeB), among other examples). Additionally and / or optionally, the p-type source / drain region 225a may include silicon germanium (SiGe). The n-type source / drain regions 225 b may include undoped silicon (Si) and / or silicon doped with n-type dopants such as phosphorus (P) (eg, phosphorus-doped silicon (SiP)) and / or arsenic (As) (arsenic-doped silicon (SiAs)), among other examples.

[0109] In some embodiments, before forming the ILD layer 250, the CESL 805 is conformally deposited over the source / drain regions 225 (including the p-type source / drain regions 225a and the n-type source / drain regions 225b) (e.g., using the deposition tool 102). Then, the ILD layer 250 is formed on the CESL 805. When forming contacts or vias for the source / drain regions 225, the CESL 805 can provide a mechanism to stop the etching process. The CESL 805 can be formed of a dielectric material having a different etching selectivity relative to adjacent layers or components. The CESL 805 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. In addition, the CESL 805 may include or may be silicon nitride (SiN). x N y ), silicon carbonitride (SICN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SICO), or combinations thereof, among other examples. CESL 805 may be deposited using a deposition technique such as ALD, CVD, or another deposition technique.

[0110] As noted above, Figure 8 Provided as an example. Other examples may be related to Figure 8 The exemplary embodiment 800 may include a Figure 8 Additional operations, fewer operations, different operations, and / or a different order of operations than those described.

[0111] Fig. 9 is a diagram of an exemplary embodiment 900 of an ILD formation process described herein. Fig. 9 is from Figure 5The multiple viewing angles shown in FIG. 1 include Figure 5 The perspective of the cross-sectional plane AA in Figure 5 The viewing angle of the cross-sectional plane BB in Figure 5 In some embodiments, the operations described in conjunction with exemplary embodiment 900 are combined with FIG. 3A to FIG. 8 The described operations are then performed.

[0112] like Fig. 9 As shown in the cross-sectional plane AA and the cross-sectional plane BB in FIG. , the ILD layer 250 is formed above the source / drain region 225 (including the p-type source / drain region 225a and the n-type source / drain region 225b). In particular, the ILD layer 250 can be formed on the CESL 805 located above the source / drain region 225 (including the p-type source / drain region 225a and the n-type source / drain region 225b). The ILD layer 250 fills the region between the dummy gate structures 505 and the region above the source / drain region 225. The ILD layer 250 is formed to reduce the possibility of damage to the source / drain region 225 and / or prevent damage to the source / drain region 225 during the replacement gate process. The ILD layer 250 can be referred to as an ILD zero (ILD0) layer or another ILD layer.

[0113] Deposition tool 102 may be used to utilize PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combinations of Figure 1 The ILD layer 250 may be deposited in one or more deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the ILD layer 250 after the ILD layer 250 is deposited.

[0114] As noted above, Fig. 9 The number and arrangement of operations and devices shown in the figure are provided as one or more examples. In practice, there may be Fig. 9 Additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown in .

[0115] FIG. 10A to FIG. 10C is a diagram of an exemplary embodiment 1000 of a replacement gate (RPG) process described herein. Exemplary embodiment 1000 includes an example of a replacement gate process for replacing a dummy gate structure 505 with a gate structure 240 (eg, a replacement gate structure) of a semiconductor device 200 . FIG. 10A to FIG. 10C is from Figure 5 The multiple viewing angles shown in FIG. 1 include Figure 5 The perspective of the cross-sectional plane AA in Figure 5The viewing angle of the cross-sectional plane BB in Figure 5 In some embodiments, the operations described in conjunction with exemplary embodiment 1000 are combined with FIG. 3A to FIG. 9 The described operations are then performed.

[0116] like Fig. 10A , a replacement gate operation is performed (e.g., by one or more of the semiconductor processing tools 102-112) to remove the dummy gate structure 505 from the semiconductor device 200. The removal of the dummy gate structure 505 leaves an opening (or recess) 1005 between the ILD layer 250 above the source / drain regions 225. The dummy gate structure 505 may be removed in one or more etching operations. Such etching operations may include a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique.

[0117] like Fig. 10B As shown in cross-sectional plane BB and cross-sectional plane CC in FIG. 1 , a nanostructure release operation (e.g., a SiGe release operation) is performed to remove the first layer 310 (e.g., a silicon germanium layer). This creates an opening 1005 between the nanostructure channels 220 (e.g., a region around the nanostructure channels 220). The nanostructure release operation may include an etching tool 108 performing an etching operation to remove the first layer 310 based on a difference in etching selectivity between the material of the first layer 310 and the material of the nanostructure channels 220 and between the material of the first layer 310 and the material of the internal spacer 245. The internal spacer 245 may be used as an etch stop layer in the etching operation to protect the source / drain region 225 from etching.

[0118] like Fig. 10C, the replacement gate operation continues, wherein the deposition tool 102 and / or the plating tool 112 forms a gate structure (e.g., a replacement gate structure) 240 in the opening 1005 between the source / drain regions 225. In particular, the gate structure 240 fills the area previously occupied by the first layer 310 between and around the nanostructure channels 220, such that the gate structure 240 wraps around the nanostructure channels 220 and surrounds the nanostructure channels 220 on at least three sides of the nanostructure channels 220. In some embodiments, the gate structure 240 completely wraps around the nanostructure channels 220 and wraps around the nanostructure channels 220 on all four sides of the nanostructure channels 220. The gate structure 240 may include a metal gate structure. Prior to forming the gate structure 240, a conformal high-k dielectric liner 1010 may be deposited on and on the sidewalls of the nanostructure channels 220. The high-k dielectric liner 1010 may be a gate dielectric layer between the gate structure 240 and the nanostructure channel 220. The gate structure 240 may include additional layers, such as an interfacial layer, a work function adjustment layer, and / or a metal electrode structure, among other examples.

[0119] The high-k dielectric liner 1010 may include one or more high-k materials (eg, dielectric materials having a dielectric constant greater than that of silicon dioxide (SiO2 - dielectric constant of approximately 3.9)). Examples include lanthanum oxide (LaO x ), hafnium oxide (HfO x ) and / or aluminum oxide (Al x O y ), and other examples. The gate structure 240 includes one or more metal materials, such as ruthenium (Ru), tungsten (W), cobalt (Co), copper (Cu), and / or molybdenum (Mo), and other examples. In some embodiments, a glue layer is included between the high-k dielectric layer 1010 and the gate structure 240 to promote adhesion between the high-k dielectric liner 1010 and the gate structure 240. Examples of materials for the glue layer may include tantalum nitride (TaN), titanium nitride (TiN), and / or another suitable glue layer material.

[0120] As noted above, FIG. 10A to FIG. 10C The number and arrangement of operations and devices shown in the figure are provided as one or more examples. In practice, there may be FIG. 10A to FIG. 10C Additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown in .

[0121] FIG. 11A to FIG. 11I is a diagram of an exemplary embodiment 1100 of forming an active area isolation structure described herein. FIG. 11A to FIG. 11I One or more of the Figure 5 One or more perspectives shown, including Figure 5 4. The perspective of the cross-sectional plane AA in FIG. 2 (eg, across the plurality of source / drain regions 225 adjacent to the sidewalls of the gate structure 240 in the x-direction) is shown.

[0122] Exemplary embodiment 1100 includes an example of selectively forming a p-type metal silicide layer on p-type source / drain regions 225a of semiconductor device 200. The p-type metal silicide layer may be selectively formed on the p-type source / drain regions because one or more p-type metals are deposited on the p-type source / drain regions and annealed to react with materials of the p-type source / drain regions, wherein the one or more p-type metals do not react (or react minimally) with materials of the n-type source / drain regions.

[0123] Go to Fig.11A , the operations described in conjunction with exemplary embodiment 1100 are combined FIG. 3A to FIG. 10C The described operations are then performed.

[0124] like Fig. 11B As shown in FIG. 1 , a dielectric layer 1105 (eg, an ILD layer) may be formed over the ILD layer 250 of the semiconductor device 200 and over the gate structure 240. The deposition tool 102 may be used to deposit dielectric layers 1105 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, or a combination thereof. Figure 1 The dielectric layer 1105 may be deposited using another type of deposition technique described herein and / or another suitable deposition technique. The dielectric layer 1105 may be deposited in one or more deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the dielectric layer 1105 after the dielectric layer 1105 is deposited. In some embodiments, the dielectric layer 1105 includes silicon carbide (SIC), lanthanum oxide (La x O y ), aluminum oxide (Al x O y ), aluminum oxynitride (AlON), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), silicon nitride (Si x N y ), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO x ), yttrium oxide (Y x O y ), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SICN), hafnium silicide (HfSi), and / or silicon oxide (SiO x ), and other examples.

[0125] like Fig. 11BAs further shown in FIG. 8 , a source / drain recess 1110a may be formed over the p-type source / drain region 225a, and a source / drain recess 1110b may be formed over the n-type source / drain region 225b. The source / drain recess 1110a may be formed through the dielectric layer 1105, through the ILD layer 250, and / or through the CESL 805, such that a top surface of the p-type source / drain region 225a is exposed through the source / drain recess 1110a. In some embodiments, the source / drain recess 1110a extends into a portion of the p-type source / drain region 225a. The source / drain recess 1110b may be formed through the dielectric layer 1105, through the ILD layer 250, and / or through the CESL 805, such that a top surface of the n-type source / drain region 225b is exposed through the source / drain recess 1110b. In some embodiments, the source / drain recess 1110b extends into a portion of the n-type source / drain region 225b.

[0126] In some embodiments, the dielectric layer 1105, the ILD layer 250 and / or the CESL 805 are etched using the pattern in the photoresist layer to form source / drain grooves 1110a and 1110b. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the dielectric layer 1105. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric layer 1105, the ILD layer 250 and / or the CESL 805 based on the pattern to form source / drain grooves 1110a and 1110b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the dielectric layer 1105 , the ILD layer 250 , and / or the CESL 805 .

[0127] like Fig. 11CAs shown in FIG. 1 , a silicide blocking layer 1115 is formed on the sidewalls of the dielectric layer 1105 in the source / drain recesses 1110a and 1110b. The silicide blocking layer 1115 is conformally deposited on the sidewalls of the dielectric layer 1105 to prevent or block silicide growth on the sidewalls of the dielectric layer 1105. The silicide blocking layer 1115 may be blanket deposited in the source / drain recesses 1110a and 1110b, and may subsequently be removed from the exposed surfaces of the p-type source / drain region 225a and the n-type source / drain region 225b, so that the silicide blocking layer 1115 remains on the sidewalls of the dielectric layer 1105 in the source / drain recesses 1110a and 1110b.

[0128] Deposition tool 102 may be used to utilize PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combinations of Figure 1 The silicide blocking layer 1115 may be deposited using another type of deposition technique described herein and / or another suitable deposition technique. The silicide blocking layer 1115 may be deposited in one or more deposition operations. The silicide blocking layer 1115 includes one or more dielectric materials that resist silicide formation, such as a nitride-containing dielectric material (e.g., silicon nitride (Si x N y ), and other examples). In some embodiments, the silicide barrier layer 1115 comprises a material composition that is the same or similar to the CESL 805. In some embodiments, the silicide barrier layer 1115 comprises silicon carbide (SIC), lanthanum oxide (La x O y ), aluminum oxide (Al x O y ), aluminum oxynitride (AlON), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), silicon nitride (Si x N y ), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO x ), yttrium oxide (Y x O y ), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SICN), hafnium silicide (HfSi), and / or silicon oxide (SiO x ), and other examples.

[0129] The etching tool 108 may be used to perform anisotropic etching of the silicide barrier layer 1115 to remove the silicide barrier layer 1115 from the bottom of the source / drain recesses 1110a and 1110b (and therefore, from the top surfaces of the p-type source / drain region 225a and the n-type source / drain region 225b) without removing (or minimally removing) the silicide barrier layer 1115 from the sidewalls of the source / drain recesses 1110a and 1110b. Anisotropic etching may include using a highly directional etching technique (such as a plasma-based etching technique) to etch the silicide barrier layer 1115 in the z-direction in the semiconductor device 200.

[0130] like Fig.11D As shown in , a p-type metal silicide layer 1120 is selectively formed on the p-type source / drain region 225a. The p-type metal silicide layer 1120 is selectively formed on the p-type source / drain region 225a because the p-type metal silicide layer 1120 is only formed on the p-type source / drain region 225a (and not formed on the n-type source / drain region 225b), without using an additional masking layer to prevent the p-type metal silicide layer 1120 from being formed on the n-type source / drain region 225b and / or other surfaces of the semiconductor device 200.

[0131] To form the p-type metal silicide layer 1120, a layer of p-type metal is deposited over the semiconductor device 200 (including over the p-type source / drain region 225a and the n-type source / drain region 225b). The p-type metal includes one or more p-type metals that react with the material of the p-type source / drain region 225a (e.g., react with germanium (Ge) of silicon germanium (SiGe) of the p-type source / drain region 225a) and do not react with the material of the n-type source / drain region 225b (e.g., do not react with silicon of the n-type source / drain region 225b). Examples of such p-type metals include iridium (Ir), ruthenium (Ru), molybdenum (Mo), rhodium (Rh), tungsten (W), and / or niobium (Nb), among other examples. Thus, the p-type metal silicide layer 1120 may include iridium silicide (IrSi), ruthenium silicide (RuSi), molybdenum silicide (MoSi), rhodium silicide (RhSi), tungsten silicide (WSi) and / or niobium silicide (NbSi), among other examples. The deposition tool 102 may be used to deposit the p-type metal silicide layer 1120 using PVD techniques, ALD techniques, CVD techniques, or a combination thereof. Figure 1 Another type of deposition technique is described and / or another suitable deposition technique is used to deposit the p-type metal.

[0132] The p-type metal is then annealed to induce a reaction between the p-type metal and the material of the p-type source / drain region 225a, thereby forming a p-type metal silicide layer 1120 on the p-type source / drain region 225a. The unreacted p-type metal can then be removed from the semiconductor device 200. The annealing of the p-type metal can be "in situ" because the elevated temperature at which the p-type metal is deposited can induce the annealing of the p-type metal. For a p-type metal silicide layer 1120 having a smaller thickness, an in situ annealing can be performed, or for a p-type metal silicide layer 1120 having a larger thickness, a separate annealing operation can be performed after the p-type metal is deposited.

[0133] like Fig.11E As shown in , an n-type metal silicide layer 1125 is formed over and / or on the exposed top surface of the n-type source / drain region 225b in the source / drain recess 1110b. To form the n-type metal silicide layer 1125, a layer of n-type metal may be blanket deposited and then annealed (in situ or separately, as described above) in the source / drain recesses 1110a and 1110b to cause a reaction between the n-type metal and the n-type source / drain region 225b to form the n-type metal silicide layer 1125. The n-type metal may also react with the p-type source / drain region 225a to form the n-type metal silicide layer 1125 on the p-type metal silicide layer 1120 over the p-type source / drain region 225a. Unreacted n-type metal may be removed from the semiconductor device 200. In some embodiments, the n-type metal silicide layer 1125 is subsequently removed from the p-type source / drain regions 225a. Alternatively, the n-type metal silicide layer 1125 may remain on the p-type metal silicide layer 1120 above the p-type source / drain regions 225a.

[0134] The n-type metal may include antimony (Sb), titanium (Ti), zirconium (Zr), yttrium (Y) and / or scandium (Sc), among other examples. Thus, the n-type metal silicide layer 1125 may include antimony silicide (SbSi), titanium silicide (TiSi), zirconium silicide (ZrSi), yttrium silicide (YSi) and / or scandium silicide (ScSi), among other examples. The deposition tool 102 may be used to deposit the n-type metal using PVD techniques, ALD techniques, CVD techniques, or a combination thereof. Figure 1 Another type of deposition technique is described and / or another suitable deposition technique is used to deposit the n-type metal.

[0135] The p-type metal silicide layer 1120 is formed on the p-type source / drain region 225a and the n-type metal silicide layer 1125 is formed on the n-type source / drain region 225b so that the contact resistance can be adjusted separately and independently for the p-type source / drain region 225a and the n-type source / drain region 225b. The silicide layer in direct contact with the p-type source / drain region 225a may have the greatest impact on the contact resistance of the p-type source / drain region 225a. Therefore, if the n-type metal silicide layer 1125 remains on the p-type metal silicide layer 1120 above the p-type source / drain region 225a, the n-type metal silicide layer 1125 has the least impact on the contact resistance of the p-type source / drain region 225a because the n-type metal silicide layer 1125 is not in direct contact with the p-type source / drain region 225a. Therefore, semiconductor processing complexity, time and / or cost for the semiconductor device 200 can be reduced with minimal performance impact by not removing the n-type metal silicide layer 1125 from the p-type source / drain region 225a (if the p-type metal silicide layer 1120 is located between the n-type metal silicide layer 1125 and the p-type source / drain region 225a).

[0136] like Fig.11F As shown in , a capping layer 1130 is formed over the n-type source / drain region 225b on the n-type metal silicide layer 1125. Optionally, the capping layer 1130 can be omitted from the n-type source / drain region 225b. The capping layer 1130 may include a titanium silicide (TiSi) layer formed "in situ" with the n-type metal silicide layer 1125. In other words, the titanium silicide layer is formed under the same vacuum as the formation of the n-type metal silicide layer 1125 (e.g., in the same processing chamber without breaking the vacuum pressure in the processing chamber). This minimizes and / or reduces the possibility of the semiconductor device 200 being exposed to atmospheric oxygen before the titanium silicide layer is formed. Otherwise, the atmospheric oxygen may cause the titanium silicide layer to oxidize. After the titanium silicide layer is formed, the deposition tool 102 can be used to implement a nitridation process for nitriding the titanium silicide layer. This increases the nitrogen concentration in the titanium silicide layer, which reduces the possibility of oxidation in the titanium silicide layer after the vacuum is removed. Alternatively, the capping layer 1130 may be formed of another metal silicide material if another type of n-type metal silicide (e.g., other than titanium silicide) is used for the n-type metal silicide layer 1125. A similar capping layer (e.g., titanium silicide or another type of metal silicide) may also be formed on the p-type metal silicide layer 1120 over the p-type source / drain regions 225a.

[0137] After forming the capping layer 1130, the layer stack on top of the p-type source / drain region 225a may include a separate p-type metal silicide layer 1120 or be combined with an n-type metal silicide layer 1125 on the p-type metal silicide layer 1120 and / or a capping layer 1130 on the n-type metal silicide layer 1125. The layer stack on top of the n-type source / drain region 225b may include a separate n-type metal silicide layer 1125 or be combined with a capping layer 1130 on the n-type metal silicide layer 1125.

[0138] In this way, the semiconductor device 200 may include a plurality of nanostructure channels 220 arranged in a direction approximately perpendicular to the semiconductor substrate 205 of the semiconductor device 200 (e.g., the z direction), a gate structure 240 wrapping each of the nanostructure channels 220, a p-type source / drain region 225a adjacent to the nanostructure channel 220, an n-type source / drain region 225b adjacent to the nanostructure channel 220, a p-type metal silicide layer 1120 on the p-type source / drain region 225a, and an n-type metal silicide layer 1125 on the n-type source / drain region 225b. If the n-type metal silicide layer 1125 is not removed from the p-type metal silicide layer 1120 over the p-type source / drain regions 225 a , the n-type metal silicide layer 1125 may also be included on the p-type metal silicide layer 1120 between the p-type metal silicide layer 1120 and the source / drain contacts 1140 a .

[0139] like Fig.11G As shown in , a conductive layer 1135 is formed in the source / drain recesses 1110a and 1110b and over the dielectric layer 1105. The conductive layer 1135 is formed over the p-type source / drain region 225a in the source / drain recess 1110a, and over the p-type metal silicide layer 1120 and the n-type metal silicide layer 1125 (if not removed) in the source / drain recess 1110a. The conductive layer 1135 is also formed over the n-type source / drain region 225b in the source / drain recess 1110b, and over the n-type metal silicide layer 1125 and the capping layer 1130 (if formed) in the source / drain recess 1110b. The deposition tool 102 and / or the plating tool 112 may be used to deposit the conductive layer 1135 using a CVD technique, a PVD technique, an ALD technique, an electroplating technique, or a combination of the above. Figure 1The conductive layer 1135 may be deposited by another deposition technique described and / or another suitable deposition technique. The conductive layer 1135 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and the conductive layer 1135 is deposited on the seed layer. In some embodiments, one or more liner layers (e.g., adhesion layers, glue layers, barrier layers) are included between the conductive layer 1135 and the sidewalls of the source / drain recesses 1110a and 1110b. One or more liner layers may include titanium silicide (TiSi), molybdenum (Mo), zirconium (Zr), ruthenium (Ru), tungsten (W), titanium nitride (TiN), yttrium (Y), iridium (Ir), antimony (Sb), scandium (Sc), niobium (Nb), rhodium (Rh), molybdenum silicon nitride (MoSiN), zirconium silicon nitride (ZrSiN), ruthenium silicon nitride (RuSiN), tungsten silicon nitride (WSiN), titanium nitride (TiN), yttrium silicon nitride (YSiN), iridium silicon nitride (IrSiN), antimony silicon nitride (SbSiN), scandium silicon nitride (ScSiN), rhodium silicon nitride (RhSiN) and / or niobium silicon nitride (NbSiN), as well as other examples.

[0140] like Fig.11H As shown in , the planarization tool 110 can be used to perform a CMP operation and / or another type of planarization operation to planarize the conductive layer 1135 after depositing the conductive layer 1135. The planarization operation causes material to be removed from the conductive layer 1135. The remaining material of the conductive layer 1135 corresponds to the source / drain contact 1140a above and / or on the p-type source / drain region 225a (where the p-type metal silicide layer 1120 is located between the p-type source / drain region 225a and the source / drain contact 1140a) and the source / drain contact 1140b above and / or on the n-type source / drain region 225b (where the n-type metal silicide layer 1125 is located between the n-type source / drain region 225b and the source / drain contact 1140b).

[0141] In some embodiments, the n-type metal silicide layer 1125 is also included between the p-type metal silicide layer 1120 and the source / drain contact 1140a if the n-type metal silicide layer 1125 is not removed from the p-type metal silicide layer 1120. In some embodiments, the source / drain contact 1140a is directly included on the p-type metal silicide layer 1120 if the n-type metal silicide layer 1125 is removed from the p-type metal silicide layer 1120.

[0142] In some embodiments, the capping layer 1130 is also included between the n-type metal silicide layer 1125 and the source / drain contact 1140b if the capping layer 1130 is formed on the n-type metal silicide layer 1125. In some embodiments, the source / drain contact 1140b is directly included on the n-type metal silicide layer 1125 if the capping layer 1130 is omitted from the n-type source / drain region 225b.

[0143] like Fig.11I As shown in FIG. 1 , an etch stop layer (ESL) 1145 is formed above and / or on dielectric layer 1105. ESL 1145 may also be formed above and / or on source / drain contacts 1140a and 1140b. Another dielectric layer 1150 (e.g., another ILD layer) is formed above and / or on ESL 1145. ESL 1145 may include silicon nitride (Si x N y ), silicon carbonitride (SICN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SICO), or combinations thereof, as well as other examples. In some embodiments, the dielectric layer 1150 includes silicon carbide (SIC), lanthanum oxide (La x O y ), aluminum oxide (Al x O y ), aluminum oxynitride (AlON), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), silicon nitride (Si x N y ), silicon (Si), zinc oxide (ZnO), zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), titanium oxide (TiO x ), yttrium oxide (Y x O y ), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), silicon carbonitride (SICN), hafnium silicide (HfSi), and / or silicon oxide (SiO x ), and other examples.

[0144] Deposition tool 102 may be used to utilize PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combinations of Figure 1 In some embodiments, planarization tool 110 may be used to planarize ESL 1145 after depositing ESL 1145. Deposition tool 102 may be used to deposit ESL 1145 using another type of deposition technique described herein and / or another suitable deposition technique. ESL 1145 may be deposited in one or more deposition operations. In some embodiments, planarization tool 110 may be used to planarize ESL 1145 after depositing ESL 1145. Deposition tool 102 may be used to planarize ESL 1145 using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combinations of Figure 1 The dielectric layer 1150 may be deposited using another type of deposition technique described herein and / or another suitable deposition technique. The dielectric layer 1150 may be deposited in one or more deposition operations. In some embodiments, the planarization tool 110 may be used to planarize the dielectric layer 1150 after the dielectric layer 1150 is deposited.

[0145] like Fig.11I As further shown in FIG. 2 , a source / drain interconnect 1155a electrically and / or physically coupled to the source / drain contact 1140a is formed through the dielectric layer 1150 and the ESL 1145. A source / drain interconnect 1155b electrically and / or physically coupled to the source / drain contact 1140b is formed through the dielectric layer 1150 and the ESL 1145. The source / drain interconnects 1155a and 1155b may be connected to other metallization layers and / or interconnects in an interconnect structure in the semiconductor device 200.

[0146] In some embodiments, the dielectric layer 1150 and the ESL 1145 are etched using a pattern in the photoresist layer to form a groove through the dielectric layer 1150 and through the ESL 1145. A groove may be formed above the source / drain contact 1140a so that the top surface of the source / drain contact 1140a is exposed through the groove. Another groove may be formed above the source / drain contact 1140b so that the top surface of the source / drain contact 1140b is exposed through the groove. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the dielectric layer 1150. An exposure tool 104 may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 may be used to develop and remove portions of the photoresist layer to expose a pattern. The etching tool 108 can be used to etch the dielectric layer 1150 and / or the ESL 1145 based on the pattern to form a groove in the dielectric layer 1150 and / or the ESL 1145. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an optional technique for etching the dielectric layer 1150 and / or the ESL 1145 based on the pattern.

[0147] The deposition tool 102 and / or the plating tool 112 may be used to deposit and / or deposit the substrate using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1Another type of deposition technique described and / or another suitable deposition technique deposits source / drain interconnect 1155a in a recess above source / drain contact 1140a. Source / drain interconnect 1155a can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and source / drain interconnect 1155a is deposited on the seed layer. In some embodiments, planarization tool 110 can be used to planarize source / drain interconnect 1155a after depositing source / drain interconnect 1155a.

[0148] The deposition tool 102 and / or the plating tool 112 may be used to deposit and / or deposit the substrate using CVD technology, PVD technology, ALD technology, electroplating technology, or a combination of the above. Figure 1 Another deposition technique described and / or another suitable deposition technique deposits source / drain interconnect 1155b in the recess above source / drain contact 1140b. Source / drain interconnect 1155b can be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and source / drain interconnect 1155b is deposited on the seed layer. In some embodiments, planarization tool 110 can be used to planarize source / drain interconnect 1155b after depositing source / drain interconnect 1155b.

[0149] like Fig.11I As further shown in , the semiconductor device 200 can have one or more dimensions. An exemplary dimension D1 includes the x-direction width of the p-type metal silicide layer 1120 on the p-type source / drain region 225a. In some embodiments, the dimension D1 is included in the range of about 1 nanometer to about 100 nanometers to achieve a sufficiently low contact resistance for the p-type source / drain region 225a. However, other values ​​for the range are within the scope of the embodiments of the present disclosure. Another exemplary dimension D2 includes the z-direction thickness of the p-type metal silicide layer 1120. In some embodiments, the dimension D2 is included in the range of about 1 nanometer to about 10 nanometers to achieve a sufficiently low contact resistance for the p-type source / drain region 225a. However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0150] An exemplary dimension D3 includes the z-direction thickness of the n-type metal silicide layer 1125 on the n-type source / drain region 225b. In some embodiments, the dimension D3 is included in the range of about 1 nanometer to about 10 nanometers to achieve a sufficiently low contact resistance for the n-type source / drain region 225b. However, other values ​​for the range are within the scope of the embodiments of the present disclosure. Another exemplary dimension D4 includes the y-direction width of the p-type metal silicide layer 1120. In some embodiments, the dimension D4 is included in the range of about 1 nanometer to about 30 nanometers to achieve a sufficiently low contact resistance for the p-type source / drain region 225a. However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0151] As noted above, FIG. 11A to FIG. 11I The number and arrangement of operations and devices shown in the figure are provided as one or more examples. In practice, there may be FIG. 11A to FIG. 11I Additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown in .

[0152] FIG. 12A to FIG. 12L is a diagram of an exemplary embodiment 1200 of forming an active area isolation structure described herein. FIG. 12A to FIG. 12L One or more of the Figure 5 One or more perspectives shown, including Figure 5 4. The perspective of the cross-sectional plane AA in FIG. 2 (eg, across the plurality of source / drain regions 225 adjacent to the sidewalls of the gate structure 240 in the x-direction) is shown.

[0153] Exemplary embodiment 1200 includes an example of forming a p-type metal silicide layer on a p-type source / drain region 225a of semiconductor device 200 using a masking layer over an n-type source / drain region 225b. Using a masking layer for the n-type source / drain region 225b enables metal to be used for a p-type metal silicide layer, such as titanium silicide (TiSi), that might otherwise be formed on the n-type source / drain region 225b. In other words, using a masking layer enables the p-type metal silicide layer to be formed using a non-selective metal.

[0154] Go to Fig. 12A , the operations described in conjunction with exemplary embodiment 1200 are combined FIG. 3A to FIG. 10C The described operations are then performed.

[0155] like Fig. 12B As shown in, combined with the above Fig. 11B Dielectric layer 1205 is formed in a similar manner as described for dielectric layer 1105. Fig. 11BSource / drain recesses 1210 a and 1210 b are formed in a similar manner as described for source / drain recesses 1110 a and 1110 b , respectively.

[0156] like Fig. 12C As shown in FIG. 1 , a silicide barrier layer 1215 is formed on the sidewall of the dielectric layer 1105. The silicide barrier layer 1215 may be formed by combining with the above Fig. 11C The silicide blocking layer 1115 is formed in a similar manner as described above.

[0157] like Fig.12D As shown in FIG. 1 , a masking layer 1220 is formed over the semiconductor device 200. The masking layer 1220 may be formed in the source / drain recess 1210a over the p-type source / drain region 225a and in the source / drain recess 1210b over the n-type source / drain region 225b. The masking layer 1220 may include aluminum oxide (Al x O y ) and / or another suitable hard mask material. The deposition tool 102 may be used to deposit the substrate using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, a combination of Figure 1 Another type of deposition technique as described and / or another suitable deposition technique to deposit masking layer 1220. Masking layer 1220 can be deposited in one or more deposition operations.

[0158] like Fig.12E As shown in FIG, portions of masking layer 1220 are removed from semiconductor device 200 (including from source / drain recesses 1210a). Removing portions of masking layer 1220 exposes p-type source / drain regions 225a through masking layer 1220. Remaining portions of masking layer 1220 remain over n-type source / drain regions 225b in source / drain recesses 1210b.

[0159] In some embodiments, the masking layer 1220 is etched using the pattern in the photoresist layer to remove the portion of the masking layer 1220. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the masking layer 1220. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove the portion of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the masking layer 1220 based on the pattern to remove the portion of the masking layer 1220. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing and / or another technology). In some embodiments, a hard mask layer is used as an optional technology for etching the masking layer 1220 based on the pattern.

[0160] like Fig.12F As shown in FIG. 1 , a p-type metal silicide layer 1225 is formed on the top surface of the p-type source / drain region 225a in the source / drain groove 1210a. The p-type metal silicide layer 1225 may be formed in a manner combined with the above Fig.11D The p-type metal silicide layer 1120 is formed in a similar manner as described above, except that in the exemplary embodiment 1200, the remaining portion of the masking layer 1220 protects the n-type source / drain regions 225b from the formation of the p-type metal silicide. This allows a non-selective p-type metal to be used for the p-type metal silicide layer 1225, such as titanium (Ti). Therefore, the p-type metal silicide layer 1225 may include titanium silicide (TiSi), alone or in combination with the above FIG. 11A to FIG. 11I One or more combinations of the other p-type metal silicide materials described.

[0161] like Figure 12G , the remaining portion of the masking layer 1220 is removed from the semiconductor device 200 (e.g., from the source / drain recesses 1210b and from the n-type source / drain regions 225b in the source / drain recesses 1210b). In some embodiments, the etching tool 108 is used to etch the masking layer 1220 to remove the remaining portion of the masking layer 1220. In some embodiments, another technique is used to remove the remaining portion of the masking layer 1220.

[0162] like Fig.12H As shown in FIG. 1 , after removing the masking layer, an n-type metal silicide layer 1230 is formed on the n-type source / drain region 225b in the source / drain groove 1210b and on the p-type metal silicide layer 1225 in the source / drain groove 1210a. The n-type metal silicide layer 1230 may be formed in combination with the above Fig.11E The n-type metal silicide layer 1125 is formed in a similar manner as described above. FIG. 11A to FIG. 11I One or more n-type metal silicide materials are described, as well as other examples of n-type metal silicide materials.

[0163] like Fig.12I As shown in Fig.11F A capping layer 1235 is formed on the n-type metal silicide layer 1230 over the n-type source / drain regions 225 b and / or on the n-type metal silicide layer 1230 over the p-type source / drain regions 225 a in a manner similar to that described for the capping layer 1130. The capping layer 1235 (if formed) is formed in-situ with the n-type metal silicide layer 1230.

[0164] After forming the capping layer 1235, the layer stack on the top surface of the p-type source / drain region 225a may include a p-type metal silicide layer 1225 (which may include a titanium silicide layer and / or another type of p-type metal silicide layer), alone or in combination with an n-type metal silicide layer 1230 on the p-type metal silicide layer 1225 and / or a capping layer 1235 on the n-type metal silicide layer 1230. After forming the capping layer 1235, the layer stack on the top surface of the n-type source / drain region 225b may include an n-type metal silicide layer 1230, alone or in combination with a capping layer 1235 on the n-type metal silicide layer 1230.

[0165] In this manner, the semiconductor device 200 may include a plurality of nanostructure channels 220 arranged in a direction (e.g., z-direction) approximately perpendicular to the semiconductor substrate 205 of the semiconductor device 200, a gate structure 240 wrapping each of the nanostructure channels 220, a p-type source / drain region 225a adjacent to the nanostructure channel 220, an n-type source / drain region 225b adjacent to the nanostructure channel 220, a p-type metal silicide layer 1225 (e.g., a titanium silicide layer and / or another type of p-type metal silicide layer) on the p-type source / drain region 225a, and an n-type metal silicide layer 1230 on the p-type metal silicide layer 1225 and on the n-type source / drain region 225b. A capping layer 1235 may be included on the n-type metal silicide layer 1230 over the p-type source / drain region 225a and / or over the n-type source / drain region 225b.

[0166] like Fig.12J As shown in FIG. 1 , a conductive layer 1240 is formed over the semiconductor device 200 so that the conductive layer 1240 fills the source / drain grooves 1210 a and 1210 b. The conductive layer 1240 may be formed in a manner combined with the above Fig.11G The conductive layer 1135 is formed in a similar manner as described above.

[0167] like Figure 12K As shown in FIG. 1 , a planarization operation is performed to planarize the conductive layer 1240 so as to be combined with the above Fig.11H Source / drain contacts 1245a and 1245b are formed in a similar manner as described for source / drain contacts 1140a and 1140b.

[0168] like Figure 12L As shown in Fig.11I ESL 1250 , dielectric layer 1255 , and source / drain interconnects 1260 a and 1260 b , respectively, are formed in a similar manner as described for ESL 1145 , dielectric layer 1150 , and source / drain interconnects 1155 a and 1155 b .

[0169] As noted above, FIG. 12A to FIG. 12L The number and arrangement of operations and devices shown in the figure are provided as one or more examples. In practice, there may be FIG. 12A to FIG. 12L Additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown in .

[0170] FIG. 13A to FIG. 13H is a diagram of an exemplary implementation 1300 of forming an active area isolation structure described herein. FIG. 13A to FIG. 13H One or more of the Figure 5 One or more perspectives shown, including Figure 5 4. The perspective of the cross-sectional plane AA in FIG. 2 (eg, across the plurality of source / drain regions 225 adjacent to the sidewalls of the gate structure 240 in the x-direction) is shown.

[0171] Exemplary embodiment 1300 includes an example of forming a first metal silicide layer of a first type on p-type source / drain region 225a and on n-type source / drain region 225b of semiconductor device 200 without using a masking layer, and then forming a second metal silicide layer of a second type different from the first type on the first metal silicide layer over p-type source / drain region 225a and over n-type source / drain region 225b without using a masking layer. The number of process steps for forming semiconductor device 200 can be reduced by forming the silicide layers for p-type source / drain region 225a and for n-type source / drain region 225b without using a masking layer, which reduces the complexity, cost and / or time of manufacturing semiconductor device 200 relative to using a masking layer.

[0172] The type of metal silicide formed for the first metal silicide layer can be selected based on the performance impact of the first metal silicide layer on the p-type source / drain region 225a, the performance impact of the first metal silicide layer on the n-type source / drain region 225b, and / or the overall performance impact on the semiconductor device 200. For example, in some embodiments, first forming a p-type metal silicide layer on the p-type source / drain region 225a and on the n-type source / drain region 225b can make the total contact resistance for the semiconductor device 200 smaller than if the n-type metal silicide layer is formed first. Therefore, in these embodiments, the p-type metal silicide layer can be formed first, and the n-type metal silicide layer can be formed on the p-type metal silicide layer. As another example, in some embodiments, if first forming a p-type metal silicide layer on the p-type source / drain region 225a and the n-type source / drain region 225b can greatly increase the contact resistance for the n-type source / drain region 225b, then an n-type metal silicide layer can be first formed on the p-type source / drain region 225a and the n-type source / drain region 225b, and then a p-type metal silicide layer can be formed on the n-type metal silicide layer.

[0173] Go to Fig.13A , the operations described in conjunction with exemplary embodiment 1300 are combined FIG. 3A to FIG. 10C The described operations are then performed.

[0174] like Fig. 13B As shown in, combined with the above Fig. 11B Dielectric layer 1305 is formed in a similar manner as described for dielectric layer 1105. Fig. 11B Source / drain recesses 1310 a and 1310 b are formed in a similar manner as described for source / drain recesses 1110 a and 1110 b , respectively.

[0175] like Fig. 13C As shown in FIG. 1 , a silicide barrier layer 1315 is formed on the sidewall of the dielectric layer 1305. The silicide barrier layer 1315 may be formed in a manner combined with the above Fig. 11C The silicide blocking layer 1115 is formed in a similar manner as described above.

[0176] like Fig.13D As shown in FIG. 1 , a first metal silicide layer 1320 is formed on the top surface of the p-type source / drain region 225a in the source / drain recess 1310a and the top surface of the n-type source / drain region 225b in the source / drain recess 1310b. In some embodiments, the first metal silicide layer 1320 includes a p-type metal silicide layer and is bonded to the top surface of the p-type source / drain region 225a. Fig.11DThe p-type metal silicide layer 1120 is formed in a similar manner as described above. In these embodiments, the first metal silicide layer 1320 may include titanium silicide (TiSi), alone or in combination with the above FIG. 11A to FIG. 11I In some embodiments, the first metal silicide layer 1320 includes an n-type metal silicide layer and is combined with one or more of the other p-type metal silicide materials described above. Fig.11E A similar manner as described for the n-type metal silicide layer 1125 is formed on the p-type source / drain region 225a in the source / drain recess 1310a and on the n-type source / drain region 225b in the source / drain recess 1310b. In these embodiments, the first metal silicide layer 1320 may include the above combined FIG. 11A to FIG. 11I One or more of the n-type metal silicide materials described, as well as other examples of n-type metal silicide materials. Metal materials that are not reacted when forming the first metal silicide layer 1320 may be removed from the semiconductor device 200 .

[0177] like Fig.13E As shown in , a second metal silicide layer 1325 is formed on the first metal silicide layer 1320 located above the p-type source / drain region 225a in the source / drain groove 1310a, and a second metal silicide layer 1325 is formed on the first metal silicide layer 1320 located above the n-type source / drain region 225b in the source / drain groove 1310b. The metal type (e.g., p-type, n-type) of the second metal silicide layer 1325 is different from that of the first metal silicide layer 1320. For example, if the first metal silicide layer 1320 includes a p-type metal silicide layer, the second metal silicide layer 1325 can be formed as an n-type metal silicide layer. As another example, if the first metal silicide layer 1320 includes an n-type metal silicide layer, the second metal silicide layer 1325 can be formed as a p-type metal silicide layer.

[0178] In some embodiments, the second metal silicide layer 1325 includes a p-type metal silicide layer and is combined with the above Fig.11D The second metal silicide layer 1325 is formed in a similar manner as described for the p-type metal silicide layer 1120. In these embodiments, the second metal silicide layer 1325 may include titanium silicide (TiSi), alone or in combination with the above FIG. 11A to FIG. 11I In some embodiments, the second metal silicide layer 1325 includes an n-type metal silicide layer and is combined with one or more of the other p-type metal silicide materials described above. Fig.11EA similar manner as described for the n-type metal silicide layer 1125 is formed on the p-type source / drain region 225a in the source / drain recess 1310a and on the n-type source / drain region 225b in the source / drain recess 1310b. In these embodiments, the second metal silicide layer 1325 may include the above combined FIG. 11A to FIG. 11I One or more of the n-type metal silicide materials described, as well as other examples of n-type metal silicide materials. Metal materials that are not reacted when forming the first metal silicide layer 1320 may be removed from the semiconductor device 200 .

[0179] In some embodiments, it can be combined with the above Fig.11F A capping layer (not shown) is formed on the second metal silicide layer 1325 over the p-type source / drain regions 225a and / or on the n-type source / drain regions 225b in a manner similar to that described for the capping layer 1130. The capping layer (if formed) is formed in situ with the second metal silicide layer 1325.

[0180] After forming the capping layer, the layer stack on the top surface of the p-type source / drain region 225a and on the top surface of the n-type source / drain region 225b may include a p-type metal silicide layer (which may include titanium silicide and / or another type of p-type metal silicide material), an n-type metal silicide layer on the p-type metal silicide layer (which may include one or more n-type metal silicide materials), and / or a capping layer on the n-type metal silicide layer. Optionally, the layer stack on the top surface of the p-type source / drain region 225a and on the top surface of the n-type source / drain region 225b may include an n-type metal silicide layer (which may include one or more n-type metal silicide materials), a p-type metal silicide layer on the n-type metal silicide layer (which may include titanium silicide and / or another type of p-type metal silicide material), and / or a capping layer on the p-type metal silicide layer.

[0181] In this manner, the semiconductor device 200 may include a plurality of nanostructure channels 220 arranged in a direction (e.g., z-direction) approximately perpendicular to the semiconductor substrate 205 of the semiconductor device 200, a gate structure 240 wrapping each of the nanostructure channels 220, a p-type source / drain region 225a adjacent to the nanostructure channels 220, an n-type source / drain region 225b adjacent to the nanostructure channels 220, a first metal silicide layer 1320 on the p-type source / drain region 225a and on the n-type source / drain region 225b, and a second metal silicide layer 1325 on the first metal silicide layer 1320 over the p-type source / drain region 225a and the n-type source / drain region 250b. The first metal silicide layer includes a first metal type, and the second metal silicide layer includes a second metal type different from the first metal type. In some embodiments, a capping layer may be included on the second metal silicide layer 1325 over the p-type source / drain region 225 a and / or over the n-type source / drain region 225 b .

[0182] like Fig.13F As shown in FIG. 1 , a conductive layer 1330 is formed over the semiconductor device 200 so that the conductive layer 1330 fills the source / drain grooves 1310 a and 1310 b. The conductive layer 1330 may be formed in a manner combined with the above Fig.11G The conductive layer 1135 is formed in a similar manner as described above.

[0183] like Figure 13G As shown in FIG. 1 , a planarization operation is performed to planarize the conductive layer 1330 so as to be combined with the above Fig.11H Source / drain contacts 1335a and 1335b are formed in a similar manner as described for source / drain contacts 1140a and 1140b.

[0184] like Fig.13H As shown in Fig.11I ESL 1340 , dielectric layer 1345 , and source / drain interconnects 1350 a and 1350 b , respectively, are formed in a similar manner as described for ESL 1145 , dielectric layer 1150 , and source / drain interconnects 1155 a and 1155 b .

[0185] As noted above, FIG. 13A to FIG. 13H The number and arrangement of operations and devices shown in the figure are provided as one or more examples. In practice, there may be FIG. 13A to FIG. 13H Additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown in .

[0186] FIG. 14A to FIG. 14Lis a diagram of an exemplary implementation 1400 of forming an active area isolation structure described herein. FIG. 14A to FIG. 14L One or more of the Figure 5 One or more perspectives shown, including Figure 5 4. The perspective of the cross-sectional plane AA in FIG. 2 (eg, across the plurality of source / drain regions 225 adjacent to the sidewalls of the gate structure 240 in the x-direction) is shown.

[0187] Exemplary embodiment 1400 includes an example of forming an n-type metal silicide layer on an n-type source / drain region 225b of semiconductor device 200 using a masking layer over a p-type source / drain region 225a. Using a masking layer for the p-type source / drain region 225a enables the n-type metal silicide layer to be formed directly on the n-type source / drain region 225b without forming an n-type metal silicide layer on the p-type source / drain region 225a. Subsequently, the p-type metal silicide layer can be formed directly on the p-type source / drain region 225a without using a masking layer because the p-type metal silicide layer formed on the n-type metal silicide layer can have minimal effect on the contact resistance of the n-type source / drain region 225b.

[0188] Go to Fig.14A , the operations described in conjunction with exemplary embodiment 1400 are combined FIG. 3A to FIG. 10C The described operations are then performed.

[0189] like Fig. 14B As shown in, combined with the above Fig. 11B Dielectric layer 1405 is formed in a similar manner as described for dielectric layer 1105. Fig. 11B Source / drain recesses 1410a and 1410b are formed in a similar manner as described for source / drain recesses 1110a and 1110b, respectively.

[0190] like Fig. 14C As shown in FIG. 1 , a silicide blocking layer 1415 is formed on the sidewall of the dielectric layer 1105. The silicide blocking layer 1415 may be formed in a manner combined with the above Fig. 11C The silicide blocking layer 1115 is formed in a similar manner as described above.

[0191] like Fig.14D As shown in FIG. 1 , a masking layer 1420 is formed over the semiconductor device 200. The masking layer 1420 may be formed in the source / drain recess 1410a over the p-type source / drain region 225a and in the source / drain recess 1410b over the n-type source / drain region 225b. The masking layer 1420 may include aluminum oxide (Al x O y) and / or another suitable hard mask material. The deposition tool 102 may be used to deposit the substrate using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, a combination of Figure 1 Another type of deposition technique as described and / or another suitable deposition technique to deposit masking layer 1420. Masking layer 1420 can be deposited in one or more deposition operations.

[0192] like Fig.14E As shown in FIG. 1 , portions of masking layer 1420 are removed from semiconductor device 200 (including from source / drain recess 1410 b). Removing portions of masking layer 1420 exposes n-type source / drain region 225 b through masking layer 1420. Remaining portions of masking layer 1420 remain over p-type source / drain region 225 a in source / drain recess 1410 a.

[0193] In some embodiments, the masking layer 1420 is etched using the pattern in the photoresist layer to remove portions of the masking layer 1420. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the masking layer 1420. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the masking layer 1420 based on the pattern to remove portions of the masking layer 1420. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an optional technique for etching the masking layer 1420 based on the pattern.

[0194] like Fig.14F As shown in FIG. 1 , an n-type metal silicide layer 1425 is formed directly on the n-type source / drain region 225b in the source / drain recess 1410b. The masking layer 1420 above the p-type source / drain region 225a prevents the n-type silicide layer 1425 from being formed on the p-type source / drain region 225a. The n-type metal silicide layer 1425 may be formed in combination with the above Fig.11E The n-type metal silicide layer 1425 is formed in a similar manner as described above. FIG. 11A to FIG. 11I One or more n-type metal silicide materials are described, as well as other examples of n-type metal silicide materials.

[0195] like Figure 14G As shown in Fig.11FA capping layer 1430 is formed on the n-type metal silicide layer 1425 above the n-type source / drain region 225b in a manner similar to that described for the capping layer 1130. The capping layer 1430, if formed, is formed in-situ with the n-type metal silicide layer 1425. Alternatively, the capping layer 1430 may be omitted from the n-type source / drain region 225b.

[0196] like Fig.14H , the remaining portion of the masking layer 1420 is removed from the semiconductor device 200 (e.g., from the source / drain recess 1410a and from the p-type source / drain region 225a in the source / drain recess 1410a). In some embodiments, the etching tool 108 is used to etch the masking layer 1420 to remove the remaining portion of the masking layer 1420. In some embodiments, another technique is used to remove the remaining portion of the masking layer 1420.

[0197] like Fig.14I As shown in FIG. 1 , after removing the masking layer 1420, a p-type metal silicide layer 1435 is directly formed on the top surface of the p-type source / drain region 225a in the source / drain groove 1410a. The p-type metal silicide layer 1435 may be formed in combination with the above Fig.11D The p-type metal silicide layer 1140a is formed in a similar manner as described above. The p-type metal silicide layer 1435 may include titanium silicide (TiSi), alone or in combination with the above FIG. 11A to FIG. 11I In some embodiments, a capping layer (not shown) may be formed on the p-type metal silicide layer 1435. In some embodiments, the p-type metal silicide layer 1435 is also formed on the n-type metal silicide layer 1425 located above the n-type source / drain region 225 b and / or on the capping layer 1430.

[0198] After forming the p-type metal silicide layer 1435, the layer stack on the top surface of the p-type source / drain region 225a may include the p-type metal silicide layer 1435 (which may include a titanium silicide layer and / or another type of p-type metal silicide layer), alone or in combination with a capping layer (e.g., a titanium silicide layer and / or another type of capping silicide) on the p-type metal silicide layer 1435. After forming the p-type metal silicide layer 1435, the layer stack on the top surface of the n-type source / drain region 225b may include the n-type metal silicide layer 1425, alone or in combination with a capping layer 1430 on the n-type metal silicide layer 1425, a p-type metal silicide layer 1435 on the capping layer 1430, and / or another capping layer on the p-type metal silicide layer 1435, as well as other examples.

[0199] In this way, the semiconductor device 200 may include a plurality of nanostructure channels 220 arranged in a direction approximately perpendicular to the semiconductor substrate 205 of the semiconductor device 200 (e.g., the z direction), a gate structure 240 wrapping each of the nanostructure channels 220, a p-type source / drain region 225a adjacent to the nanostructure channel 220, an n-type source / drain region 225b adjacent to the nanostructure channel 220, an n-type metal silicide layer 1425 on the n-type source / drain region 225b, and a p-type metal silicide layer 1435 on the p-type source / drain region 225a and on the n-type metal silicide layer 1425. The capping layer 1430 may be included on the n-type metal silicide layer 1425 over the n-type source / drain region 225 b and / or on the p-type metal silicide layer 1435 over the p-type source / drain region 225 a and / or over the n-type source / drain region 225 b .

[0200] like Fig.14J As shown in FIG. 1 , a conductive layer 1440 is formed over the semiconductor device 200 so that the conductive layer 1440 fills the source / drain grooves 1410 a and 1410 b. The conductive layer 1440 may be formed in a manner combined with the above Fig.11G The conductive layer 1135 is formed in a similar manner as described above.

[0201] like Figure 14K As shown in FIG. 1 , a planarization operation is performed to planarize the conductive layer 1440 so as to be combined with the above Fig.11H Source / drain contacts 1445a and 1445b are formed in a similar manner as described for source / drain contacts 1140a and 1140b.

[0202] like Figure 14L As shown in Fig.11I ESL 1450 , dielectric layer 1455 , and source / drain interconnects 1460 a and 1460 b , respectively, are formed in a similar manner as described for ESL 1145 , dielectric layer 1150 , and source / drain interconnects 1155 a and 1155 b .

[0203] As noted above, FIG. 14A to FIG. 14L The number and arrangement of operations and devices shown in the figure are provided as one or more examples. In practice, there may be FIG. 14A to FIG. 14L Additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown in .

[0204] Fig.151500 is a diagram of exemplary components of the device 1500 described herein. In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may include one or more devices 1500 and / or one or more components of the device 1500. Fig.15 As shown in , device 1500 may include a bus 1510 , a processor 1520 , a memory 1530 , an input component 1540 , an output component 1550 , and / or a communication component 1560 .

[0205] The bus 1510 may include one or more components that enable wired and / or wireless communication between components of the device 1500. The bus 1510 may include one or more components that enable wired and / or wireless communication between components of the device 1500. Fig.15 Two or more components of the computer system 1510 are coupled together, such as via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 1510 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 1520 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or another type of processing component. Processor 1520 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1520 may include one or more processors that can be programmed to implement one or more operations or processes described elsewhere herein.

[0206] Memory 1530 may include volatile and / or non-volatile memory. For example, memory 1530 may include random access memory (RAM), read-only memory (ROM), a hard drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1530 may include internal memory (e.g., RAM, ROM, or hard drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 1530 may be a non-temporary computer-readable medium. Memory 1530 may store information, one or more instructions, and / or software (e.g., one or more software applications) related to the operation of device 1500. In some embodiments, memory 1530 may include one or more memories such as coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1520) via bus 1510. The communicatively coupled between processor 1520 and memory 1530 may enable processor 1520 to read and / or process information stored in memory 1530 and / or store information in memory 1530.

[0207] Input assembly 1540 can enable device 1500 to receive input, such as user input and / or sensed input. For example, input assembly 1540 can include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope and / or actuator. Output assembly 1550 can enable device 1500 to provide output, such as via display, speaker and / or light emitting diode. Communication assembly 1560 can enable device 1500 to communicate with other devices via wired connection and / or wireless connection. For example, communication assembly 1560 can include receiver, transmitter, transceiver, modem, network interface card and / or antenna.

[0208] Device 1500 can implement one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1530) can store an instruction group (e.g., one or more instructions or codes) executed by processor 1520. Processor 1520 can execute the instruction group to implement one or more operations or processes described herein. In some embodiments, execution of the instruction group by one or more processors 1520 enables one or more processors 1520 and / or device 1500 to implement one or more operations or processes described herein. In some embodiments, hard-wired circuits can be used instead of instructions or in combination with instructions to implement one or more operations or processes described herein. Additionally or optionally, processor 1520 can be configured to implement one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardware circuits and software.

[0209] Fig.15 The number and arrangement of components shown in FIG. 1 are provided as examples. Device 1500 may include Fig.15 Additional components, fewer components, different components, or differently arranged components than those shown in. Additionally or alternatively, a component group (eg, one or more components) of device 1500 may implement one or more functions described as being implemented by another component group of device 1500.

[0210] Fig.16 is a flow chart of an exemplary process 1600 associated with forming a semiconductor device described herein. In some embodiments, Fig.16 One or more process blocks of are implemented using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-112). Additionally or alternatively, Fig.16One or more process blocks of may be implemented using one or more components of the device 1500 , such as the processor 1520 , the memory 1530 , the input component 1540 , the output component 1550 , and / or the communication component 1560 .

[0211] like Fig.16 As shown in , process 1600 may include forming a plurality of nanostructure channel layers arranged in a direction (z-direction) approximately perpendicular to a semiconductor substrate of a semiconductor device (block 1610). For example, one or more of semiconductor processing tools 102-112 may be used to form a plurality of nanostructure channel layers (e.g., nanostructure channels 220) arranged in a direction (e.g., z-direction) approximately perpendicular to a semiconductor substrate (e.g., semiconductor substrate 205) of a semiconductor device (e.g., semiconductor device 200), as described herein.

[0212] like Fig.16 As further shown in FIG. 1 , process 1600 may include forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers (block 1620). For example, one or more of semiconductor processing tools 102-112 may be used to form a p-type source / drain region (e.g., p-type source / drain region 225a) adjacent to the plurality of nanostructured channel layers, as described herein.

[0213] like Fig.16 As further shown in FIG. 1 , process 1600 may include forming n-type source / drain regions adjacent to the plurality of nanostructured channel layers (block 1630). For example, one or more of semiconductor processing tools 102-112 may be used to form n-type source / drain regions (e.g., n-type source / drain regions 225b) adjacent to the plurality of nanostructured channel layers, as described herein.

[0214] like Fig.16 As further shown in FIG. 1 , process 1600 may include forming a gate structure encapsulating each of the plurality of nanostructure channel layers (block 1640). For example, one or more of semiconductor processing tools 102-112 may be used to form a gate structure (e.g., gate structure 240) encapsulating each of the plurality of nanostructure channel layers, as described herein.

[0215] like Fig.16 As further shown in FIG. 1 , process 1600 may include forming a p-type metal silicide layer on the p-type source / drain region (block 1650). For example, one or more of semiconductor processing tools 102-112 may be used to form a p-type metal silicide layer (e.g., p-type metal silicide layer 1120, p-type metal silicide layer 1225) on the p-type source / drain region as described herein.

[0216] like Fig.16As further shown in FIG. 1 , process 1600 may include forming an n-type metal silicide layer on the n-type source / drain region after forming the p-type metal silicide layer on the p-type source / drain region (block 1660). For example, one or more of semiconductor processing tools 102-112 may be used to form an n-type metal silicide layer (e.g., n-type metal silicide layer 1125, n-type metal silicide layer 1230) on the n-type source / drain region after forming the p-type metal silicide layer on the p-type source / drain region, as described herein.

[0217] Process 1600 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0218] In a first embodiment, process 1600 includes: forming a first source / drain contact (e.g., source / drain contact 1140a, source / drain contact 1245a) above the p-type metal silicide layer; and forming a second source / drain contact (e.g., source / drain contact 1140b, source / drain contact 1245b) above the n-type metal silicide layer.

[0219] In a second embodiment, alone or in combination with the first embodiment, forming an n-type metal silicide layer includes forming a portion of the n-type metal silicide layer on the p-type metal silicide layer, and wherein forming a first source / drain contact includes forming a first source / drain contact above the portion of the n-type metal silicide layer located on the p-type metal silicide layer.

[0220] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming an n-type metal silicide layer includes forming a portion of the n-type metal silicide layer on the p-type metal silicide layer, wherein process 1600 also includes: removing a portion of the n-type metal silicide layer from the p-type metal silicide layer, and wherein forming a first source / drain contact includes forming a first source / drain contact after removing a portion of the n-type metal silicide layer from the p-type metal silicide layer.

[0221] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, a p-type metal silicide layer is selectively formed on a p-type source / drain region, and there is no masking layer over an n-type source / drain region. For example, the p-type metal silicide layer is formed such that the p-type metal silicide layer grows only on the p-type source / drain region, which enables the p-type metal silicide layer to be formed without using a masking layer over the n-type source / drain region. The p-type metal silicide layer can be selectively formed on the p-type source / drain region because one or more p-type metals (e.g., iridium (Ir), ruthenium (Ru), molybdenum (Mo), rhodium (Rh) and / or niobium (Nb), as well as other examples) are deposited and annealed on the p-type source / drain region to react with the material of the p-type source / drain region, wherein the one or more p-type metals do not react (or react minimally) with the material of the n-type source / drain region.

[0222] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, process 1600 includes: before forming a p-type metal silicide layer, forming a masking layer (e.g., masking layer 1220) above the n-type source / drain region, wherein forming the p-type metal silicide layer includes forming the p-type metal silicide layer when the masking layer protects the n-type source / drain region.

[0223] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, process 1600 includes: forming a capping layer (e.g., capping layer 1130, capping layer 1235) on the p-type metal silicide layer and the n-type metal silicide layer, wherein the p-type metal silicide layer, the n-type metal silicide layer, and the capping layer are all formed under the same vacuum (e.g., are all formed "in situ").

[0224] Although Fig.16 An exemplary block diagram of process 1600 is shown, but in some embodiments, process 1600 includes Fig.16 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 1600. Additionally or alternatively, two or more of the blocks of process 1600 may be implemented in parallel.

[0225] Fig.17 is a flow chart of an exemplary process 1700 associated with forming a semiconductor device described herein. In some embodiments, Fig.17 One or more process blocks of are implemented using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-112). Additionally or alternatively, Fig.17One or more process blocks of may be implemented using one or more components of the device 1500 , such as the processor 1520 , the memory 1530 , the input component 1540 , the output component 1550 , and / or the communication component 1560 .

[0226] like Fig.17 As shown in , process 1700 may include: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device (block 1710). For example, one or more of semiconductor processing tools 102-112 may be used to form a plurality of nanostructure channel layers (e.g., nanostructure channels 220) arranged in a direction approximately perpendicular to a semiconductor substrate (e.g., semiconductor substrate 205) of a semiconductor device (e.g., semiconductor device 200) (e.g., z-direction), as described herein.

[0227] like Fig.17 As further shown in FIG. 1 , process 1700 may include forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers (block 1720). For example, one or more of semiconductor processing tools 102-112 may be used to form a p-type source / drain region (e.g., p-type source / drain region 225a) adjacent to the plurality of nanostructured channel layers, as described herein.

[0228] like Fig.17 As further shown in FIG. 1 , process 1700 may include forming n-type source / drain regions adjacent to the plurality of nanostructured channel layers (block 1730). For example, one or more of semiconductor processing tools 102-112 may be used to form n-type source / drain regions (e.g., n-type source / drain regions 225b) adjacent to the plurality of nanostructured channel layers, as described herein.

[0229] like Fig.17 As further shown in FIG. 1 , process 1700 may include forming a gate structure encapsulating each of the plurality of nanostructure channel layers (block 1740). For example, one or more of semiconductor processing tools 102-112 may be used to form a gate structure (e.g., gate structure 240) encapsulating each of the plurality of nanostructure channel layers, as described herein.

[0230] like Fig.17 As further shown in FIG. 1 , process 1700 may include forming a masking layer on the p-type source / drain region (block 1750). For example, one or more of semiconductor processing tools 102-112 may be used to form a masking layer (e.g., masking layer 1420) on the p-type source / drain region as described herein.

[0231] like Fig.17As further shown in FIG. 1 , process 1700 may include forming a first metal silicide layer on the n-type source / drain region when the masking layer protects the p-type source / drain region (block 1760). For example, one or more of semiconductor processing tools 102-112 may be used to form a first metal silicide layer (e.g., n-type metal silicide layer 1425) on the n-type source / drain region when the masking layer protects the p-type source / drain region, as described herein. In some embodiments, the first metal silicide layer includes an n-type metal silicide.

[0232] like Fig.17 As further shown in FIG. 1 , process 1700 may include removing the masking layer from the p-type source / drain region after forming the first metal silicide layer (block 1770). For example, one or more of semiconductor processing tools 102-112 may be used to remove the masking layer from the p-type source / drain region after forming the first metal silicide layer, as described herein.

[0233] like Fig.17 As further shown in FIG. 1 , process 1700 may include forming a second metal silicide layer on the p-type source / drain region after removing the masking layer (block 1780). For example, one or more of semiconductor processing tools 102-112 may be used to form a second metal silicide layer (e.g., p-type metal silicide layer 1435) on the p-type source / drain region after removing the masking layer, as described herein.

[0234] Process 1700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0235] In a first embodiment, forming a masking layer includes: forming a masking layer on a p-type source / drain region and on an n-type source / drain region; and removing a first portion of the masking layer from the n-type source / drain region, wherein a second portion of the masking layer remains on the p-type source / drain region.

[0236] In a second embodiment, alone or in combination with the first embodiment, forming the second metal silicide layer includes forming the second metal silicide layer on the first metal silicide layer located on the n-type source / drain region.

[0237] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the second metal silicide layer includes a p-type metal silicide.

[0238] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the second metal silicide layer includes a titanium silicide (TiSi) layer.

[0239] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the process 1700 includes forming a titanium silicide (TiSi) layer (eg, capping layer 1430 ) on the first metal silicide layer.

[0240] Although Fig.17 An exemplary block diagram of process 1700 is shown, but in some embodiments, process 1700 includes Fig.17 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 1700. Additionally or alternatively, two or more of the blocks of process 1700 may be implemented in parallel.

[0241] Fig.18 is a flow chart of an exemplary process 1800 associated with forming a semiconductor device described herein. In some embodiments, Fig.18 One or more process blocks of are implemented using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-112). Additionally or alternatively, Fig.18 One or more process blocks of may be implemented using one or more components of the device 1500 , such as the processor 1520 , the memory 1530 , the input component 1540 , the output component 1550 , and / or the communication component 1560 .

[0242] like Fig.18 As shown in , process 1800 may include: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device (block 1810). For example, one or more of semiconductor processing tools 102-112 may be used to form a plurality of nanostructure channel layers (e.g., nanostructure channels 220) arranged in a direction approximately perpendicular to a semiconductor substrate (e.g., semiconductor substrate 205) of a semiconductor device (e.g., semiconductor device 200) (e.g., z-direction), as described herein.

[0243] like Fig.18 As further shown in FIG. 1 , process 1800 may include forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers (block 1820). For example, one or more of semiconductor processing tools 102-112 may be used to form a p-type source / drain region (e.g., p-type source / drain region 225a) adjacent to the plurality of nanostructured channel layers, as described herein.

[0244] like Fig.18As further shown in FIG. 1 , process 1800 may include forming n-type source / drain regions adjacent to the plurality of nanostructured channel layers (block 1830). For example, one or more of semiconductor processing tools 102-112 may be used to form n-type source / drain regions (e.g., n-type source / drain regions 225b) adjacent to the plurality of nanostructured channel layers, as described herein.

[0245] like Fig.18 As further shown in FIG. 1 , process 1800 may include forming a gate structure encapsulating each of the plurality of nanostructure channel layers (block 1840). For example, one or more of semiconductor processing tools 102-112 may be used to form a gate structure (e.g., gate structure 240) encapsulating each of the plurality of nanostructure channel layers, as described herein.

[0246] like Fig.18 As further shown in FIG. 1 , process 1800 may include forming a first metal silicide layer on the p-type source / drain region and on the n-type source / drain region (block 1850). For example, one or more of semiconductor processing tools 102-112 may be used to form a first metal silicide layer (e.g., first metal silicide layer 1320) on the p-type source / drain region and on the n-type source / drain region, as described herein. In some embodiments, the first metal silicide layer includes a first metal type.

[0247] like Fig.18 As further shown in FIG. 1 , process 1800 may include forming a second metal silicide layer on the first metal silicide layer over the p-type source / drain region and the n-type source / drain region (block 1860). For example, one or more of semiconductor processing tools 102-112 may be used to form a second metal silicide layer (e.g., second metal silicide layer 1325) on the first metal silicide layer over the p-type source / drain region and the n-type source / drain region, as described herein. In some embodiments, the second metal silicide layer includes a second metal type different from the first metal type.

[0248] Process 1800 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0249] In a first embodiment, the first metal type is an n-type metal and the second metal type is a p-type metal.

[0250] In a second embodiment, either alone or in combination with the first embodiment, the process 1800 includes forming a titanium silicide (TiSi) layer on the second metal silicide layer.

[0251] In a third embodiment, alone or in combination with one or more of the first and second embodiments, the p-type metal includes at least one of iridium (Ir), ruthenium (Ru), molybdenum (Mo), rhodium (Rh), or niobium (Nb).

[0252] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the n-type metal includes at least one of antimony (Sb), zirconium (Zr), yttrium (Y), or scandium (Sc).

[0253] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the first metal type is a p-type metal and the second metal type is an n-type metal.

[0254] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the process 1800 includes forming a titanium silicide (TiSi) layer on the second metal silicide layer.

[0255] Although Fig.18 An exemplary block diagram of process 1800 is shown, but in some embodiments, process 1800 includes Fig.18 Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 1800. Additionally or alternatively, two or more of the blocks of process 1800 may be implemented in parallel.

[0256] In this way, the technology described herein enables the formation of corresponding (different) types of metal silicide layers for the p-type source / drain regions and n-type source / drain regions of a nanostructure transistor for a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer can be selectively formed above the p-type source / drain region of the first nanostructure transistor (e.g., so that the p-type metal silicide layer is not formed above the n-type source / drain region), and an n-type metal silicide layer can be formed above the n-type source / drain region of the second nanostructure transistor (this can be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region and a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for the p-type source / drain region and the n-type source / drain region.

[0257] As described in more detail above, some embodiments described herein provide methods. The method includes: forming a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes: forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The method includes: forming an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The method includes: forming a gate structure that wraps each of the plurality of nanostructured channel layers. The method includes: forming a p-type metal silicide layer on the p-type source / drain region. The method includes: after forming the p-type metal silicide layer on the p-type source / drain region, forming an n-type metal silicide layer on the n-type source / drain region.

[0258] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps around each of the plurality of nanostructured channel layers. The semiconductor device includes a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes a first metal silicide layer located on the p-type source / drain region and on the n-type source / drain region, wherein the first metal silicide layer includes a first metal type. The semiconductor device includes a second metal silicide layer located on the first metal silicide layer above the p-type source / drain region and the n-type source / drain region, wherein the second metal silicide layer includes a second metal type different from the first metal type.

[0259] As described in more detail above, some embodiments described herein provide methods. The method includes: forming a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes: forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The method includes: forming an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The method includes: forming a gate structure that wraps each of the plurality of nanostructured channel layers. The method includes: forming a masking layer on the p-type source / drain region. The method includes: forming a first metal silicide layer on the n-type source / drain region when the masking layer protects the p-type source / drain region, wherein the first metal silicide layer includes an n-type metal silicide. The method includes: after forming the first metal silicide layer, removing the masking layer from the p-type source / drain region. The method includes: after removing the masking layer, forming a second metal silicide layer on the p-type source / drain region.

[0260] As described in more detail above, some embodiments described herein provide methods. The method includes: forming a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes: forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The method includes: forming an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The method includes: forming a gate structure that wraps around each of the plurality of nanostructured channel layers. The method includes: forming a first metal silicide layer on the p-type source / drain region and on the n-type source / drain region, wherein the first metal silicide layer includes a first metal type. The method includes: forming a second metal silicide layer on the first metal silicide layer above the p-type source / drain region and the n-type source / drain region, wherein the second metal silicide layer includes a second metal type different from the first metal type.

[0261] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps each of the plurality of nanostructured channel layers. The semiconductor device includes a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes a p-type metal silicide layer located on the p-type source / drain region. The semiconductor device includes an n-type metal silicide layer located on the n-type source / drain region.

[0262] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps each of the plurality of nanostructured channel layers. The semiconductor device includes a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes a p-type metal silicide layer located on the p-type source / drain region. The semiconductor device includes an n-type metal silicide layer located on the n-type source / drain region and on the p-type metal silicide layer.

[0263] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps each of the plurality of nanostructured channel layers. The semiconductor device includes a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type metal silicide layer located on the p-type source / drain region and on the n-type source / drain region. The semiconductor device includes a p-type metal silicide layer located on the n-type metal silicide layer.

[0264] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps each of the plurality of nanostructured channel layers. The semiconductor device includes a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes a p-type metal silicide layer located on the p-type source / drain region and on the n-type source / drain region. The semiconductor device includes an n-type metal silicide layer located on the p-type metal silicide layer.

[0265] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to the semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps each of the plurality of nanostructured channel layers. The semiconductor device includes a p-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type source / drain region adjacent to the plurality of nanostructured channel layers. The semiconductor device includes an n-type metal silicide layer located on the n-type source / drain region. The semiconductor device includes a p-type metal silicide layer located on the p-type source / drain region and on the n-type metal silicide layer.

[0266] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructure channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructure channel layers; forming a gate structure wrapping each of the plurality of nanostructure channel layers; forming a p-type metal silicide layer on the p-type source / drain region; and after forming the p-type metal silicide layer on the p-type source / drain region, forming an n-type metal silicide layer on the n-type source / drain region.

[0267] In some embodiments, the method further comprises: forming a first source / drain contact over the p-type metal silicide layer; and forming a second source / drain contact over the n-type metal silicide layer. In some embodiments, forming the n-type metal silicide layer comprises: forming a portion of the n-type metal silicide layer over the p-type metal silicide layer; and wherein forming the first source / drain contact comprises: forming the first source / drain contact over the portion of the n-type metal silicide layer over the p-type metal silicide layer. In some embodiments, forming the n-type metal silicide layer comprises: forming a portion of the n-type metal silicide layer over the p-type metal silicide layer; wherein the method further comprises: removing the portion of the n-type metal silicide layer from the p-type metal silicide layer; and wherein forming the first source / drain contact comprises: forming the first source / drain contact after removing the portion of the n-type metal silicide layer from the p-type metal silicide layer. In some embodiments, the p-type metal silicide layer is selectively formed on the p-type source / drain region, and there is no masking layer on the n-type source / drain region. In some embodiments, the method further includes: before forming the p-type metal silicide layer, forming a masking layer above the n-type source / drain region, wherein forming the p-type metal silicide layer includes: forming the p-type metal silicide layer when the masking layer protects the n-type source / drain region. In some embodiments, the method further includes: forming a capping layer on the p-type metal silicide layer and on the n-type metal silicide layer, wherein the p-type metal silicide layer, the n-type metal silicide layer, and the capping layer are all formed under the same vacuum.

[0268] Some other embodiments of the present application provide a semiconductor device, comprising: a plurality of nanostructured channel layers, the plurality of nanostructured channel layers being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructured channel layers; a p-type source / drain region adjacent to the plurality of nanostructured channel layers; an n-type source / drain region adjacent to the plurality of nanostructured channel layers; a first metal silicide layer located on the p-type source / drain region and on the n-type source / drain region, wherein the first metal silicide layer comprises a first metal type; and a second metal silicide layer located on the first metal silicide layer above the p-type source / drain region and the n-type source / drain region, wherein the second metal silicide layer comprises a second metal type different from the first metal type.

[0269] In some embodiments, the first metal type is an n-type metal; and wherein the second metal type is a p-type metal. In some embodiments, the semiconductor device further comprises: a titanium silicide (TiSi) layer located on the second metal silicide layer. In some embodiments, the p-type metal comprises at least one of the following metals: iridium (Ir); ruthenium (Ru); molybdenum (Mo); rhodium (Rh); or niobium (Nb). In some embodiments, the n-type metal comprises at least one of the following metals: antimony (Sb); zirconium (Zr); yttrium (Y); or scandium (Sc). In some embodiments, the first metal type is a p-type metal; and wherein the second metal type is an n-type metal. In some embodiments, the semiconductor device further comprises: a titanium silicide (TiSi) layer located on the second metal silicide layer.

[0270] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructure channel layers; forming an n-type source / drain region adjacent to the plurality of nanostructure channel layers; forming a gate structure wrapping each of the plurality of nanostructure channel layers; forming a masking layer on the p-type source / drain region; forming a first metal silicide layer on the n-type source / drain region when the masking layer protects the p-type source / drain region, wherein the first metal silicide layer comprises an n-type metal silicide; after forming the first metal silicide layer, removing the masking layer from the p-type source / drain region; and after removing the masking layer, forming a second metal silicide layer on the p-type source / drain region.

[0271] In some embodiments, forming the shielding layer comprises: forming the shielding layer on the p-type source / drain region and on the n-type source / drain region; and removing a first portion of the shielding layer from the n-type source / drain region, wherein a second portion of the shielding layer remains on the p-type source / drain region. In some embodiments, forming the second metal silicide layer comprises: forming the second metal silicide layer on the first metal silicide layer located on the n-type source / drain region. In some embodiments, the second metal silicide layer comprises a p-type metal silicide. In some embodiments, the second metal silicide layer comprises titanium silicide (TiSi). In some embodiments, the method further comprises: forming a titanium silicide (TiSi) layer on the first metal silicide layer.

[0272] The terms "approximately" and "substantially" may refer to a value of a given amount or magnitude that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that in view of the embodiments of the present disclosure, the terms "approximately" and "substantially" may refer to a percentage of a value of a given amount.

[0273] As used herein, "satisfying a threshold" may (depending on the context) refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, etc.

[0274] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers; forming n-type source / drain regions adjacent to the plurality of nanostructured channel layers; forming a gate structure encapsulating each of the plurality of nanostructured channel layers; forming a p-type metal silicide layer on the p-type source / drain region; as well as After forming the p-type metal silicide layer on the p-type source / drain region, an n-type metal silicide layer is formed on the n-type source / drain region.

2. The method according to claim 1, further comprising: forming a first source / drain contact above the p-type metal silicide layer; as well as A second source / drain contact is formed over the n-type metal silicide layer.

3. The method according to claim 2, wherein: Forming the n-type metal silicide layer comprises: forming a portion of the n-type metal silicide layer on the p-type metal silicide layer; and Wherein, forming the first source / drain contact comprises: The first source / drain contact is formed over the portion of the n-type metal silicide layer that is located on the p-type metal silicide layer.

4. The method according to claim 2, wherein: Forming the n-type metal silicide layer comprises: forming a portion of the n-type metal silicide layer on the p-type metal silicide layer; Wherein, the method further comprises: removing the portion of the n-type metal silicide layer from the p-type metal silicide layer; and Wherein, forming the first source / drain contact comprises: The first source / drain contacts are formed after removing the portion of the n-type metal silicide layer from the p-type metal silicide layer.

5. The method according to claim 1, wherein: The p-type metal silicide layer is selectively formed on the p-type source / drain region, and there is no masking layer on the n-type source / drain region.

6. The method according to claim 1, further comprising: Before forming the p-type metal silicide layer, a masking layer is formed above the n-type source / drain region. Wherein, forming the p-type metal silicide layer comprises: The p-type metal silicide layer is formed while the masking layer protects the n-type source / drain region.

7. The method according to claim 1, further comprising: forming a capping layer on the p-type metal silicide layer and the n-type metal silicide layer, The p-type metal silicide layer, the n-type metal silicide layer and the capping layer are all formed under the same vacuum.

8. A semiconductor device comprising: a plurality of nanostructured channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructured channel layers; a p-type source / drain region adjacent to the plurality of nanostructure channel layers; an n-type source / drain region adjacent to the plurality of nanostructure channel layers; a first metal silicide layer, located on the p-type source / drain region and the n-type source / drain region, wherein the first metal silicide layer comprises a first metal type; and a second metal silicide layer, located on the first metal silicide layer above the p-type source / drain region and the n-type source / drain region, The second metal silicide layer includes a second metal type different from the first metal type.

9. The semiconductor device according to claim 8, wherein: The first metal type is an n-type metal; and Wherein, the second metal type is a p-type metal.

10. A method of forming a semiconductor device, comprising: forming a plurality of nanostructure channel layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device; forming a p-type source / drain region adjacent to the plurality of nanostructured channel layers; forming n-type source / drain regions adjacent to the plurality of nanostructured channel layers; forming a gate structure encapsulating each of the plurality of nanostructured channel layers; forming a masking layer on the p-type source / drain region; When the masking layer protects the p-type source / drain region, a first metal silicide layer is formed on the n-type source / drain region, Wherein, the first metal silicide layer comprises n-type metal silicide; After forming the first metal silicide layer, removing the masking layer from the p-type source / drain region; as well as After removing the masking layer, a second metal silicide layer is formed on the p-type source / drain region.

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