Semiconductor structure and forming method thereof
By introducing a resistive layer into the semiconductor structure and connecting it to the capacitor structure, the problem of insufficient performance of the existing MIM capacitors is solved, and the characteristic impedance of the circuit and the yield of the die are improved.
Patent Information
- Application Number
- CN202311036138.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-16
- Publication Date
- 2025-02-25
AI Technical Summary
The performance of existing MIM capacitors needs to be improved, especially in terms of high capacitance density, voltage linearity, precise capacitance value control and high reliability.
A semiconductor structure is designed, including a substrate, a capacitance region and a resistive region. A multi-layered capacitance structure is formed on the capacitance region, and a resistive layer connected to the capacitance structure is formed on the resistive region.
By introducing a resistor layer, the voltage-regulating circuit needs for precision resistance is met, the distance between the resistor region and the capacitance region is reduced, the distributed inductance and distributed capacitance value is reduced, the characteristic impedance of the circuit is improved, the possibility of system reflection and oscillation is reduced, and the performance of the semiconductor structure and the yield of the die are improved.
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Figure CN119521758A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] Capacitors are passive components commonly used in VLSI. Capacitors mainly include polysilicon-insulator-polysilicon (PIP) capacitors, metal-insulator-silicon (MIS) capacitors, and metal-insulator-metal (MIM) capacitors.
[0003] With the rapid development of wireless communication technology, people hope to implant high-performance decoupling and bypass capacitors suitable for the system on chip (SoC) into the metal interconnection process of the integrated circuit to obtain a powerful RF system. This requires that the implanted capacitor should have high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability. MIM capacitors cause little interference to transistors and can provide better linearity and symmetry. Therefore, the use of MIM capacitors will be the development trend of RF and analog / mixed signal integrated circuits.
[0004] However, the performance of the MIM capacitor formed by the prior art needs to be improved. Summary of the invention
[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.
[0006] To solve the above problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including a capacitor region and a resistor region adjacent to the capacitor region; a capacitor structure located on the capacitor region, the capacitor structure including a plurality of first electrode layers, a plurality of second electrode layers and a plurality of dielectric layers, the second electrode layer being located between two adjacent first electrode layers, and each dielectric layer being located between adjacent first electrode layers and second electrode layers; and at least one resistor layer located on the resistor region, each resistor layer being connected to a first electrode layer or a second electrode layer.
[0007] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a capacitor region and a resistor region adjacent to the capacitor region; forming a capacitor structure on the capacitor region, the capacitor structure including a plurality of first electrode layers, a plurality of second electrode layers and a plurality of dielectric layers, the second electrode layer is located between two adjacent first electrode layers, and each dielectric layer is located between adjacent first electrode layers and second electrode layers; forming at least one resistor layer on each resistor region, and each resistor layer is connected to a first electrode layer or a second electrode layer.
[0008] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0009] In the semiconductor structure of the technical solution of the present invention, each resistance layer is connected to a first electrode layer or a second electrode layer of the capacitor area. On the one hand, the resistance layer is introduced while retaining the capacitor structure, thereby meeting the demand of the voltage stabilizing circuit for precision resistors; on the other hand, the resistance layer in the semiconductor structure is connected to the first electrode layer and the second electrode layer of the capacitor structure, thereby reducing the distance between the resistance area and the capacitor area, thereby reducing the distance between the leads, reducing the distributed inductance and distributed capacitance values, improving the characteristic impedance of the circuit, reducing the possibility of reflection and oscillation in the system, improving the performance of the semiconductor structure, and improving the yield of wafer production.
[0010] In the method for forming a semiconductor structure of the technical solution of the present invention, each resistance layer is connected to a first electrode layer or a second electrode layer in the capacitor area. On the one hand, the resistance layer is introduced while retaining the capacitor structure, thereby meeting the demand for precision resistors in the voltage stabilizing circuit; on the other hand, the resistance layer in the semiconductor structure is connected to the first electrode layer and the second electrode layer of the capacitor structure, thereby reducing the distance between the resistance area and the capacitor area, thereby reducing the distance between the leads, reducing the distributed inductance and distributed capacitance values, improving the characteristic impedance of the circuit, reducing the possibility of reflection and oscillation in the system, improving the performance of the semiconductor structure, and improving the yield of wafer production. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figures 1 to 13 is a schematic cross-sectional structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention;
[0012] Figures 14 to 25 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION
[0013] As the background technology, the performance of the MIM capacitor formed by the prior art needs to be improved.
[0014] On the one hand, in the voltage stabilization circuit, in addition to high-density capacitors, precision resistors are also required; on the other hand, from the circuit point of view, the closer the distance between the capacitor and the resistor, the better the consistency between the produced chip and the designed simulation chip.
[0015] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein each resistance layer is connected to a first electrode layer or a second electrode layer in a capacitor region. On the one hand, the resistance layer is introduced while retaining the capacitor structure, thereby satisfying the demand for precision resistors in a voltage stabilizing circuit; on the other hand, the resistance layer in the semiconductor structure is connected to the first electrode layer and the second electrode layer of the capacitor structure, thereby reducing the distance between the resistance region and the capacitor region, thereby reducing the distance between the leads, reducing the distributed inductance and distributed capacitance values, improving the characteristic impedance of the circuit, reducing the possibility of reflection and oscillation in the system, improving the performance of the semiconductor structure, and improving the yield of wafer fabrication.
[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0017] Figures 1 to 13 It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.
[0018] Please refer to Figure 1 , providing a substrate 100, the substrate 100 includes a capacitor region I and a resistor region II adjacent to the capacitor region I.
[0019] The material of the substrate 100 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.
[0020] Capacitor region I is used to form a capacitor structure 101 (such as Figure 7 Provides a structural basis.
[0021] The resistance region II is used for forming the resistance layer 105 (such as Figure 2 Provides a structural basis.
[0022] The substrate 100 further includes a first connection region III, and the resistance region II is located between the capacitance region I and the first connection region III.
[0023] Specifically, in this embodiment, the substrate 100 has a plurality of third interconnection layers 116 and a fourth interconnection layer 117 .
[0024] In this embodiment, the substrate 100 further has a plurality of device structures (not shown), and the third interconnection layer 116 and the fourth interconnection layer 117 are electrically connected to the plurality of device structures (not shown), respectively.
[0025] In this embodiment, a capacitor structure 101 is subsequently formed on the capacitor region I. The capacitor structure 101 includes a plurality of first electrode layers 102 (eg, Figure 7 As shown), a plurality of second electrode layers 103 (as Figure 7 ) and several dielectric layers 104 (as shown Figure 7 As shown), the second electrode layer 103 is located between two adjacent first electrode layers 102, and each dielectric layer 104 is located between the adjacent first electrode layer 102 and the second electrode layer 103; at least one resistance layer 105 (as shown) is formed on each resistance region II Figure 7 As shown in FIG. 1 , each resistor layer 105 is connected to any first electrode layer 102. In this embodiment, a resistor layer 105 is formed, and the resistor layer 105 is connected to the bottom first electrode layer 102. The formation process of the capacitor structure 101 and the resistor layer 105 can be referred to in Figures 2 to 13 .
[0026] Please refer to Figure 2 and Figure 3 , Figure 2 yes Figure 3 A top view of Figure 3 yes Figure 2 A schematic cross-sectional structure diagram along the AA' direction shows that a first electrode layer 102 and a resistor layer 105 are formed on a substrate 100, the first electrode layer 102 is located on the capacitor region I, and the resistor layer 105 is located on the resistor region II; a dielectric layer 104 is formed on the first electrode layer 102 and the resistor layer 105. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0027] The first electrode layer 102 has a plurality of third openings 106. The third conductive plugs 111 (eg Fig.10 As shown in FIG. 1 , the third opening 106 is penetrated by the third opening 106 , and the distance from the sidewall of the third opening 106 to the third conductive plug 111 is greater than 0.
[0028] Specifically, in this embodiment, the resistance layer 105 is also located on the first connection region III.
[0029] The formation process of the first electrode layer 102 and the resistance layer 105 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0030] In this embodiment, the first electrode layer 102 and the resistance layer 105 are formed by an atomic layer deposition process.
[0031] The material of the first electrode layer 102 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0032] The material of the resistance layer 105 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0033] Specifically, in this embodiment, the thickness range of the first electrode layer 102 is
[0034] Specifically, in this embodiment, the thickness range of the resistor layer 105 is
[0035] The dielectric layer 104 may be formed by an atomic layer deposition process, a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, a sputtering deposition process, an ion beam deposition process or an ion beam assisted deposition process.
[0036] In this embodiment, the dielectric layer 104 is formed by an atomic layer deposition process.
[0037] The function of the dielectric layer 104 is to isolate the adjacent first electrode layer 102 and the second electrode layer 103 ; the material of the dielectric layer 104 includes: hafnium oxide, zirconium oxide, lanthanum oxide or aluminum oxide.
[0038] In other embodiments, multiple resistance layers can be formed, and each resistance layer is connected to any first electrode layer.
[0039] At least one second electrode layer 103 and at least one first electrode layer 102 are formed on the first electrode layer 102 to form a capacitor structure 101. The capacitor structure 101 includes a plurality of first electrode layers 102, a plurality of second electrode layers 103 and a plurality of dielectric layers 104. The second electrode layer 103 is located between two adjacent first electrode layers 102. There is a dielectric layer 104 between adjacent first electrode layers 102 and second electrode layers 103. For details, please refer to Figures 4 to 7 .
[0040] Please refer to Figure 4 and Figure 5 , Figure 4 yes Figure 5 A top view of Figure 5 yes Figure 4 The cross-sectional structure diagram along the AA' direction shows that a second electrode layer 103 is formed on the first electrode layer 102, and a dielectric layer 104 is formed on the second electrode layer 103. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0041] The second electrode layer 103 has a plurality of first openings 107 (eg Fig.10 The second conductive plug 110 (as shown) formed subsequently Fig.10 As shown in FIG. 1 , the first opening 107 is penetrated by the first opening 107 , and the distance from the sidewall of the first opening 107 to the second conductive plug 110 is greater than 0.
[0042] The formation process of the second electrode layer 103 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0043] In this embodiment, the second electrode layer 103 is formed by an atomic layer deposition process.
[0044] The material of the second electrode layer 103 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0045] Specifically, in this embodiment, the thickness range of the second electrode layer 103 is
[0046] The dielectric layer 104 may be formed by an atomic layer deposition process, a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, a sputtering deposition process, an ion beam deposition process or an ion beam assisted deposition process.
[0047] In this embodiment, the dielectric layer 104 is formed by an atomic layer deposition process.
[0048] The function of the dielectric layer 104 is to isolate the adjacent first electrode layer 102 and the second electrode layer 103 ; the material of the dielectric layer 104 includes: hafnium oxide, zirconium oxide, lanthanum oxide or aluminum oxide.
[0049] Please refer to Figure 6 and Figure 7 , Figure 6 yes Figure 7 A top view of Figure 7 yes Figure 6 The schematic cross-sectional structure diagram along the AA' direction shows that the first electrode layer 102 is formed on the second electrode layer 103. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0050] The first electrode layer 102 has a plurality of third openings 106. The third conductive plugs 111 (eg Fig.10 As shown in FIG. 1 , the third opening 106 is penetrated by the third opening 106 , and the distance from the sidewall of the third opening 106 to the third conductive plug 111 is greater than 0.
[0051] The formation process of the first electrode layer 102 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0052] In this embodiment, the first electrode layer 102 is formed by an atomic layer deposition process.
[0053] The material of the first electrode layer 102 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0054] Specifically, in this embodiment, the thickness range of the first electrode layer 102 is
[0055] Please refer to Figure 8 and Fig. 9 , Figure 8 yes Fig. 9 A top view of Fig. 9 yes Figure 8 The cross-sectional structure diagram along the AA' direction shows that a dielectric layer 108 is formed on the substrate 100, and the dielectric layer 108 covers each first electrode layer 102, each second electrode layer 103 and each dielectric layer 104. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0056] The depth of the dielectric layer 108 determines the depth of the first conductive plug 109 (eg Fig.11 As shown), the second conductive plug 110 (as Fig.11 As shown) and the third conductive plug 111 (as shown Fig.11 shown) depth.
[0057] Please refer to Fig.10 and Fig.11 , Fig.10 yes Fig.11 A top view of Fig.11 yes Fig.10 The schematic cross-sectional structure diagram along the AA' direction shows that after forming the dielectric layer 108, a first conductive plug 109 is formed on the first connection region III, the first conductive plug 109 penetrates the resistor layer 105 and is electrically connected to the resistor layer 105; a second conductive plug 110 is formed on the capacitor region I, the second conductive plug 110 penetrates the capacitor structure 101. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0058] When the resistance layer 105 is connected to the first electrode layer 102 , the second conductive plug 110 is connected to the first electrode layer 102 , and the second conductive plug 110 is electrically insulated from the second electrode layer 103 .
[0059] The second electrode layer 103 has a plurality of first openings 107 . The second conductive plugs 110 penetrate through the first openings 107 . A distance s from the sidewall of the first opening 107 to the second conductive plugs 110 is greater than 0.
[0060] When the resistance layer 105 is connected to the first electrode layer 102 , the third conductive plug 111 is connected to the second electrode layer 103 , and the third conductive plug 111 is electrically insulated from the first electrode layer 102 .
[0061] The first electrode layer 102 has a plurality of third openings 106 . The third conductive plugs 111 penetrate through the third openings 106 . A distance s from the sidewall of the third opening 106 to the third conductive plugs 111 is greater than 0.
[0062] The method for forming the first conductive plug 109 includes: forming a first mask layer (not shown) on the surface of the dielectric layer 108, wherein the first mask layer (not shown) exposes a portion of the surface of the dielectric layer 108; using the first mask layer (not shown) as a mask, etching the dielectric layer 108, the resistor layer 105 and the substrate 100 to form a first through hole (not shown); and forming the first conductive plug 109 in the first through hole (not shown).
[0063] The material of the first conductive plug 109 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0064] The method for forming the second conductive plug 110 includes: forming a second mask layer (not shown) on the surface of the dielectric layer 108, the second mask layer (not shown) exposing a portion of the surface of the dielectric layer 108; using the second mask layer (not shown) as a mask, etching the dielectric layer 108, the capacitor structure 101 and the substrate 100 until the surface of the third interconnect layer 116 is exposed to form a second through hole (not shown); and forming the second conductive plug 110 in the second through hole (not marked).
[0065] The material of the second conductive plug 110 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0066] The method for forming the third conductive plug 111 includes: forming a third mask layer (not shown) on the surface of the dielectric layer 108, the third mask layer (not shown) exposing a portion of the surface of the dielectric layer 108; using the third mask layer (not shown) as a mask, etching the dielectric layer 108, the capacitor structure 101 and the substrate 100 until the surface of the fourth interconnect layer 117 is exposed to form a third through hole (not shown); and forming the third conductive plug 111 in the third through hole (not shown).
[0067] The material of the third conductive plug 111 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0068] Please refer to Fig.12 and Fig.13 , Fig.12 yes Fig.13 A top view of Fig.13 yes Fig.12The cross-sectional structure diagram along the AA' direction forms a first conductive layer 112 located on the top surface of the first conductive plug 109, a second conductive layer 113 located on the top surface of the second conductive plug 110, and a fourth conductive layer (not shown) located on the third conductive plug 111. The substrate 100 and the dielectric layer 108 are not shown in the top view of the drawings of this embodiment.
[0069] The first conductive plug 109 is electrically connected to the first conductive layer 112 ; the second conductive plug 110 is electrically connected to the second conductive layer 113 .
[0070] Specifically, in this embodiment, the method further includes: forming a plurality of first interconnection layers 114 on the capacitor structure 101 , each of the first interconnection layers 114 being connected to a plurality of second conductive plugs 110 . The second conductive layer 113 is connected to the first interconnection layer 114 .
[0071] In this embodiment, the method further includes forming a plurality of second interconnection layers 115 on the capacitor structure 101. Each second interconnection layer 115 is connected to a plurality of third conductive plugs 111, and the second interconnection layer 115 and the first interconnection layer 114 are parallel to each other.
[0072] Specifically, in this embodiment, the capacitor structure 101 is located on the third interconnect layer 116 and the fourth interconnect layer 117, each third interconnect layer 116 is connected to a plurality of second conductive plugs 110, each fourth interconnect layer 117 is connected to a plurality of third conductive plugs 111, the third interconnect layer 116 and the fourth interconnect layer 117 are parallel to each other, and the third interconnect layer 116 and the fourth interconnect layer 117 are not parallel to the first interconnect layer 114 or the second interconnect layer 115.
[0073] In this embodiment, the resistance layer 105 is connected to the first electrode layer 102 of the capacitor area I. On the one hand, the resistance layer 105 is introduced while retaining the capacitor structure 101, thereby meeting the demand of the voltage stabilization circuit for precision resistors. On the other hand, the resistance layer 105 in the semiconductor structure is connected to the first electrode layer 102 of the capacitor structure 101, thereby reducing the distance between the resistance area II and the capacitor area I, thereby reducing the distance of the leads, reducing the distributed inductance and distributed capacitance values, improving the characteristic impedance of the circuit, reducing the possibility of reflection and oscillation in the system, improving the performance of the semiconductor structure, and improving the yield of wafer fabrication.
[0074] Figures 14 to 25 1 is a schematic cross-sectional view of a semiconductor structure forming process according to another embodiment of the present invention. The top view of the embodiment of the present invention does not show the substrate 100.
[0075] In this embodiment, the formation process of the semiconductor structure is further described on the basis of the above embodiment, and the rest is the same as the above embodiment, except that: in this embodiment, a resistor layer 105 is formed, and the resistor layer 105 is connected to the second electrode layer 103. The following will be described in detail with reference to the accompanying drawings.
[0076] Please refer to Fig.15 , providing a substrate 100, the substrate 100 includes a capacitor region I and a resistor region II adjacent to the capacitor region I.
[0077] The material of the substrate 100 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.
[0078] Capacitor region I is used to form a capacitor structure 101 (such as Fig.19 Provides a structural basis.
[0079] The resistance region II is used for forming the resistance layer 105 (such as Fig.19 Provides a structural basis.
[0080] The substrate 100 further includes a first connection region III, and the resistance region II is located between the capacitance region I and the first connection region III.
[0081] Specifically, in this embodiment, the substrate 100 has a plurality of seventh interconnection layers 118 and eighth interconnection layers 119 .
[0082] In this embodiment, the substrate 100 further has a plurality of device structures (not shown), and the seventh interconnection layer 118 and the eighth interconnection layer 119 are electrically connected to the plurality of device structures (not shown), respectively.
[0083] In this embodiment, a capacitor structure 101 is subsequently formed on the capacitor region I. The capacitor structure 101 includes a plurality of first electrode layers 102 (eg, Fig.19 As shown), a plurality of second electrode layers 103 (as Fig.19 ) and several dielectric layers 104 (as shown Fig.19 As shown), the second electrode layer 103 is located between two adjacent first electrode layers 102, and each dielectric layer 104 is located between the adjacent first electrode layer 102 and the second electrode layer 103; at least one resistance layer 105 (as shown) is formed on each resistance region II Fig.19 As shown), each resistor layer 105 is connected to any second electrode layer 103.
[0084] In this embodiment, a resistor layer 105 is formed, and the resistor layer 105 is connected to the second electrode layer 103. The formation process of the capacitor structure 101 and the resistor layer 105 can be referred to Figures 14 to 25 .
[0085] Please refer to Fig.14 and Fig.15 , Fig.14 yes Fig.15 A top view of Fig.15 yes Fig.14 The cross-sectional structure diagram along the BB' direction shows that a first electrode layer 102 is formed on the substrate 100, and the first electrode layer 102 is located on the capacitor region I; a dielectric layer 104 is formed on the first electrode layer 102. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0086] The first electrode layer 102 has a plurality of second openings 120. The second conductive plugs 110 (eg Fig. 22 As shown in the figure, the second opening 120 is penetrated, and the distance from the sidewall of the second opening 120 to the second conductive plug 110 is greater than 0.
[0087] The formation process of the first electrode layer 102 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0088] In this embodiment, the first electrode layer 102 is formed by an atomic layer deposition process.
[0089] The material of the first electrode layer 102 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0090] Specifically, in this embodiment, the thickness of the first electrode layer 102 is in the range of
[0091] Specifically, in this embodiment, the dielectric layer 104 is also formed on the surfaces of the resistance region II and the first connection region III.
[0092] The dielectric layer 104 may be formed by an atomic layer deposition process, a plasma chemical vapor deposition process, a low pressure chemical vapor deposition process, a sputtering deposition process, an ion beam deposition process or an ion beam assisted deposition process.
[0093] In this embodiment, the dielectric layer 104 is formed by an atomic layer deposition process.
[0094] The function of the dielectric layer 104 is to isolate the adjacent first electrode layer 102 and the second electrode layer 103 ; the material of the dielectric layer 104 includes: hafnium oxide, zirconium oxide, lanthanum oxide or aluminum oxide.
[0095] A second electrode layer 103 and a resistor layer 105 are formed on the first electrode layer 102, and at least one first electrode layer 102 is located on the second electrode layer 103 to form a capacitor structure 101. The second electrode layer 103 is located on the capacitor region I, and the resistor layer 105 is located on the resistor region II. The capacitor structure 101 includes a plurality of first electrode layers 102, a plurality of second electrode layers 103, and a plurality of dielectric layers 104. The second electrode layer 103 is located between two adjacent first electrode layers 102, and a dielectric layer 104 is provided between adjacent first electrode layers 102 and second electrode layers 103. For details, please refer to Figures 16 to 19 .
[0096] Please refer to Fig.16 and Fig.17 , Fig.16 yes Fig.17 A top view of Fig.17 yes Fig.16 The cross-sectional structure diagram along the BB' direction shows that a second electrode layer 103 and a resistor layer 105 are formed on the first electrode layer 102, and a dielectric layer 104 is formed on the second electrode layer 103. The substrate 100 and the dielectric layer 104 are not shown in the top view of the drawings of this embodiment.
[0097] The second electrode layer 103 has a plurality of fourth openings 121. The third conductive plugs 111 formed subsequently penetrate the fourth openings 121, and the sidewalls of the fourth openings 121 extend to the third conductive plugs 111 (eg, Fig. 22 The distance shown) is greater than 0.
[0098] Specifically, in this embodiment, the second electrode layer 103 is located on the capacitor region I, and the resistor layer 105 is located on the resistor region II.
[0099] Specifically, in this embodiment, the resistance layer 105 is also located on the first connection region III.
[0100] The formation process of the second electrode layer 103 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0101] In this embodiment, the second electrode layer 103 is formed by an atomic layer deposition process.
[0102] The material of the second electrode layer 103 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0103] Specifically, in this embodiment, the thickness range of the second electrode layer 103 is
[0104] The formation process of the resistance layer 105 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0105] In this embodiment, the resistance layer 105 is formed by an atomic layer deposition process.
[0106] The material of the resistance layer 105 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0107] Specifically, in this embodiment, the thickness range of the resistor layer 105 is
[0108] In other embodiments, multiple resistance layers can be formed, and each resistance layer is connected to any second electrode layer.
[0109] Please refer to Fig.18 and Fig.19 , Fig.18 yes Fig.19 A top view of Fig.19 yes Fig.18 The cross-sectional structure diagram along the BB' direction shows that at least one first electrode layer 102 is formed on the second electrode layer 103. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0110] The first electrode layer 102 has a plurality of second openings 120. The second conductive plugs 110 (eg Fig. 22 As shown in the figure, the second opening 120 is penetrated, and the distance from the sidewall of the second opening 120 to the second conductive plug 110 is greater than 0.
[0111] The formation process of the first electrode layer 102 includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.
[0112] In this embodiment, the first electrode layer 102 is formed by an atomic layer deposition process.
[0113] The material of the first electrode layer 102 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0114] Specifically, in this embodiment, the thickness range of the first electrode layer 102 is
[0115] Please refer to Fig. 20 and Fig.21 , Fig. 20 yes Fig.21 A top view of Fig.21 yes Fig. 20 The cross-sectional structural diagram along the BB′ direction shows that a dielectric layer 108 is formed on the substrate 100 , and the dielectric layer 108 covers each first electrode layer 102 , each second electrode layer 103 , and each dielectric layer 104 .
[0116] The depth of the dielectric layer 108 determines the depth of the first conductive plug 109 (eg Fig.23 As shown), the second conductive plug 110 (as Fig.23 As shown) and the third conductive plug 111 (as shown Fig.23 shown) depth.
[0117] Please refer to Fig. 22 and Fig.23 , Fig. 22 yes Fig.23 A top view of Fig.23 yes Fig. 22 The schematic cross-sectional structure diagram along the BB' direction shows that after forming the dielectric layer 108, a first conductive plug 109 is formed on the first connection region III, the first conductive plug 109 penetrates the resistor layer 105 and is electrically connected to the resistor layer 105; a second conductive plug 110 is formed on the capacitor region I, the second conductive plug 110 penetrates the capacitor structure 101. The substrate 100 and the dielectric layer 104 are not shown in the top view of the accompanying drawings of this embodiment.
[0118] When the resistance layer 105 is connected to the second electrode layer 103 , the second conductive plug 110 is connected to the second electrode layer 103 , and the second conductive plug 110 is electrically insulated from the first electrode layer 102 .
[0119] The first electrode layer 102 has a plurality of second openings 120 . The second conductive plugs 110 penetrate through the second openings 120 . A distance s from the sidewall of the second opening 120 to the second conductive plugs 110 is greater than zero.
[0120] When the resistance layer 105 is connected to the second electrode layer 103 , the third conductive plug 111 is connected to the first electrode layer 102 , and the third conductive plug 111 is electrically insulated from the second electrode layer 103 .
[0121] The second electrode layer 102 has a plurality of fourth openings 121 . The third conductive plugs 111 penetrate through the fourth openings 121 . A distance s from the sidewall of the fourth opening 121 to the third conductive plugs 111 is greater than 0.
[0122] The method for forming the first conductive plug 109 includes: forming a first mask layer (not shown) on the surface of the dielectric layer 108, wherein the first mask layer (not shown) exposes a portion of the surface of the dielectric layer 108; using the first mask layer (not shown) as a mask, etching the dielectric layer 108, the resistor layer 105 and the substrate 100 to form a first through hole (not shown); and forming the first conductive plug 109 in the first through hole (not shown).
[0123] The material of the first conductive plug 109 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0124] The method for forming the second conductive plug 110 includes: forming a second mask layer (not shown) on the surface of the dielectric layer 108, the second mask layer (not shown) exposing a portion of the surface of the dielectric layer 108; using the second mask layer (not shown) as a mask, etching the dielectric layer 108, the capacitor structure 101 and the substrate 100 until the surface of the seventh interconnect layer 118 is exposed to form a second through hole (not shown); and forming the second conductive plug 110 in the second through hole (not marked).
[0125] The material of the second conductive plug 110 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0126] The method for forming the third conductive plug 111 includes: forming a third mask layer (not shown) on the surface of the dielectric layer 108, the third mask layer (not shown) exposing a portion of the surface of the dielectric layer 108; using the third mask layer (not shown) as a mask, etching the dielectric layer 108, the capacitor structure 101 and the substrate 100 until the surface of the eighth interconnection layer 119 is exposed to form a third through hole (not shown); and forming the third conductive plug 111 in the third through hole (not shown).
[0127] The material of the third conductive plug 111 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0128] Please refer to Fig.24 and Fig.25 , Fig.24 yes Fig.25 A top view of Fig.25 yes Fig.24 The cross-sectional structure diagram along the BB' direction forms a first conductive layer 112 located on the top surface of the first conductive plug 109, a third conductive layer 123 located on the top surface of the second conductive plug 110, and a fifth conductive layer (not shown) located on the third conductive plug 111. The substrate 100 and the dielectric layer 108 are not shown in the top view of the drawings of this embodiment.
[0129] The first conductive plug 109 is electrically connected to the first conductive layer 112 ; the second conductive plug 110 is electrically connected to the third conductive layer 123 .
[0130] Specifically, in this embodiment, the method further includes: forming a plurality of fifth interconnect layers 122 on the capacitor structure 101 , each of the fifth interconnect layers 122 being connected to a plurality of second conductive plugs 110 . The third conductive layer 123 is connected to the fifth interconnect layer 122 .
[0131] In this embodiment, the method further includes forming a plurality of sixth interconnection layers 124 on the capacitor structure 101. Each sixth interconnection layer 124 is connected to a plurality of third conductive plugs 111, and the sixth interconnection layer 124 and the fifth interconnection layer 122 are parallel to each other.
[0132] Specifically, in the present embodiment, the capacitor structure 101 is located on the seventh interconnect layer 118 and the eighth interconnect layer 119, each seventh interconnect layer 118 is connected to a plurality of second conductive plugs 110, each eighth interconnect layer 119 is connected to a plurality of third conductive plugs 111, the seventh interconnect layer 118 and the eighth interconnect layer 119 are parallel to each other, and the seventh interconnect layer 118 and the eighth interconnect layer 119 are not parallel to the fifth interconnect layer 122 or the sixth interconnect layer 124.
[0133] In this embodiment, the resistance layer 105 is connected to the second electrode layer 103 of the capacitor area I. On the one hand, the resistance layer 105 is introduced while retaining the capacitor structure 101, thereby meeting the demand of the voltage stabilization circuit for precision resistance. On the other hand, the resistance layer 105 in the semiconductor structure is connected to the second electrode layer 103 of the capacitor structure 101, thereby reducing the distance between the resistance area II and the capacitor area I, thereby reducing the distance of the leads, reducing the distributed inductance and distributed capacitance values, improving the characteristic impedance of the circuit, reducing the possibility of reflection and oscillation in the system, improving the performance of the semiconductor structure, and improving the yield of wafer fabrication.
[0134] Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.12 and Fig.13 , including: a substrate 100, the substrate 100 includes a capacitor area I and a resistor area II adjacent to the capacitor area I; a capacitor structure 101 located on the capacitor area I, the capacitor structure 101 includes a plurality of first electrode layers 102, a plurality of second electrode layers 103 and a plurality of dielectric layers 104, the second electrode layer 103 is located between two adjacent first electrode layers 102, and each dielectric layer 104 is located between adjacent first electrode layers 102 and second electrode layers 103; at least one resistor layer 105 located on the resistor area II, each resistor layer 105 is connected to a first electrode layer 102 or a second electrode layer 103.
[0135] Specifically, in this embodiment, the resistance layer 105 is connected to a first electrode layer 102 .
[0136] The semiconductor structure includes a substrate 100 , wherein the substrate 100 includes a capacitor region I and a resistor region II adjacent to the capacitor region I.
[0137] The material of the substrate 100 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.
[0138] Specifically, in this embodiment, the substrate 100 further includes a first connection region III, and the resistance region II is located between the capacitance region I and the first connection region III.
[0139] The semiconductor structure includes: a capacitor structure 101 located on the capacitor region I, the capacitor structure 101 includes a plurality of first electrode layers 102, a plurality of second electrode layers 103 and a plurality of dielectric layers 104, the second electrode layer 103 is located between two adjacent first electrode layers 102, and each dielectric layer 104 is located between adjacent first electrode layers 102 and second electrode layers 103.
[0140] The material of the first electrode layer 102 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0141] The thickness of the first electrode layer 102 is in the range of
[0142] The material of the second electrode layer 103 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0143] The thickness of the second electrode layer 103 is in the range of
[0144] The material of the dielectric layer 104 includes hafnium oxide, zirconium oxide, lanthanum oxide or aluminum oxide.
[0145] The semiconductor structure includes: at least one resistance layer 105 located on the resistance region II, and each resistance layer 105 is connected to a first electrode layer 102 .
[0146] The resistance layer 105 is also located on the first connection region III.
[0147] The material of the resistance layer 105 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0148] Specifically, in this embodiment, the thickness range of the resistor layer 105 is
[0149] The semiconductor structure includes a third interconnect layer 116 and a fourth interconnect layer 117 located in the substrate 100 .
[0150] The semiconductor structure includes a dielectric layer 108 located on a substrate 100 , wherein the dielectric layer 108 covers each first electrode layer 102 , each second electrode layer 103 and each dielectric layer 104 .
[0151] The semiconductor structure includes: a first conductive plug 109 located on the first connection region III, the first conductive plug 109 penetrates the resistance layer 105 and is electrically connected to the resistance layer 105; and a first conductive layer 112 located on the top surface of the first conductive plug 109.
[0152] The material of the first conductive plug 109 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0153] The semiconductor structure includes: a second conductive plug 110 located on the capacitor region I, and the second conductive plug 110 penetrates the capacitor structure 101 .
[0154] The material of the second conductive plug 110 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0155] The semiconductor structure includes: a plurality of first interconnection layers 114 located on the capacitor structure 101 , each of the first interconnection layers 114 being connected to a plurality of second conductive plugs 110 ; and a second conductive layer 113 electrically connected to the plurality of first interconnection layers 114 .
[0156] The semiconductor structure includes: a third conductive plug 111 located on the capacitor region I, the third conductive plug 111 penetrates the capacitor structure 101, the third conductive plug 111 is connected to the second electrode layer 103, and the third conductive plug 111 is electrically insulated from the first electrode layer 102.
[0157] The material of the third conductive plug 111 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0158] The semiconductor structure includes: a plurality of second interconnection layers 115 located on the capacitor structure 101 , each second interconnection layer 115 is connected to a plurality of third conductive plugs 111 ; and the second interconnection layer 115 and the first interconnection layer 114 are parallel to each other.
[0159] Specifically, in this embodiment, the capacitor structure 101 is located on the third interconnect layer 116 and the fourth interconnect layer 117, each third interconnect layer 116 is connected to a plurality of second conductive plugs 110, each fourth interconnect layer 117 is connected to a plurality of third conductive plugs 111, the third interconnect layer 116 and the fourth interconnect layer 117 are parallel to each other, and the third interconnect layer 116 and the fourth interconnect layer 117 are not parallel to the first interconnect layer 114 or the second interconnect layer 115.
[0160] Correspondingly, another embodiment of the present invention further provides a semiconductor structure, please continue to refer to Fig.24 and Fig.25, including: a substrate 100, the substrate 100 includes a capacitor area I and a resistor area II adjacent to the capacitor area I; a capacitor structure 101 located on the capacitor area I, the capacitor structure 101 includes a plurality of first electrode layers 102, a plurality of second electrode layers 103 and a plurality of dielectric layers 104, the second electrode layer 103 is located between two adjacent first electrode layers 102, and each dielectric layer 104 is located between adjacent first electrode layers 102 and second electrode layers 103; at least one resistor layer 105 located on the resistor area II, each resistor layer 105 is connected to a first electrode layer 102 or a second electrode layer 103.
[0161] Specifically, in this embodiment, the resistance layer 105 is connected to a second electrode layer 103 .
[0162] The semiconductor structure includes a substrate 100 , wherein the substrate 100 includes a capacitor region I and a resistor region II adjacent to the capacitor region I.
[0163] The material of the substrate 100 includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.
[0164] Specifically, in this embodiment, the substrate 100 further includes a first connection region III, and the resistance region II is located between the capacitance region I and the first connection region III.
[0165] The semiconductor structure includes: a capacitor structure 101 located on the capacitor region I, the capacitor structure 101 includes a plurality of first electrode layers 102, a plurality of second electrode layers 103 and a plurality of dielectric layers 104, the second electrode layer 103 is located between two adjacent first electrode layers 102, and each dielectric layer 104 is located between adjacent first electrode layers 102 and second electrode layers 103.
[0166] The material of the first electrode layer 102 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0167] The thickness of the first electrode layer 102 is in the range of
[0168] The material of the second electrode layer 103 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0169] The thickness of the second electrode layer 103 is in the range of
[0170] The material of the dielectric layer 104 includes hafnium oxide, zirconium oxide, lanthanum oxide or aluminum oxide.
[0171] The semiconductor structure includes: at least one resistance layer 105 located on the resistance region II, and each resistance layer 105 is connected to a second electrode layer 103 .
[0172] The resistance layer 105 is also located on the first connection region III.
[0173] The material of the resistance layer 105 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, titanium oxide, platinum, nickel and tungsten.
[0174] Specifically, in this embodiment, the thickness range of the resistor layer 105 is
[0175] The semiconductor structure includes a seventh interconnection layer 118 and an eighth interconnection layer 119 located in the substrate 100 .
[0176] The semiconductor structure includes a dielectric layer 108 located on a substrate 100 , wherein the dielectric layer 108 covers each first electrode layer 102 , each second electrode layer 103 and each dielectric layer 104 .
[0177] The semiconductor structure includes: a first conductive plug 109 located on the first connection region III, the first conductive plug 109 penetrates the resistance layer 105 and is electrically connected to the resistance layer 105; and a first conductive layer 112 located on the top surface of the first conductive plug 109.
[0178] The material of the first conductive plug 109 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0179] The semiconductor structure includes: a second conductive plug 110 located on the capacitor region I, and the second conductive plug 110 penetrates the capacitor structure 101 .
[0180] The material of the second conductive plug 110 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0181] The semiconductor structure includes: a plurality of fifth interconnection layers 122 located on the capacitor structure 101 , each of the fifth interconnection layers 122 being connected to a plurality of second conductive plugs 110 ; and a third conductive layer 123 electrically connected to the plurality of fifth interconnection layers 122 .
[0182] The semiconductor structure includes: a third conductive plug 111 located on the capacitor region I, the third conductive plug 111 penetrates the capacitor structure 101, the third conductive plug 111 is connected to the first electrode layer 102, and the third conductive plug 111 is electrically insulated from the second electrode layer 103.
[0183] The material of the third conductive plug 111 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.
[0184] The semiconductor structure includes: a plurality of sixth interconnection layers 124 located on the capacitor structure 101 , each of the sixth interconnection layers 124 is connected to a plurality of third conductive plugs 111 ; and the sixth interconnection layer 124 and the fifth interconnection layer 122 are parallel to each other.
[0185] Specifically, in the present embodiment, the capacitor structure 101 is located on the seventh interconnect layer 118 and the eighth interconnect layer 119, each seventh interconnect layer 118 is connected to a plurality of second conductive plugs 110, each eighth interconnect layer 119 is connected to a plurality of third conductive plugs 111, the seventh interconnect layer 118 and the eighth interconnect layer 119 are parallel to each other, and the seventh interconnect layer 118 and the eighth interconnect layer 119 are not parallel to the fifth interconnect layer 122 or the sixth interconnect layer 124.
[0186] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a capacitor region and a resistor region adjacent to the capacitor region; A capacitor structure located on the capacitor region, the capacitor structure comprising a plurality of first electrode layers, a plurality of second electrode layers and a plurality of dielectric layers, the second electrode layers being located between two adjacent first electrode layers, and each dielectric layer being located between adjacent first electrode layers and second electrode layers; At least one resistance layer is located on the resistance area, and each of the resistance layers is connected to one of the first electrode layers or one of the second electrode layers.
2. The semiconductor structure according to claim 1, wherein: The substrate further includes a first connection region, the resistance region is located between the capacitance region and the first connection region; and the resistance layer is also located on the first connection region.
3. The semiconductor structure according to claim 2, wherein: Also includes: a first conductive plug located on the first connection area, the first conductive plug penetrating the resistance layer and electrically connected to the resistance layer; A first conductive layer is located on a top surface of the first conductive plug.
4. The semiconductor structure according to claim 1, wherein: Also includes: A second conductive plug is located on the capacitor region, and the second conductive plug penetrates the capacitor structure.
5. The semiconductor structure according to claim 4, characterized in that When the resistance layer is connected to the first electrode layer, the second conductive plug is connected to the first electrode layer, and the second conductive plug is electrically insulated from the second electrode layer.
6. The semiconductor structure according to claim 5, characterized in that It also includes: a plurality of first interconnection layers located on the capacitor structure, each of the first interconnection layers being connected to a plurality of second conductive plugs; and a second conductive layer electrically connected to the plurality of first interconnection layers.
7. The semiconductor structure according to claim 6, wherein: Also includes: A third conductive plug is located on the capacitor area, the third conductive plug passes through the capacitor structure, the third conductive plug is connected to the second electrode layer, and the third conductive plug is electrically insulated from the first electrode layer; a plurality of second interconnect layers are located on the capacitor structure, each of the second interconnect layers is connected to a plurality of third conductive plugs, and the second interconnect layers are parallel to the first interconnect layers.
8. The semiconductor structure according to claim 7, wherein: Also includes: A plurality of third interconnect layers and a fourth interconnect layer are located on the substrate, the capacitor structure is located on the third interconnect layer and the fourth interconnect layer, each third interconnect layer is connected to a plurality of second conductive plugs, each fourth interconnect layer is connected to a plurality of third conductive plugs, the third interconnect layer and the fourth interconnect layer are parallel to each other, and the third interconnect layer and the fourth interconnect layer are not parallel to the first interconnect layer or the second interconnect layer.
9. The semiconductor structure according to claim 5, characterized in that The second electrode layer has a plurality of first openings therein, the second conductive plugs penetrate through the first openings, and the distance from the sidewall of the first opening to the second conductive plugs is greater than zero.
10. The semiconductor structure according to claim 4, wherein: When the resistance layer is connected to the second electrode layer, the second conductive plug is connected to the second electrode layer, and the second conductive plug is electrically insulated from the first electrode layer.
11. The semiconductor structure according to claim 10, characterized in that The invention also includes: a plurality of fifth interconnection layers located on the capacitor structure, each of the fifth interconnection layers being connected to a plurality of second conductive plugs; and a third conductive layer electrically connected to the plurality of fifth interconnection layers.
12. The semiconductor structure according to claim 11, wherein: Also includes: a third conductive plug located on the capacitor region, the third conductive plug penetrating the capacitor structure, the third conductive plug connected to the first electrode layer, and the third conductive plug electrically insulated from the second electrode layer; and a plurality of sixth interconnect layers located on the capacitor structure, each of the sixth interconnect layers being connected to a plurality of third conductive plugs, and the sixth interconnect layers being parallel to the fifth interconnect layers.
13. The semiconductor structure according to claim 13, wherein: Also includes: A plurality of seventh interconnection layers and an eighth interconnection layer are located on the substrate, the capacitor structure is located on the seventh interconnection layer and the eighth interconnection layer, each seventh interconnection layer is connected to a plurality of second conductive plugs, each eighth interconnection layer is connected to a plurality of third conductive plugs, the seventh interconnection layer and the eighth interconnection layer are parallel to each other, and the seventh interconnection layer and the eighth interconnection layer are not parallel to the fifth interconnection layer or the sixth interconnection layer.
14. The semiconductor structure according to claim 10, wherein: The first electrode layer has a plurality of second openings, the second conductive plugs penetrate the second openings, and the distance from the sidewall of the second opening to the second conductive plugs is greater than zero.
15. The semiconductor structure according to claim 1, wherein: The thickness of the first electrode layer is in the range of The thickness of the second electrode layer is in the range of 16. The semiconductor structure according to claim 1, wherein: Also includes: A dielectric layer is located on the substrate, and the dielectric layer covers each of the first electrode layers, each of the second electrode layers and each of the dielectric layers.
17. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a capacitor region and a resistor region adjacent to the capacitor region; forming a capacitor structure on the capacitor region, the capacitor structure comprising a plurality of first electrode layers, a plurality of second electrode layers and a plurality of dielectric layers, wherein the second electrode layer is located between two adjacent first electrode layers, and each dielectric layer is located between adjacent first electrode layers and second electrode layers; At least one resistance layer is formed on each of the resistance areas, and each of the resistance layers is connected to one of the first electrode layers or one of the second electrode layers.
18. The method for forming a semiconductor structure according to claim 17, wherein: The substrate further includes a first connection region, the resistance region is located between the capacitance region and the first connection region; and the resistance layer is also located on the first connection region.
19. The method for forming a semiconductor structure according to claim 18, further comprising: forming a first conductive plug on the first connection area, wherein the first conductive plug penetrates the resistance layer and is electrically connected to the resistance layer; A first conductive layer is formed on a top surface of the first conductive plug.
20. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: A second conductive plug is formed on the capacitor area, the second conductive plug penetrates the capacitor structure, and is connected to the first electrode layer when the resistor layer is connected to the first electrode layer, and is connected to the second electrode layer when the resistor layer is connected to the second electrode layer.