Semiconductor device

Abstract

The semiconductor device may include: a back wiring in a first back interlayer insulating film; a fin-type pattern on the back surface wiring; a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film; a gate electrode on the fin-type pattern; a first source / drain pattern on one side of the gate electrode; and a backside source / drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. A backside source / drain contact may connect the backside wiring and the first source / drain pattern. The backside source / drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source / drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0106222 filed in the Korean Intellectual Property Office on August 14, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor devices. Background Art

[0004] As one of scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or a silicon body) having a fin or nanowire shape is formed on a substrate and a gate is formed on a surface of the multi-channel active pattern.

[0005] Since this multi-gate transistor uses a three-dimensional channel, it is easy to perform scaling. In addition, even if the gate length of the multi-gate transistor is not increased, the current control capability can be improved. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0006] Meanwhile, as the pitch size of semiconductor devices decreases, research for reducing capacitance and ensuring electrical stability between contacts in the semiconductor devices may be required. Summary of the invention

[0007] Aspects of the present disclosure provide a semiconductor device capable of improving performance and reliability of elements.

[0008] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment of the present disclosure, a semiconductor device may include: a first back-side interlayer insulating film; a back-side wiring, in the first back-side interlayer insulating film, the back-side wiring includes a first surface and a second surface opposite to each other in a first direction; a fin pattern, on the first surface of the back-side wiring, the fin pattern extending in a second direction; a second back-side interlayer insulating film, between the fin pattern and the first back-side interlayer insulating film, the fin pattern and the second back-side interlayer insulating film define a back-side contact hole, the back-side contact hole includes a first back-side contact hole and a second back-side contact hole fluidly connected to each other, the first back-side contact hole is on the bottom of the second back-side contact hole and in the fin pattern, and the second back-side contact hole is in the second back-side interlayer insulating film; a gate electrode, on the fin pattern, and extending in a third direction; a first source / drain pattern, on a first side of the gate electrode, and on the fin pattern; a back-side source / drain contact, on the first surface of the back-side wiring and in the back-side contact hole, the back-side source / drain contact connecting the back-side wiring and the first source / drain pattern. The back-side source / drain contact may include an upper pattern and a lower pattern. The upper pattern of the back source / drain contact may be between the lower pattern of the back source / drain contact and the first source / drain pattern. The upper pattern of the back source / drain contact may fill at least a portion of the first back contact hole, and the upper pattern of the back source / drain contact may have a single conductive film structure.

[0010] According to an embodiment of the present disclosure, a semiconductor device may include: a first back-side interlayer insulating film; a back-side wiring, in the first back-side interlayer insulating film, the back-side wiring includes a first surface and a second surface opposite to each other in a first direction; a fin pattern, on the first surface of the back-side wiring, the fin pattern extending in a second direction; a second back-side interlayer insulating film, between the fin pattern and the first back-side interlayer insulating film; a gate electrode, on the fin pattern, and extending in a third direction; a source / drain pattern, on the first side surface of the gate electrode and on the fin pattern; a back-side source / drain contact, in the second back-side interlayer insulating film and the fin pattern, the back-side source / drain contact connects the back-side wiring and the source / drain pattern; and a contact silicide film, between the back-side source / drain contact and the source / drain pattern. The back-side source / drain contact may include an upper pattern and a lower pattern. The upper pattern may be in contact with the fin pattern and the contact silicide film. The lower pattern may be in contact with the second back-side interlayer insulating film. The upper pattern of the back-side source / drain contact may have a single conductive film structure made of metal. An interface between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact faces the back wiring, and has a convex shape or an inclined shape facing the back wiring.

[0011] According to an embodiment of the present disclosure, a semiconductor device may include a first back-side interlayer insulating film; a back-side wiring, wherein the back-side wiring includes a first surface and a second surface opposite to each other in a first direction; a fin pattern, wherein the fin pattern extends along a second direction on the first surface of the back-side wiring; and a second back-side interlayer insulating film, wherein the fin pattern and the second back-side interlayer insulating film define a back-side contact hole between the fin pattern and the first back-side interlayer insulating film, the back-side contact hole including a first back-side contact hole and a second back-side contact hole in fluid communication with each other, the first back-side contact hole being disposed between the first back-side contact hole and the second back-side interlayer insulating film. The back side contact hole is provided with a plurality of sheet patterns on the bottom of the contact hole and in the fin pattern, and the second back side contact hole is in the second back side interlayer insulating film; a plurality of sheet patterns on the fin pattern and spaced apart from the fin pattern in the first direction; a gate electrode on the fin pattern, the gate electrode extending in the third direction and surrounding the plurality of sheet patterns; a source / drain pattern on the side surface of the gate electrode and on the fin pattern; a back side source / drain contact on the first surface of the back side wiring, the back side source / drain contact connecting the back side wiring and the source / drain pattern; and a contact silicide film between the back side source / drain contact and the source / drain pattern. The back side source / drain contact may include an upper pattern and a lower pattern. The upper pattern of the back side source / drain contact may contact the fin pattern and the contact silicide film. The lower pattern of the back side source / drain contact may contact the second back side interlayer insulating film. The upper pattern of the back side source / drain contact may have a single conductive film structure made of metal. The lower pattern of the back side source / drain contact may include a back side contact pad and a back side contact plug. The back contact pad and the back contact plug may include metal. The back contact pad may contact the upper pattern of the back source / drain contact and the second back interlayer insulating film. The back contact pad may define a back pad groove, and the back contact plug may fill the back pad groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 are example layout diagrams for describing semiconductor devices according to some example embodiments;

[0014] Figure 2 is along Figure 1 A cross-sectional view taken along line AA;

[0015] Figure 3 is along Figure 1 A cross-sectional view taken along line BB;

[0016] Figure 4 is along Figure 1 A cross-sectional view taken along line CC and line DD;

[0017] Figure 5 yes Figure 2 An enlarged view of a portion P;

[0018] Figure 6 yes Figure 2 An enlarged view of part Q;

[0019] Figures 7 to 10 are views for describing a semiconductor device according to some example embodiments;

[0020] Figures 11 to 13 are views for describing a semiconductor device according to some example embodiments;

[0021] Fig.14 and Fig.15 are views for describing a semiconductor device according to some example embodiments;

[0022] Figures 16 to 18 are views for describing a semiconductor device according to some example embodiments;

[0023] Fig.19 and Fig. 20 are views for describing a semiconductor device according to some example embodiments;

[0024] Figure 21 to Figure 23 are views for describing a semiconductor device according to some example embodiments;

[0025] Figure 24 to Figure 26 are views for describing a semiconductor device according to some example embodiments; and

[0026] Figures 27 to 33 is an intermediate operation diagram for describing a method for fabricating a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0027] The terms "first", "second", etc. used herein are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, within the technical spirit of the present disclosure, the first element or component mentioned below can be a second element or component.

[0028] Expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than modifying the individual elements in the list. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0029] In the drawings of semiconductor devices according to some example embodiments, a fin transistor (FinFET) including a channel region having a fin pattern shape, a transistor including a nanowire or a nanosheet, and a multi-bridge channel field effect transistor (MBCFET) are shown. TM ) is shown as an example, but the present disclosure is not limited thereto.

[0030] The semiconductor device according to some example embodiments may include a tunnel FET, a three-dimensional (3D) transistor, or a vertical FET. The semiconductor device according to some example embodiments may include a planar transistor. In addition, the technical concept of the present disclosure may be applied to a FET based on a two-dimensional (2D) material and its heterostructure.

[0031] In addition, the semiconductor device according to some example embodiments may further include a bipolar junction transistor, a lateral double diffused metal oxide semiconductor (LDMOS) transistor, and the like.

[0032] Will refer to Figures 1 to 6 Semiconductor devices according to some example embodiments are described.

[0033] Figure 1 are example layout diagrams for describing semiconductor devices according to some example embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along line AA. Figure 3 is along Figure 1 A cross-sectional view taken along line BB. Figure 4 is along Figure 1 A cross-sectional view taken along line CC and line DD. Figure 5 yes Figure 2 An enlarged view of part P. Figure 6 yes Figure 2 For ease of explanation, Figure 1 The front side wiring structure 195 is not shown.

[0034] Although not shown, a cross-sectional view taken along the second active pattern AP2 in the first direction X may be similar to Figure 2 .

[0035] Reference Figures 1 to 6 , a semiconductor device according to some example embodiments may include a first active pattern AP1, a second active pattern AP2, a plurality of gate electrodes 120, a first source / drain pattern 150, a second source / drain pattern 160, a first back side source / drain contact 170, a second back side source / drain contact 270, a first front side source / drain contact 175, a second front side source / drain contact 275, a first back side wiring 50, a second back side wiring 60, and a front side wiring structure 195.

[0036] The first backside wiring 50 and the second backside wiring 60 may be disposed in the first backside interlayer insulating film 290. Each of the first backside wiring 50 and the second backside wiring 60 may extend in the first direction X. The first backside wiring 50 may be spaced apart from the second backside wiring 60 in the second direction Y.

[0037] As an example, the first backside wiring 50 and the second backside wiring 60 may be power lines for supplying power to the semiconductor device. As another example, the first backside wiring 50 and the second backside wiring 60 may be signal lines for providing operation signals of the semiconductor device. As yet another example, one of the first backside wiring 50 and the second backside wiring 60 may be a power line, and the other may be a signal line.

[0038] The first backside wiring 50 may include a first surface 50_S1 and a second surface 50_S2 opposite to each other in the third direction Z. The second backside wiring 60 may include a first surface 60_S1 and a second surface 60_S2 opposite to each other in the third direction Z. Here, the first direction X may intersect the second direction Y and the third direction Z. In addition, the second direction Y may intersect the third direction Z.

[0039] The first backside wiring 50 and the second backside wiring 60 are shown as having a trapezoidal cross section, but are not limited thereto. Although not shown, the first backside wiring 50 and the second backside wiring 60 may have a rectangular cross section. The first backside wiring 50 will be described as an example. The width of the first surface 50_S1 of the first backside wiring in the second direction Y may be less than the width of the second surface 50_S2 of the first backside wiring in the second direction Y.

[0040] For example, the first back side wiring 50 and the second back side wiring 60 may be formed using a damascene process. After forming a trench extending in the first direction X in the first back side interlayer insulating film 290 , the first back side wiring 50 may be formed by filling the trench with a conductive material.

[0041] The first backside wiring 50 and the second backside wiring 60 are shown as having a single conductive film structure, but are not limited thereto. Although not shown, the first backside wiring 50 and the second backside wiring 60 may have a multi-conductive film structure including a contact pad and a contact plug, such as Figure 2 and Figure 4 1 and 2. The lower pattern 170B of the first back side source / drain contact is shown in FIG.

[0042] The first backside wiring 50 and the second backside wiring 60 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The 2D material may include a two-dimensional allotrope or a two-dimensional compound, and may include, for example, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide, but is not limited thereto. That is, since the above-mentioned 2D materials are listed only as examples, the 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above-mentioned materials.

[0043] Although not shown, each of the first backside wiring 50 and the second backside wiring 60 may extend along the second direction Y. In this case, Figure 1 The shapes of the cross-sectional views taken along the lines AA, BB, CC, and DD may vary.

[0044] The second back-side interlayer insulating film 291 may be disposed on the first back-side interlayer insulating film 290. The second back-side interlayer insulating film 291 may be disposed on the first surface 50_S1 of the first back-side wiring 50 and the first surface 60_S1 of the second back-side wiring 60.

[0045] The second back interlayer insulating film 291 may include an upper surface 291US. The second back interlayer insulating film 291 may include a lower surface opposite to the upper surface 291US of the second back interlayer insulating film in the third direction Z. The lower surface of the second back interlayer insulating film 291 faces the first back wiring 50 and the second back wiring 60 .

[0046] Each of the first back-side interlayer insulating film 290 and the second back-side interlayer insulating film 291 may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low-k material. The dielectric constant of the low-k material may have a value less than 3.9 of the dielectric constant of silicon oxide.

[0047] The first and second active patterns AP1 and AP2 may be disposed on the second back interlayer insulating film 291. The second back interlayer insulating film 291 may be disposed between the first back interlayer insulating film 290 and the first active pattern AP1 and between the first back interlayer insulating film 290 and the second active pattern AP2.

[0048] Each of the first active pattern AP1 and the second active pattern AP2 may extend longer in the first direction X. For example, the first active pattern AP1 and the second active pattern AP2 may be disposed on the first back side wiring 50 and the second back side wiring 60, respectively. The first active pattern AP1 and the second active pattern AP2 may be disposed on the first surface 50_S1 of the first back side wiring and the first surface 60_S1 of the second back side wiring, respectively. The first surface 50_S1 of the first back side wiring and the first surface 60_S1 of the second back side wiring may face the first active pattern AP1 and the second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may be disposed on the upper surface 291US of the second back side interlayer insulating film.

[0049] The first active pattern AP1 and the second active pattern AP2 may be spaced apart from each other in the second direction Y. The first active pattern AP1 and the second active pattern AP2 may be adjacent to each other in the second direction Y.

[0050] The first active pattern AP1 is shown to be closest to the second active pattern AP2 in the second direction Y, but is not limited thereto. An additional active pattern may also be disposed between the first active pattern AP1 and the second active pattern AP2.

[0051] As an example, the first active pattern AP1 may be a region where a p-type transistor is formed, and the second active pattern AP2 may be a region where an n-type transistor is formed. As another example, the first active pattern AP1 and the second active pattern AP2 may be a region where a p-type transistor is formed. As yet another example, the first active pattern AP1 and the second active pattern AP2 may be a region where an n-type transistor is formed. Hereinafter, the first active pattern AP1 and the second active pattern AP2 will be described as regions where transistors of different conductivity types are formed.

[0052] Each of the first active pattern AP1 and the second active pattern AP2 may be a multi-channel active pattern. For example, the first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1. The second active pattern AP2 may include a second lower pattern BP2 and a plurality of second sheet patterns NS2. In a semiconductor device according to some example embodiments, each of the first active pattern AP1 and the second active pattern AP2 may be an active pattern including nanosheets or nanowires.

[0053] The first and second lower patterns BP1 and BP2 may be disposed on the second back interlayer insulating film 291. The second back interlayer insulating film 291 may be disposed between the first back interlayer insulating film 290 and the first lower pattern BP1 and between the first back interlayer insulating film 290 and the second lower pattern BP2.

[0054] The first lower pattern BP1 and the second lower pattern BP2 may protrude in the third direction Z. The first lower pattern BP1 and the second lower pattern BP2 may each be a fin type pattern.

[0055] Each of the first and second lower patterns BP1 and BP2 may extend long in the first direction X. The first lower pattern BP1 may be spaced apart from the second lower pattern BP2 in the second direction Y. The first and second lower patterns BP1 and BP2 may be separated by a fin trench extending in the first direction X.

[0056] The first lower pattern BP1 may include a first surface BP1_S1 and a second surface BP1_S2 that are opposite to each other in the third direction Z. The second surface BP1_S2 of the first lower pattern may face the second back-side interlayer insulating film 291, the first back-side wiring 50, and the second back-side wiring 60. The first back-side wiring 50 and the second back-side wiring 60 may be disposed on the second surface BP1_S2 of the first lower pattern. The second surface BP1_S2 of the first lower pattern faces the upper surface 291US of the second back-side interlayer insulating film. For example, the first lower pattern BP1 may be in contact with the upper surface 291US of the second back-side interlayer insulating film.

[0057] For example, the second surface BP1_S2 of the first lower pattern may be a lower surface of the first lower pattern BP1. The first surface BP1_S1 of the first lower pattern may be an upper surface of the first lower pattern BP1.

[0058] Similar to the first lower pattern BP1, the second lower pattern BP2 may also include a first surface and a second surface opposite to each other in the third direction Z. The second surface of the second lower pattern BP2 may face the second back-side interlayer insulating film 291, the first back-side wiring 50, and the second back-side wiring 60. For example, the second lower pattern BP2 may be in contact with the upper surface 291US of the second back-side interlayer insulating film.

[0059] The first lower pattern BP1 may include a sidewall connecting the first surface BP1_S1 of the first lower pattern and the second surface BP1_S2 of the first lower pattern. The sidewall of the first lower pattern BP1 may extend along the first direction X. The second lower pattern BP2 may include a sidewall extending along the first direction X. The sidewall of the second lower pattern BP2 faces the sidewall of the first lower pattern BP1.

[0060] A plurality of first sheet patterns NS1 may be disposed on the first lower pattern BP1. A plurality of first sheet patterns NS1 may be disposed on the first surface BP1_S1 of the first lower pattern. The plurality of first sheet patterns NS1 may be spaced apart from the first lower pattern BP1 in the third direction Z.

[0061] The plurality of second sheet patterns NS2 may be disposed on the second lower pattern BP2. The plurality of second sheet patterns NS2 may be disposed on a first surface of the second lower pattern BP2. The plurality of second sheet patterns NS2 may be spaced apart from the second lower pattern BP2 in the third direction Z.

[0062] The first and second sheet patterns NS1 and NS2 may be disposed on the first surface 50_S1 of the first and second back-side wirings and the first surface 60_S1 of the second back-side wirings.

[0063] Although it is illustrated that the three first sheet patterns NS1 and the three second sheet patterns NS2 are all disposed in the third direction Z, this is merely for convenience of description, and the present disclosure is not limited thereto.

[0064] exist Figure 2 and Figure 5 The first sheet pattern NS1 may include an upper surface NS1_US and a lower surface NS1_BS. The upper surface NS1_US of the first sheet pattern is opposite to the lower surface NS1_BS of the first sheet pattern in the third direction Z. The lower surface NS1_BS of the first sheet pattern may face the first and second backside wirings 50 and 60 .

[0065] The first sheet pattern NS1 may include a first end NS1_E1 and a second end NS1_E2. The first end NS1_E1 and the second end NS1_E2 of the first sheet pattern are spaced apart in the first direction X. The first end NS1_E1 and the second end NS1_E2 of the first sheet pattern may be portions connected to source / drain patterns 150 and 160 described later, respectively.

[0066] The first sheet pattern NS1 may include an uppermost sheet pattern farthest from the first backside wiring 50 and the second backside wiring 60. The upper surface AP1_US of the first active pattern may be an upper surface of the uppermost sheet pattern of the first sheet pattern NS1. The description of the second active pattern AP2 and the second sheet pattern NS2 may be substantially the same as the description of the first active pattern AP1 and the first sheet pattern NS1.

[0067] The first and second lower patterns BP1 and BP2 may each include silicon or germanium as an elemental semiconductor material. In addition, the first and second lower patterns BP1 and BP2 may each include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0068] The IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge) and tin (Sn) with a Group IV element.

[0069] The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0070] Each of the first sheet pattern NS1 and the second sheet pattern NS2 may include one of silicon or germanium as an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. The width of the first sheet pattern NS1 in the second direction Y may increase or decrease in proportion to the width of the first lower pattern BP1 in the second direction Y. The width of the second sheet pattern NS2 in the second direction Y may increase or decrease in proportion to the width of the second lower pattern BP2 in the second direction Y.

[0071] The first sheet patterns NS1 will be described as an example. Each of the first sheet patterns NS1 disposed on the first lower pattern BP1 is shown to have the same width in the second direction Y, but is not limited thereto.

[0072] The field insulating film 105 may be disposed on the first back side wiring 50 and the second back side wiring 60. For example, the field insulating film 105 may be disposed on the first surface 50_S1 of the first back side wiring and the first surface 60_S1 of the second back side wiring.

[0073] The field insulating film 105 may be disposed on the sidewalls of the first lower pattern BP1 and the sidewalls of the second lower pattern BP2. As an example, the field insulating film 105 may cover the entire sidewalls of the first lower pattern BP1 and the entire sidewalls of the second lower pattern BP2. Although not shown, as another example, the field insulating film 105 may cover a portion of the sidewalls of the first lower pattern BP1 and / or a portion of the sidewalls of the second lower pattern BP2.

[0074] The field insulating film 105 does not cover the first surface BP1_S1 of the first lower pattern and the first surface of the second lower pattern BP2. For the first backside wiring 50 and the second backside wiring 60, the first sheet pattern NS1 and the second sheet pattern NS2 are arranged to be higher than the upper surface of the field insulating film 105. The field insulating film 105 may include an upper surface and a lower surface opposite to each other in the third direction Z. The lower surface of the field insulating film 105 faces the first backside wiring 50 and the second backside wiring 60. The lower surface of the field insulating film 105 may be in contact with the second backside interlayer insulating film 291.

[0075] The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film 105 is illustrated as a single-layer film, this is merely for convenience of description, and the present disclosure is not limited thereto.

[0076] A plurality of gate structures GS may be disposed on the upper surface of the field insulating film 105. Each gate structure GS may extend in the second direction Y. The gate structures GS may be disposed to be spaced apart from each other in the first direction X. The gate structures GS may be adjacent to each other in the first direction X.

[0077] The gate structure GS may be disposed on the first active pattern AP1 and the second active pattern AP2. The gate structure GS may intersect the first active pattern AP1 and the second active pattern AP2.

[0078] The gate structure GS may intersect the first lower pattern BP1 and the second lower pattern BP2. The gate structure GS may surround each of the first sheet patterns NS1. The gate structure GS may surround each of the second sheet patterns NS2.

[0079] Although the gate structure GS is shown to be disposed across the first active region and the second active region, this is only for convenience of explanation and the present disclosure is not limited thereto. That is, a portion of the gate structure GS may be disposed on the field insulating film 105 and a gate separation structure ( Fig.24 and Fig.25 The GCS in is divided into two parts.

[0080] The gate structure GS may include, for example, a gate electrode 120 , a gate insulating film 130 , a gate spacer 140 , and a gate capping pattern 145 .

[0081] The gate structure GS may include a plurality of inner gate structures I_GS disposed between first sheet patterns NS1 adjacent in the third direction Z and between the first lower pattern BP1 and the first sheet pattern NS1. The inner gate structure I_GS may be disposed between a first surface BP1_S1 of the first lower pattern and a lower surface NS1_BS of the first sheet pattern and between an upper surface NS1_US of the first sheet pattern and a lower surface NS1_BS of the first sheet pattern facing the third direction Z. The inner gate structure I_GS may include a gate electrode 120 and a gate insulating film 130.

[0082] The number of the inner gate structures I_GS may be the same as the number of the first sheet patterns NS1. The inner gate structures I_GS contact the first surface BP1_S1 of the first lower pattern, the upper surface NS1_US of the first sheet pattern, and the lower surface NS1_BS of the first sheet pattern. In the semiconductor device according to some example embodiments, the inner gate structures I_GS may contact the source / drain patterns 150 and 160 described later.

[0083] The inner gate structure I_GS includes a gate electrode 120 and a gate insulating film 130 disposed between the first sheet patterns NS1 adjacent to each other and between the first lower pattern BP1 and the first sheet pattern NS1.

[0084] Although not shown, the inner gate structure I_GS may be disposed between the second sheet patterns NS2 adjacent to each other in the third direction Z and between the second lower pattern BP2 and the second sheet pattern NS2.

[0085] The gate electrode 120 may be disposed on the first and second lower patterns BP1 and BP2. The gate electrode 120 may intersect the first and second lower patterns BP1 and BP2. The gate electrode 120 may surround the first and second sheet patterns NS1 and NS2.

[0086] exist Figure 2 In the cross-sectional view of FIG. 1 , the upper surface 120US of the gate electrode is shown as a concave surface, but is not limited thereto. The upper surface 120US of the gate electrode may also be a flat surface.

[0087] The gate electrode 120 may include at least one of a metal, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaCN), tungsten (WN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), tantalum aluminum nitride (TiAlN), tungsten aluminum nitride (TaCN), tungsten nitride (WN), tantalum aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN ), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof, but not limited thereto. The conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the above materials, but not limited thereto.

[0088] The gate insulating film 130 may extend along the upper surface of the field insulating film 105, the first surface BP1_S1 of the first lower pattern, and the first surface of the second lower pattern BP2. The gate insulating film 130 may surround the plurality of first sheet patterns NS1. The gate insulating film 130 may surround the plurality of second sheet patterns NS2. The gate insulating film 130 may be disposed along the periphery of the first sheet pattern NS1 and the periphery of the second sheet pattern NS2. The gate electrode 120 may be disposed on the gate insulating film 130.

[0089] The gate insulating film 130 is disposed between the gate electrode 120 and the first sheet pattern NS1 and between the gate electrode 120 and the second sheet pattern NS2. In the semiconductor device according to some example embodiments, the gate insulating film 130 included in the inner gate structure I_GS may contact source / drain patterns 150 and 160 described later.

[0090] The gate insulating film 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0091] Although the gate insulating film 130 is shown as a single-layer film, this is only for convenience of explanation, and the present disclosure is not limited thereto. The gate insulating film 130 may include a plurality of films. The gate insulating film 130 may also include an interface layer and a high-k insulating film disposed between the first active pattern AP1 and the gate electrode 120 and between the second active pattern AP2 and the gate electrode 120. For example, the interface layer may not be formed along the contour of the upper surface of the field insulating film 105.

[0092] The semiconductor device according to some example embodiments may include a negative capacitance (NC) FET using a negative capacitor.For example, the gate insulating film 130 may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0093] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series with each other and the capacitance of each capacitor has a positive value, the total capacitance is reduced compared to the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series with each other has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0094] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series with each other, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series with each other may increase. By utilizing the increase in the total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0095] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may also be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0096] The ferroelectric material film may also include doped dopants. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0097] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0098] When the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 atomic % (at %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0099] When the dopant is silicon (Si), the ferroelectric material film may include 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 to 80 at% zirconium.

[0100] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0101] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0102] The thickness of the ferroelectric material film may have ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness representing the ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0103] As an example, the gate insulating film 130 may include one ferroelectric material film. As another example, the gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film 130 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0104] The gate spacer 140 may be disposed on the sidewall of the gate electrode 120. The gate spacer 140 may not be disposed between the first lower pattern BP1 and the first sheet pattern NS1 and between the first sheet patterns NS1 adjacent to each other in the third direction Z.

[0105] The gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 140 is shown as a single-layer film, this is only for ease of description and the present disclosure is not limited thereto.

[0106] The gate capping pattern 145 may be disposed on the gate electrode 120. An upper surface 145US of the gate capping pattern may be located on the same plane as an upper surface of the first interlayer insulating film 190. Although not shown, the gate capping pattern 145 may be disposed between the gate spacers 140.

[0107] The gate capping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The gate capping pattern 145 may include a material having an etch selectivity with respect to the first interlayer insulating film 190 .

[0108] The first source / drain pattern 150 may be disposed on the first active pattern AP1. The first source / drain pattern 150 may be disposed on the first lower pattern BP1.

[0109] The first source / drain pattern 150 may be disposed between the gate electrodes 120 adjacent to each other in the first direction X. The first source / drain pattern 150 may be disposed on the side surface of the gate electrode 120. The first source / drain pattern 150 may be in contact with the first active pattern AP1. The first source / drain pattern 150 may be in contact with the first sheet pattern NS1. The first source / drain pattern 150 may be disposed on the first surface 50_S1 of the first back-side wiring and the first surface 60_S1 of the second back-side wiring. The first source / drain pattern 150 may be connected to the first end NS1_E1 of the first sheet pattern NS1.

[0110] The second source / drain pattern 160 may be disposed on the first active pattern AP1. The second source / drain pattern 160 may be disposed on the first lower pattern BP1.

[0111] The second source / drain pattern 160 may be disposed between the gate electrodes 120 adjacent to each other in the first direction X. The second source / drain pattern 160 may be disposed on a side surface of the gate electrode 120 .

[0112] The gate electrode 120 may be disposed between the first source / drain pattern 150 and the second source / drain pattern 160. The first source / drain pattern 150 may be disposed on one side of the gate electrode 120, and the second source / drain pattern 160 may be disposed on the other side of the gate electrode 120.

[0113] The second source / drain pattern 160 may contact the first active pattern AP1. The second source / drain pattern 160 may contact the first sheet pattern NS1. The second source / drain pattern 160 may be disposed on the first surface 50_S1 of the first backside wiring and the first surface 60_S1 of the second backside wiring. The second source / drain pattern 160 may be connected to the second end NS1_E2 of the first sheet pattern NS1.

[0114] The first source / drain pattern 150 and the second source / drain pattern 160 may be in contact with the first lower pattern BP1. A bottom surface 150BS of the first source / drain pattern and a bottom surface 160BS of the second source / drain pattern may be in contact with the first lower pattern BP1.

[0115] Although not shown, a source / drain pattern may be disposed on the second lower pattern BP2 between the gate electrodes 120. The source / drain pattern on the second lower pattern BP2 may be connected to an end portion of the second sheet pattern NS2.

[0116] The first source / drain pattern 150 and the second source / drain pattern 160 may be included in a source / drain of a transistor using the first sheet pattern NS1 as a channel region.

[0117] The first source / drain pattern 150 and the second source / drain pattern 160 may each include an epitaxial pattern. The first source / drain pattern 150 and the second source / drain pattern 160 may each include a semiconductor material.

[0118] The first source / drain pattern 150 and the second source / drain pattern 160 may include, for example, silicon or germanium as an elemental semiconductor material. In addition, the first source / drain pattern 150 and the second source / drain pattern 160 may include, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge) and tin (Sn), or a compound obtained by doping carbon (C), silicon (Si), germanium (Ge) and tin (Sn) with a group IV element. The first source / drain pattern 150 and the second source / drain pattern 160 may each include an epitaxial film made of a semiconductor. Although the first source / drain pattern 150 and the second source / drain pattern 160 are both shown as a single film, this is only for ease of explanation, and the present disclosure is not limited thereto.

[0119] The first source / drain pattern 150 and the second source / drain pattern 160 may include a dopant doped into a semiconductor material. The first source / drain pattern 150 and the second source / drain pattern 160 may include a dopant of the same conductivity type.

[0120] As an example, the first source / drain pattern 150 and the second source / drain pattern 160 include, for example, a p-type dopant. The p-type dopant may include at least one of boron (B) and gallium (Ga), but is not limited thereto.

[0121] As another example, the first source / drain pattern 150 and the second source / drain pattern 160 include, for example, an n-type dopant. The n-type dopant may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), but is not limited thereto.

[0122] although Figure 4 1 and 160 are shown as being hexagonal in shape, but the present disclosure is not limited thereto. Although not shown, the shapes of the first source / drain pattern 150 and the second source / drain pattern 160 may be pentagonal or quadrilateral in shape.

[0123] The first front side interlayer insulating film 190 is disposed on the first lower pattern BP1, the second lower pattern BP2, and the field insulating film 105. The first front side interlayer insulating film 190 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 160. The first front side interlayer insulating film 190 may not cover the upper surface of the gate capping pattern 145. For example, the upper surface of the first front side interlayer insulating film 190 may be located on the same plane as the upper surface 145US of the gate capping pattern.

[0124] The first front-side interlayer insulating film 190 may be disposed on the first surface 50_S1 of the first back-side wiring and the first surface 60_S1 of the second back-side wiring. The first front-side interlayer insulating film 190 is disposed on the upper surface 291US of the second back-side interlayer insulating film.

[0125] The first front-side interlayer insulating film 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may include, for example, tetraethylorthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), toner silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but is not limited thereto.

[0126] Although not shown, the source / drain etch stop film may extend along the outline of the first source / drain pattern 150 and the outline of the second source / drain pattern 160. The source / drain etch stop film may be disposed between the first source / drain pattern 150 and the first front-side interlayer insulating film 190 and between the second source / drain pattern 160 and the first front-side interlayer insulating film 190. The source / drain etch stop film may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0127] The first back side source / drain contact 170 may extend longer in the third direction Z. The first back side source / drain contact 170 may be connected to the first source / drain pattern 150 . For example, the first back side source / drain contact 170 may be electrically connected to the first source / drain pattern 150 .

[0128] The first back side source / drain contact 170 may be disposed between the first source / drain pattern 150 and the first back side wiring 50. The first back side source / drain contact 170 connects the first source / drain pattern 150 and the first back side wiring 50.

[0129] The first back side source / drain contact 170 may be connected to the first back side wiring 50. The first back side source / drain contact 170 may be connected to the first surface 50_S1 of the first back side wiring.

[0130] The first back source / drain contact 170 may be disposed within the second back interlayer insulating film 291 and the first lower pattern BP1. For example, the first back source / drain contact 170 may penetrate the second back interlayer insulating film 291 and the first lower pattern BP1. The first back source / drain contact 170 extends from the lower surface of the second back interlayer insulating film 291 to the first source / drain pattern 150.

[0131] For example, a depth from the upper surface AP1_US of the first active pattern to the lower surface 170BS of the first back side source / drain contact may be the same as a depth from the upper surface AP1_US of the first active pattern to the lower surface of the second back side interlayer insulating film 291 .

[0132] The first back side source / drain contact 170 may be disposed in the back side contact hole 170H. The first back side source / drain contact 170 may fill the back side contact hole 170H.

[0133] The back contact holes 170H may include a first back contact hole 170H_U and a second back contact hole 170H_B. The first back contact hole 170H_U may be formed on a bottom surface of the second back contact hole 170H_B. The first back contact hole 170H_U may extend from the bottom of the second back contact hole 170H_B toward the first source / drain pattern 150.

[0134] The back contact hole 170H may be disposed in the second back interlayer insulating film 291 and the first lower pattern BP1. Since the back contact hole 170H extends into the first source / drain pattern 150, a portion of the back contact hole 170H may be disposed in the first source / drain pattern 150.

[0135] The first back contact hole 170H_U may be disposed in the first lower pattern BP1 and the first source / drain pattern 150. The second back contact hole 170H_B may be disposed in the second back interlayer insulating film 291. The bottom surface of the second back contact hole 170H_B may be defined by the second surface BP1_S2 of the first lower pattern. In other words, the first back contact hole 170H_U may not be disposed in the second back interlayer insulating film 291. The second back contact hole 170H_B may not be disposed in the first lower pattern BP1.

[0136] The first back side source / drain contact 170 may be disposed in the back side contact hole 170H. The first back side source / drain contact 170 may fill the back side contact hole 170H.

[0137] The first back source / drain contact 170 may include a lower pattern 170B and an upper pattern 170U. The upper pattern 170U of the first back source / drain contact may be disposed between the lower pattern 170B of the first back source / drain contact and the first source / drain pattern 150. The lower pattern 170B of the first back source / drain contact may include a lower surface 170BS of the first back source / drain contact.

[0138] The upper pattern 170U of the first back source / drain contact may fill at least a portion of the first back contact hole 170H_U. The lower pattern 170B of the first back source / drain contact may fill at least a portion of the second back contact hole 170H_B. For example, the upper pattern 170U of the first back source / drain contact may fill the entire first back contact hole 170H_U. The upper pattern 170U of the first back source / drain contact may not include a portion extending along the bottom surface of the second back contact hole 170H_B.

[0139] The upper pattern 170U of the first back side source / drain contact may include an interface 170U_IF facing the first back side wiring 50. The interface 170U_IF of the upper pattern of the first back side source / drain contact may face the first back side wiring 50. For example, the lower pattern 170B of the first back side source / drain contact may contact the entire interface 170U_IF of the upper pattern of the first back side source / drain contact.

[0140] The interface 170U_IF of the upper pattern of the first back side source / drain contact may have a convex shape. For example, from a cross-sectional view, the interface 170U_IF of the upper pattern of the first back side source / drain contact may be a convex curved surface.

[0141] The first source / drain pattern 150 may be connected to the upper pattern 170U of the first back side source / drain contact 170. The first back side wiring 50 may be connected to the lower pattern 170B of the first back side source / drain contact 170.

[0142] For example, the first back side source / drain contact 170 may be in contact with the first lower pattern BP1 and the second back side interlayer insulating film 291. The upper pattern 170U of the first back side source / drain contact may be in contact with the first lower pattern BP1. The lower pattern 170B of the first back side source / drain contact may be in contact with the second back side interlayer insulating film 291. Although not shown, a contact insulating pad including an insulating material may be provided between the upper pattern 170U of the first back side source / drain contact and the first lower pattern BP1.

[0143] Although not shown, Figure 4 In the embodiment, when the width of the first back contact hole 170H_U in the second direction Y increases, at least a portion of the sidewall of the first back contact hole 170H_U may be defined by the field insulating film 105. In this case, the upper pattern 170U of the first back source / drain contact may contact the field insulating film 105.

[0144] The upper pattern 170U of the first back source / drain contact may have a single conductive film structure. The upper pattern 170U of the first back source / drain contact may not have a multi-conductive film structure including different conductive materials. The upper pattern 170U of the first back source / drain contact may be formed of a single conductive material. In this case, the upper pattern 170U of the first back source / drain contact may include impurities that are unintentionally introduced during the process of forming the upper pattern 170U of the first back source / drain contact.

[0145] As an example, the upper pattern 170U of the first back source / drain contact may be formed of a single grain. As another example, the upper pattern 170U of the first back source / drain contact may include a plurality of grains separated by grain boundaries. The upper pattern 170U of the first back source / drain contact may include a metal, for example, one of tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), iridium (Ir), and copper (Cu), but is not limited thereto. For example, the upper pattern 170U of the first back source / drain contact may include a metal that can be selectively grown on a conductive material.

[0146] The lower pattern 170B of the first back source / drain contact may have a multi-conductive film structure. The lower pattern 170B of the first back source / drain contact may include a back contact pad 170B_BM and a back contact plug 170B_PL. The back contact pad 170B_BM may extend along the sidewall of the second back contact hole 170H_B, the bottom surface of the second back contact hole 170H_B, and the interface 170U_IF of the upper pattern of the first back source / drain contact. For example, the back contact pad 170B_BM may contact the upper pattern 170U of the first back source / drain contact and the second back interlayer insulating film 291.

[0147] The back contact pad 170B_BM may define a back pad groove 170R_BM. The back contact plug 170B_PL may be disposed on the back contact pad 170B_BM. The back contact plug 170B_PL may fill the back pad groove 170R_BM.

[0148] The back contact pad 170B_BM and the back contact plug 170B_PL may include metal, for example, one of tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), iridium (Ir), and copper (Cu), but are not limited thereto.

[0149] The back contact pad 170B_BM includes a metal different from the upper pattern 170U of the first back source / drain contact. As an example, the back contact plug 170B_PL may include the same metal as the upper pattern 170U of the first back source / drain contact. As another example, the back contact plug 170B_PL may include a metal different from the upper pattern 170U of the first back source / drain contact.

[0150] The second back side source / drain contact 270 electrically connected to the source / drain pattern on the second lower pattern BP2 may have a shape similar to Figure 2 Although not shown, the second back side source / drain contact 270 may be connected to the second back side wiring 60 .

[0151] The first front side source / drain contact 175 may extend longer in the third direction Z. The first front side source / drain contact 175 may be connected to the second source / drain pattern 160 . For example, the first front side source / drain contact 175 may be electrically connected to the second source / drain pattern 160 .

[0152] The first front side source / drain contact 175 is disposed on the first surface BP1_S1 of the first lower pattern. The first front side source / drain contact 175 may be disposed within the first front side interlayer insulating film 190 and the second source / drain pattern 160. A portion of the first front side source / drain contact 175 may be disposed within the second source / drain pattern 160. The first front side source / drain contact 175 does not penetrate the first lower pattern BP1.

[0153] A height from the upper surface AP1_US of the first active pattern to the upper surface 175US of the first front side source / drain contact may be the same as a height from the upper surface AP1_US of the first active pattern to the upper surface 145US of the gate capping pattern.

[0154] Although the first front side source / drain contact 175 is shown to have a single conductive film structure, the present disclosure is not limited thereto. Although not shown, the first front side source / drain contact 175 may have a multi-conductive film structure including a contact pad and a contact plug, similar to the lower pattern 170B of the first back side source / drain contact.

[0155] The first front side source / drain contact 175 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive oxide, a conductive metal carbonitride, and a two-dimensional material.

[0156] The second front side source / drain contact 275 is electrically connected to the source / drain pattern on the second lower pattern BP2 and may have a shape similar to Figure 2 The shapes are the same or similar.

[0157] The first contact silicide film 155 may be disposed between the first back source / drain contact 170 and the first source / drain pattern 150. The first contact silicide film 155 contacts the first back source / drain contact 170. The first contact silicide film 155 may contact the upper pattern 170U of the first back source / drain contact.

[0158] The second contact silicide film 165 may be disposed between the first front side source / drain contact 175 and the second source / drain pattern 160. The second contact silicide film 165 contacts the first front side source / drain contact 175. The first contact silicide film 155 and the second contact silicide film 165 may each include a metal silicide material.

[0159] The second front side interlayer insulating film 191 may be disposed on the first front side interlayer insulating film 190, the gate structure GS, and the first front side source / drain contact 175. Although not shown, the second front side interlayer insulating film 191 may be disposed on the second front side source / drain contact 275. The second front side interlayer insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low-k material.

[0160] Front wiring structure 195 may be disposed within second front interlayer insulating film 191 . Front wiring structure 195 is disposed on first surface 50_S1 of first back wiring and first surface 60_S1 of second back wiring. Front wiring structure 195 may include front via plug 196 and front wiring 197 .

[0161] The front side wiring structure 195 may be connected to the first front side source / drain contact 175. The front side wiring structure 195 may be connected to the upper surface 175US of the first front side source / drain contact.

[0162] The first front side source / drain contact 175 may be disposed between the front side wiring structure 195 and the second source / drain pattern 160. The first front side source / drain contact 175 may connect the front side wiring structure 195 and the second source / drain pattern 160. The first front side source / drain contact 175 may be connected to the front side wiring 197. For example, the front side wiring structure 195 may not be connected to the first source / drain pattern 150 connected to the first back side source / drain contact 170.

[0163] Although not shown, the front side wiring structure 195 may be connected to the first source / drain pattern 150 through another front side source / drain contact. That is, the front side wiring structure 195 may be connected to the first back side source / drain contact 170 via the first source / drain pattern 150.

[0164] Front-side via plug 196 and front-side wiring 197 may each include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0165] Although both the front side via plug 196 and the front side wiring 197 are shown to have a single conductive film structure, this is only for convenience of explanation, and the present disclosure is not limited thereto. Although not shown, for example, at least one of the front side via plug 196 and the front side wiring 197 may have a multi-conductive film structure. As another example, the front side wiring structure 195 may have an integrated structure in which there is no interface separation between the front side via plug 196 and the front side wiring 197.

[0166] Figures 7 to 101 is a view for describing a semiconductor device according to some example embodiments. Figures 1 to 6 The points described are different. For reference, Figures 7 to 10 They are Figure 2 A magnified view of part Q.

[0167] Reference Figure 2 and Figure 7 , in the semiconductor device according to some example embodiments, the lower pattern 170B of the first back side source / drain contact may fill a portion of the first back side contact hole 170H_U.

[0168] For example, a portion of the lower pattern 170B of the first back-side source / drain contact may protrude more toward the first source / drain pattern 150 than an upper surface 291US of the second back-side interlayer insulating film.

[0169] Reference Figure 2 and Figure 8 , in the semiconductor device according to some example embodiments, the upper pattern 170U of the first back side source / drain contact may fill a portion of the second back side contact hole 170H_B.

[0170] The upper pattern 170U of the first back side source / drain contact may make contact with at least a portion of a bottom surface of the second back side contact hole 170H_B.

[0171] For example, a portion of the upper pattern 170U of the first back side source / drain contact may protrude more toward the first back side wiring 50 than the second surface BP1_S2 of the first lower pattern.

[0172] Reference Figure 2 and Fig. 9 In the semiconductor device according to some example embodiments, the first back side contact hole 170H_U may be disposed within the second back side interlayer insulating film 291 , the first lower pattern BP1 , and the first source / drain pattern 150 .

[0173] For example, the bottom surface of the second back contact hole 170H_B may be defined by the second back interlayer insulating film 291 .

[0174] Reference Figure 2 and Fig.10 , in the semiconductor device according to some example embodiments, the second back side contact hole 170H_B may be disposed within the second back side interlayer insulating film 291 and the first lower pattern BP1 .

[0175] A portion of a sidewall of the second back contact hole 170H_B may be defined by the first lower pattern BP1. A bottom surface of the second back contact hole 170H_B may be defined by the first lower pattern BP1.

[0176] Figures 11 to 13 2 is a view for describing a semiconductor device according to some example embodiments. Fig.14 and Fig.15 1 is a view for describing a semiconductor device according to some example embodiments. Figures 1 to 6 The points described are different.

[0177] As a reference, Fig.13 yes Fig.11 A magnified view of part Q, and Fig.15 yes Fig.14 A magnified view of part Q.

[0178] Reference Figures 11 to 13 , in the semiconductor device according to some example embodiments, an interface 170U_IF of an upper pattern of the first back-side source / drain contact may have an inclined shape.

[0179] For example, in Fig.11 In the cross-sectional view shown, an interface 170U_IF of the upper pattern of the first back-side source / drain contact may have a shape inclined with respect to the second surface BP1_S2 of the first lower pattern.

[0180] The crystal structure of the metal included in the upper pattern 170U of the first back source / drain contact may affect the shape of the interface 170U_IF of the upper pattern of the first back source / drain contact. That is, the shape of the interface 170U_IF of the upper pattern of the first back source / drain contact 170 may be different depending on the cutting direction of the first back source / drain contact 170. For example, in the case of Fig.12 In the cross-sectional view shown, an interface 170U_IF of the upper pattern of the first back-side source / drain contact may be parallel to the second surface BP1_S2 of the first lower pattern.

[0181] Although not shown, as an example, Fig.12 In the cross-sectional view shown, an interface 170U_IF of the upper pattern of the first back-side source / drain contact may have a shape inclined with respect to the second surface BP1_S2 of the first lower pattern.

[0182] Although not shown, as another example, in Fig.11 In the cross-sectional view shown in FIG. 1 , the interface 170U_IF of the upper pattern of the first back source / drain contact may be parallel to the second surface BP1_S2 of the first lower pattern. Fig.12 In the illustrated cross-sectional view, an interface 170U_IF of the upper pattern of the first back-side source / drain contact may have an inclined shape.

[0183] Reference Fig.14 and Fig.15 , in the semiconductor device according to some example embodiments, the lower pattern 170B of the first back-side source / drain contact may include a seam pattern 170SE.

[0184] For example, the back side contact plug 170B_PL may include a seam pattern 170SE. Although it is illustrated that the seam pattern 170SE extends to the bottom surface 170BS of the first back side source / drain contact, the present disclosure is not limited thereto.

[0185] Figures 16 to 18 2 is a view for describing a semiconductor device according to some example embodiments. Fig.19 and Fig. 20 1 is a view for describing a semiconductor device according to some example embodiments. Figures 1 to 6 The points described are different.

[0186] Reference Figures 16 to 18 , in the semiconductor device according to some example embodiments, the lower pattern 170B of the first back side source / drain contact may have a single conductive film structure.

[0187] The first back source / drain contact 170 may further include a contact capping pattern 170S disposed between the lower pattern 170B of the first back source / drain contact and the upper pattern 170U of the first back source / drain contact. For example, the contact capping pattern 170S contacts the lower pattern 170B of the first back source / drain contact and the upper pattern 170U of the first back source / drain contact.

[0188] The contact capping pattern 170S may extend along the interface 170U_IF of the upper pattern of the first back side source / drain contact. For example, the contact capping pattern 170S may be formed only on the interface 170U_IF of the upper pattern of the first back side source / drain contact.

[0189] The lower pattern 170B of the first back source / drain contact may include, for example, one of tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), iridium (Ir), and copper (Cu), but is not limited thereto. As an example, the lower pattern 170B of the first back source / drain contact may include a metal different from the upper pattern 170U of the first back source / drain contact. The lower pattern 170B of the first back source / drain contact may include the same metal as the upper pattern 170U of the first back source / drain contact.

[0190] The contact capping pattern 170S may include, for example, one of a metal oxide and a metal nitride. The metal oxide included in the contact capping pattern 170S may be an oxide of a metal included in the upper pattern 170U of the first back source / drain contact. The metal nitride included in the contact capping pattern 170S may be a nitride of a metal included in the upper pattern 170U of the first back source / drain contact. For example, when the upper pattern 170U of the first back source / drain contact includes molybdenum (Mo), the contact capping pattern 170S may include one of molybdenum oxide and molybdenum nitride.

[0191] Reference Fig.19 and Fig. 20 , the semiconductor device according to some example embodiments may further include a sacrificial epitaxial pattern 160SC.

[0192] The sacrificial epitaxial pattern 160SC may be disposed between the second source / drain pattern 160 and the first backside wiring 50. For example, the sacrificial epitaxial pattern 160SC may be disposed between the second source / drain pattern 160 and the second backside interlayer insulating film 291. For example, the sacrificial epitaxial pattern 160SC may contact the second backside interlayer insulating film 291.

[0193] For example, the sacrificial epitaxial pattern 160SC may be disposed under a source / drain pattern not connected to the back source / drain contact. That is, the sacrificial epitaxial pattern 160SC may be disposed under the second source / drain pattern 160 not connected to the first back source / drain contact 170 .

[0194] The sacrificial epitaxial pattern 160SC may include a semiconductor material having an etch selectivity with respect to the first lower pattern BP1. When the first lower pattern BP1 is a silicon fin type pattern, the sacrificial epitaxial pattern 160SC may include silicon-germanium. For example, the sacrificial epitaxial pattern 160SC may be a silicon-germanium pattern.

[0195] Figure 21 to Figure 23 1 is a view for describing a semiconductor device according to some example embodiments. Figures 1 to 6 The points described are different.

[0196] Reference Fig.21 In the semiconductor device according to some example embodiments, the first source / drain pattern 150 and the second source / drain pattern 160 may include outer sidewalls contacting the first sheet pattern NS1 and the inner gate structure I_GS.

[0197] The outer sidewalls of the first source / drain pattern 150 and the second source / drain pattern 160 may have a corrugated shape.

[0198] Reference Fig. 22, in the semiconductor device according to some example embodiments, the gate structure GS may further include a plurality of inner spacers 140_IN.

[0199] The inner spacer 140_IN may be disposed between the first sheet patterns NS1 and between the first lower pattern BP1 and the first sheet pattern NS1 adjacent to each other in the third direction Z. The inner spacer 140_IN is disposed between the inner gate structure I_GS and the first source / drain pattern 150. The inner spacer 140_IN is disposed between the inner gate structure I_GS and the second source / drain pattern 160.

[0200] The inner gate structure I_GS may not contact the first source / drain pattern 150. The inner gate structure I_GS may not contact the second source / drain pattern 160.

[0201] For example, the first source / drain pattern 150 and the second source / drain pattern 160 may include an n-type dopant.

[0202] Reference Fig.23 In the semiconductor device according to some example embodiments, the first active pattern AP1 may not include the first sheet pattern ( Figure 2 NS1 in the .

[0203] Inner gate structure ( Figure 2 I_GS in is not disposed between the first source / drain pattern 150 and the second source / drain pattern 160, but Fig.23 In other respects Figure 3 similar.

[0204] Figure 24 to Figure 26 1 is a view for describing a semiconductor device according to some example embodiments. Figures 1 to 6 The points described are different.

[0205] As a reference, Fig.24 are example layout diagrams for describing semiconductor devices according to some example embodiments. Fig.25 is along Fig.24 A cross-sectional view taken along line BB. Fig.26 is along Fig.24 A cross-sectional view taken along lines CC and DD. Fig.24 , a cross-sectional view taken along the first active pattern AP1 may be similar to Figure 2 Same or similar.

[0206] Reference Figure 24 to Figure 26 , the semiconductor device according to some example embodiments may further include a channel separation structure CCW and a gate separation structure GCS.

[0207] The trench separation structure CCW may be disposed on the first surface 50_S1 of the first backside wiring and the first surface 60_S1 of the second backside wiring. For example, the trench separation structure CCW may be disposed on the second backside interlayer insulating film 291. The trench separation structure CCW may be disposed between the first lower pattern BP1 and the second lower pattern BP2. The trench separation structure CCW may extend along the first direction X.

[0208] The channel separation structure CCW may separate the first lower pattern BP1 and the second lower pattern BP2 from each other. The channel separation structure CCW may contact the second back-side interlayer insulating film 291. The channel separation structure CCW may separate the first sheet pattern NS1 and the second sheet pattern NS2 from each other. The first lower pattern BP1 and the second lower pattern BP2 cover a portion of the sidewall of the channel separation structure CCW. The sidewall of the channel separation structure CCW may extend along the first direction X.

[0209] Although not shown, the channel separation structure CCW may not contact the second back-side interlayer insulating film 291. The first lower pattern BP1 and the second lower pattern BP2 may be connected by a semiconductor material.

[0210] The first lower pattern BP1 and the second lower pattern BP2 may include a first sidewall and a second sidewall opposite to each other in the second direction Y. The first sidewall of the first lower pattern BP1 faces the first sidewall of the second lower pattern BP2. The trench separation structure CCW may be in contact with the first lower pattern BP1 and the second lower pattern BP2. The trench separation structure CCW may be in contact with the first sidewall of the first lower pattern BP1 and the first sidewall of the second lower pattern BP2. The field insulating film 105 may be in contact with the second sidewall of the first lower pattern BP1 and the second sidewall of the second lower pattern BP2.

[0211] The plurality of first sheet patterns NS1 and the plurality of second sheet patterns NS2 are in contact with the channel separation structure CCW. The first sheet pattern NS1 and the second sheet pattern NS2 may protrude in the second direction Y from a sidewall of the channel separation structure CCW.

[0212] In such Fig.25 In the cross-sectional view shown, the gate capping pattern 145 may be disposed on the channel separation structure CCW, but is not limited thereto. Although not shown, an upper surface of the channel separation structure CCW may be located on the same plane as an upper surface of the gate capping pattern 145 .

[0213] The trench separation structure CCW includes an insulating material. The trench separation structure CCW may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and at least one of a combination thereof. Although the channel separation structure CCW is shown as a single-layer film, this is only for ease of explanation and the present disclosure is not limited thereto.

[0214] The gate separation structure GCS may be disposed on the first surface 50_S1 of the first backside wiring and the first surface 60_S1 of the second backside wiring. For example, the gate separation structure GCS may be disposed on the second backside interlayer insulating film 291. The gate separation structure GCS may extend along the first direction X. The gate separation structure GCS may be disposed on the field insulating film 105. A portion of the gate separation structure GCS may be disposed within the first front-side interlayer insulating film 190.

[0215] The gate separation structure GCS may be in contact with the field insulation film 105 . The gate separation structure GCS may protrude more than the upper surface of the field insulation film 105 in the third direction Z. For example, a portion of the gate separation structure GCS may be recessed in the field insulation film 105 .

[0216] The channel separation structure CCW may be disposed between the gate separation structures GCS adjacent to each other along the second direction Y. Although not shown, the gate separation structure GCS may be disposed between the channel separation structures CCW adjacent to each other along the second direction Y. A plurality of first sheet patterns NS1 and a plurality of second sheet patterns NS2 are disposed between the channel separation structures CCW and the gate separation structures GCS adjacent to each other along the second direction Y.

[0217] For example, the gate separation structure GCS may not extend to the second back-side interlayer insulating film 291. The gate separation structure GCS may not contact the second back-side interlayer insulating film 291. Although not shown, the gate separation structure GCS may contact the second back-side interlayer insulating film 291.

[0218] The gate separation structure GCS includes an insulating material. The gate separation structure GCS may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the gate separation structure GCS is shown as a single-layer film, this is only for ease of explanation and the present disclosure is not limited thereto.

[0219] The gate electrode 120 and the gate insulating film 130 may be disposed between the channel separation structure CCW and the gate separation structure GCS. Since the first and second sheet patterns NS1 and NS2 contact the channel separation structure CCW, the gate electrode 120 and the gate insulating film 130 do not surround each first sheet pattern NS1 in a cross-sectional view.

[0220] The first source / drain pattern 150 and the second source / drain pattern 160 may be disposed between the channel separation structure CCW and the gate separation structure GCS. For example, the first source / drain pattern 150 and the second source / drain pattern 160 may contact the sidewall of the channel separation structure CCW.

[0221] For example, the first source / drain pattern 150 and the second source / drain pattern 160 may include dopants of the same conductive type.

[0222] Figures 27 to 33 is an intermediate operation diagram for describing a method for manufacturing a semiconductor device according to some example embodiments. For reference, Figures 27 to 33 Can be used for manufacturing reference Figures 1 to 6 A method for a semiconductor device is described.

[0223] Reference Fig. 27 , a first source / drain pattern 150 and a second source / drain pattern 160 are formed on the first lower pattern BP1 on the substrate 100 .

[0224] The substrate 100 may include an upper surface 100US and a lower surface 100BS opposite to each other in a third direction Z. The substrate 100 may be bulk silicon or silicon on insulator (SOI). Different from this, the substrate 100 may be a silicon substrate and may include another material, for example, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0225] The first active pattern AP1 may be disposed on the upper surface 100US of the substrate. The first lower pattern BP1 may protrude in the third direction Z from the upper surface 100US of the substrate.

[0226] Before forming the first source / drain pattern 150 and the second source / drain pattern 160 , the gate spacer 140 may be formed on the first lower pattern BP1 .

[0227] The first front-side interlayer insulating film 190 may be formed on the first source / drain pattern 150 and the second source / drain pattern 160. Subsequently, the first sheet pattern NS1 is formed on the first lower pattern BP1. Thus, the first active pattern AP1 is formed on the upper surface 100US of the substrate.

[0228] Subsequently, a gate insulating film 130 and a gate electrode 120 surrounding the first sheet pattern NS1 may be formed on the first lower pattern BP1. A gate capping pattern 145 may be formed on the gate electrode 120. Thus, a gate structure GS may be formed on the first active pattern AP1. An upper surface 145US of the gate capping pattern may be located on the same plane as an upper surface of the first front-side interlayer insulating film 190.

[0229] Although not shown, a source / drain etch stopper film may be further formed between the first front-side interlayer insulating film 190 and the first source / drain pattern 150 and between the first front-side interlayer insulating film 190 and the second source / drain pattern 160 .

[0230] Reference Fig.28 , a first front side source / drain contact 175 is formed on the upper surface 100US of the substrate.

[0231] The first front side source / drain contact 175 is connected to the second source / drain pattern 160. Before forming the first front side source / drain contact 175, a second contact silicide film 165 may be formed on the second source / drain pattern 160.

[0232] Subsequently, a front side wiring structure 195 is formed on the gate structure GS and the first front side source / drain contact 175. The front side wiring structure 195 may be connected to the first front side source / drain contact 175.

[0233] Reference Fig.28 and Fig.29 , after forming the front-side wiring structure 195 , the substrate 100 may be removed.

[0234] The first lower pattern BP1 includes a first surface BP1_S1 and a second surface BP1_S2 that are opposite to each other in the third direction Z. When the substrate 100 is removed, the second surface BP1_S2 of the first lower pattern may be exposed.

[0235] Although not shown, the thickness of the substrate 100 may be reduced by removing a portion of the substrate 100 .

[0236] Subsequently, a second back-side interlayer insulating film 291 may be formed on the second surface BP1_S2 of the first lower pattern.

[0237] Reference Fig.29 and Fig.30 , the back contact hole 170H may be formed in the second back interlayer insulating film 291 and the first lower pattern BP1.

[0238] The back contact hole 170H may expose the first source / drain pattern 150. The back contact hole 170H may include a first back contact hole 170H_U and a second back contact hole 170H_B. For example, the first back contact hole 170H_U may be formed in the first lower pattern BP1 and the first source / drain pattern 150. The second back contact hole 170H_B may be formed in the second back interlayer insulating film 291.

[0239] Reference Fig.30 and Fig.31 , a first contact silicide film 155 may be formed on the first source / drain pattern 150 .

[0240] The first contact silicide film 155 may be formed along the first source / drain pattern 150 exposed by the first back contact hole 170H_U.

[0241] Reference Fig.31 and Fig.32 , an upper pattern 170U of a first back side source / drain contact may be formed within the back side contact hole 170H.

[0242] For example, the upper pattern 170U of the first back source / drain contact may be formed in the first back contact hole 170H_U. The upper pattern 170U of the first back source / drain contact may fill the first back contact hole 170H_U. The upper pattern 170U of the first back source / drain contact may contact the first contact silicide film 155.

[0243] For example, the upper pattern 170U of the first back-side source / drain contact may be formed using a selective growth method. In the selective growth method, a pattern may be selectively formed on a conductive material.

[0244] In a method for manufacturing a semiconductor device according to some example embodiments, after forming the upper pattern 170U of the first back side source / drain contact, a surface treatment process may be additionally performed on the upper pattern 170U of the first back side source / drain contact using a gas containing oxygen or nitrogen.

[0245] Reference Fig.32 and Fig.33 , the lower pattern 170B of the first back side source / drain contact may be formed on the upper pattern 170U of the first back side source / drain contact.

[0246] The lower pattern 170B of the first back source / drain contact may be formed in the back contact hole 170H. The lower pattern 170B of the first back source / drain contact may be formed in the second back contact hole 170H_B. Thus, the first back source / drain contact 170 may be formed in the back contact hole 170H.

[0247] Later, in Figures 2 to 4 In the embodiment, the first back side wiring 50 and the second back side wiring 60 may be formed on the first back side source / drain contact 170 .

[0248] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the present embodiment without departing from the principles of the present invention. Therefore, the disclosed present embodiment is provided as a non-limiting example only in a descriptive sense, and not for the purpose of limitation.

Claims

1. A semiconductor device, comprising: a first back-side interlayer insulating film; a backside wiring including a first surface and a second surface opposite to each other in a first direction in the first backside interlayer insulating film; a fin pattern, on the first surface of the backside wiring, the fin pattern extending along a second direction; a second back-side interlayer insulating film between the fin pattern and the first back-side interlayer insulating film, the fin pattern and the second back-side interlayer insulating film defining back-side contact holes, the back-side contact holes including a first back-side contact hole and a second back-side contact hole in fluid communication with each other, the first back-side contact hole being on a bottom of the second back-side contact hole and in the fin pattern, and the second back-side contact hole being in the second back-side interlayer insulating film; a gate electrode on the fin pattern and extending along a third direction; a first source / drain pattern on a first side of the gate electrode and on the fin pattern; a back source / drain contact on the first surface of the back wiring and in the back contact hole, the back source / drain contact connecting the back wiring and the first source / drain pattern, wherein: The back source / drain contact comprises an upper pattern and a lower pattern, The upper pattern of the back source / drain contact is between the lower pattern of the back source / drain contact and the first source / drain pattern, The upper pattern of the back source / drain contact fills at least a portion of the first back contact hole, and The upper pattern of the back source / drain contact has a single conductive film structure.

2. The semiconductor device according to claim 1, wherein The lower pattern of the back source / drain contact includes a back contact pad and a back contact plug, The back contact pad contacts the upper pattern of the back source / drain contact and defines a back pad groove, and The back side contact plug fills the back side pad groove.

3. The semiconductor device according to claim 2, wherein: The back side contact plug includes a seam pattern.

4. The semiconductor device according to claim 2, wherein: The upper pattern of the back source / drain contact and the back contact plug each include one of molybdenum Mo, tungsten W, ruthenium Ru, cobalt Co, iridium Ir, and copper Cu.

5. The semiconductor device according to claim 2, further comprising: A contact silicide film between the back source / drain contact and the first source / drain pattern, wherein: The upper pattern of the back side source / drain contact is in contact with the contact silicide film and the fin pattern.

6. The semiconductor device according to claim 1, wherein The lower pattern of the back source / drain contact has a single conductive film structure, and The lower pattern of the back side source / drain contact fills at least a portion of the second back side contact hole.

7. The semiconductor device according to claim 6, wherein: The back source / drain contact further includes a contact capping pattern between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact.

8. The semiconductor device according to claim 1, wherein An interface between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact faces the back wiring and has a convex shape facing the back wiring.

9. The semiconductor device according to claim 1, wherein: An interface between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact faces the back wiring and has an inclined shape facing the back wiring.

10. The semiconductor device according to claim 1, further comprising: a second source / drain pattern on the fin pattern and on a second side of the gate electrode, a front side source / drain contact connected to the second source / drain pattern, and Front side wiring is connected to the front side source / drain contacts.

11. The semiconductor device according to claim 10, further comprising: A sacrificial epitaxial pattern between the second source / drain pattern and the backside wiring, wherein: The sacrificial epitaxial pattern is in contact with the second back-side interlayer insulating film.

12. The semiconductor device according to claim 10, further comprising: A plurality of sheet-like patterns are arranged on the fin-shaped pattern, wherein: The plurality of sheet patterns are spaced apart from the fin pattern in the first direction, and The second source / drain pattern contacts the plurality of sheet patterns.

13. A semiconductor device comprising: a first back-side interlayer insulating film; a backside wiring including a first surface and a second surface opposite to each other in a first direction in the first backside interlayer insulating film; a fin pattern, on the first surface of the backside wiring, the fin pattern extending along a second direction; a second back-side interlayer insulating film between the fin pattern and the first back-side interlayer insulating film; a gate electrode on the fin pattern and extending along a third direction; a source / drain pattern on a first side surface of the gate electrode and on the fin pattern; a back source / drain contact, in the second back interlayer insulating film and the fin pattern, the back source / drain contact connecting the back wiring and the source / drain pattern; as well as A contact silicide film is provided between the back source / drain contact and the source / drain pattern, wherein The back source / drain contact comprises an upper pattern and a lower pattern, The upper pattern is in contact with the fin pattern and the contact silicide film, The lower pattern is in contact with the second back-side interlayer insulating film, The upper pattern of the back source / drain contact has a single conductive film structure made of metal, and An interface between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact faces the back wiring, and has a convex shape or an inclined shape facing the back wiring.

14. The semiconductor device according to claim 13, wherein: The lower pattern of the back source / drain contact includes a back contact pad and a back contact plug, The back contact pad contacts the upper pattern of the back source / drain contact and defines a back pad groove, and The back side contact plug fills the back side pad groove.

15. The semiconductor device according to claim 13, wherein: The back source / drain contact further includes a contact capping pattern between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact, and The lower pattern of the back source / drain contact has a single conductive film structure.

16. The semiconductor device according to claim 15, wherein: The contact capping pattern includes one of metal, metal oxide and metal nitride, The metal oxide is an oxide of a metal material included in the upper pattern of the back source / drain contact, and The metal nitride is a nitride of the metal material included in the upper pattern of the back side source / drain contact.

17. The semiconductor device according to claim 13, wherein: The lower surface of the fin pattern is in contact with the second back-side interlayer insulating film, and A portion of the upper pattern of the back side source / drain contact protrudes more toward the back side wiring than the lower surface of the fin pattern.

18. The semiconductor device according to claim 13, wherein: The upper surface of the second back-side interlayer insulating film is in contact with the fin pattern, and A portion of the lower pattern of the back-side source / drain contact protrudes more toward the source / drain pattern than the upper surface of the second back-side interlayer insulating film.

19. A semiconductor device comprising: a first back-side interlayer insulating film; a backside wiring including a first surface and a second surface opposite to each other in a first direction in the first backside interlayer insulating film; a fin pattern, on the first surface of the backside wiring, the fin pattern extending along a second direction; a second back-side interlayer insulating film between the fin pattern and the first back-side interlayer insulating film, the fin pattern and the second back-side interlayer insulating film defining back-side contact holes, the back-side contact holes including a first back-side contact hole and a second back-side contact hole in fluid communication with each other, the first back-side contact hole being on a bottom of the second back-side contact hole and in the fin pattern, and the second back-side contact hole being in the second back-side interlayer insulating film; a plurality of sheet patterns on the fin pattern and spaced apart from the fin pattern in the first direction; a gate electrode, on the fin-shaped pattern, the gate electrode extending along a third direction and surrounding the plurality of sheet-shaped patterns; a source / drain pattern on a side surface of the gate electrode and on the fin pattern; a back source / drain contact, on the first surface of the back wiring, the back source / drain contact connecting the back wiring and the source / drain pattern; as well as A contact silicide film is provided between the back source / drain contact and the source / drain pattern, wherein The back source / drain contact comprises an upper pattern and a lower pattern, The upper pattern of the back source / drain contact is in contact with the fin pattern and the contact silicide film, The lower pattern of the back source / drain contact is in contact with the second back interlayer insulating film, The upper pattern of the back source / drain contact has a single conductive film structure made of metal, The lower pattern of the back source / drain contact includes a back contact pad and a back contact plug, The back contact pad and the back contact plug include metal, the back contact pad is in contact with the upper pattern of the back source / drain contact and the second back interlayer insulating film, The back contact pad defines a back pad groove, and The back side contact plug fills the back side pad groove.

20. The semiconductor device according to claim 19, wherein An interface between the upper pattern of the back source / drain contact and the lower pattern of the back source / drain contact faces the back wiring, and has a convex shape or an inclined shape facing the back wiring.

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