TBC battery structure and preparation method thereof

Abstract

The invention relates to a TBC battery structure and a preparation method thereof, and belongs to the technical field of photovoltaic modules, the TBC battery structure comprises a first region and a second region which are deposited on the back surface of a silicon wafer and are alternately arranged at intervals, the first region comprises a first passivation contact region, a first passivation non-contact region and a first electrode, and the second region comprises a second passivation contact region and a second electrode; the second region comprises a second passivation contact region, a second passivation non-contact region and a second electrode, and the polarity of the first region is opposite to that of the second region; the cross-sectional area of the first passivation contact region and the second passivation contact region is smaller than the cross-sectional area of the first passivation non-contact region and the second passivation non-contact region. According to the invention, the preparation process of the TBC battery structure is optimized, the parasitic absorption of the Poly layer is reduced, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaic modules, and in particular relates to a TBC battery structure and a preparation method thereof. Background Art

[0002] The TBC (Tunneling Oxide Passivated Contact Back Contact) battery is a battery that combines the structural characteristics of the tunneling oxide passivated contact battery (TOPCon) and the inter-back contact (IBC) battery to obtain the advantages of unobstructed front side of the battery, high open circuit voltage and large short circuit current.

[0003] As attached Figure 1 As shown, the structure of the TBC battery in the related art includes a first area 2 and a second area 3 deposited on a silicon wafer 1, the first area 2 includes a first tunneling layer 221, a first polysilicon layer 222 and a first electrode 213 arranged in sequence from a side close to the silicon wafer 1 to a side away from the silicon wafer 1, the first area 2 includes a third tunneling layer 321, a third polysilicon layer 322 and a second electrode 313 arranged in sequence from a side close to the silicon wafer 1 to a side away from the silicon wafer 1, and its preparation method includes polishing, PPoly, boron diffusion, primary patterning, etching, N Poly, phosphorus diffusion, secondary patterning, texturing and passivation to form a battery structure, and the thickness of the Poly layer in the first area 2 of the battery structure that contacts the electrode is 300nm, and the thickness of the Poly layer in the second area 3 that contacts the electrode is 200nm.

[0004] The TBC battery structure preparation process in the related art is complicated, and the first area and the second area need to be prepared separately. Therefore, at least two high-temperature doping processes and two patterning processes are required to complete the battery preparation. In addition, the thickness of the Poly layer in the PN area on the back of the battery in the related art is relatively thick, resulting in serious parasitic absorption of the Poly layer, which limits the improvement of the battery conversion efficiency. Summary of the invention

[0005] In order to optimize the preparation process of the TBC battery structure while reducing the parasitic absorption of the Poly layer and improving the battery conversion efficiency, the present application provides a TBC battery structure and a preparation method thereof.

[0006] In the first aspect, the present application provides a TBC battery structure, which adopts the following technical solution:

[0007] A TBC battery structure, comprising a first region and a second region deposited on the back side of a silicon wafer and arranged alternately, wherein the first region comprises a first passivation contact region, a first passivation non-contact region and a first electrode, and the second region comprises a second passivation contact region, a second passivation non-contact region and a second electrode, and the first region and the second region have opposite polarities;

[0008] The first passivation non-contact region includes a first tunneling layer and a first polysilicon layer sequentially arranged from a side close to the silicon wafer to a side away from the silicon wafer, the first passivation contact region includes a second tunneling layer and a second polysilicon layer sequentially arranged from a side close to the first polysilicon layer to a side away from the first polysilicon layer, and the first electrode forms an ohmic contact with the second polysilicon layer;

[0009] The second passivation non-contact region includes a third tunneling layer and a third polysilicon layer sequentially arranged from a side close to the silicon wafer to a side away from the silicon wafer, the second passivation contact region includes a fourth tunneling layer and a fourth polysilicon layer sequentially arranged from a side close to the third polysilicon layer to a side away from the third polysilicon layer, and the second electrode forms an ohmic contact with the fourth polysilicon layer;

[0010] The cross-sectional areas of the first passivation contact region and the second passivation contact region are smaller than the cross-sectional areas of the first passivation non-contact region and the second passivation non-contact region.

[0011] By adopting the above technical solution, since the cross-sectional areas of the first passivation contact area and the second passivation contact area are smaller than the cross-sectional areas of the first passivation non-contact area and the second passivation non-contact area, the thickness of the polysilicon layer that is not in contact with the electrode of the battery structure of the present application has a thinner structure, and the passivation contact area on the back of the silicon wafer adopts a complete SiOx / Poly structure, and the passivation non-contact area adopts a thin layer of SiOx / Poly passivation structure, which not only ensures the passivation and contact performance, but also reduces the thickness of the Poly layer, reduces its parasitic absorption, and is conducive to improving the battery efficiency;

[0012] The first passivation contact area and the second passivation contact area are both areas in contact with the electrode. The second tunneling layer and the fourth tunneling layer of the first passivation contact area and the second passivation contact area can block the diffusion of a portion of the doping source, so that the concentration in the Poly layer is distributed in a stepped manner, that is, the side close to the silicon wafer has a low concentration, and the side far from the silicon wafer has a high concentration, which plays a role in improving the battery conversion efficiency.

[0013] Preferably, the first tunneling layer in the first passivation non-contact region and the third tunneling layer in the second passivation non-contact region have the same thickness, which is 1.5-2.5 nm.

[0014] More preferably, the first tunneling layer in the first passivation non-contact region and the third tunneling layer in the second passivation non-contact region have the same thickness, both of which are 1.5 to 2 nm.

[0015] Preferably, the second tunneling layer of the first passivation contact region and the fourth tunneling layer of the second passivation contact region have the same thickness, both of which are 0.5-1.5 nm.

[0016] More preferably, the second tunneling layer of the first passivation contact region and the fourth tunneling layer of the second passivation contact region have the same thickness, both of which are 0.5-1 nm.

[0017] Preferably, the first polysilicon layer in the first passivation contact region and the third polysilicon layer in the second passivation contact region have the same thickness, which is 30-100 nm.

[0018] More preferably, the first polysilicon layer in the first passivation contact region and the third polysilicon layer in the second passivation contact region have the same thickness, which is 30-50 nm.

[0019] Preferably, the second polysilicon layer in the first passivation contact region and the fourth polysilicon layer in the second passivation contact region have the same thickness, which is 100-200 nm.

[0020] More preferably, the second polysilicon layer in the first passivation contact region and the fourth polysilicon layer in the second passivation contact region have the same thickness, which is 100-150 nm.

[0021] In a second aspect, the present application provides a method for preparing a TBC battery structure, comprising the following steps:

[0022] S1. Polishing: Use alkali solution to polish the silicon wafer to remove the damaged layer and form a flat plane structure;

[0023] S2, deposition of the stacked Poly region: depositing a stacked layer on the back side of the polished silicon wafer, first synchronously depositing the first tunneling layer and the third tunneling layer, then synchronously depositing the first polysilicon layer and the third polysilicon layer, the second tunneling layer and the fourth tunneling layer, the second polysilicon layer and the fourth polysilicon layer in sequence;

[0024] S3. Preparation of PN doping source: Directional injection of P-type and N-type doping sources according to specific patterns by printing;

[0025] S4, annealing: anneal the printed silicon wafer at high temperature to achieve PN region doping. The annealing temperature is 850-950°C and the annealing time is 10-40 minutes.

[0026] S5. Laser patterning: After annealing, the wafer is patterned to remove the phosphosilicate glass and borosilicate glass that are not in contact with the electrode, as well as the stacked tunneling oxide layer and polysilicon layer in the undoped area;

[0027] S6, texturing: texturing the front side of the patterned silicon wafer, and thinning the second polysilicon layer and the fourth polysilicon layer in the back PN region that are not in contact with the electrode and are not doped to form a GAP (height difference);

[0028] S7, passivation: Deposit a passivation film on the front and back of the textured silicon wafer, with a thickness of 3-8 nm;

[0029] S8, Metallization: Print P-type and N-type silver paste on the back of the passivated silicon wafer respectively, and sinter them to complete the electrode preparation.

[0030] By adopting the above technical solution, the P / N Poly layer of the present application is completed in one step, has the same stacking structure, and realizes doping of two different polarities at the same annealing temperature. When the annealing temperature is 850-950°C, the manufactured battery structure has good performance; when the temperature is lower than this range, it will lead to insufficient activation of the doping source, resulting in poor performance; when the temperature is higher than this range, the doping source will be over-activated, thereby destroying the oxide layer to form a passivation effect, resulting in poor battery performance.

[0031] Preferably, in step 3, the doping concentration of the first polysilicon layer is 1×10 19 atom / cm 3 ~5×10 19 atom / cm 3 The doping concentration of the second polysilicon layer is 5×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the third polysilicon layer is 5×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the fourth polysilicon layer is 1×10 20 atom / cm 3 ~1×10 21 atom / cm 3 .

[0032] Preferably, in step 7, the raw material of the passivation film is two or more of aluminum oxide, silicon nitride, silicon oxynitride or silicon oxide.

[0033] Preferably, in step 1, the grain size of the planar structure is 25-30 um.

[0034] By adopting the above technical solution, the grain size on the surface of the silicon wafer after polishing will affect the battery performance. When the grain size is too small, it is easy to fail to etch the damaged layer, and when the grain size is too large, it will be detrimental to the production of the battery structure. When the grain size is 25-30um, it has better battery performance.

[0035] In summary, this application has the following beneficial effects:

[0036] 1. The cell structure of the present application has a relatively thin polysilicon layer that is not in contact with the electrode, and the passivation contact area on the back of the silicon wafer adopts a complete SiOx / Poly structure, and the passivation non-contact area adopts a thin SiOx / Poly passivation structure, which not only ensures the passivation and contact performance, but also reduces the thickness of the Poly layer, reduces its parasitic absorption, and is conducive to improving the cell efficiency;

[0037] The first passivation contact area and the second passivation contact area are both areas in contact with the electrode. The second tunneling layer and the fourth tunneling layer of the first passivation contact area and the second passivation contact area can block the diffusion of a portion of the doping source, so that the concentration in the Poly layer is distributed in a stepped manner, that is, the side close to the silicon wafer has a low concentration, and the side far from the silicon wafer has a high concentration, which plays a role in improving the battery conversion efficiency.

[0038] 2. The battery structure of the present application can block the penetration of part of the doping source by setting a second polysilicon layer and a fourth polysilicon layer of the same thickness, so that the concentration in the Poly layer is distributed in a step-by-step manner, thereby improving the battery efficiency. At the same time, it can block the printed silver paste from etching the non-contact area and protect the structural integrity of the non-contact area.

[0039] 3. The preparation method of the present application completes the P / N Poly layer in one step, has the same laminated structure, and realizes doping of two different polarities at the same annealing temperature. When the annealing temperature is 850-950°C, the manufactured battery structure has good performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is the back structure of a TBC battery in the prior art.

[0041] Figure 2 This is the back structure of the TBC battery of this application.

[0042] Figure 3 This is a diagram of the TBC battery structure molding process of Example 2 and Comparative Example 3.

[0043] Explanation of the accompanying drawings: 1. Silicon wafer; 2. First region; 21. First passivation contact region; 211. Second tunneling layer; 212. Second polysilicon layer; 22. First passivation non-contact region; 221. First tunneling layer; 222. First polysilicon layer; 3. Second region; 31. Second passivation contact region; 311. Fourth tunneling layer; 312. Fourth polysilicon layer; 32. Second passivation non-contact region; 321. Third tunneling layer; 322. Third polysilicon layer; 4. First electrode; 5. Second electrode. DETAILED DESCRIPTION

[0044] The experimental methods in the following examples of the present invention, where no specific conditions are specified, are usually carried out under conventional conditions or under conditions recommended by the manufacturers. The various commonly used chemical reagents used in the examples are all commercially available products.

[0045] The following describes the invention in conjunction with specific embodiments.

[0046] Example 1

[0047] like Figure 2 As shown, a TBC battery structure includes a first region 2 and a second region 3 deposited on the back side of a silicon wafer 1 and alternately arranged, wherein the first region 2 includes a first passivation contact region 21, a first passivation non-contact region 22 and a first electrode 4, and the second region 3 includes a second passivation contact region 31, a second passivation non-contact region 32 and a second electrode 5, and the first region 2 and the second region 3 have opposite polarities;

[0048] The first passivation non-contact region 22 includes a first tunneling layer 221 and a first polysilicon layer 222 sequentially arranged from a side close to the silicon wafer 1 to a side away from the silicon wafer 1, the first passivation contact region 21 includes a second tunneling layer 211 and a second polysilicon layer 212 sequentially arranged from a side close to the first polysilicon layer 222 to a side away from the first polysilicon layer 222, and the first electrode 4 forms an ohmic contact with the second polysilicon layer 212;

[0049] The second passivation non-contact region 32 includes a third tunneling layer 321 and a third polysilicon layer 322 which are sequentially arranged from a side close to the silicon wafer 1 to a side away from the silicon wafer 1, and the second passivation contact region 31 includes a fourth tunneling layer 311 and a fourth polysilicon layer 312 which are sequentially arranged from a side close to the third polysilicon layer 322 to a side away from the third polysilicon layer 322, and the second electrode 5 forms an ohmic contact with the fourth polysilicon layer 312.

[0050] The cross-sectional areas of the first passivation contact region 21 and the second passivation contact region 31 are smaller than the cross-sectional areas of the first passivation non-contact region 22 and the second passivation non-contact region 32 .

[0051] A method for preparing a TBC battery structure comprises the following steps:

[0052] S1, polishing: polishing the silicon wafer 1 with an alkali solution, using an alkali solution with a volume fraction of 8% NaOH and a polishing additive with a volume fraction of 2% to remove the damaged layer and form a flat planar structure, wherein the grain size of the planar structure is 25 um;

[0053] S2, deposition of the laminated Poly region: depositing a laminated layer on the back side of the polished silicon wafer 1, tunneling the oxide layer (SiO2) and the polysilicon layer (Poly); the first tunneling layer 221 of the first passivation non-contact region 21 and the third tunneling layer 321 of the second passivation non-contact region 31 have the same thickness, both of which are 1.5 to 2.5 nm;

[0054] The second tunneling layer 211 of the first passivation contact region 21 and the fourth tunneling layer 311 of the second passivation contact region 31 have the same thickness, which is 0.5-1.5 nm.

[0055] The first polysilicon layer 222 of the first passivation non-contact region 22 and the third polysilicon layer 322 of the second passivation non-contact region 32 have the same thickness, both of which are 30 to 100 nm;

[0056] The second polysilicon layer 212 of the first passivation contact region 21 and the fourth polysilicon layer 312 of the second passivation contact region 31 have the same thickness, which is 100-300 nm.

[0057] S3. Preparation of PN doping source: Directional injection of P-type and N-type doping sources according to specific patterns by printing;

[0058] The doping concentration of the first polysilicon layer is 1×10 19 atom / cm 3 ~5×10 19 atom / cm 3 The doping concentration of the second polysilicon layer is 5×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the third polysilicon layer is 5×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the fourth polysilicon layer is 1×10 20 atom / cm 3 ~1×10 21 atom / cm 3 ;

[0059] S4, annealing: annealing the printed silicon wafer 1 at high temperature to achieve PN region doping, the annealing time is 25 minutes, and the annealing temperature is 850° C.;

[0060] S5. Laser patterning: After annealing, the wafer is patterned to remove the phosphosilicate glass and borosilicate glass that are not in contact with the electrode, as well as the stacked tunneling oxide layer and polysilicon layer in the undoped area;

[0061] S6, texturing; completing the texturing of the front side of the patterned silicon wafer 1, and simultaneously removing the second polysilicon layer 212 and the fourth polysilicon layer 312 of the back PN region that are not in contact with the electrode and are not doped to form a GAP (height difference);

[0062] S7, passivation: the texturing-finished silicon wafer 1 is subjected to passivation film deposition on the front and back sides, respectively, using an ALD device to deposit Al2O3 using trimethylaluminum (TMA) and water (H2O) as reaction sources, and using a PECVD device to deposit a passivation anti-reflection film using silane (SiH4), ammonia (NH3), and laughing gas (N2O) as reaction gases, wherein the film layer is silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx) in a weight ratio of 1:1:1, and the deposited film thickness is 3nm;

[0063] S8, metallization: printing P and N type silver pastes on the back of the passivated silicon wafer 1 respectively, and sintering to complete the electrode preparation.

[0064] Example 2-3

[0065] A TBC battery structure, which is different from Example 1 in that the process parameters of the preparation method are different.

[0066] The preparation process parameters of the TBC battery structure of Examples 1-3 are shown in Table 1.

[0067] Table 1 Preparation process parameters of TBC battery structure of Examples 1-3

[0068]

[0069] Comparative Example

[0070] Comparative Example 1-2

[0071] A TBC battery structure, which is different from Example 2 in that the annealing temperature in S4 is different.

[0072] The annealing temperature in S4 in Comparative Example 1 was 820°C.

[0073] The annealing temperature in S4 in Comparative Example 2 was 980°C.

[0074] Comparative Example 3

[0075] like Figure 1As shown, a TBC battery structure, which is different from Example 2 in that it includes a first region 2 and a second region 3 deposited on a silicon wafer 1, the first region 2 includes a first tunneling layer 221 and a first polysilicon layer 222 sequentially arranged from a side close to the silicon wafer 1 to a side away from the silicon wafer 1, and a first electrode 4 is provided on the side of the first polysilicon layer 222 away from the first tunneling layer 221, the first region 2 includes a third tunneling layer 321 and a third polysilicon layer 322 sequentially arranged from a side close to the silicon wafer 1 to a side away from the silicon wafer 1, and a second electrode 5 is provided on the side of the third polysilicon layer 322 away from the third tunneling layer 321, and a preparation method thereof includes polishing, P Poly, boron diffusion, primary patterning, etching, N Poly, phosphorus diffusion, secondary patterning, texturing and passivation to form a battery back structure, wherein the phosphorus diffusion temperature is 900°C, the diffusion time is 100 min, the boron diffusion temperature is 830°C, and the boron diffusion time is 15 min.

[0076] The structural changes of the back side of the battery during the preparation process of Comparative Example 3 and Example 2 are shown in the figure below: Figure 3 shown.

[0077] Comparative Example 4

[0078] A TBC battery structure, which is different from Example 2 in that the phosphosilicate glass and borosilicate glass in contact with the electrode and the stacked tunneling oxide layer and polysilicon layer in the undoped area are not removed in step 5; and the second polysilicon layer and the fourth polysilicon layer in the back PN region that are not in contact with the electrode and the undoped GAP are not removed synchronously in step 6.

[0079] Performance testing

[0080] The battery structures of Examples 1-3 and Comparative Examples 1-2 were tested using a sinton WCT120 device. The test results are shown in Table 2.

[0081] Table 2 Test results of Examples 1-3 and Comparative Examples 1-2

[0082]

[0083] It can be seen from the test results in Table 2 that Examples 1-3 are better than Comparative Examples 1-2. This is because in the preparation method of the present application, the P / N Poly layer is completed in one step, has the same laminated structure, and realizes doping of two different polarities at the same annealing temperature. When the annealing temperature is 850-950°C, the manufactured battery structure has good performance; when the temperature is lower than this range (i.e., Comparative Example 1), the activation amount of the doping source is insufficient, resulting in poor performance; when the temperature is higher than this range (i.e., Comparative Example 2), the doping source is over-activated, thereby destroying the oxide layer to form a passivation effect, resulting in poor battery performance.

[0084] The battery structures of Example 2 and Comparative Example 3 were tested, and the test results are shown in Table 3.

[0085] Table 3 Test results of Example 2 and Comparative Example 3

[0086] Voc(mV) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) Eta(%) Comparative Example 3 741.5 41.8 84.5 26.19 Example 2 740.8 41.95 84.39 26.23

[0087] Combining Example 2 and Comparative Example 3 and the test results of Table 3, it can be seen that the test results of the short-circuit current density, open-circuit voltage, fill factor and photoelectric conversion efficiency of the TBC battery structure of the present application can basically reach the level of Comparative Example 3 or are better than Comparative Example 3. It is speculated that this may be because the battery structure of Example 2 of the present application, by setting a second polysilicon layer and a fourth polysilicon layer of the same thickness, can, on the one hand, block the infiltration of part of the doping source, thereby making the concentration in the Poly layer present a step-by-step distribution, thereby improving the battery efficiency. On the other hand, it can block the printed silver paste from etching the non-contact area and protect the structural integrity of the non-contact area.

[0088] In addition, combined with Figure 3 It can also be seen that in terms of preparation process, in the preparation process of Comparative Example 3, two temperatures are required to perform high-temperature diffusion on two different electrodes respectively. For different electrodes, different optimal temperatures are required to achieve improved battery effects. Therefore, for the technical solution of Comparative Example 3, the improvement of its battery efficiency depends on the use of different optimal temperatures for different electrodes to improve battery performance; but in Example 2 of the present application, the same annealing temperature is used for two different electrodes to control the temperature equilibrium point when the two electrodes activate the ion source. Although part of the battery performance will be sacrificed, the doping of the ion source is directional through process adjustment. In addition, during the texturing process, parts of the second polysilicon layer and the fourth polysilicon layer that are not in contact with the electrodes are removed, thereby retaining their contact performance while reducing parasitic absorption and satisfying their passivation performance, thereby improving battery efficiency.

[0089] Example 2 and Comparative Example 4 were tested, and the test results are shown in Table 4.

[0090] Table 4 Test results of Example 2 and Comparative Example 4

[0091] <![CDATA[Jsc(mA / cm 2 )]]> Example 2 41.95 Comparative Example 4 41.7

[0092] Combining Example 2 and Comparative Example 4 and the experimental data test results in Table 4, it can be seen that when the second polysilicon layer and the fourth polysilicon layer that are not in contact with the electrode are not removed (Comparative Example 4), the electrode structure formed will have a large parasitic absorption, resulting in a decrease in battery efficiency.

[0093] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A TBC cell structure, comprising a first region (2) and a second region (3) deposited on the back side of a silicon wafer (1) and arranged alternately and spaced apart, characterized in that: The first region (2) comprises a first passivation contact region (21), a first passivation non-contact region (22) and a first electrode (4); the second region (3) comprises a second passivation contact region (31), a second passivation non-contact region (32) and a second electrode (5); the first region (2) and the second region (3) have opposite polarities; The first passivation non-contact region (22) comprises a first tunneling layer (221) and a first polysilicon layer (222) which are sequentially arranged from a side close to the silicon wafer (1) to a side away from the silicon wafer (1); the first passivation contact region (21) comprises a second tunneling layer (211) and a second polysilicon layer (212) which are sequentially arranged from a side close to the first polysilicon layer (222) to a side away from the first polysilicon layer (222); and the first electrode (4) forms an ohmic contact with the second polysilicon layer (212); The second passivation non-contact region (32) comprises a third tunneling layer (321) and a third polysilicon layer (322) arranged in sequence from a side close to the silicon wafer (1) to a side away from the silicon wafer (1), the second passivation contact region (31) comprises a fourth tunneling layer (311) and a fourth polysilicon layer (312) arranged in sequence from a side close to the third polysilicon layer (322) to a side away from the third polysilicon layer (322), and the second electrode (5) forms an ohmic contact with the fourth polysilicon layer (312); The cross-sectional areas of the first passivation contact region (21) and the second passivation contact region (31) are both smaller than the cross-sectional areas of the first passivation non-contact region (22) and the second passivation non-contact region (32).

2. A TBC battery structure according to claim 1, characterized in that: The first tunneling layer (221) of the first passivation non-contact region (22) and the third tunneling layer (321) of the second passivation non-contact region (32) have the same thickness, both of which are 1.5 to 2.5 nm.

3. A TBC battery structure according to claim 1, characterized in that: The second tunneling layer (211) of the first passivation contact region (21) and the fourth tunneling layer (311) of the second passivation contact region (31) have the same thickness, both of which are 0.5 to 1.5 nm.

4. A TBC battery structure according to claim 1, characterized in that: The first polysilicon layer (222) of the first passivation non-contact region (22) and the third polysilicon layer (322) of the second passivation non-contact region (32) have the same thickness, both of which are 30 to 100 nm.

5. A TBC battery structure according to claim 1, characterized in that: The second polysilicon layer (212) of the first passivation contact region (21) and the fourth polysilicon layer (312) of the second passivation contact region (31) have the same thickness, both of which are 100 to 200 nm.

6. A method for preparing a TBC battery structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, polishing: polishing the silicon wafer (1) with an alkali solution to remove the damaged layer and form a flat plane structure; S2, deposition of a stacked layer Poly region: depositing a stacked layer on the back side of the polished silicon wafer (1), first synchronously depositing a first tunneling layer (221) and a third tunneling layer (321), then synchronously depositing a first polysilicon layer (222) and a third polysilicon layer (322), a second tunneling layer (211) and a fourth tunneling layer (311), a second polysilicon layer (212) and a fourth polysilicon layer (312) in sequence; S3. Preparation of PN doping source: Directional injection of P-type and N-type doping sources according to specific patterns by printing; S4, annealing: annealing the printed silicon wafer (1) at high temperature to achieve PN region doping, the annealing temperature is 850-950° C., and the annealing time is 10-40 minutes; S5, laser patterning: using patterning on the annealed silicon wafer (1), the phosphosilicate glass and borosilicate glass not in contact with the electrode and the stacked tunnel oxide layer and polysilicon layer in the undoped area are removed; S6, texturing: completing texturing on the front side of the patterned silicon wafer (1), and at the same time thinning the second polysilicon layer (212) and the fourth polysilicon layer (312) in the back PN region that are not in contact with the electrode and are not doped to form a GAP; S7, passivation: depositing a passivation film on the front and back sides of the textured silicon wafer (1), with the thickness of the deposited film being 3-8 nm; S8, metallization: printing P-type and N-type silver pastes on the back of the passivated silicon wafer (1), and sintering to complete electrode preparation.

7. The method for preparing a TBC battery structure according to claim 6, characterized in that: In step 3, the doping concentration of the first polysilicon layer is 1×10 19 atom / cm 3 ~5×10 19 atom / cm 3 The doping concentration of the second polysilicon layer is 5×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the third polysilicon layer is 5×10 19 atom / cm 3 ~1×10 20 atom / cm 3 The doping concentration of the fourth polysilicon layer is 1×10 20 atom / cm 3 ~1×10 21 atom / cm 3 .

8. The method for preparing a TBC battery structure according to claim 6, characterized in that: In step 7, the raw materials of the passivation film are two or more of aluminum oxide, silicon nitride, silicon oxynitride or silicon oxide.

9. The method for preparing a TBC battery structure according to claim 6, characterized in that: In step 1, the grain size of the planar structure is 25-30um.

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