Microelectronic component and method for producing microelectronic component

Abstract

The invention relates to a microelectronic component (100, 200, 300) having a metal conductor (106, 206, 306) on a first dielectric layer (104, 204, 304), the metal conductor (106, 206, 306) having a polygonal, in particular rectangular, cross-section, and the metal conductor (106, 206, 306) having a region (107, 207, 307) having a corner, the corner facing away from the first dielectric layer (104, 204, 304), the metal conductor (106, 206, 306) having a first dielectric layer (104, 204, 304), the first dielectric layer (104, 204, 304) having a second dielectric layer (104, 204, 304), and the second dielectric layer (104, 204, 304) having a second dielectric layer (104, 204, 304). The invention is characterized in that at least one second layer (109, 209, 309) having a second permittivity and a second conductivity is arranged on the region (107, 207, 307) having the corner, and a fourth layer (111, 211, 311) having a fourth permittivity and a fourth conductivity is arranged on the second layer (109, 209, 309), the second permittivity has a value greater than the fourth permittivity, and the second conductivity has a value greater than the fourth conductivity.

Description

Technical Field

[0001] The invention relates to a microelectronic component and a method for producing a microelectronic component. Background Art

[0002] Electrical insulation is used for data transmission between different voltage domains in the high voltage range. The data transmission itself can be carried out optically and inductively or capacitively with integrated electrical insulation. In the automotive sector, the respective coils of an inductor or the plates of a capacitor are sometimes at strongly different potentials. The difference in potential ranges over 500 V.

[0003] The electrical insulation is either directly integrated into the semiconductor technology of the ASIC or integrated as a separate chip in a system-in-package. The maximum loadability and service life of the insulation are defined by the maximum electric field within the insulation structure.

[0004] A disadvantage here is that weak points occur at corners and edges of the electrically conductive material due to excessively high fields.

[0005] US Pat. No. 929 96 97 B2 describes an electrical insulation using a capacitor, in which an insulating layer is arranged below the upper plate of the capacitor.

[0006] A disadvantage here is that slowly onset degradation effects above the metal plate impair the service life of the structural element.

[0007] Document DE 10 2013 206 899 A1 describes the rounding of corners and edges.

[0008] A disadvantage here is that only thick metal layers can be processed.

[0009] The object of the present invention is to overcome these disadvantages. Summary of the invention

[0010] The microelectronic component comprises a metal conductor on a first dielectric layer, wherein the metal conductor has a polygonal, in particular rectangular, cross section and has a region with a corner, wherein the corner faces away from the first dielectric layer. According to the invention, at least one second layer is arranged on the region with the corner, the second layer having a second permittivity and a second conductivity. A fourth layer is arranged on the second layer, the fourth layer having a fourth permittivity and a fourth conductivity, wherein the second permittivity has a value greater than the fourth permittivity and the second conductivity has a value greater than the fourth conductivity. In other words, the metal edge or corner is surrounded by the field-reducing multilayer system.

[0011] An advantage here is that the electric field at the metal edges is low, so that the service life of the component is increased.

[0012] In one embodiment, the corners are rounded.

[0013] The advantage here is that the electric field at the metal edge is further reduced.

[0014] In another configuration, the metallic conductor is arranged in the high voltage region with the corners facing the low voltage region.

[0015] The advantage here is that the electrical strength in the high-voltage region of the component is increased. In addition, the service life of the component is significantly improved for high voltages.

[0016] In one configuration, a third layer is arranged in places on the at least one second layer, the third layer having a third permittivity and a third conductivity, wherein the third permittivity has a value between the second permittivity and a fourth permittivity and the third conductivity has a value between the second conductivity and the fourth conductivity.

[0017] It is advantageous here that the electric field, in particular at roundings, corners and edges of the at least one second layer, is reduced, thereby increasing the reliability of the component.

[0018] In another configuration, the third layer is arranged in places on the sixth dielectric layer, wherein the sixth dielectric layer is arranged between the metallic conductor and the first dielectric layer.

[0019] Advantageously, the electric field is reduced, in particular at rounded portions, corners and edges of at least one second layer. In addition, field-increasing corners in the third layer are avoided and the reliability of the structural element is further increased.

[0020] In one embodiment, at least one second layer has a defect site

[0021] It is advantageous here to use the Poole-Frenkel conduction mechanism, which greatly reduces the electric field at the edge.

[0022] In another configuration, the second layer includes SiN.

[0023] The advantage here is that the charges introduced due to the high voltage load and the field load associated therewith can flow away. In addition, SiN is a material widely used in semiconductor process engineering.

[0024] In another configuration, the metallic conductor is part of a capacitor.

[0025] In another configuration, the metallic conductor is part of the coil.

[0026] According to the method for producing a microelectronic structural element of the present invention, the microelectronic structural element has a metal conductor on a first dielectric layer, wherein the metal conductor has a polygonal, especially rectangular, cross section, and the metal conductor has a region with a corner, wherein the corner faces away from the first dielectric layer, the method comprising: applying a second layer on the region with the corner by means of CVD, PE-CVD, HDP-CVD, ALD or electroless deposition, the second layer having a second permittivity and a second conductivity, and applying a fourth layer by means of CVD, PE-CVD, HDP-CVD, ALD or electroless deposition, the fourth layer having a fourth permittivity and a fourth conductivity, wherein the second permittivity has a value greater than the fourth permittivity, and the second conductivity has a value greater than the fourth conductivity.

[0027] This has the advantage that the multilayer system is simple to produce.

[0028] Further advantages emerge from the following description of exemplary embodiments and from the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention is described below based on preferred embodiments and the accompanying drawings. The drawings show:

[0030] Figure 1a A microelectronic structure element according to the invention is shown,

[0031] Figure 1b shows a fragment of a first exemplary embodiment of a microelectronic component,

[0032] Figure 2 shows a fragment of a second exemplary embodiment of a microelectronic component,

[0033] Figure 3 A detail of a third exemplary embodiment of a microelectronic component is shown. DETAILED DESCRIPTION

[0034] Figure 1aA microelectronic structural element 100 according to the present invention is shown. The microelectronic structural element 100 has a high-voltage region 101 and a low-voltage region 102. The microelectronic structural element 100 comprises a semiconductor substrate 103, for example a semiconductor substrate made of silicon. Alternatively, the semiconductor substrate 103 may comprise a wide bandgap material, for example SiC or GaN. A first dielectric layer 104 is arranged on the semiconductor substrate 103, which is, for example, at a reference potential, i.e., grounded. In the high-voltage region 101, a capacitor is shown by way of example for electrical insulation. However, a coil may also be provided as an alternative, which is not shown here. Therefore, a first metal plate 105 is arranged in the first dielectric layer. A metal conductor 106 is arranged vertically spaced apart from the first metal plate 105, and the metal conductor has a rectangular cross section. The metal conductor 106 has a region 107, which has a corner or edge of the metal conductor 106. The corner or edge faces away from the first dielectric layer 104 and faces the low-voltage region 102 or the ground terminal 114. The low voltage region 102 includes various structural elements 115. In this embodiment, the metal conductor 106 is electrically attached by means of a high voltage attachment terminal 116. Over the region 107, a polyimide 117 is locally arranged. The polyimide 117 is mechanically separated from the high voltage attachment terminal 116 by a molding mass 118.

[0035] Figure 1b A fragment of a first exemplary embodiment of a microelectronic component 100 is shown. Figure 1a . A sixth dielectric layer 110 is arranged on the first dielectric layer 104. A fifth dielectric layer 108 is arranged on the sixth dielectric layer 110. A metal conductor 106 having a rectangular cross section is arranged locally on the fifth dielectric layer 108. The metal conductor includes a corner or edge, which faces away from the first dielectric layer 104. The corner or edge is located on the upper side of the metal conductor 106. A second layer 109 is arranged locally on the metal conductor 106, and the second layer has a second permittivity and a second conductivity. A fourth layer 111 is arranged on the second layer 109, and the fourth layer has a fourth permittivity and a fourth conductivity. Here, the second permittivity is greater than the fourth permittivity. The second conductivity is also greater than the fourth conductivity. The second layer 109 includes, for example, SiN, and the fourth layer 111 includes, for example, SiO2. The fourth layer 111 serves as a passivation portion. A top passivation layer 112 is arranged on the fourth layer 111 and comprises, for example, SiON. The sixth dielectric layer 110 comprises, for example, SiON, and the fifth dielectric layer 108 comprises, for example, SiN.

[0036] Figure 2 A fragment of a second exemplary embodiment of a microelectronic component is shown. The fragment shows a region 207 which can be arranged in Figure 1a At the position of area 107 in. Figure 2The same reference numerals as in Figure 1b The third layer 213 is arranged between the second layer 209 and the fourth layer 211, wherein the third layer 213 is flush with the second layer 209 in the direction toward the low-volt region. The third layer 213 has a third permittivity and a third conductivity. Here, the value of the second permittivity is greater than the value of the third permittivity, wherein the value of the third permittivity is greater than the value of the fourth permittivity. The second conductivity is greater than the third conductivity, and the third conductivity is greater than the fourth conductivity.

[0037] In an alternative exemplary embodiment, the permittivity may decrease continuously starting from the second layer 209 up to the fourth layer 211 , so that no permittivity jump occurs at the layer transitions between the second layer 209 , the third layer 213 , and the fourth layer 211 .

[0038] In both the first and second exemplary embodiments, the etching of second layers 109 and 209 and of third layer 213 occurs jointly after the structuring of metal layers 106 and 206 .

[0039] Figure 3 A fragment of a third exemplary embodiment of a microelectronic component is shown. The fragment shows a region 307 which can be arranged in Figure 1a At the position of area 107 in. Figure 3 The same reference numerals as in Figure 2 Here, the third layer 313 is not flush with the second layer 309, because the third layer 313 is deposited on the second layer 309 after the second layer 309 is structured. As a result, the corners or edges of the second layer 309 are also protected from the influence of high fields.

[0040] The second layer 109, 209 and 309 can be metallic, for example. Alternatively, the second layer 109, 209 and 309 has defect sites, so that a Poole-Frank conduction mechanism can occur during operation of the microelectronic component 100. Alternatively, the second layer 109, 209 and 309 has SiN.

[0041] The third layers 213 and 313 include, for example, SiON.

[0042] The invention can also be used in metallic conductors that have a rectangular or polygonal cross section in the low-voltage region 102 or at the ground terminal 114. Furthermore, the invention can be used in deeper layers, for example in the lower metal plane within the first dielectric layer.

[0043] The high-voltage structural element may include not only a capacitor but also a coil. That is, the applicability of the present invention is not limited to capacitive couplers but may also be used for inductive couplers or a combination of the two.

[0044] The structure according to the invention can be used not only in chips which contain only electrically insulating structures, for example for signal transmission from the high-voltage side to the low-voltage side or vice versa, but also in chips which additionally include further electrical structural elements, such as resistors, capacitors, coils and transistors.

[0045] Furthermore, there are no restrictions with regard to the number of electrically conductive metal layers present in the chip.

[0046] Furthermore, the invention can also be used for other electrically conductive layers, such as polysilicon. In this case, the electrically conductive layer can have any desired three-dimensional shape.

Claims

1. A microelectronic component (100, 200, 300) having a metal conductor (106, 206, 306) on a first dielectric layer (104, 204, 304), wherein: The metal conductor (106, 206, 306) has a polygonal, in particular rectangular, cross section, and has a region (107, 207, 307) having a corner, wherein the corner faces away from the first dielectric layer (104, 204, 304), characterized in that at least one second layer (109, 209, 309) is arranged on the region (107, 207, 307) having the corner, the second layer having a second permittivity and a second conductivity, and a fourth layer (111, 211, 311) is arranged on the second layer (109, 209, 309), the fourth layer having a fourth permittivity and a fourth conductivity, wherein the second permittivity has a value greater than the fourth permittivity and the second conductivity has a value greater than the fourth conductivity.

2. The microelectronic component (100, 200, 300) according to claim 1, characterized in that The corners are rounded.

3. The microelectronic component (100, 200, 300) according to any one of claims 1 or 2, characterized in that The metal conductor (106, 206, 306) is arranged in the high-voltage region (101), and the corner faces the low-voltage region (102).

4. The microelectronic component (100, 200, 300) according to any one of the preceding claims, characterized in that A third layer (213, 313) is locally arranged on the at least one second layer (209, 309), the third layer having a third permittivity and a third conductivity, wherein the third permittivity has a value between the second permittivity and the fourth permittivity, and the third conductivity has a value between the second conductivity and the fourth conductivity.

5. The microelectronic structure element (300) according to claim 4, characterized in that The third layer (313) is partially arranged on a sixth dielectric layer (310), wherein the sixth dielectric layer (310) is arranged between the metal conductor (306) and the first dielectric layer (304).

6. The microelectronic component (100, 200, 300) according to any one of the preceding claims, characterized in that The at least one second layer (109, 209, 309) has defect sites.

7. The microelectronic component (100, 200, 300) according to any one of the preceding claims, characterized in that The at least one second layer (109, 209, 309) includes SiN.

8. The microelectronic component (100, 200, 300) according to any one of the preceding claims, characterized in that The metal conductor (106, 206, 306) is part of a capacitor.

9. The microelectronic component (100, 200, 300) according to any one of the preceding claims, characterized in that The metal conductor (106, 206, 306) is part of a coil.

10. Method for producing a microelectronic component having a metallic conductor on a first dielectric layer, wherein: The metal conductor has a polygonal, in particular rectangular, cross section and has a region with a corner, wherein the corner faces away from the first dielectric layer, and the method comprises the following steps: applying a second layer onto the region having the corner by means of CVD, PE-CVD, HDP-CVD, ALD or electroless deposition, the second layer having a second permittivity and a second conductivity, Applying a fourth layer onto the region having the corner by means of CVD, PE-CVD, HDP-CVD, ALD or electroless deposition, the fourth layer having a fourth permittivity and a fourth conductivity, wherein the second permittivity has a value greater than the fourth permittivity and the second conductivity has a value greater than the fourth conductivity.

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