Decoder, decoding method, memory controller, and memory system

Abstract

The decoder is based on a mode that a plurality of cyclic permutation matrixes in a layer of a check matrix corresponding to a frame of code word are subjected to message updating in an inter-block serial decoding mode, and a posterior probability storage module (701) is configured to store posterior probability messages corresponding to the cyclic permutation matrixes respectively; the node message storage module (702) is configured to store messages transmitted to the variable nodes by the check nodes respectively corresponding to each cyclic permutation matrix; the message updating module (703) is configured to sequentially receive posterior probability messages respectively corresponding to each cyclic permutation matrix and messages transmitted to variable nodes by check nodes according to a first sequence, sequentially outputting a message transmitted to the variable node by the updated check node corresponding to each cyclic permutation matrix and an updated posterior probability message according to a second sequence; the first sequence is the same as or different from the second sequence.

Description

Decoder, decoding method, memory controller, and memory system Technical Field

[0001] The present disclosure relates to, but is not limited to, a decoder, a decoding method, a memory controller, a memory system, and an electronic device. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices, such as solid-state drives (SSDs). SSDs, due to their fast read and write speeds, vibration resistance, low power consumption, quiet operation, low heat generation, and lightweight design, have been widely used in military, automotive, industrial, medical, and aviation applications. However, memory systems in related technologies still face numerous challenges that need to be addressed.

[0003] Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a decoder is provided, which updates a message by using inter-block serial decoding of multiple cyclic permutation matrices in a layer of a check matrix corresponding to a frame of codewords. The decoder includes:

[0005] The posterior probability storage module is configured to: store the posterior probability message corresponding to each of the circulant permutation matrices;

[0006] A node message storage module is configured to: store messages transmitted from the check nodes corresponding to each of the circulant permutation matrices to the variable nodes; and

[0007] The message update module is configured to: sequentially receive the posterior probability messages corresponding to each of the circulant permutation matrices and the messages transmitted by the check nodes to the variable nodes in a first order, and sequentially output the updated messages transmitted by the check nodes to the variable nodes and the updated posterior probability messages corresponding to each of the circulant permutation matrices in a second order; the first order and the second order may be the same or different.

[0008] In some embodiments, the message update module includes: a first storage unit, a second storage unit;

[0009] The first storage unit is configured to: store symbol values ​​of messages transmitted to check nodes by variable nodes corresponding to the plurality of cyclic permutation matrices; the first storage unit is provided with a first read address and a first write address, and the first write address causes the first storage unit to sequentially input the symbol values ​​of the messages transmitted to the check nodes by the variable nodes corresponding to each of the cyclic permutation matrices in the first order, and the first read address causes the first storage unit to sequentially output the symbol values ​​of the messages transmitted to the check nodes by the variable nodes corresponding to each of the cyclic permutation matrices in the second order;

[0010] The second storage unit is configured to: store the latest messages of the check nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes; the second storage unit is provided with a second read address and a second write address, and the second write address enables the second storage unit to input the latest messages of the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes in sequence according to the first order, and the second read address enables the second storage unit to output the latest messages of the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes in sequence according to the second order.

[0011] In some embodiments, the first storage unit and the second storage unit each include a random access memory.

[0012] In some embodiments, the depth of the first storage unit is: the total weight of the quasi-cyclic low-density parity-check code basis matrix, and the width is: the product of the size of a cyclic permutation matrix and the width of a message transmitted from a check node to a variable node;

[0013] The depth of the second storage unit is the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the size of a cyclic permutation matrix.

[0014] In some embodiments, the message update module further includes: a first calculation unit, a message update unit transmitted by the check node to the variable node;

[0015] The first calculation unit is configured to: calculate the minimum value, the second minimum value, and the symbol exclusive OR value corresponding to one layer of the check matrix;

[0016] The message update unit transmitted by the check node to the variable node is configured to: receive, in sequence in the second order, the symbol values ​​of the message transmitted to the check node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit, and receive the minimum value, the second minimum value, and the symbol exclusive OR value corresponding to one layer of the check matrix calculated by the first calculation unit, and output, in sequence in the second order, the message transmitted to the variable node by the updated check node corresponding to each of the cyclic permutation matrices.

[0017] In some implementations, the message update module further includes: an inverse permutation unit;

[0018] The inverse permutation unit is configured to: permute the sequence of messages transmitted by the check node to the variable node, which are output by the message update unit in the second order and correspond to each of the cyclic permutation matrices, from the order of the check nodes to the order of the corresponding variable nodes.

[0019] In some embodiments, the message update module further includes: a second computing unit;

[0020] The second calculation unit is configured to: based on the message corresponding to each of the cyclic permutation matrices obtained by the inverse permutation unit, the message corresponding to each of the cyclic permutation matrices stored in the second storage unit, and the message corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module, output the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order.

[0021] In some embodiments, the posterior probability storage module includes two real dual-port random access memories.

[0022] In some embodiments, the message update module further includes: a third computing unit;

[0023] The third computing unit is configured to: receive in sequence, in the first order, the latest posterior probability messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module, and receive in sequence, in the first order, the latest messages passed from the check node to the variable node corresponding to each of the cyclic permutation matrices stored in the negative node message storage module, and output in sequence, in the first order, the messages passed from the variable node corresponding to each of the cyclic permutation matrices to the check node.

[0024] In some embodiments, the message update module further includes: a replacement unit;

[0025] The permutation unit is configured to permutate the sequence of messages transmitted from the variable nodes corresponding to each of the circulant permutation matrices outputted by the third calculation unit to the check nodes, replacing the sequence of messages from the order of the variable nodes to the order of the corresponding check nodes.

[0026] According to a second aspect of an embodiment of the present disclosure, a memory controller is provided, comprising a decoder as described in any one of the above embodiments.

[0027] According to a third aspect of an embodiment of the present disclosure, a memory system is provided, comprising the memory controller described in the above embodiment and a memory device coupled to the memory controller.

[0028] According to a fourth aspect of the embodiments of the present disclosure, an electronic device is provided, comprising the decoder described in any one of the above embodiments, and a memory device coupled to the decoder.

[0029] According to a fifth aspect of an embodiment of the present disclosure, a decoding method is provided. In a message updating process using inter-block serial decoding for multiple cyclic permutation matrices in a layer of a check matrix corresponding to a frame of codewords, the method includes:

[0030] Utilizing a posterior probability storage module to store the posterior probability messages corresponding to each of the circulant permutation matrices;

[0031] Using a node message storage module to store messages transmitted from a check node corresponding to each of the circulant permutation matrices to a variable node;

[0032] The message update module is used to sequentially receive the posterior probability messages corresponding to each of the circulant permutation matrices and the messages transmitted by the check nodes to the variable nodes in a first order, and sequentially output the updated messages transmitted by the check nodes to the variable nodes and the updated posterior probability messages corresponding to each of the circulant permutation matrices in a second order; the first order and the second order are the same or different.

[0033] In some embodiments, the step of sequentially outputting, in the second order, messages transmitted to variable nodes by updated check nodes corresponding to each of the circulant permutation matrices and updated posterior probability messages includes:

[0034] A first storage unit is used to store the symbol values ​​of messages transmitted to the check node by the variable nodes corresponding to the plurality of cyclic permutation matrices; the first storage unit is provided with a first read address and a first write address, and the first write address causes the first storage unit to sequentially input the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to each of the cyclic permutation matrices in the first order, and the first read address causes the first storage unit to sequentially output the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to each of the cyclic permutation matrices in the second order;

[0035] A second storage unit is used to store the latest messages of the check nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes; the second storage unit is provided with a second read address and a second write address, and the second write address enables the second storage unit to input the latest messages of the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes in sequence according to the first sequence, and the second read address enables the second storage unit to output the latest messages of the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes in sequence according to the second sequence.

[0036] In some embodiments, the outputting, in the second order, messages transmitted by the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes includes:

[0037] Calculating, by the first calculation unit, a minimum value, a second minimum value, and a symbol exclusive-OR value corresponding to one layer of the check matrix;

[0038] The message update unit that is used to update the check node to the variable node receives, in sequence in the second order, the symbol values ​​of the messages transmitted to the check node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit, and receives the minimum value, the second minimum value, and the symbol exclusive OR value corresponding to one layer of the check matrix calculated by the first calculation unit, and outputs, in sequence in the second order, the messages transmitted to the variable node by the updated check node corresponding to each of the cyclic permutation matrices.

[0039] In some embodiments, the step of sequentially outputting, in the second order, messages transmitted to variable nodes by updated check nodes corresponding to each of the circulant permutation matrices and updated posterior probability messages includes:

[0040] The message update unit that transmits the check node to the variable node in a second order and that corresponds to each of the cyclic permutation matrices is used to transmit the check node to the variable node. The sequence of messages transmitted by the updated check node to the variable node is replaced by the order of the check nodes to the order of the corresponding variable nodes.

[0041] In some implementations, outputting the updated posterior probability messages corresponding to each of the circulant permutation matrices in sequence in the second order includes:

[0042] The updated posterior probability message corresponding to each of the cyclic permutation matrices is output in sequence in a second order based on the message corresponding to each of the cyclic permutation matrices obtained by the second calculation unit based on the permutation of the inverse permutation unit, the message corresponding to each of the cyclic permutation matrices stored in the second storage unit, and the message corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module.

[0043] In some embodiments, the step of sequentially outputting, in the second order, messages transmitted to variable nodes by updated check nodes corresponding to each of the circulant permutation matrices and updated posterior probability messages includes:

[0044] The third computing unit is used to sequentially receive, in the first order, the latest posterior probability messages corresponding to each of the circulant permutation matrices stored in the posterior probability storage module, and sequentially receive, in the first order, the latest messages transmitted from the check node to the variable node corresponding to each of the circulant permutation matrices stored in the negative node message storage module, and output, in the first order, the messages transmitted from the variable node corresponding to each of the circulant permutation matrices to the check node.

[0045] In some embodiments, the step of sequentially outputting, in the second order, messages transmitted to variable nodes by updated check nodes corresponding to each of the circulant permutation matrices and updated posterior probability messages includes:

[0046] A permutation unit is used to permutate the sequence of messages transmitted from the variable nodes corresponding to each of the circulant permutation matrices outputted by the third calculation unit to the check nodes, replacing the sequence of messages from the variable nodes to the sequence of messages from the variable nodes to the check nodes.

[0047] In some embodiments, the method further includes: receiving an updated a posteriori probability message corresponding to each of the cyclic permutation matrices, and substituting the received updated a posteriori probability message corresponding to each of the cyclic permutation matrices into a check equation for verification; if all the check equations are satisfied, the decoding is determined to be successful; if all the check equations are not satisfied, the decoding is determined to have failed, and the next iteration is required to update the a posteriori probability message and the message passed from the check node to the variable node until the decoding is successful or the maximum number of iterations is reached. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0049] FIG2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0050] FIG2 b is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0051] FIG3 a is a schematic diagram showing the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0052] FIG3 b is a schematic diagram of an exemplary memory device including peripheral circuits according to an embodiment of the present disclosure;

[0053] FIG4 is a cross-sectional schematic diagram of a memory array including memory strings according to an embodiment of the present disclosure;

[0054] FIG5 is a schematic diagram of an exemplary memory including a memory array and peripheral circuits according to an embodiment of the present disclosure;

[0055] FIG6 is a schematic diagram of the framework structure of a decoder according to an embodiment of the present disclosure;

[0056] FIG7 is a schematic structural diagram of a decoder according to an embodiment of the present disclosure;

[0057] FIG8 is a schematic structural diagram of a posterior probability storage module according to an embodiment of the present disclosure;

[0058] FIG9 is a schematic diagram of a memory system according to an embodiment of the present disclosure;

[0059] FIG10 is a schematic diagram of an implementation flow of a decoding method according to an embodiment of the present disclosure;

[0060] FIG11 is a schematic diagram of a framework flow of a decoding method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0062] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0063] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0064] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0065] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure.

[0068] FIG1 shows a block diagram of an exemplary system 100 with memory according to some aspects of the present disclosure. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 may include a host 108 and a memory system 102, and memory system 102 has one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit) or a system on chip (e.g., an application processor) of an electronic device. Host 108 can be configured to send data to memory device 104 or receive data from memory device 104.

[0069] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital card, a compact flash card, a universal serial bus flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0070] The memory controller 106 can be configured to control the operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some embodiments, the memory controller 106 is also configured to process error correction codes for data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with the external device via at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect protocol, the Peripheral Component Interconnect High Speed ​​protocol, the Advanced Technology Attachment protocol, the Serial Advanced Technology Attachment protocol, the Parallel Advanced Technology Attachment protocol, the Minicomputer Mini Interface protocol, the Enhanced MiniDisk Interface protocol, the Integrated Drive Electronics protocol, a firmware protocol, and the like.

[0071] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example, as shown in FIG2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ). In another example, as shown in FIG2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG1 ). In some implementations, the storage capacity and / or operating speed of SSD 206 is greater than the storage capacity and / or operating speed of memory card 202 .

[0072] Figure 3a illustrates a schematic structural diagram of a memory array of a three-dimensional NAND memory. As shown in Figure 3a, the memory array of the three-dimensional NAND memory comprises several parallel, staggered rows of memory cells parallel to gate isolation structures. Every four rows of memory cells are separated by gate isolation structures and upper select gate isolation structures, and each memory cell row includes multiple memory cells. The gate isolation structures may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks (blocks). The multiple second gate isolation structures may divide the memory blocks into multiple finger storage areas (finger). An upper select gate isolation structure disposed between each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The memory block shown in Figure 3a includes six memory slices. In practical applications, the number of memory slices in a memory block is not limited to this number. The memory cells in a memory slice coupled to a word line may be referred to as a memory page (page), where a memory page is a physical page.

[0073] It should be noted that the number of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in FIG3a is merely illustrative and does not limit the number of memory cell rows contained in a finger storage area of ​​the 3D NAND memory disclosed herein. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted based on actual conditions, such as 2, 4, 8, or 16.

[0074] FIG3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to memory array 301. For illustration, memory array 301 is described as a three-dimensional NAND-type memory array, wherein memory cells 306 are NAND memory cells, and memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0075] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0076] As shown in FIG3b , each memory string 308 may include a bottom selected transistor (BST) 310 at its source terminal and a top selected transistor (TST) 312 at its drain terminal. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having TST 312) or a deselect voltage (e.g., 0 V) ​​to the corresponding TST 312 via one or more TSLs (Top selected lines) 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having BST 310) or a deselect voltage (e.g., 0 V) ​​to the corresponding BST 310 via one or more BSLs (Bottom Selected lines) 315.

[0077] As shown in FIG3 b , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits can be related to the number of memory strings 308 coupled by the word line 318 in a memory block 304. Each word line 318 can include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320 and a gate line coupled to the control gates. Referring to FIG. 3 a above, a memory page 320 includes multiple memory cells 306, each of which is isolated by an upper select gate isolation structure and a gate isolation structure. The multiple memory cells between the upper select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the upper select gate isolation structure. The memory cells in a memory slice that share the same word line form a programmable (read / write) page.

[0078] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory array 301 including memory strings 308 according to aspects of the present disclosure. As shown in FIG4 , memory strings 308 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be alternately stacked, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array 301 is primarily related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0079] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0080] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0081] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0082] Referring back to FIG3 b , the peripheral circuitry 302 can be coupled to the memory array 301 via the bit lines 316 , word lines 318 , source lines 314 , BSLs 315 , and TSLs 313 . The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via the bit lines 316 , word lines 318 , source lines 314 , BSLs 315 , and TSLs 313 . The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, FIG5 illustrates some exemplary peripheral circuitry, where the peripheral circuitry 302 includes a page buffer / sense amplifier 504 , a column decoder / bit line driver 506 , a row decoder / word line driver 508 , a voltage generator 510 , a control logic circuit 512 , a register 514 , an interface 516 , and a data bus 518 . It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0083] The page buffer / sense amplifier 504 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 based on control signals from the control logic circuit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic circuit 512 and select one or more memory strings 308 by applying a bit line voltage generated by the voltage generator 510.

[0084] The row decoder / wordline driver 508 can be configured to be controlled by the control logic circuit 512 and to select / deselect the memory blocks 304 of the memory array 301 and to select / deselect the word lines 318 of the memory blocks 304. The row decoder / wordline driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / wordline driver 508 can also select / deselect and drive the BSL 315 and TSL 313. As described in detail below, the row decoder / wordline driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic circuit 512 and to generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0085] The control logic circuit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic circuit 512 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic circuit 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic circuit 512, as well as buffer status information received from the control logic circuit 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 301 or relay or buffer data from the memory array 301.

[0086] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0087] Three-dimensional NAND memory, a storage device that offers greater stability and faster and more convenient data read and write than traditional disk storage, has become a ubiquitous part of everyday life. To meet the ever-increasing storage demand, the process size of 3D NAND memory continues to shrink, increasing the number of information bits in a single flash memory cell. The cell types have evolved from single-level cell (SLC) to multi-level cell (MLC), triple-level cell (TLC), and quad-level cell (QLC). This has resulted in a continuously increasing probability of flash memory errors, making the Bose Chaudhuri Hocquenghem (BCH) error correction code inadequate for ensuring data security. Low-density parity check (LDPC), an error correction method with error correction capabilities approaching the Shannon limit, is gradually replacing BCH as the error correction coding method in next-generation flash memory controllers.

[0088] In some embodiments of the present disclosure, a decoder includes a posterior probability storage module, a node message storage module, and a message update module. During the message update process using inter-block serial decoding for multiple cyclic permutation matrices (CPMs) in a layer of a check matrix corresponding to a frame of codewords, the message update module uses a FIFO to temporarily store the relevant values ​​of messages transmitted by variable nodes to the check nodes. The FIFO also temporarily stores intermediate calculated values ​​of messages transmitted by variable nodes to the check nodes corresponding to a layer of the check matrix. Because the FIFO is a first-in, first-out memory, the data that enters the FIFO first is output first, and the input and output order of the data are consistent. While this eliminates waiting cycles, the update results corresponding to each layer of the check matrix still need to be output sequentially according to the order in which the messages transmitted by the variable nodes to the check nodes were input into the message update module. This results in a low degree of freedom and is not conducive to subsequent optimization. Furthermore, the flag signal added by the decoder to indicate the newness of the posterior probability message used by the variable node to transmit the message to the check node increases control complexity. Improving throughput, degrees of freedom, and simplifying system implementation have become urgent issues to be addressed.

[0089] To address one or more of the above problems, an embodiment of the present disclosure provides a decoder, as shown in FIG6 , which updates messages using inter-block serial decoding of multiple cyclic permutation matrices in a layer of a parity check matrix corresponding to a frame of codewords. The decoder includes:

[0090] The posterior probability storage module 701 is configured to: store the posterior probability message corresponding to each of the cyclic permutation matrices;

[0091] The node message storage module 702 is configured to: store the message transmitted from the check node corresponding to each of the circulant permutation matrices to the variable node; and

[0092] The message update module 703 is configured to: sequentially receive the posterior probability messages corresponding to each of the circulant permutation matrices and the messages transmitted by the check nodes to the variable nodes in a first order, and sequentially output the updated messages transmitted by the check nodes to the variable nodes and the updated posterior probability messages corresponding to each of the circulant permutation matrices in a second order; the first order and the second order may be the same or different.

[0093] Here, the posterior probability storage module 701 is connected to the message update module 703 , and the message update module 703 is connected to the node message storage module 702 .

[0094] The decoder provided by the embodiment of the present disclosure includes a quasi-cyclic low-density parity-check code layered decoder.

[0095] Table 1

[0096] Table 1 above lists an example of a check matrix. The check matrix in Table 1 has the following layers: mb = 3, the number of columns: nb = 4, the size of a circulant permutation matrix: cmp_size = 5, the total weight of the base matrix: 8, and the eight non-zero submatrices are numbered 1-8 from top to bottom and from left to right. Non-zero submatrices 1-3 and the first all-zero submatrix from top to bottom constitute the first layer, non-zero submatrices 4-6 and the second all-zero submatrix from top to bottom constitute the second layer, and non-zero submatrices 7-8 and the third all-zero submatrix from top to bottom and the fourth all-zero submatrix constitute the third layer. Non-zero submatrix 1, non-zero submatrix 4, and the first all-zero submatrix from left to right constitute the first column, non-zero submatrix 2, non-zero submatrix 5, and non-zero submatrix 7 constitute the second column. The other columns are similar and will not be repeated here. Here, v0-v19 are the variable node messages corresponding to each column, and c0-c14 are the check node messages corresponding to each row.

[0097] Figure 7 is a schematic diagram of the architecture of a decoder provided by an embodiment of the present disclosure; Figure 8 is a schematic diagram of the structure of a posterior probability storage module 701 provided by an embodiment of the present disclosure. The decoder will be further described below in conjunction with Figures 6, 7, 8 and Table 1.

[0098] In some embodiments, the posterior probability storage module 701 includes two real dual-port random access memories (RAMs).

[0099] RD1 and RD2 shown in FIG7 are two read ports of the posterior probability storage module 701 , and WR1 and WR2 are two write ports of the posterior probability storage module 701 .

[0100] During the first iteration, the posterior probability message stored in the posterior probability storage module is a log-likelihood ratio (LLR) message.

[0101] In the embodiment of the present disclosure, the depth of each real dual-port RAM in the posterior probability storage module 701 is nb, and the width is the width of a posterior probability message * cmp_size. For example, the width of the posterior probability message of a node is quantized to 8 bits, so the width is 8*5=40 bits. The depth of the posterior probability storage module 701 is 4, and address 0 stores the posterior probability message LLR (y0, y1, y2, y3, y4) of v0 to v4, which is 40 bits in total; address 1 stores the posterior probability message LLR (y5, y6, y7, y8, y9) of v5 to v9; address 2 stores the posterior probability message LLR of v 10 ~v 14 The node posterior probability message LLR(y 10 ,y 11 ,y 12 ,y 13 ,y 14 ); Address 3 stores v 15 ~v 19 The node posterior probability message LLR(y 15 ,y 16 ,y 17 ,y 18 ,y 19 ).

[0102] At the beginning of decoding, the ping_pong signal is set to 0, and the LLR in Input the initial channel message into llr_ram_0. When nb initial channel messages are cached, the ping_pong signal is inverted. During the decoding process, the updated posterior probability message is LLR. updated Stored in llr_ram_0, the second frame codeword initial channel message is stored in llr_ram_1.

[0103] It can be understood that the posterior probability storage module 701 in the embodiment of the present disclosure includes two real dual-port RAMs, one for decoding the current codeword and the other for storing the initial channel message of the next frame codeword. Reading and writing can be performed independently. The next layer of the check matrix can directly read the current posterior probability message during the decoding process. The posterior probability message no longer needs to be judged as new or old, and the calculation of the new and old flag signals is removed, thereby simplifying the decoding architecture.

[0104] In some specific examples, the node message storage module 702 includes a simple dual-port RAM, with a depth equal to the total weight of the base matrix and a width equal to the width of the message (C2V message) transmitted by a check node to the variable node * cmp_size. For example, the width of the C2V message of a check node is quantized to 6 bits, and the depth of the node message storage module 702 is 8. Address 0 can access the C2V message of the non-zero submatrix 1, which has a width of 6*5=30 bits, including 5 check node messages of c4 transmitted to v0, c0 transmitted to v1, c1 transmitted to v2, c2 transmitted to v3, and c3 transmitted to v4; address 1 can access the C2V message of the non-zero submatrix 2, which has a width of 30 bits, including the check node messages of c3 transmitted to v5, c4 transmitted to v6, c0 transmitted to v7, c1 transmitted to v8, and c2 transmitted to v9; addresses 2 to 7 store the C2V messages of the non-zero submatrices 3 to 8 respectively. The message output from the node message storage module 702 to the message update module 703 is shown in FIG.

[0105] In some specific examples, the message update module 703 includes a fourth computing unit 707 configured to invert the message transmitted from the check node to the variable node in the node message storage module 702 to obtain the negative of the latest message transmitted from the check node to the variable node corresponding to each cyclic permutation matrix. The order of input data and output data from the fourth computing unit 707 is the same, both in the first order. In some specific examples, the fourth computing unit 707 can be a multiplier.

[0106] Taking the first layer of the check matrix in Table 1 as an example, when the order of the circulant permutation matrices corresponding to the input data in the fourth computing unit 707 is: non-zero submatrix 2 → non-zero submatrix 1 → non-zero submatrix 3, then the order of the circulant permutation matrices corresponding to the output data from the fourth computing unit 707 is: non-zero submatrix 2 → non-zero submatrix 1 → non-zero submatrix 3.

[0107] In some embodiments, the message update module 703 further includes: a third calculation unit 706;

[0108] The third calculation unit 706 is configured to: receive the latest posterior probability messages corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module 701 in sequence in the first order, and receive the latest messages passed to the variable nodes by the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module 702 in sequence in the first order, and output the messages passed to the check nodes by the variable nodes corresponding to each of the cyclic permutation matrices in sequence in the first order.

[0109] Here, the message calculated by the third calculation unit 706 is as shown in FIG. 7 . It is a message transmitted from the variable nodes corresponding to the plurality of circulant permutation matrices in one layer of the check matrix to the check node.

[0110] In some embodiments, the message update module 703 includes: a permutation unit 711; the permutation unit 711 is configured to: permutate the sequence of messages passed to the check nodes by the variable nodes corresponding to each of the cyclic permutation matrices output by the third calculation unit 706 from the order of the variable nodes to the order of the corresponding check nodes.

[0111] In some specific examples, the permutation unit 711 includes a barrel shifter, which can perform a cyclic shift on the input message vector, so that the first calculation unit 705 can calculate the minimum value and the second minimum value of the non-zero elements in a row. For example, the message (V2C message) transmitted by the variable node corresponding to the non-zero submatrix 1 to the check node is LLR (v02c4, v12c0, v22c1, v32c2, v42c3), the V2C message corresponding to the non-zero submatrix 2 is LLR (v52c3, v62c4, v72c0, v82c1, v92c2), and the V2C message corresponding to the non-zero submatrix 3 is LLR (v 15 2c0,v 16 2c1, v 17 2c2, v 18 2c3, v 19 2c4). The shift factor of the non-zero submatrix may not be 0, so the V2C message is cyclically shifted to align the V2C message vectors corresponding to the non-zero elements of the check matrix.

[0112] That is, the V2C message corresponding to the non-zero submatrix 1 is LLR (v02c4, v12c0, v22c1, v32c2, v42c3), which needs to be cyclically shifted left by 1 to become LLR (v12c0, v22c1, v32c2, v42c3, v02c4) output; the V2C message corresponding to the non-zero submatrix 2 is LLR (v52c3, v62c4, v72c0, v 8v sdv 2c1, v92c2) needs to be circularly shifted left by 2 to become LLR (v72c0, v82c1, v92c2, v52c3, v62c4) output; the V2C message corresponding to the non-zero submatrix 3 is LLR (v 15 2c0,v 16 2c1, v 17 2c2, v 18 2c3, v 19 2c4) Circular left shift 0 becomes LLR (v 15 2c0,v 16 2c1, v 172c2, v 18 2c3, v 19 2c4) output.

[0113] In some embodiments, the message update module 703 includes: a first storage unit 708, a second storage unit 709;

[0114] The first storage unit 708 is configured to: store the symbol values ​​of the messages transmitted to the check nodes by the variable nodes corresponding to the plurality of cyclic permutation matrices; the first storage unit 708 is provided with a first read address and a first write address, and the first write address causes the first storage unit 708 to sequentially input the symbol values ​​of the messages transmitted to the check nodes by the variable nodes corresponding to each of the cyclic permutation matrices in the first order, and the first read address causes the first storage unit 708 to sequentially output the symbol values ​​of the messages transmitted to the check nodes by the variable nodes corresponding to each of the cyclic permutation matrices in the second order;

[0115] The second storage unit 709 is configured to: store the latest message of the check node corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module 702 and passed to the variable node; the second storage unit 709 is provided with a second read address and a second write address, and the second write address enables the second storage unit 709 to input the latest message of the check node corresponding to each of the cyclic permutation matrices stored in the negative node message storage module 702 and passed to the variable node in sequence according to the first order, and the second read address enables the second storage unit 709 to output the latest message of the check node corresponding to each of the cyclic permutation matrices stored in the negative node message storage module 702 and passed to the variable node in sequence according to the second order.

[0116] In some embodiments, the first storage unit 708 and the second storage unit 709 both include random access memories.

[0117] In some specific examples, the first storage unit 708 and the second storage unit 709 include simple dual-port RAM.

[0118] It should be noted that the first storage unit 708 and the second storage unit 709 are not limited to the random access memory proposed in the above embodiment, and can also be other memories including read addresses and write addresses.

[0119] Here, the first storage unit 708 stores the symbol value of the message transmitted to the check node by the variable node corresponding to the multiple cyclic permutation matrices after the permutation by the permutation unit 711. The second storage unit 709 stores the negative C2V message, that is, the negative C2V message shown in FIG. And the output value is involved in the calculation in the second calculation unit 704. Since the updated C2V message has not been rewritten into the node message storage module 702, the node message update module 703 stores the old C2V message of the last iteration of a frame codeword, so the second storage unit 709 stores the negative C2V message of the last iteration.

[0120] It is understood that since RAM has a read address and a write address, data can be written to and read from any location in the RAM. The first storage unit 708 provided in the disclosed embodiment has a first read address and a first write address, allowing it to write a V2C message corresponding to any cyclic permutation matrix in a layer. Furthermore, the first storage unit 708 can freely output the symbol value of the V2C message corresponding to any cyclic permutation matrix in a layer. Therefore, when updating the C2V message, the output order of the updated C2V message for any cyclic permutation matrix can be determined, providing optimization flexibility. The second storage unit 709 has a second read address and a second write address, allowing it to write a negative C2V message corresponding to any cyclic permutation matrix in a layer. Furthermore, the second storage unit 709 can freely output a negative C2V message corresponding to any cyclic permutation matrix in a layer. Therefore, when updating the posterior probability message, the output order of the posterior probability message corresponding to any cyclic permutation matrix in a layer of the check matrix can be determined.

[0121] In some embodiments, the depth of the first storage unit 708 is: the total weight of the quasi-cyclic low-density parity-check code basis matrix, and the width is: the product of the size of a cyclic permutation matrix and the width of a message transmitted from a check node to a variable node;

[0122] The depth of the second storage unit 709 is the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the size of a cyclic permutation matrix.

[0123] In some embodiments, the message update module 703 further includes: a first calculation unit 705, a message update unit 713 transmitted by the check node to the variable node;

[0124] The first calculation unit 705 is configured to: calculate the minimum value, the second minimum value, and the symbol exclusive OR value corresponding to one layer of the check matrix;

[0125] The message updating unit 713 transmitted by the check node to the variable node is configured to: receive the symbol values ​​of the message transmitted to the check node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit 708 in sequence in the second order, and receive the minimum value, the second minimum value, and the symbol XOR value corresponding to one layer of the check matrix calculated by the first calculation unit 705, and output the message transmitted to the variable node by the updated check node corresponding to each of the cyclic permutation matrices in sequence in the second order.

[0126] In some specific examples, the message update module 703 further includes a third storage unit 710 configured to cache the minimum value, the second minimum value, and the XOR value of a layer of the check matrix calculated by the first calculation unit 705 .

[0127] In some specific examples, the third storage unit 710 includes a FIFO.

[0128] In some specific examples, the first calculation unit 705 can calculate the minimum value and second minimum value of the V2C message corresponding to one layer of the check matrix based on the V2C message output by the permutation unit 711, and output the column position of the minimum value. After the permuted V2C message corresponding to the first layer of the cyclic permutation matrix is ​​output, the minimum value, column position, second minimum value, and XOR value of the V2C message corresponding to the first layer can be obtained and output to the third storage unit 710. In some specific examples, the message update unit 713 for the check node to transmit to the variable node can read the minimum value, column position, second minimum value, and XOR value of the variable node corresponding to one layer of the check matrix cached in the third storage unit 710, and simultaneously read the V2C message symbol value from the first storage unit 708. Based on the data read from the first storage unit 708 and the data read from the third storage unit 710, it is determined whether the current node has a minimum value. If it is a minimum value, the check node message is assigned the second minimum value; otherwise, the check node message is assigned the minimum value. The C2V messages corresponding to the first layer of the updated check matrix are LLR(c02v1, c12v2, c22v3, c32v4, c42v0), LLR(c02v7, c12v8, c22v9, c32v5, c42v6), LLR(c02v 15 , c12v 16 , c22v 17 , c32v 18 , c42v 19 ).

[0129] In some embodiments, the message update module 703 further includes: an inverse permutation unit 712;

[0130] The inverse permutation unit 712 is configured to: permute the sequence of messages transmitted by the check node to the variable node by the message update unit 713 output in the second order and corresponding to each of the cyclic permutation matrices, which are transmitted by the check node to the variable node, by replacing the sequence by the order of the check nodes with the sequence by the order of the corresponding variable nodes.

[0131] It is understandable that the inverse permutation unit 712 here cyclically shifts the message output by the message update unit 713 passed from the check node to the variable node. The sum of the shift values ​​of the inverse permutation unit 712 and the permutation unit 711 equals the size of a cyclic permutation matrix.

[0132] In some specific examples, the inverse permutation unit 712 cyclically shifts the message transmitted by the check node to the variable node output by the message update unit 713: the LLR (c02v1, c12v2, c22v3, c32v4, c42v0) corresponding to the non-zero submatrix 1 is cyclically shifted to the left by 4 to become LLR (c42v0, c02v1, c12v2, c22v3, c32v4); the LLR (c02v7, c12v8, c22v9, c32v5, c42v6) corresponding to the non-zero submatrix 2 is cyclically shifted to the left by 3 to become LLR (c32v5, c42v6, c02v7, c12v8, c22v9); the LLR (c02v7, c12v8, c22v9) corresponding to the non-zero submatrix 3 is cyclically shifted to the left by 3 to become LLR (c32v5, c42v6, c02v7, c12v8, c22v9); 15 , c12v 16 , c22v 17 , c32v 18 , c42v 19 ) Circular left shift 0 becomes LLR(c02v 15 , c12v 16 , c22v 17 , c32v 18 , c42v 19 ).

[0133] The message outputted by the inverse permutation unit 712 is the updated C2V message corresponding to one layer of the check matrix, i.e., The message output from the inverse permutation unit 712 enters the node message storage module 702 on one path and enters the second calculation unit 704 on the other path to participate in the calculation.

[0134] In some embodiments, the message update module 703 further includes: a second calculation unit 704;

[0135] The second calculation unit 704 is configured to: based on the message corresponding to each of the cyclic permutation matrices obtained by the inverse permutation unit 712, the message corresponding to each of the cyclic permutation matrices stored in the second storage unit 709, and the message corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module 701, output the updated posterior probability message corresponding to each of the cyclic permutation matrices in a second order.

[0136] Here, the second calculation unit 704 includes a first sub-calculation unit 7041 and a second sub-calculation unit 7042, wherein the first sub-calculation unit 7041 is configured to: Add After obtaining ΔC2V, the second calculation unit is configured to add ΔC2V to the posterior probability message stored in the posterior probability storage module 701 to obtain the updated posterior probability message LLR. updated .

[0137] In some specific examples, the first sub-computing unit 7041 and the second sub-computing unit 7042 include adders.

[0138] In the embodiment of the present disclosure, the message update module 703 receives the messages corresponding to each of the cyclic permutation matrices in a first order, and the message update module 703 outputs the messages corresponding to each of the cyclic permutation matrices in a second order, and the first order and the second order can be the same or different. This allows the output order of the messages corresponding to any cyclic permutation matrix in a layer of the check matrix to be freely selected, thereby increasing the degree of freedom, facilitating the optimization of convergence time, and improving throughput.

[0139] Based on the above decoder, an embodiment of the present disclosure further provides a memory controller, comprising the decoder described in any one of the above embodiments.

[0140] Based on the above memory controller, an embodiment of the present disclosure further provides a memory system, including the memory controller described in the above embodiment and a memory device coupled to the memory controller.

[0141] FIG9 shows a block diagram of a memory system 601. Memory system 601 includes a memory controller 602 and a memory device 603. Memory controller 602 is used to control memory device 603 to perform read and write operations. Memory controller 602 and memory device 603 can be coupled in any suitable manner. Memory controller 602 includes a control unit (CPU) 608, a data buffer 609, an error correction module 606, a host I / F 605, and a memory I / F 607. In the disclosed embodiment, memory device 603 may be a semiconductor memory for storing non-volatile data, such as a NAND memory. Memory system 601 is connected to a host 604. Host I / F 605 outputs commands and valid data (write data) received from host 604 to an internal bus 610, and sends valid data (read data) read from memory device 603 and responses from control unit 608 to host 604.

[0142] The control unit 608 can instruct the memory I / F 607 to write valid data, parity check data, and check matrix to the memory device 603 according to the command from the host 604. In addition, the control unit can instruct the memory I / F 607 to read valid data, parity check data, and check matrix from the memory device according to the command from the host 604.

[0143] The error correction module 606 here includes an encoding unit and a decoding unit. The encoding unit encodes the valid data of a predetermined size written to generate parity data (such as low-density parity check code LDPC) and a corresponding check matrix. The parity data and the corresponding check matrix generated by the encoding unit can be stored in a memory device. The decoding unit uses the parity data and the corresponding check matrix for decoding. The decoding unit here includes a decoder. The parity check code and the corresponding check matrix during decoding can be obtained from the memory device.

[0144] Based on the above memory system, an embodiment of the present disclosure further provides an electronic device, comprising the decoder described in any one of the above embodiments, and a memory device coupled to the decoder.

[0145] Here, the decoder may be built into the memory controller, or may not be built into the memory controller but be provided outside the memory controller.

[0146] Here, the specific structure and composition of the memory controller, memory system, and electronic device can be referred to the detailed introduction of Figures 1, 2a, 2b, 3a, 3b, 4, and 5 mentioned above. For the sake of brevity, they will not be repeated here.

[0147] Based on the above decoder, an embodiment of the present disclosure further provides a decoding method for layered decoding of quasi-cyclic low-density parity-check codes. In a message update process using inter-block serial decoding for multiple cyclic permutation matrices in a layer of a check matrix corresponding to a frame of codewords, as shown in FIG10 , the method includes:

[0148] Utilizing a posterior probability storage module to store posterior probability messages;

[0149] Utilize the node message storage module to store the message transmitted by the check node to the variable node;

[0150] The message update module is used to sequentially receive, in a first order, the latest posterior probability messages corresponding to each of the circulant permutation matrices stored in the posterior probability storage module, and sequentially receive, in the first order, the latest check node-to-variable node messages corresponding to each of the circulant permutation matrices stored in the node message storage module, and output, in a second order, the updated check node-to-variable node messages corresponding to each of the circulant permutation matrices, and output, in a second order, the updated posterior probability messages corresponding to each of the circulant permutation matrices; the first order is the same as or different from the second order.

[0151] In some embodiments, the outputting, in sequence in the second order, the messages transmitted from the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes, and the outputting, in sequence in the second order, the updated posterior probability messages corresponding to each of the circulant permutation matrices, include:

[0152] The third computing unit is used to sequentially receive, in the first order, the latest posterior probability messages corresponding to each of the circulant permutation matrices stored in the posterior probability storage module, and sequentially receive, in the first order, the latest messages transmitted from the check node to the variable node corresponding to each of the circulant permutation matrices stored in the negative node message storage module, and output, in the first order, the messages transmitted from the variable node corresponding to each of the circulant permutation matrices to the check node.

[0153] The above embodiment mainly reads the posterior probability message in the posterior probability message and the message transmitted to the variable node by the check node message in the node message storage module, and uses the third calculation unit to calculate the message transmitted to the check node by the variable node.

[0154] In some embodiments, the outputting, in sequence in the second order, the messages transmitted from the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes, and the outputting, in sequence in the second order, the updated posterior probability messages corresponding to each of the circulant permutation matrices, include:

[0155] A permutation unit is used to permutate the sequence of messages transmitted from the variable nodes corresponding to each of the circulant permutation matrices outputted by the third calculation unit to the check nodes, replacing the sequence of messages from the variable nodes to the sequence of messages from the variable nodes to the check nodes.

[0156] The above embodiment mainly utilizes the permutation unit to perform cyclic shift on the message transmitted from the variable node to the check node so as to facilitate transmission to the first calculation unit for corresponding calculation.

[0157] In some embodiments, the outputting, in sequence in the second order, the messages transmitted from the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes, and the outputting, in sequence in the second order, the updated posterior probability messages corresponding to each of the circulant permutation matrices, include:

[0158] A first storage unit is used to store the symbol values ​​of messages transmitted to the check node by the variable nodes corresponding to the plurality of cyclic permutation matrices; the first storage unit is provided with a first read address and a first write address, and the first write address causes the first storage unit to sequentially input the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to each of the cyclic permutation matrices in the first order, and the first read address causes the first storage unit to sequentially output the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to each of the cyclic permutation matrices in the second order;

[0159] A second storage unit is used to store the latest messages of the check nodes corresponding to the multiple cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes; the second storage unit is provided with a second read address and a second write address, and the second write address enables the second storage unit to input the latest messages of the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes in sequence according to the first sequence, and the second read address enables the second storage unit to output the latest messages of the check nodes corresponding to each of the cyclic permutation matrices stored in the negative node message storage module and passed to the variable nodes in sequence according to the second sequence.

[0160] In some embodiments, the outputting, in the second order, messages transmitted by the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes includes:

[0161] Calculating, by the first calculation unit, a minimum value, a second minimum value, and a symbol exclusive-OR value corresponding to one layer of the check matrix;

[0162] The message update unit that is used to update the check node to the variable node receives, in sequence in the second order, the symbol values ​​of the messages transmitted to the check node by the variable node corresponding to each of the cyclic permutation matrices stored in the first storage unit, and receives the minimum value, the second minimum value, and the symbol exclusive OR value corresponding to one layer of the check matrix calculated by the first calculation unit, and outputs, in sequence in the second order, the messages transmitted to the variable node by the updated check node corresponding to each of the cyclic permutation matrices.

[0163] The above embodiment mainly calculates the message transmitted from the variable node to the check node after the cyclic shift in the permutation unit to obtain the updated message transmitted from the check node to the variable node.

[0164] In some embodiments, the outputting, in sequence in the second order, the messages transmitted from the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes, and the outputting, in sequence in the second order, the updated posterior probability messages corresponding to each of the circulant permutation matrices, include:

[0165] The message update unit that transmits the check node to the variable node in a second order and that corresponds to each of the cyclic permutation matrices is used to transmit the check node to the variable node. The sequence of messages transmitted by the updated check node to the variable node is replaced by the order of the check nodes to the order of the corresponding variable nodes.

[0166] The above embodiment mainly performs cyclic shift on the message transmitted from the updated check node to the variable node by using the inverse permutation unit, so as to facilitate subsequent participation in calculation in the second calculation unit.

[0167] In some embodiments, outputting the updated posterior probability messages corresponding to each of the circulant permutation matrices in sequence in the second order includes:

[0168] The updated posterior probability message corresponding to each of the cyclic permutation matrices is output in sequence in a second order based on the message corresponding to each of the cyclic permutation matrices obtained by the second calculation unit based on the permutation of the inverse permutation unit, the message corresponding to each of the cyclic permutation matrices stored in the second storage unit, and the message corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module.

[0169] The above embodiment mainly adds the message transmitted from the negative check node output from the second storage unit to the variable node and the message transmitted from the updated and shifted check node output from the inverse permutation unit to the variable node, using the second calculation unit to obtain an updated posterior probability message.

[0170] In some embodiments, the method further includes: receiving an updated a posteriori probability message corresponding to each of the cyclic permutation matrices, and substituting the received updated a posteriori probability message corresponding to each of the cyclic permutation matrices into a check equation for verification; if all the check equations are satisfied, the decoding is determined to be successful; if all the check equations are not satisfied, the decoding is determined to have failed, and the next iteration is required to update the a posteriori probability message and the message passed from the check node to the variable node until the decoding is successful or the maximum number of iterations is reached.

[0171] The above embodiment mainly determines whether the number of iterations has been reached.

[0172] FIG11 is a decoding flow chart provided by an embodiment of the present disclosure. The decoding method provided by the above embodiment will be further introduced below in conjunction with FIG7 and FIG11.

[0173] After the initial channel message of a frame codeword is stored, decoding begins and the posterior probability message in the posterior probability storage module is read, as shown in FIG7 As shown, the posterior probability message of a cyclic permutation matrix is ​​read at a time. The C2V message read from the node message storage module is inverted and The V2C message obtained by adding them up enters the replacement unit, and the inverted C2V message is stored in the second storage unit.

[0174] The V2C message passes through the permutation unit and undergoes cyclic shift. The permuted V2C message takes its symbol value and stores it in the first storage unit. It then enters the first calculation unit for calculation. The first calculation unit outputs the minimum value, column position, next minimum value, and symbol XOR value corresponding to the V2C message of one layer of the check matrix, and caches them in the third storage unit. The message update unit, which is passed to the variable node by the check node, reads the data in the third storage unit and the V2C message symbol value cached in the first storage unit to update the C2V message.

[0175] The updated C2V message is cyclically shifted by the inverse permutation unit and stored in the node message storage module. At the same time, the second storage unit reads the negative C2V message stored in the node message storage module, and the second calculation unit adds the negative C2V message to the updated C2V message to obtain ΔC2V.

[0176] Read out the posterior probability message stored in the posterior probability storage module, as shown in FIG7 As shown, Added to ΔC2V by the second calculation unit to obtain the updated posterior probability message LLR updated The updated posterior probability message is stored in the posterior probability storage module to participate in subsequent message updates.

[0177] The above process is a message update process in an iterative process. After one iteration is completed, it is determined whether the maximum number of iterations has been reached. If not, the next iterative decoding is performed. Otherwise, the decoding is terminated and the decoded codeword is output.

[0178] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0179] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0180] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A decoder, based on a method of updating a message by using a block serial decoding method for a plurality of cyclic permutation matrices in a layer of a check matrix corresponding to a frame of codewords, the decoder comprising: The posterior probability storage module is configured to: store the posterior probability messages corresponding to each of the circulant permutation matrices; A node message storage module is configured to: store messages transmitted from the check nodes corresponding to each of the circulant permutation matrices to the variable nodes; as well as The message updating module is configured to: sequentially receive the a posteriori probability messages corresponding to each of the circulant permutation matrices and the messages transmitted by the check nodes to the variable nodes in a first order, and sequentially output the updated messages transmitted by the check nodes to the variable nodes and the updated a posteriori probability messages corresponding to each of the circulant permutation matrices in a second order; the first order is the same as or different from the second order.

2. The decoder according to claim 1, wherein: The message update module includes: a first storage unit and a second storage unit; The first storage unit is configured to: store the symbol values ​​of the messages transmitted to the check nodes by the variable nodes corresponding to the plurality of the cyclic permutation matrices; the first storage unit is provided with a first read address and a first write address, and the first storage unit is enabled to sequentially input the symbol values ​​of the messages transmitted to the check nodes by the variable nodes respectively corresponding to each of the cyclic permutation matrices according to the first sequence through the first write address, and to sequentially output the symbol values ​​of the messages transmitted to the check nodes by the variable nodes respectively corresponding to each of the cyclic permutation matrices according to the second sequence through the first read address; The second storage unit is configured to: store the latest check node message transmitted to the variable node corresponding to the plurality of the circulant permutation matrices stored in the negative node message storage module; the second storage unit is provided with a second read address and a second write address, and the second write address is used to store the latest check node message transmitted to the variable node. The second storage unit is configured to input the latest message passed to the variable node by each of the circulant permutation matrices stored in the negative node message storage module in sequence according to the first order, and the second storage unit is configured to output the latest message passed to the variable node by each of the circulant permutation matrices stored in the negative node message storage module in sequence according to the second order through the second read address.

3. The decoder according to claim 2, wherein: The first storage unit and the second storage unit each include a random access memory.

4. The decoder according to claim 2, wherein: The depth of the first storage unit is: the total weight of the quasi-cyclic low-density parity check code base matrix, and the width is: the product of the size of a cyclic permutation matrix and the width of a message transmitted from a check node to a variable node; The depth of the second storage unit is: the total weight of the quasi-cyclic low-density parity-check code base matrix, and the width is the size of a cyclic permutation matrix.

5. The decoder according to claim 2, wherein: The message update module also includes: a first calculation unit, a message update unit that the check node transmits to the variable node; The first calculation unit is configured to: calculate a minimum value, a second minimum value, and a symbol XOR value corresponding to a layer of the check matrix; The message updating unit that the check node transmits to the variable node is configured to: receive in sequence in the second order the symbol values ​​of the message transmitted to the check node by the variable node corresponding to each of the circulant permutation matrices respectively stored in the first storage unit, and receive the minimum value, the second minimum value, and the symbol XOR value corresponding to a layer of the check matrix calculated by the first calculation unit, and output in sequence in the second order the message transmitted to the variable node by the updated check node corresponding to each of the circulant permutation matrices respectively.

6. The decoder according to claim 5, wherein: The message update module also includes: an inverse permutation unit; The inverse permutation unit is configured to: permute the sequence of messages passed by the check nodes to the variable nodes output by the message update unit passing the check nodes to the variable nodes in the second order and corresponding to each of the circulant permutation matrices respectively, from the order of the check nodes to the order of the corresponding variable nodes.

7. The decoder according to claim 6, wherein: The message update module further includes: a second calculation unit; The second computing unit is configured to output updated a posteriori probability messages corresponding to each of the cyclic permutation matrices in a second order based on the message corresponding to each of the cyclic permutation matrices obtained by the inverse permutation unit, the message corresponding to each of the cyclic permutation matrices stored in the second storage unit, and the message corresponding to each of the cyclic permutation matrices stored in the posterior probability storage module.

8. The decoder according to claim 1, wherein: The a posteriori probability storage module includes two real dual-port random access memories.

9. The decoder according to claim 2, wherein: The message update module further includes: a third computing unit; The third computing unit is configured to: sequentially receive the latest a posteriori probability messages corresponding to each of the circulant permutation matrices stored in the a posteriori probability storage module in the first order, and sequentially receive the latest messages passed to variable nodes by the check nodes corresponding to each of the circulant permutation matrices stored in the negative node message storage module in the first order, and sequentially output the messages passed to the check nodes by the variable nodes corresponding to each of the circulant permutation matrices in the first order.

10. The decoder according to claim 9, wherein: The message update module further includes: a replacement unit; The permutation unit is configured to: transmit the sequence of messages of the variable nodes corresponding to each of the circulant permutation matrices outputted by the third calculation unit to the check nodes by The order is replaced by the order of the corresponding check nodes.

11. A memory controller comprising the decoder according to any one of claims 1 to 10.

12. A memory system comprising the memory controller according to claim 11 and a memory device coupled to the memory controller.

13. An electronic device, comprising the decoder according to any one of claims 1 to 10, and a memory device coupled to the decoder.

14. A decoding method, in which a plurality of cyclic permutation matrices in a layer of a check matrix corresponding to a frame of codewords are updated by using inter-block serial decoding, the method comprising: Using a posterior probability storage module to store the posterior probability messages corresponding to each of the circulant permutation matrices; Using a node message storage module to store messages transmitted to variable nodes by check nodes corresponding to each of the circulant permutation matrices; The message updating module is used to sequentially receive the a posteriori probability messages corresponding to each of the circulant permutation matrices and the messages transmitted by the check nodes to the variable nodes in a first order, and sequentially output the updated messages transmitted by the check nodes to the variable nodes and the updated a posteriori probability messages corresponding to each of the circulant permutation matrices in a second order; the first order is the same as or different from the second order.

15. The decoding method according to claim 14, wherein: The method of sequentially outputting the messages transmitted to the variable nodes by the updated check nodes corresponding to each of the circulant permutation matrices and the updated posterior probability messages in the second order comprises: A first storage unit is used to store the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to the plurality of circulant permutation matrices; the first storage unit is provided with a first read address and a first write address, and the first storage unit is enabled to sequentially input the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to each of the circulant permutation matrices in the first order through the first write address, and the first storage unit is enabled to sequentially input the symbol values ​​of the messages transmitted to the check node by the variable nodes corresponding to each of the circulant permutation matrices in the second order through the first read address. Outputting the symbol value of the message transmitted to the check node by the variable node corresponding to each of the circulant permutation matrices; A second storage unit is used to store the latest messages passed to variable nodes by the check nodes corresponding to the multiple circulant permutation matrices stored in the negative node message storage module; the second storage unit is provided with a second read address and a second write address, and the second write address enables the second storage unit to sequentially input the latest messages passed to variable nodes by each of the circulant permutation matrices stored in the negative node message storage module in the first order, and the second read address enables the second storage unit to sequentially output the latest messages passed to variable nodes by each of the circulant permutation matrices stored in the negative node message storage module in the second order.

16. The decoding method according to claim 15, wherein: The step of sequentially outputting in the second order the updated check nodes corresponding to each of the circulant permutation matrices and transmitting to the variable nodes the messages includes: Calculate the minimum value, the second minimum value, and the signed XOR value corresponding to one layer of the check matrix by using the first calculation unit; The message update unit that uses the check node to pass to the variable node receives, in sequence in the second order, the symbol values ​​of the messages passed to the check node by the variable node corresponding to each of the circulant permutation matrices stored in the first storage unit, and receives the minimum value, the second minimum value, and the symbol XOR value corresponding to a layer of the check matrix calculated by the first calculation unit, and outputs, in sequence in the second order, the messages passed to the variable node by the updated check node corresponding to each of the circulant permutation matrices.

17. The decoding method according to claim 16, wherein: The method of sequentially outputting the messages transmitted to the variable nodes by the updated check nodes corresponding to each of the circulant permutation matrices and the updated posterior probability messages in the second order comprises: The message update unit outputs the check nodes to the variable nodes in the second order and transmits the updated check nodes corresponding to each of the circulant permutation matrices to the variable nodes by using the inverse permutation unit. The sequence of messages of the variable nodes is replaced by the order of the check nodes to the order of the corresponding variable nodes.

18. The decoding method according to claim 17, wherein: The step of sequentially outputting updated a posteriori probability messages corresponding to each of the circulant permutation matrices in the second order comprises: The updated posterior probability messages corresponding to each of the circulant permutation matrices are output in sequence in a second order based on the message corresponding to each of the circulant permutation matrices obtained by the inverse permutation unit, the message corresponding to each of the circulant permutation matrices stored in the second storage unit, and the message corresponding to each of the circulant permutation matrices stored in the posterior probability storage module.

19. The decoding method according to claim 15, wherein: The method of sequentially outputting the messages transmitted to the variable nodes by the updated check nodes corresponding to each of the circulant permutation matrices and the updated posterior probability messages in the second order comprises: A third computing unit is used to sequentially receive, in the first order, the latest a posteriori probability messages corresponding to each of the circulant permutation matrices stored in the posterior probability storage module, and sequentially receive, in the first order, the latest messages passed from the check nodes to the variable nodes corresponding to each of the circulant permutation matrices stored in the negative node message storage module, and output, in the first order, the messages passed from the variable nodes corresponding to each of the circulant permutation matrices to the check nodes.

20. The decoding method according to claim 19, wherein: The method of sequentially outputting the messages transmitted to the variable nodes by the updated check nodes corresponding to each of the circulant permutation matrices and the updated posterior probability messages in the second order comprises: The sequence of messages transmitted to the check nodes by the variable nodes corresponding to each of the circulant permutation matrices outputted from the third calculation unit is permuted by a permutation unit from the sequence of the variable nodes to the sequence of the corresponding check nodes.

21. The decoding method according to claim 14, wherein: The method also includes: receiving updated a posteriori probability messages corresponding to each of the cyclic permutation matrices, and substituting the received updated a posteriori probability messages corresponding to each of the cyclic permutation matrices into a check equation for verification; if all the check equations are satisfied, the decoding is determined to be successful; if all the check equations are not satisfied, the decoding is determined to have failed, and the next iteration is required to update the a posteriori probability messages and the messages transmitted by the check nodes to the variable nodes until the decoding is successful or the maximum number of iterations is reached.

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