Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate cap layer, a gate electrode, a source electrode, and a drain electrode. The barrier layer is located on the side, away from the substrate, of the channel layer. The gate cap layer is located on the side, away from the substrate, of the barrier layer and comprises free P-type impurities and a complex formed by combining the P-type impurities and hydrogen impurities. The gate cap layer comprises a first part and a second part, the complex concentration in the first part is smaller than that in the second part, and hydrogen impurities in the second part are uniformly distributed. The gate is on the first portion, and the source and the drain are on the second portion. The semiconductor device is used for avoiding the problems of uneven etching and interface damage caused by etching a gate cap layer while realizing an enhanced high electron mobility transistor. The semiconductor device is applied to the electronic equipment to improve the performance of the electronic equipment.

Description

Semiconductor device and manufacturing method thereof, and electronic device Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Due to the improved switching characteristics, faster switching frequency, and lower losses of gallium nitride (GaN) materials, GaN power devices offer improved switching performance and are smaller in size, enabling smaller, lighter, more efficient, and more energy-efficient power systems. GaN power devices are primarily used in fast chargers for smartphones and computers, and they hold great promise for future applications such as electric vehicles, photovoltaic power generation, uninterruptible power supplies (UPS), and data centers.

[0003] A high electron mobility transistor (HEMT) is a semiconductor device that is widely used as a radio frequency device or a power device due to its advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability.

[0004] For GaN HEMT devices, due to the presence of high-concentration two-dimensional electron gas (2DEG), the gate cannot deplete the 2DEG in the channel at zero bias. That is, when the gate voltage is zero, current still flows in the channel. Therefore, a negative bias must be applied to the gate to deplete the 2DEG under the gate and put the HEMT into the off state. However, this will reduce circuit safety, increase the complexity of circuit design, and increase power consumption in applications. Therefore, realizing an enhancement-mode HEMT in the off state at zero gate bias is crucial to promoting the application of GaN HEMT devices in the power field.

[0005] Currently, GaN HEMT enhancement-mode devices primarily utilize cascode technology or p-GaN gate technology. Cascode technology cascades an enhancement-mode silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET) and a depletion-mode HEMT into a single device, achieving an enhancement-mode HEMT by controlling the enhancement-mode MOSFET. However, the GaN HEMT enhancement-mode devices implemented using this technology suffer from high switching power consumption, and the additional MOSFET increases system size, packaging complexity, and cost.

[0006] p-GaN gate technology employs a p-GaN gate cap layer beneath the gate to raise the energy band at the channel position and deplete the 2DEG in the channel, thereby realizing an enhancement-mode HEMT device. However, when using p-GaN gate technology to fabricate enhancement-mode HEMT devices, the p-GaN gate cap layer must be etched. Controlling the roughness, uniformity, and selectivity of the etching process is difficult, which can easily lead to uneven etching and interface damage.

[0007] Summary of the Invention

[0008] Embodiments of the present application provide a semiconductor device, a method for preparing the same, and an electronic device for realizing an enhanced high electron mobility transistor while avoiding the problems of uneven etching and interface damage caused by etching the p-GaN gate cap layer, thereby improving the performance of the semiconductor device.

[0009] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0010] In a first aspect, the present application provides a semiconductor device comprising a substrate, a channel layer, a barrier layer, a gate cap layer, a gate, a source, and a drain. The channel layer is located on one side of the substrate; the barrier layer is located on the side of the channel layer away from the substrate; the gate cap layer is located on the side of the barrier layer away from the substrate; the gate cap layer comprises free P-type impurities and a complex formed by combining P-type impurities and hydrogen impurities; the gate cap layer comprises a first portion and a second portion, the second portion being located at least on either side of the first portion; the concentration of the complex in the first portion is less than the concentration of the complex in the second portion, and the hydrogen impurities in the second portion are uniformly distributed. The gate, source, and drain are located on the side of the gate cap layer away from the substrate. The gate is located on the first portion, and the source and drain are located on the second portion.

[0011] In the semiconductor device provided herein, a gate cap layer is located on a side of the barrier layer away from the channel layer. The gate cap layer includes free P-type impurities and a complex formed by combining P-type impurities with hydrogen impurities. The concentration of the complex in the first portion of the gate cap layer is lower than the concentration of the complex in the second portion of the gate cap layer. That is, the free P-type impurities in the first portion are greater than those in the second portion, and the hole concentration in the first portion is greater than the hole concentration in the second portion. The first portion contacts the gate, and the second portion contacts the source and drain. Thus, when the voltage applied to the gate is zero, the two-dimensional electron gas in the channel layer below the gate can be depleted by the holes in the first portion, while the two-dimensional electron gas below the source and drain can be retained, thereby realizing an enhancement-mode HEMT.

[0012] Furthermore, because the gate, source, and drain electrodes are all disposed on the gate cap layer, which is a single-layer structure covering the barrier layer, etching of the gate cap layer is not required when fabricating the semiconductor device provided by the embodiments of the present application. This allows for the realization of an enhancement-mode HEMT while avoiding issues such as uneven etching or interface damage caused by etching the gate cap layer, thereby improving the yield, performance, and reliability of the semiconductor device.

[0013] At the same time, since the gate cap layer is a whole layer structure covering the barrier layer, there is no need to use a secondary epitaxial growth process to form the gate cap layer when preparing the semiconductor device provided in the embodiment of the present application. This not only avoids the problem of a large amount of impurities remaining between the barrier layer and the gate cap layer due to interface treatment of the barrier layer, affecting the performance of the semiconductor device, but also improves the quality of the gate cap layer.

[0014] In the embodiment of the present application, the hydrogen impurities in the second portion of the gate cap layer are uniformly distributed. Specifically, the hydrogen impurities in the second portion are doped into the gate cap layer's forming material during the gate cap layer formation process. Thus, compared to enhancement-mode HEMTs fabricated by first forming an entire gate cap layer and then performing hydrogen plasma implantation on portions of the gate cap layer not in contact with the gate, the semiconductor device provided in the embodiment of the present application does not require hydrogen plasma implantation, is less susceptible to damage to the barrier layer, and is less likely to affect the mobility of the two-dimensional electron gas, thereby ensuring the dynamic characteristics of the semiconductor device.

[0015] In some embodiments, the P-type impurities include Group II elements.

[0016] In some embodiments, the P-type impurity includes magnesium.

[0017] In some embodiments, the concentration of the P-type impurities is in the range of 1×10 18 cm -3 ~1×10 21 cm -3 This effectively depletes the two-dimensional electron gas in the channel layer below the gate when the gate voltage is zero, placing the semiconductor device in a normally-off state and realizing an enhancement-mode HEMT. Furthermore, it prevents excessive levels of P-type impurities, ensuring the performance and quality of the gate cap layer, and thus the semiconductor device.

[0018] In some embodiments, the semiconductor device further comprises a nucleation layer, the nucleation layer being located between the substrate and the channel layer. In embodiments of the present application, by providing the nucleation layer, it is possible to mitigate the difference in thermal expansion coefficient between the channel layer and the substrate, and mitigate the difference in lattice coefficient between the channel layer and the substrate, thereby making the lattice growth of the channel layer more uniform. Furthermore, the nucleation layer can also mitigate stress in the channel layer, thereby preventing the semiconductor device from fracturing due to high stress in the channel layer when the channel layer is directly formed on the substrate.

[0019] In some embodiments, the material of the nucleation layer includes aluminum nitride.

[0020] In some embodiments, the semiconductor device further includes a buffer layer located between the nucleation layer and the channel layer. Providing a buffer layer in the semiconductor device can improve the voltage resistance of the semiconductor device, thereby preventing the semiconductor device from being broken down when the operating voltage of the semiconductor device is high, thereby improving the operating stability of the semiconductor device.

[0021] In some embodiments, the buffer layer is a superlattice structure. The buffer layer provided in the embodiments of the present application adopts a superlattice structure. On the one hand, it can improve the breakdown resistance of the buffer layer by alternating two film layers of different materials, thereby further improving the high-voltage resistance of the semiconductor device. On the other hand, the use of a superlattice structure can also regulate the stress of the buffer layer, so that when the channel layer is formed on the side of the buffer layer away from the substrate, the stress change of the buffer layer is small, thereby improving the structural stability of the semiconductor device.

[0022] In some embodiments, the buffer layer comprises aluminum nitride and aluminum gallium nitride. Since aluminum nitride and aluminum gallium nitride have better pressure resistance than gallium nitride, using aluminum nitride and aluminum gallium nitride materials to prepare the buffer layer can further improve the pressure resistance of the buffer layer.

[0023] In some embodiments, the semiconductor device further includes an insertion layer positioned between the channel layer and the barrier layer. The polarization effects of the channel layer, insertion layer, and barrier layer can generate a higher two-dimensional electron gas concentration. Furthermore, the insertion layer can reduce alloy disorder scattering, thereby increasing two-dimensional electron gas mobility and improving the output characteristics of the semiconductor device.

[0024] In some embodiments, the material of the insertion layer includes aluminum nitride.

[0025] In some embodiments, the gate cap layer is made of gallium nitride.

[0026] In some embodiments, two-dimensional electron gas exists in the channel layer, and when the voltage on the gate is zero, the two-dimensional electron gas is depleted in a region of the channel layer below the first portion.

[0027] In a second aspect, the present application provides a method for preparing a semiconductor device, which comprises: forming a channel layer on a substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a gate cap layer on a side of the barrier layer away from the substrate; the gate cap layer comprises a complex formed by a combination of P-type impurities and hydrogen impurities, the gate cap layer comprising a first part and a second part, the second part being located at least on both sides of the first part; breaking the chemical bond between the P-type impurities and the hydrogen impurities in the complex located in the first part, so that the concentration of the complex in the first part is less than the concentration of the complex in the second part; forming a gate on the first part, and forming a source and a drain on the second part.

[0028] In some embodiments, breaking the chemical bond between the P-type impurity and the hydrogen impurity in the composite within the first portion includes forming a mask layer on a side of the gate cap layer facing away from the substrate, the mask layer having an opening that exposes the first portion, and performing laser annealing on the gate cap layer based on the mask layer to break the chemical bond between the P-type impurity and the hydrogen impurity in the composite within the first portion.

[0029] In some embodiments, forming a gate cap layer on a side of the barrier layer away from the substrate includes: forming a gate cap layer on a side of the barrier layer away from the substrate based on a reaction gas including ammonia, hydrogen, trimethylgallium and bismuth magnesium, or a reaction gas including ammonia, nitrogen, trimethylgallium and bismuth magnesium.

[0030] In some embodiments, before forming the channel layer on the substrate, the preparation method further includes: forming a nucleation layer on the substrate.

[0031] In some embodiments, after forming the nucleation layer on the substrate and before forming the channel layer on the substrate, the preparation method further includes: forming a buffer layer on a side of the nucleation layer away from the substrate, wherein the buffer layer is a superlattice structure.

[0032] In some embodiments, after forming the channel layer on the substrate and before forming the barrier layer on a side of the channel layer away from the substrate, the preparation method further includes: forming an insertion layer on a side of the channel layer away from the substrate.

[0033] In a third aspect, the present application provides an electronic device, comprising a circuit board and a semiconductor device as described in any of the above embodiments; the semiconductor device is electrically connected to the circuit board.

[0034] Among them, the technical effects brought about by any design method in the second to third aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0036] FIG2 is a diagram showing a state of the semiconductor device being prepared according to the preparation method provided in FIG1 ;

[0037] FIG3 is a flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application;

[0038] 4 to 6 are diagrams showing the manufacturing state of the semiconductor device corresponding to the manufacturing method provided in FIG. 3 ;

[0039] FIG7 is a flow chart of forming a gate cap layer according to an embodiment of the present application;

[0040] 8 and 9 are diagrams showing the state of the semiconductor device being prepared according to the preparation method provided in FIG. 3 ;

[0041] FIG10 is a flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0042] 11 and 12 are diagrams showing the state of the semiconductor device being prepared according to the preparation method provided in FIG. 10 ;

[0043] FIG13 is a flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0044] FIG14 is a diagram showing a state of the semiconductor device being prepared according to the preparation method provided in FIG13 ;

[0045] FIG15 is a flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0046] FIG16 is a diagram showing a state of the semiconductor device being prepared according to the preparation method provided in FIG15 ;

[0047] FIG17 is a flow chart of another method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0048] FIG18 is a diagram showing a state of the semiconductor device being prepared according to the preparation method provided in FIG17 ;

[0049] FIG19 is a structural diagram of a semiconductor device provided in an embodiment of the present application;

[0050] FIG20 is a structural diagram of another semiconductor device provided in an embodiment of the present application;

[0051] FIG21 is a structural diagram of another semiconductor device provided in an embodiment of the present application;

[0052] FIG22 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0053] FIG23 is a flowchart of a working process of a power switch provided in an embodiment of the present application. DETAILED DESCRIPTION

[0054] The following describes the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. In the description of the present application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship. For example, A / B can represent A or B.

[0055] The "and / or" in this application is only a way to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0056] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0057] To facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0058] At the same time, in the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0059] As shown in FIG1 , in order to avoid the problems of uneven etching and interface damage caused by etching the p-GaN gate cap layer, in some embodiments, a method for preparing a semiconductor device is provided. Referring to FIG2 , the method includes:

[0060] S101 , forming a barrier layer 102 on the channel layer 101 .

[0061] S102 , forming a hard mask layer 103 on a side of the barrier layer 102 away from the channel layer 101 , wherein the hard mask layer 103 has a preset opening 104 , and the preset opening 104 exposes a portion of the surface of the barrier layer 102 away from the channel layer 101 .

[0062] S103 , performing selective epitaxial growth of a p-GaN material in the preset opening 104 to form a p-GaN gate cap layer 105 .

[0063] S104 , forming a gate 106 on a side of the p-GaN gate cap layer 105 away from the channel layer 101 . Exemplarily, while forming the gate 106 , a source 107 and a drain 108 may also be formed on a side of the barrier layer 102 away from the channel layer 101 .

[0064] In the above embodiment, the difference in the adhesion coefficient of gallium (Ga) atoms on the surface of the barrier layer 102 and the surface of the hard mask layer 103 is utilized to selectively grow the p-GaN gate cap layer 105 on the barrier layer 102, thereby eliminating the need to etch the p-GaN gate cap layer 105, thereby avoiding the problems of uneven etching or interface damage caused by etching the p-GaN gate cap layer 105.

[0065] However, in actual operation, it is necessary to first form a whole hard mask layer 103 on the barrier layer 102, and then pattern the hard mask layer 103 using photoresist to obtain the hard mask layer 103 with the preset opening 104. Therefore, before the selective epitaxial growth of the p-GaN material in the preset opening 104 is performed, the surface of the barrier layer 102 exposed by the preset opening 104 needs to be processed (for example, etching, cleaning, etc.). As a result, a large amount of impurities such as silicon (Si) and oxygen (O) will remain at the interface between the barrier layer 102 and the p-GaN gate cap layer 105. These impurities easily react with the barrier layer 102 to form compounds, thereby affecting the control ability of the gate and further affecting the performance of the semiconductor device. At the same time, the presence of these impurities can easily lead to leakage of the semiconductor device.

[0066] Furthermore, since the hard mask layer 103 needs to be formed outside the growth chamber, after forming the barrier layer 102 on the channel layer 101, the unfinished semiconductor device needs to be removed from the growth chamber. After the hard mask layer 103 is formed, the semiconductor device with the hard mask layer 103 formed is placed back into the growth chamber for selective epitaxial growth of the p-GaN material. In other words, the p-GaN gate cap layer 105 in the above embodiment needs to be formed using a secondary epitaxial growth process. However, in the early stages of the secondary epitaxial growth process, the quality of the epitaxially formed material is poor, which can easily lead to poor quality of the semiconductor device.

[0067] In view of the above problems, an embodiment of the present application provides a method for manufacturing a semiconductor device 100, as shown in FIG3 , the method comprising:

[0068] S100 , as shown in FIG. 4 , a channel layer 20 is formed on a substrate 10 .

[0069] In some examples, the material of substrate 10 may include silicon, silicon carbide (SiC), or sapphire. When the material of substrate 10 includes silicon, substrate 10 may be a silicon on insulator (SOI) substrate. Alternatively, substrate 10 may be a silicon wafer.

[0070] In some embodiments, the material of the channel layer 20 may include gallium nitride (GaN).

[0071] In some embodiments, a channel layer 20 can be formed on one side of the substrate 10 using a reaction gas comprising ammonia (NH3), hydrogen (H2), and trimethyl gallium. Hydrogen can be used as a carrier gas to deliver the reaction gas into the growth chamber. Ammonia can be used as a nitrogen source, and trimethyl gallium is used to provide the Group III element. For example, nitrogen (N2) can be used to replace hydrogen to deliver the reaction gas into the growth chamber.

[0072] It is understood that, in the preparation method provided in the embodiment of the present application, the reaction gas used to prepare the channel layer 20 is not limited thereto.

[0073] In some embodiments, when forming the channel layer 20 on one side of the substrate 10 , the reaction temperature may be 1050 degrees Celsius (° C.). In the embodiments of the present application, the reaction temperature for forming the channel layer 20 is not limited to 1050 degrees Celsius, and the reaction temperature may also be other values ​​that are conducive to the formation of the channel layer 20 .

[0074] In some examples, the thickness of the channel layer 20 may be 500 nm. It is understood that the thickness of the channel layer 20 in the present application is not limited thereto, and the thickness of the channel layer 20 may be adjusted according to the structure and performance requirements of the semiconductor device 100 .

[0075] S200 , as shown in FIG. 5 , a barrier layer 30 is formed on a side of the channel layer 20 away from the substrate 10 .

[0076] The barrier layer 30 can be used to cooperate with the channel layer 20 to generate a two-dimensional electron gas (2DEG) between the channel layer 20 and the barrier layer 30 through polarization. The two-dimensional electron gas can efficiently conduct electrons under the action of an electric field.

[0077] The material of the barrier layer 30 may include aluminum gallium nitride (AlGaN).

[0078] In some embodiments, a barrier layer 30 can be formed on the side of the channel layer 20 away from the substrate 10 using a reaction gas including ammonia, hydrogen (or nitrogen), trimethyl aluminum (trimethyl aluminum) and trimethyl gallium. Hydrogen or nitrogen can be used as a carrier gas to transport the reaction gas into the growth chamber. Trimethyl aluminum and trimethyl gallium are used to provide Group III elements, and nitrogen can be used as a nitrogen source. In the preparation method provided in the embodiment of the present application, the reaction gas for preparing the barrier layer 30 is not limited thereto.

[0079] In some embodiments, when forming the barrier layer 30 on the side of the channel layer 20 away from the substrate 10, the reaction temperature may be 1050 degrees Celsius. In the embodiments of the present application, the reaction temperature for forming the barrier layer 30 is not limited to 1050 degrees Celsius, and the reaction temperature may also be other values ​​that are conducive to the formation of the barrier layer 30.

[0080] In some embodiments, the barrier layer 30 may be formed to a thickness of 12 nanometers (nm). It is understood that the thickness of the barrier layer 30 in this application is not limited thereto, and those skilled in the art may adjust the thickness of the barrier layer 30 according to the structure and performance requirements of the semiconductor device 100.

[0081] S300. As shown in FIG6 , a gate cap layer 40 is formed on a side of the barrier layer 30 away from the substrate 10. The gate cap layer 40 includes a complex formed by the combination of P-type impurities and hydrogen impurities. The gate cap layer 40 includes a first portion 41 and a second portion 42. The second portion 42 is located at least on both sides of the first portion 41. FIG6 shows the microstructure of the gate cap layer 40. The complex formed by the combination of P-type impurities and hydrogen impurities in the gate cap layer 40 is shown as a black circle.

[0082] Illustratively, “the second portion 42 is at least located on both sides of the first portion 41 ” may mean that the second portion 42 is located on both sides of the first portion, or that the second portion 42 is arranged around the circumference of the first portion 41 .

[0083] In some embodiments, the material of the gate cap layer 40 may include gallium nitride.

[0084] In some embodiments, the P-type impurities may include Group II elements.

[0085] For example, the P-type impurity may include a Group IIA element, such as one or a combination of at least two of beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), and barium (Ba). When the P-type impurity includes a Group IIA element, the P-type impurity can more easily combine with the hydrogen impurity to form a complex.

[0086] Of course, the P-type impurities may also be elements in Group IIB, such as one or a combination of at least two of zinc (Zn), mercury (Hg), and cadmium (Cd).

[0087] Since magnesium has a lower ionization energy among P-type impurities than other P-type impurities, it is easy to be doped and is also easy to combine with hydrogen to form a complex. Therefore, in some examples, the P-type impurity may include magnesium. In this case, the complex formed by the P-type impurity and the hydrogen impurity may include a Mg-H complex.

[0088] In some examples, the gate cap layer 40 may be formed on a side of the barrier layer 30 away from the substrate 10 by doping a material forming the gate cap layer 40 with P-type impurities.

[0089] Based on this, as shown in FIG7 , step S300 of forming a gate cap layer 40 on a side of the barrier layer 30 away from the substrate 10 includes:

[0090] S310, based on ammonia, hydrogen, trimethyl gallium and bismuth magnesium (C 10 H 10 Mg) or a reaction gas including ammonia, nitrogen, trimethyl gallium and bis(cyclopentadienyl)magnesium is used to form a gate cap layer 40 on a side of the barrier layer 30 away from the substrate 10.

[0091] Magnesium cyclopentadienyl can provide P-type impurities for gate cap layer 40. Hydrogen or nitrogen can be used as carrier gases to transport the gases into the growth chamber. Ammonia, hydrogen, trimethylgallium, and magnesium cyclopentadienyl all contain hydrogen, so the formed gate cap layer 40 may contain hydrogen impurities. The hydrogen impurities can form complexes with the P-type impurities during the formation of gate cap layer 40.

[0092] It is understandable that the reaction gas provided in this application is not limited thereto, and the source of the P-type impurities is not limited to bismuth magnesium, and can be selected according to the design requirements of the semiconductor device 100 .

[0093] In some embodiments, the concentration of P-type impurities may be in the range of 1×10 18 cm -3 ~1×10 21 cm -3For example, the concentration of P-type impurities can be 1×10 18 cm -3 , 5×10 18 cm -3 , 1×10 19 cm -3 , 4×10 19 cm -3 , 6×10 19 cm -3 , 1×10 20 cm -3 , 5×10 20 cm -3 , 1×10 21 cm -3 .

[0094] It is understood that not all of the P-type impurities doped in the gate cap layer 40 can combine with the H impurities to form a complex, and therefore free P-type impurities may still exist in the gate cap layer 40. The P-type impurities in the "P-type impurity concentration" described in the above embodiments of the present application include not only the P-type impurities used to form a complex, but also the free P-type impurities.

[0095] In this way, on the one hand, the concentration of P-type impurities will not be too high, thereby not affecting the performance of the gate cap layer 40; on the other hand, the concentration of P-type impurities will not be too low, so that when the voltage applied to the gate is zero, the P-type impurities are sufficient to deplete the electrons (two-dimensional electron gas) in the channel layer, thereby putting the semiconductor device in a normally-off state.

[0096] Likewise, not all hydrogen impurities doped in the gate cap layer 40 can necessarily combine with the P-type impurities to form a complex, so free hydrogen impurities may still exist in the gate cap layer 40 .

[0097] Since P-type impurities and hydrogen impurities are introduced into the reactants for forming the gate cap layer 40 in the above-mentioned embodiments of the present application, after the gate cap layer 40 is formed, free P-type impurities and free hydrogen impurities, as well as a complex formed by the combination of P-type impurities and hydrogen impurities can be evenly distributed in the gate cap layer 40.

[0098] In some embodiments, when forming the gate cap layer 40 on the side of the barrier layer 30 away from the substrate 10, the reaction temperature may be 950 degrees Celsius. In the embodiments of the present application, the reaction temperature for forming the gate cap layer 40 is not limited to 950 degrees Celsius, and the reaction temperature may also be other values ​​that are conducive to the formation of the gate cap layer 40.

[0099] In some examples, the gate cap layer 40 may have a thickness of 80 nm. It is understood that the thickness of the gate cap layer 40 in this application is not limited thereto and may be adjusted according to the structure and performance requirements of the semiconductor device 100 .

[0100] In some embodiments, the substrate 10 may be placed in a growth chamber, and metal-organic chemical vapor deposition (MOCVD) may be used as a growth technique to form the channel layer 20 , the barrier layer 30 , and the gate cap layer 40 on the substrate 10 .

[0101] S400 , as shown in FIG8 , breaks the chemical bond between the P-type impurity and the hydrogen impurity in the complex in the first portion 41 , so that the concentration of the complex in the first portion 41 is lower than the concentration of the complex in the second portion 42 .

[0102] 8 , after the chemical bond between the P-type impurity and the hydrogen impurity in the complex within the first portion 41 is broken, the P-type impurity may still exist in the first portion 41 , while the hydrogen impurity may diffuse into the air in a free state.

[0103] "Breaking the chemical bonds between the P-type impurities and the hydrogen impurities in the complex within the first portion 41" may mean breaking the chemical bonds between the P-type impurities and the hydrogen impurities in all the complexes within the first portion 41, or breaking the chemical bonds between the P-type impurities and the hydrogen impurities in some of the complexes within the first portion 41, as long as it can be ensured that after step S400, the activated P-type impurities in the first portion 41 can first deplete the two-dimensional electron gas thereunder.

[0104] S500 , as shown in FIG. 9 , a gate 51 is formed on the first portion 41 , and a source 52 and a drain 53 are formed on the second portion 42 .

[0105] Exemplarily, the material of the gate 51 may include metal, such as nickel, gold, etc.

[0106] For example, the source electrode 52 and the drain electrode 53 may be made of metal, such as titanium, aluminum, gold, etc.

[0107] For example, a device processing technology may be used to form a gate 51 on the first portion 41 , and a source 52 and a drain 53 on the second portion 42 .

[0108] The gate 51 forms a Schottky contact with the first portion 41, and the source 52 and drain 53 form ohmic contacts with the second portion 42. The source 52 and drain 53 are configured to allow the two-dimensional electron gas to flow within the channel layer 20 between the source 52 and drain 53 under the action of an electric field. The gate 51 is located between the source 52 and drain 53 and is configured to allow or prevent the passage of the two-dimensional electron gas.

[0109] In the embodiment of the present application, there is no limitation on the thickness of the gate 51 , the source 52 and the drain 53 , as long as the performance requirements of the semiconductor device can be met.

[0110] In the above-described embodiment of the present application, a full-layer gate cap layer 40 is first grown on the side of the barrier layer 30 away from the substrate 10. Both the first portion 41 and the second portion 42 of the gate cap layer 40 contain a complex formed by a combination of a P-type impurity and a hydrogen impurity. The first portion 41 of the gate cap layer 40 is then treated to break the chemical bonds between the P-type impurity and the hydrogen impurity in the complex within the first portion 41. This activates the P-type impurity within the first portion 41 of the gate cap layer 40, increasing the hole concentration within the first portion 41 and thereby depleting the two-dimensional electron gas below the first portion 41. While the P-type impurity within the second portion 42 remains passivated by the hydrogen impurity, the two-dimensional electron gas below the second portion 42 is retained. After forming the gate 51, source 52, and drain 53, when the voltage applied to the gate 51 is zero, the two-dimensional electron gas disappears below the gate 51, and the semiconductor device 100 is turned off, thereby realizing an enhancement-mode HEMT. The second portion 42 below the source 52 and the drain 53 maintains high resistance due to the presence of the P-type impurities in the form of a complex, which is beneficial to improving current collapse and leakage of the semiconductor device.

[0111] In the fabrication methods provided in the above-described embodiments of the present application, etching of the gate cap layer 40 is not required, thereby avoiding problems such as uneven etching or interface damage caused by etching the gate cap layer 40, thereby improving the yield, performance, and reliability of the resulting semiconductor device. Furthermore, since etching of the gate cap layer 40 is not required, the fabrication process is simplified, improving process efficiency, and eliminating reliance on expensive and complex etching equipment, thereby reducing fabrication costs.

[0112] Compared to implementing an enhancement-mode HEMT device by forming a gate cap layer beneath the gate using a secondary epitaxial growth process, the embodiments of the present application, on the one hand, do not require interface treatment of the barrier layer, thereby avoiding problems such as weakened gate control capability and semiconductor device leakage caused by the presence of impurities such as silicon and oxygen. Furthermore, the embodiments of the present application can directly grow the gate cap layer 40 on the barrier layer 30 without the use of a secondary epitaxial growth technique, resulting in higher quality epitaxially grown materials and, consequently, better quality of the resulting semiconductor device 100.

[0113] It is worth mentioning that, compared with the method of forming an entire gate cap layer and then performing hydrogen plasma injection on the portion of the gate cap layer that is not in contact with the gate, thereby obtaining an enhanced HEMT that does not require etching, the preparation method provided in the embodiment of the present application does not require plasma injection, thereby avoiding physical damage to the barrier layer caused by the plasma injection process and the adverse effects on the mobility of the two-dimensional electron gas, thereby ensuring the dynamic characteristics of the semiconductor device.

[0114] 10 to 12 , the step S400 in the above embodiment, in which the chemical bond between the P-type impurity and the hydrogen impurity in the complex within the first portion 41 is broken, is further described.

[0115] As shown in FIG10 , step S400 of breaking the chemical bond between the P-type impurities and the hydrogen impurities in the complex within the first portion 41 includes:

[0116] S410 , as shown in FIG. 11 , a mask layer 11 is formed on a side of the gate cap layer 40 away from the substrate 10 . The mask layer 11 has an opening 111 , and the opening 111 exposes the first portion 41 .

[0117] Exemplarily, the material of the mask layer 11 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), titanium nitride (TiN), etc.

[0118] Illustratively, the mask layer 11 may be formed on the side of the gate cap layer 40 away from the substrate 10 by a deposition method. For example, the mask layer 11 may be formed on the side of the gate cap layer 40 away from the substrate 10 by a chemical vapor deposition process.

[0119] In some embodiments, before forming the mask layer 11 on the side of the gate cap layer 40 away from the substrate 10 , the semiconductor device with the gate cap layer 40 formed thereon may be taken out of the growth chamber, thereby preparing the mask layer 11 outside the growth chamber.

[0120] In some examples, a whole mask layer 11 can be first formed on the side of the gate cap layer 40 away from the substrate 10, and then a photoresist layer can be formed on the side of the mask layer 11 away from the substrate 10. The photoresist layer can be patterned by processes such as exposure and development, and finally the mask layer 11 can be etched using the patterned photoresist layer to form an opening 111.

[0121] In the embodiment of the present application, there is no limitation on the number, shape and arrangement position of the openings 111 in the mask layer 11 and they can be designed according to the requirements of the semiconductor device.

[0122] S420 , as shown in FIG. 12 , laser annealing is performed on the gate cap layer 40 based on the mask layer 11 to break the chemical bond between the P-type impurities and the hydrogen impurities in the complex within the first portion 41 .

[0123] The downward arrow in Figure 12 represents laser light. During laser annealing of the gate cap layer 40 based on the mask layer 11, a portion of the laser light is directed onto the mask layer 11, while another portion of the laser light passes through the opening 111 of the mask layer 11 and is directed onto the first portion 41 of the gate cap layer 40. The high-energy laser light raises the temperature of the first portion 41, thereby breaking the chemical bonds between the P-type impurities and the hydrogen impurities in the complex within the first portion 41.

[0124] For example, after laser annealing is performed on the gate cap layer 40 , the mask layer 11 may be removed.

[0125] For example, a laser with a wavelength of 355 nanometers and a frequency of 20 kHz can be used to perform laser annealing on the gate cap layer 40. The laser wavelength and laser frequency used in the embodiments of the present application are not limited thereto. The laser annealing equipment can be selected based on the energy required to break the chemical bond between the P-type impurity and the hydrogen impurity, thereby adjusting the laser wavelength and frequency.

[0126] For example, when the gate cap layer 40 is laser annealed based on the mask layer 11 , the atmosphere may be a nitrogen atmosphere.

[0127] The above-described embodiment of the present application utilizes a mask layer 11 having an opening 111 and a laser annealing process to simultaneously break the chemical bonds between the P-type impurities and the hydrogen impurities in the composite within the first portion 41 while preserving the chemical bonds between the P-type impurities and the hydrogen impurities in the composite within the second portion 42. This allows the two-dimensional electron gas in the channel layer 20 below the first portion 41 to be depleted while the two-dimensional electron gas in the channel layer 20 below the second portion 42 is retained. In this manner, an enhancement-mode HEMT can be realized without etching the gate cap layer 40.

[0128] At the same time, compared with the traditional thermal annealing process, the laser annealing process has the characteristics of high energy, fast speed, small damage to the material and precise controllable annealing range. Therefore, it can achieve ultra-fast annealing of the gate cap layer 40, improve process efficiency and shorten process time.

[0129] In addition to the steps of the preparation method provided in the above embodiment, in some embodiments, as shown in FIG13 , before forming the channel layer 20 on the substrate 10 in step S100 , the preparation method may further include:

[0130] S110 , as shown in FIG. 14 , a nucleation layer 60 is formed on the substrate 10 .

[0131] Among them, the nucleation layer 60 can be used to alleviate the lattice coefficient mismatch and thermal expansion coefficient mismatch between the material of the substrate 10 and the material of the channel layer 20, thereby avoiding the problem of excessive stress in the channel layer 20 when the channel layer 20 is directly formed on the substrate 10, resulting in the fracture of the channel layer 20 or other film layers.

[0132] For example, the material of the nucleation layer 60 may include aluminum nitride.

[0133] In some examples, a reaction gas including ammonia, hydrogen, and trimethylaluminum may be used to form the nucleation layer 60 on one side of the substrate 10. The hydrogen may be replaced by nitrogen.

[0134] In some examples, when forming the nucleation layer 60 on the substrate 10 , the reaction temperature may be 1100 degrees Celsius. The thickness of the formed nucleation layer 60 may be 200 nanometers.

[0135] In the embodiment of the present application, the reaction gas, reaction temperature, and thickness of the nucleation layer 60 for forming the nucleation layer 60 are not limited to the above embodiment and can be adjusted according to actual needs.

[0136] In some embodiments, the substrate 10 may be placed in a growth chamber, and a metal organic chemical vapor deposition (MOCVD) technique may be used to form a nucleation layer 60 on the substrate 10 .

[0137] In some embodiments, as shown in FIG. 15 , after forming the nucleation layer 60 on the substrate 10 in step S110 and before forming the channel layer 20 on the substrate 10 in step S100 , the preparation method further includes:

[0138] S120: As shown in FIG16 , a buffer layer 70 is formed on a side of the nucleation layer 60 away from the substrate 10. The buffer layer 70 may be a superlattice structure.

[0139] For example, the material of the buffer layer 70 may include aluminum nitride (AlN) and aluminum gallium nitride (AlGaN). Since aluminum nitride and aluminum gallium nitride have better pressure resistance than gallium nitride, using aluminum nitride and aluminum gallium nitride to prepare the buffer layer 70 can further improve the pressure resistance of the buffer layer 70.

[0140] For example, the number of superlattice pairs in buffer layer 70 can be 90. For example, when the material of buffer layer 70 includes aluminum nitride and aluminum gallium nitride, buffer layer 70 can include 90 aluminum nitride layers and 90 aluminum gallium nitride layers stacked alternately. The thickness of a single aluminum nitride layer can be 5 nanometers, and the thickness of a single aluminum gallium nitride layer can be 25 nanometers.

[0141] It is understandable that the material of the buffer layer 70 and the superlattice structure provided in the embodiment of the present application are not limited thereto and can be designed according to the performance requirements of the semiconductor device 100 .

[0142] By forming the buffer layer 70 , the voltage resistance of the semiconductor device 100 can be improved. When the operating voltage of the semiconductor device 100 is relatively high (eg, 650V), the semiconductor device 100 can be prevented from being broken down, thereby improving the operating stability of the semiconductor device 100 .

[0143] The buffer layer 70 provided in the embodiments of the present application utilizes a superlattice structure. This, on the one hand, utilizes alternating layers of two different materials to improve the breakdown resistance of the buffer layer 70, thereby further improving the high-voltage resistance of the semiconductor device 100. Furthermore, the superlattice structure can also regulate the stress of the buffer layer 70. Thus, when the channel layer 20 is formed on the side of the buffer layer 70 away from the substrate 10, the stress of the buffer layer 70 changes less, thereby improving the structural stability of the semiconductor device 100.

[0144] In some embodiments, the substrate 10 may be placed in a growth chamber, and metal organic chemical vapor deposition may be used as a growth technique to form the buffer layer 70 on a side of the nucleation layer 60 away from the substrate 10 .

[0145] When the material of buffer layer 70 includes aluminum nitride or aluminum gallium nitride, a reaction gas including ammonia, hydrogen (or nitrogen), trimethylaluminum, and trimethylgallium can be used to form buffer layer 70. Hydrogen (or nitrogen) can be used as a carrier gas to deliver the reaction gas into the growth chamber.

[0146] In some examples, when forming the buffer layer 70 on the substrate 10 , the reaction temperature may be 1000 degrees Celsius. The reaction temperature for forming the buffer layer 70 in the embodiment of the present application is not limited to 1000 degrees Celsius, and the reaction temperature may also be other values ​​that are conducive to the formation of the buffer layer 70 .

[0147] When the material of the nucleation layer 60 is aluminum nitride and the film layer of the buffer layer 70 closest to the substrate 10 is an aluminum nitride layer, in an embodiment of the present application, forming the nucleation layer 60 before forming the buffer layer 70 can also improve the formation quality of the buffer layer 70, thereby improving the quality and yield of the semiconductor device.

[0148] In some embodiments, as shown in FIG. 17 , after forming the channel layer 20 on the substrate 10 in step S100 and before forming the barrier layer 30 on a side of the channel layer 20 away from the substrate 10 in step S200 , the preparation method may further include:

[0149] S130. Referring to FIG. 18 and FIG. 19 , an insertion layer 80 is formed on a side of the channel layer 20 away from the substrate 10. The polarization effect of the channel layer 20, the insertion layer 80, and the barrier layer 30 can generate a higher two-dimensional electron gas concentration. Furthermore, the insertion layer 80 can reduce alloy disorder scattering, thereby increasing the two-dimensional electron gas mobility, thereby improving the output characteristics of the semiconductor device 100.

[0150] For example, the material of the insertion layer 80 may include aluminum nitride, and the thickness of the insertion layer 80 may be 0.4 nanometers. It is understood that the material and thickness of the insertion layer 80 in this application are not limited thereto, and the material and thickness of the insertion layer 80 can be designed according to the performance requirements of the semiconductor device.

[0151] In some embodiments, a reaction gas including ammonia, hydrogen, and trimethylaluminum may be used to form the insertion layer 80 on a side of the channel layer 20 away from the substrate 10. The hydrogen may be replaced by nitrogen.

[0152] In some embodiments, when forming the insertion layer 80 on a side of the channel layer 20 away from the substrate 10 , the reaction temperature may be 1050 degrees Celsius.

[0153] In some embodiments, the substrate 10 may be placed in a growth chamber, and metal organic chemical vapor deposition (MOCVD) may be used as a growth technique to form the insertion layer 80 on the substrate 10 .

[0154] In order to better grow other film layers (for example, the channel layer 20 , the nucleation layer 60 or the buffer layer 70 , etc.) on the substrate 10 , the substrate 10 may be subjected to high-temperature surface cleaning to remove the oxide layer on the substrate 10 before growing or forming the film layers on the substrate 10 .

[0155] For example, the substrate 10 may be subjected to high-temperature surface cleaning in a hydrogen atmosphere at a temperature of 1100 degrees Celsius. Hydrogen has reducing properties and can reduce the oxide layer on the surface of the substrate 10 under high temperature conditions.

[0156] For example, the substrate 10 may be subjected to high-temperature surface cleaning in the growth chamber, so that the film layer can be grown directly after the substrate 10 is cleaned, thereby avoiding the re-oxidation of the substrate surface during the process of moving the substrate.

[0157] For example, the time for performing high-temperature surface cleaning on the substrate 10 may be 5 minutes.

[0158] It is understandable that in the embodiment of the present application, the temperature and time for high-temperature surface cleaning of the substrate 10 are not limited and can be adaptively adjusted according to the processing conditions.

[0159] As shown in FIG9 , some embodiments of the present application provide a semiconductor device 100 , which can be manufactured by the method for manufacturing the semiconductor device 100 provided in any of the above embodiments.

[0160] The semiconductor device 100 includes a substrate 10 , a channel layer 20 , a barrier layer 30 , a gate cap layer 40 , a gate 51 , a source 52 , and a drain 53 .

[0161] The material of the substrate 10 may include silicon, silicon carbide, or sapphire. When the material of the substrate 10 includes silicon, the substrate 10 may be a silicon-on-insulator substrate. Alternatively, the substrate 10 may be a silicon wafer.

[0162] The channel layer 20 is located on one side of the substrate 10. For example, the material of the channel layer 20 may include gallium nitride.

[0163] The barrier layer 30 is located on a side of the channel layer 20 away from the substrate 10. For example, the material of the barrier layer 30 may include aluminum gallium nitride.

[0164] The channel layer 20 and the barrier layer 30 form a heterojunction. Through polarization, a two-dimensional electron gas is formed in the region where the channel layer 20 and the barrier layer contact each other. The two-dimensional electron gas can efficiently transmit electrons under the action of an electric field.

[0165] The gate cap layer 40 is located on the side of the barrier layer 30 away from the substrate 10. The gate cap layer 40 includes free P-type impurities and a composite formed by combining the P-type impurities with hydrogen impurities. The gate cap layer 40 includes a first portion 41 and a second portion 42, with the second portion 42 located on at least two sides of the first portion 41. The composite concentration in the first portion 41 is lower than that in the second portion 42, and the hydrogen impurities in the second portion 42 are uniformly distributed.

[0166] “The second portion 42 is at least located on both sides of the first portion 41 ” may mean that the second portion 42 is located on both sides of the first portion, or that the second portion 42 is disposed around the circumference of the first portion 41 .

[0167] In some embodiments, the material of the gate cap layer 40 may include gallium nitride.

[0168] In some embodiments, the P-type impurities may include Group II elements.

[0169] The P-type impurities may include Group IIA elements, such as one or a combination of at least two of beryllium, magnesium, calcium, strontium, and barium. When the P-type impurities include Group IIA elements, the P-type impurities may more easily combine with hydrogen impurities to form a complex.

[0170] Of course, the P-type impurities may also be elements in Group IIB, such as one of zinc, mercury, and cadmium, or a combination of at least two of them.

[0171] Since magnesium has a lower ionization energy among P-type impurities than other P-type impurities, it is easy to be doped and is also easy to combine with hydrogen substances to form a complex. Therefore, in some examples, the P-type impurity may include magnesium. In this case, the complex formed by the P-type impurity and the hydrogen impurity may include a Mg-H complex.

[0172] The gate 51 , the source 52 and the drain 53 are located on a side of the gate cap layer 40 away from the substrate 10 . The gate 51 is located on the first portion 41 , and the source 52 and the drain 53 are located on the second portion 42 .

[0173] For example, the gate electrode 51 may be made of a metal such as nickel, gold, etc. The source electrode 52 and the drain electrode 53 may be made of a metal such as titanium, aluminum, gold, etc.

[0174] The gate 51 forms a Schottky contact with the first portion 41, and the source 52 and drain 53 form ohmic contacts with the second portion 42. The source 52 and drain 53 are configured to allow the two-dimensional electron gas to flow within the channel layer 20 between the source 52 and drain 53 under the action of an electric field. The gate 51 is located between the source 52 and drain 53 and is configured to allow or prevent the passage of the two-dimensional electron gas.

[0175] In the semiconductor device 100 provided herein, the gate cap layer 40 is located on a side of the barrier layer 30 away from the channel layer 20. The gate cap layer 40 includes free P-type impurities and a complex formed by combining the P-type impurities with hydrogen impurities. The concentration of the complex in the first portion 41 of the gate cap layer 40 is lower than that in the second portion 42 of the gate cap layer 40. That is, the free P-type impurities in the first portion 41 are greater than those in the second portion 42, and the hole concentration in the first portion 41 is greater than that in the second portion 42. The first portion 41 contacts the gate 51, while the second portion 42 contacts the source 52 and the drain 53. Thus, when the voltage on the gate 51 is zero, the two-dimensional electron gas in the region of the channel layer 20 below the gate 51 (or the first portion 41) can be depleted by the holes in the first portion 41, while the two-dimensional electron gas below the source 52 and the drain 53 can be retained, thereby realizing an enhancement-mode HEMT. The second portion 42 below the source 52 and the drain 53 can maintain high resistance due to the presence of the P-type impurities in the form of a complex, thereby facilitating improvement of current collapse and leakage of the semiconductor device 100 .

[0176] Furthermore, since the gate 51, source 52, and drain 53 are all disposed on the gate cap layer 40, and the gate cap layer 40 is a complete layer structure covering the barrier layer 30, it is not necessary to etch the gate cap layer 40 when fabricating the semiconductor device 100 provided in the embodiment of the present application. This allows for the realization of an enhancement-mode HEMT while avoiding problems such as uneven etching or interface damage caused by etching the gate cap layer, thereby improving the yield, performance, and reliability of the semiconductor device 100.

[0177] At the same time, since the gate cap layer is a whole layer structure covering the barrier layer 30, there is no need to use a secondary epitaxial growth process to form the gate cap layer when preparing the semiconductor device 100 provided in the embodiment of the present application. This not only avoids the problem of a large amount of impurities remaining between the barrier layer and the gate cap layer due to interface treatment of the barrier layer, which affects the performance of the semiconductor device, but also improves the quality of the gate cap layer 40.

[0178] In the embodiment of the present application, the hydrogen impurities in the second portion 42 of the gate cap layer 40 are uniformly distributed. That is, the hydrogen impurities in the second portion 42 are doped into the material forming the gate cap layer during the process of forming the gate cap layer 40. Thus, compared to enhancement-mode HEMTs fabricated by first forming an entire gate cap layer and then performing hydrogen plasma implantation on portions of the gate cap layer not in contact with the gate, the semiconductor device provided in the embodiment of the present application does not require hydrogen plasma implantation, is less likely to damage the barrier layer 30, and is less likely to affect the mobility of the two-dimensional electron gas, thereby ensuring the dynamic characteristics of the semiconductor device.

[0179] In some embodiments, the concentration of P-type impurities ranges from 1×10 18 cm -3 ~1×10 21 cm -3 .

[0180] This effectively depletes the two-dimensional electron gas in the channel layer 20 below the gate 51 when the gate 51 voltage is zero, placing the semiconductor device 100 in a normally-off state and realizing an enhancement-mode HEMT. Furthermore, it prevents excessive levels of P-type impurities, thereby ensuring the performance and quality of the gate cap layer 40 and, consequently, the semiconductor device.

[0181] It can be understood that the “P-type impurities” described herein include not only free P-type impurities, but also P-type impurities located in the complex.

[0182] Similarly, the “hydrogen impurities” described in the above embodiments include not only free hydrogen impurities, but also hydrogen impurities located in the complex.

[0183] Considering that when the channel layer is formed directly on the substrate, the semiconductor device may be easily broken due to excessive stress generated in the channel layer, in some embodiments, as shown in Figure 20, the semiconductor device 100 may further include a nucleation layer 60, which is located between the substrate 10 and the channel layer 20.

[0184] By providing the nucleation layer 60 in the embodiment of the present application, the difference in thermal expansion coefficient between the channel layer 20 and the substrate 10 can be mitigated, as can the difference in lattice coefficient between the channel layer 20 and the substrate, thereby achieving more uniform lattice growth in the channel layer 20. Furthermore, the nucleation layer 60 can also alleviate stress in the channel layer 20, preventing the semiconductor device from fracturing due to high stress in the channel layer when the channel layer is directly formed on the substrate.

[0185] In some examples, the material of the nucleation layer 60 may include aluminum nitride. The thickness of the nucleation layer 60 may be 200 nanometers. It is understood that the material and thickness of the nucleation layer 60 are not limited thereto and can be designed according to actual needs.

[0186] In some embodiments, as shown in FIG. 21 , the semiconductor device 100 may further include a buffer layer 70 , where the buffer layer 70 is located between the nucleation layer 60 and the channel layer 20 .

[0187] By providing a buffer layer 70 in the semiconductor device 100 , the voltage resistance of the semiconductor device 100 can be improved, thereby preventing the semiconductor device from being broken down when the operating voltage of the semiconductor device 100 is relatively high (for example, 650 volts), thereby improving the operating stability of the semiconductor device 100 .

[0188] In some embodiments, the buffer layer 70 may be a superlattice structure.

[0189] A superlattice structure is a multilayer film that uses two different materials to alternately grow thin layers of a few nanometers to tens of nanometers and has a periodic structure. The buffer layer 70 provided in the embodiment of the present application adopts a superlattice structure. On the one hand, it can improve the breakdown resistance of the buffer layer 70 by alternating film layers of two different materials, thereby further improving the high-voltage resistance of the semiconductor device 100. On the other hand, the use of a superlattice structure can also regulate the stress of the buffer layer 70. Therefore, when the channel layer 20 is formed on the side of the buffer layer 70 away from the substrate 10, the stress of the buffer layer 70 changes less, thereby improving the structural stability of the semiconductor device 100.

[0190] In some examples, the number of superlattice pairs of buffer layer 70 is 90 pairs.

[0191] In some embodiments, the material of the buffer layer 70 may include aluminum nitride and aluminum gallium nitride. Since aluminum nitride and aluminum gallium nitride have better pressure resistance than gallium nitride, using aluminum nitride and aluminum gallium nitride to prepare the buffer layer 70 can further improve the pressure resistance of the buffer layer 70.

[0192] The buffer layer 70 is made of aluminum nitride and aluminum gallium nitride, that is, the superlattice structure includes an alternating arrangement of aluminum nitride layers and aluminum gallium nitride layers. For example, the thickness of the aluminum nitride layer can be 5 nanometers, and the thickness of the aluminum gallium nitride layer can be 25 nanometers.

[0193] It can be understood that the superlattice logarithm, film layer materials and thicknesses provided in the above embodiments are merely exemplary descriptions, and specific values ​​and materials can be adjusted according to the performance requirements of the semiconductor device.

[0194] In some embodiments, as shown in FIG. 19 , the semiconductor device 100 may further include an insertion layer 80 located between the channel layer 20 and the barrier layer 30 .

[0195] In this way, the polarization effect of the channel layer 20, the insertion layer 80 and the barrier layer 30 can produce a higher two-dimensional electron gas concentration, and the insertion layer 80 can reduce alloy disorder scattering to increase the two-dimensional electron gas mobility, which is beneficial to improving the output characteristics of the semiconductor device.

[0196] In some examples, the material of the insertion layer 80 includes aluminum nitride. The thickness of the insertion layer 80 can be 0.4 nanometers. It is understood that the material and thickness of the insertion layer 80 are not limited to this and can be designed according to actual needs.

[0197] As shown in FIG22 , an embodiment of the present application provides an electronic device 1000 , which can be, for example, a charger, a small household appliance (such as a soymilk maker or a robot vacuum), a mobile phone, a computer, an electric car, a data center, or the like. The embodiment of the present application does not impose any particular limitation on the specific form of the electronic device.

[0198] As shown in FIG. 22 , the electronic device 1000 may further include a circuit board 200 (eg, a printed circuit board (PCB)), and the semiconductor device 100 may be electrically connected to the circuit board 200 .

[0199] When electronic device 1000 is a charger, semiconductor device 100 can be used in the charger's power switch 300. As shown in FIG23 , power switch 300 may further include an input filter 301, a rectifier circuit 302, a switching power transistor 303, a transformer 304, an output filter 305, a pulse width modulation circuit 306, and a switch driver 307. Semiconductor device 100 serves as the switching power transistor 303.

[0200] The output end of the input filter 301 is connected to the input end of the rectifier circuit 302, the output end of the rectifier circuit 302 is connected to the input end of the switching power transistor 303, the output end of the switching power transistor 303 is connected to the input end of the transformer 304, the output end of the transformer 304 is connected to the input end of the output filter 305, the output end of the output filter 305 is connected to the input end of the pulse width modulation circuit 306, the output end of the pulse width modulation circuit 306 is connected to the input end of the switch driver 307, and the output end of the switch driver 307 is connected to the control end of the switching power transistor 303.

[0201] Figure 23 shows a flowchart of the operation of power switch 300. In power switch 300, input filter 301 and rectifier circuit 302 convert the input power into direct current (e.g., converting alternating current into direct current, or vice versa). Switching power transistor 303 performs high-speed on-off switching, converting the DC output from input filter 301 and rectifier circuit 302 into high-frequency alternating current (AC). This is then supplied to transformer 304 for voltage transformation. The transformed power is then output by output filter 305, generating one or more desired voltages. The output power, through pulse-width modulation circuit 306 and switch driver 307, can also provide feedback control to switching power transistor 303, further improving the output voltage of power switch 300.

[0202] The semiconductor device 100 can also be connected to other circuits through the circuit board 200. For example, the semiconductor device 100 can be electrically connected to the input filter 301, the rectifier circuit 302, the transformer 304, the output filter 305, the pulse width modulation circuit 306 and the switch driver 307 through the circuit board 200.

[0203] The beneficial effects that can be achieved by the electronic device 1000 provided in the embodiment of the present application are the same as the beneficial effects that can be achieved by the semiconductor device 100 and the method for preparing the semiconductor device 100 provided in the above-mentioned embodiment of the present application.

[0204] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0205] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a channel layer, located on one side of the substrate; a barrier layer, located on a side of the channel layer away from the substrate; a gate cap layer located on a side of the barrier layer away from the substrate; the gate cap layer comprising free P-type impurities and a composite formed by combining the P-type impurities and hydrogen impurities; the gate cap layer comprising a first portion and a second portion, the second portion being located at least on both sides of the first portion; a concentration of the composite in the first portion being less than a concentration of the composite in the second portion, and the hydrogen impurities in the second portion being uniformly distributed; The gate, source and drain are located on a side of the gate cap layer away from the substrate; the gate is located on the first portion, and the source and drain are located on the second portion.

2. The semiconductor device according to claim 1, wherein The P-type impurities include Group II elements.

3. The semiconductor device according to claim 1 or 2, wherein: The P-type impurities include magnesium.

4. The semiconductor device according to any one of claims 1 to 3, wherein The concentration range of the P-type impurities is 1×10 18 cm -3 ~1×10 21 cm -3 .

5. The semiconductor device according to any one of claims 1 to 4, wherein: Also includes: A nucleation layer is located between the substrate and the channel layer.

6. The semiconductor device according to claim 5, wherein The material of the nucleation layer includes aluminum nitride.

7. The semiconductor device according to claim 5 or 6, characterized in that Also includes: A buffer layer is located between the nucleation layer and the channel layer.

8. The semiconductor device according to claim 7, wherein: The buffer layer is a superlattice structure.

9. The semiconductor device according to claim 7 or 8, characterized in that The material of the buffer layer includes aluminum nitride and aluminum gallium nitride.

10. The semiconductor device according to any one of claims 1 to 9, wherein: Also includes: An insertion layer is located between the channel layer and the barrier layer.

11. The semiconductor device according to claim 10, wherein: The material of the insertion layer includes aluminum nitride.

12. The semiconductor device according to any one of claims 1 to 11, wherein: The gate cap layer is made of gallium nitride.

13. The semiconductor device according to any one of claims 1 to 12, wherein: Two-dimensional electron gas exists in the channel layer. When the voltage on the gate is zero, the channel layer is located in a region below the first portion, and the two-dimensional electron gas is depleted.

14. A method for preparing a semiconductor device, characterized in that: include: forming a channel layer on the substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a gate cap layer on a side of the barrier layer away from the substrate; the gate cap layer comprises a complex formed by combining P-type impurities and hydrogen impurities, the gate cap layer comprises a first portion and a second portion, the second portion being located at least on both sides of the first portion; breaking a chemical bond between a P-type impurity and a hydrogen impurity in the complex in the first portion, so that a concentration of the complex in the first portion is lower than a concentration of the complex in the second portion; A gate is formed on the first portion, and a source and a drain are formed on the second portion.

15. The preparation method according to claim 14, characterized in that The breaking of the chemical bond between the P-type impurity and the hydrogen impurity in the complex within the first portion comprises: forming a mask layer on a side of the gate cap layer away from the substrate, wherein the mask layer has an opening, and the opening exposes the first portion; Laser annealing is performed on the gate cap layer based on the mask layer to break chemical bonds between the P-type impurities and the hydrogen impurities in the complex within the first portion.

16. The preparation method according to claim 14 or 15, characterized in that: The forming of a gate cap layer on a side of the barrier layer away from the substrate comprises: A gate cap layer is formed on a side of the barrier layer away from the substrate based on a reaction gas including ammonia, hydrogen, trimethyl gallium and bismuthocene magnesium, or a reaction gas including ammonia, nitrogen, trimethyl gallium and bismuthocene magnesium.

17. The preparation method according to any one of claims 14 to 16, characterized in that Before forming the channel layer on the substrate, the preparation method further includes: A nucleation layer is formed on the substrate.

18. The preparation method according to claim 17, characterized in that: After forming the nucleation layer on the substrate and before forming the channel layer on the substrate, the preparation method further includes: A buffer layer is formed on a side of the nucleation layer away from the substrate, and the buffer layer is a superlattice structure.

19. The preparation method according to any one of claims 14 to 18, characterized in that After forming the channel layer on the substrate and before forming the barrier layer on a side of the channel layer away from the substrate, the preparation method further comprises: An insertion layer is formed on a side of the channel layer away from the substrate.

20. An electronic device, characterized in that: include: circuit boards; The semiconductor device according to any one of claims 1 to 13; The semiconductor device is electrically connected to the circuit board.

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