Self-testing device for ultrasonic transducer array

Abstract

The invention discloses a self-testing device for an ultrasonic transducer array, relates to the technical field of transducer array testing, and solves the technical problem that the development speed of a transducer array integration process is too slow due to insufficient transducer array testing accuracy and efficiency. According to the technical scheme, the magnitude of a to-be-measured capacitor is obtained by calculating the rising time and the falling time of charging and discharging of the to-be-measured capacitor, and measurement of array elements in a transducer array is achieved; and meanwhile, a reference capacitor is introduced to reduce current errors and inaccuracy caused by circuit parasitic capacitance. By means of the self-testing device, measurement of electrical parameters of all mainstream transducers can be achieved, and the development speed of the transducer array integration process is greatly increased.

Description

Technical Field

[0001] The present application relates to the technical field of transducer array testing, and in particular to a self-testing device for an ultrasonic transducer array. Background Art

[0002] Large-scale one-dimensional or two-dimensional ultrasonic transducer arrays usually contain one thousand or even tens of thousands of array elements, which are connected to the ultrasonic imaging host through a flexible PCB or ASIC as a substrate. How to efficiently evaluate the electrical connection performance of each transducer array element and the substrate has always been a very difficult problem. The most direct approach is to connect each transducer array element to the host for testing. However, this approach is time-consuming and inefficient, and the test accuracy is limited by the parasitic capacitance and impedance mismatch caused by the wires. Therefore, there is an urgent need for an efficient testing method that can achieve fast measurement while ensuring measurement accuracy.

[0003] Generally, the capacitance of the transducer is measured to measure whether the transducer array element has established an effective electrical connection with the substrate. The electrical characteristics of the transducer can be modeled by the BVD (Butterworth-van-Dyke) model, such as Figure 1 As shown. There are many different types of transducers, such as PZT, CMUT, PMUT, PVDF, etc. These transducers can be divided into two categories, single-ended and double-ended. In a single-ended transducer, the bottom electrode is usually grounded or connected to a fixed level, and the top electrode is connected to the circuit for signal amplification. A double-ended transducer has three ports, and its Outter electrode and Inner electrode are connected to the circuit. By measuring the capacitance Cp of each transducer array element, the electrical connection characteristics of the transducer array element and the substrate as well as the physical characteristics of the transducer itself can be effectively evaluated.

[0004] The capacitance of each transducer element can be measured using a built-in self-test circuit (BIST). Figure 2a and Figure 2b The BIST circuit shown is for a single-ended ultrasonic transducer or other sensor, and its current source The capacitor to be tested will be charged and discharged. Charge to or from Discharge to The comparator output will be higher or lower than the reference voltage when the input is higher or lower than the reference voltage. It is known that The size of the capacitor to be tested can be measured by the counter on the chip or system side to measure the rise time of the charge and discharge of the capacitor to be tested. and fall time Calculated, expressed as: (1) in, Represents a current source The error, Indicates the magnitude of the circuit's parasitic capacitance.

[0005] However, the above BIST circuit cannot eliminate the error of the reference current and the inaccuracy caused by the circuit parasitic capacitance, and is lacking in efficiency and accuracy in testing the transducer array. Summary of the invention

[0006] The present application provides a self-testing device for an ultrasonic transducer array, the technical purpose of which is to improve the test accuracy and efficiency of the transducer array, so as to significantly increase the development speed of the transducer array integration process.

[0007] The above technical objectives of this application are achieved through the following technical solutions: A self-testing device for an ultrasonic transducer array, comprising: A charge-discharge module for charging and discharging a reference capacitor, a capacitor module to be measured, and a circuit parasitic capacitor; A comparison / amplification module for obtaining the charge and discharge time of the reference capacitor, the capacitor module to be tested, and the circuit parasitic capacitor; The size of the capacitor module to be measured is obtained according to the charge and discharge time of the reference capacitor, the capacitor module to be measured and the circuit parasitic capacitance; The comparison / amplification module includes at least one comparator or at least one amplifier, each of which includes two input terminals and one output terminal, one input terminal is connected to the charge and discharge module, and the other input terminal is connected to the reference voltage.

[0008] Further, the charging and discharging module includes at least one charging and discharging unit, and each charging and discharging unit includes a charging unit and a discharging unit; or each charging and discharging unit includes a charging unit and a reset switch; Or each charge and discharge unit includes a discharge unit and a setting switch.

[0009] Further, the capacitance module to be measured includes a capacitance to be measured, the comparison / amplification module includes a comparator / amplifier, and the charge-discharge module includes a charge-discharge unit; One end of the circuit parasitic capacitor is grounded; the other end is connected to the charge and discharge unit, and is connected to the reference capacitor through a reference switch; One end of the reference capacitor is grounded, and the other end is connected to the charge and discharge unit and the circuit parasitic capacitance through a reference switch; One end of the capacitor to be tested is grounded; the other end is connected to the charge and discharge unit through the switch to be tested, and is connected to the reference capacitor through the switch to be tested and the reference switch; When the charge-discharge unit includes a charge unit and a discharge unit, the charge unit and the discharge unit are both connected to a reference capacitor through a reference switch, connected to a capacitor to be tested through a switch to be tested, connected to a circuit parasitic capacitor, and connected to an input terminal of a comparator / amplifier; When the charge-discharge unit includes a charging unit and a reset switch, the charging unit and the reset switch are connected to the reference capacitor through the reference switch, connected to the capacitor to be tested through the switch to be tested, connected to the circuit parasitic capacitance, and connected to an input terminal of the comparator / amplifier; When the charge and discharge unit includes a discharge unit and a set switch, the discharge unit and the set switch are connected to the reference capacitor through the reference switch, connected to the capacitor to be tested through the test switch, connected to the circuit parasitic capacitance, and connected to an input terminal of the comparator / amplifier.

[0010] Further, the charge and discharge module includes a first charge and discharge unit and a second charge and discharge unit, the comparison / amplification module includes a first comparator / amplifier and a second comparator / amplifier, the capacitance module to be measured includes a first capacitance to be measured, a second capacitance to be measured, a first switch and a second switch, and the switch to be measured includes a first switch to be measured and a second switch to be measured; One input end of the first comparator / amplifier and the second comparator / amplifier are both connected to a reference voltage, another input end of the first comparator / amplifier is connected to the output of the first charge and discharge unit, another input end of the second comparator / amplifier is connected to the output of the second charge and discharge unit, and the output ends of the first comparator / amplifier and the second comparator / amplifier are both connected to a logic gate module; When the first charge-discharge unit and the second charge-discharge unit both include a charging unit and a discharging unit, the charging unit and the discharging unit of the first charge-discharge unit are both connected to the reference capacitor through a reference switch, and connected to the first capacitor to be measured and the circuit parasitic capacitance through a first switch to be measured; the charging unit and the discharging unit of the second charge-discharge unit are connected to the second capacitor to be measured through a second switch to be measured; When the first charge-discharge unit and the second charge-discharge unit both include a charging unit and a reset switch, the charging unit and the reset switch of the first charge-discharge unit are connected to the reference capacitor through the reference switch, and connected to the first capacitor to be measured and the circuit parasitic capacitance through the first switch to be measured; the charging unit and the reset switch of the second charge-discharge unit are connected to the second capacitor to be measured through the second switch to be measured; When the first charge and discharge unit and the second charge and discharge unit both include a discharge unit and a set switch, the discharge unit and the set switch of the first charge and discharge unit are connected to the reference capacitor through the reference switch, and connected to the first capacitor to be measured and the circuit parasitic capacitance through the first switch to be measured; the discharge unit and the set switch of the second charge and discharge unit are connected to the second capacitor to be measured through the second switch to be measured.

[0011] Further, one end of the first capacitor to be tested is grounded; the other end is grounded through a first switch, connected to the first charge and discharge unit through the first switch to be tested, and connected to the reference capacitor through the first switch to be tested and the reference switch; One end of the second capacitor to be tested is grounded; the other end is grounded through a second switch and connected to the second charge and discharge unit through the second switch to be tested; One end of the circuit parasitic capacitor is grounded through a first switch, connected to the first charge-discharge unit through a first switch to be tested, and connected to a reference capacitor through the first switch to be tested and a reference switch; the other end is grounded through a second switch, and connected to the second charge-discharge unit through a second switch to be tested; One end of the first switch is grounded, and the other end is connected to the first charge and discharge unit through the first switch to be tested, and is connected to the reference capacitor through the first switch to be tested and the reference switch; one end of the second switch is grounded, and the other end is connected to the second charge and discharge unit through the second switch to be tested.

[0012] Furthermore, the capacitor module to be tested also includes a third switch; one end of the third switch is connected to the first charge and discharge unit, connected to the first switch, the first capacitor to be tested and one end of the circuit parasitic capacitance through the first switch to be tested, and connected to the reference capacitor through the reference switch; the other end of the third switch is connected to the second charge and discharge unit, and connected to the second switch, the second capacitor to be tested and the other end of the circuit parasitic capacitance through the second switch to be tested.

[0013] Further, the first switch, the second switch, the first switch to be tested and the second switch to be tested are all MOS switches.

[0014] Furthermore, the self-test device further comprises a self-test selection module and an amplification selection module; the self-test selection module comprises a first capacitor and a self-test selection switch connected in parallel; the amplification selection module comprises a second capacitor, a resistor and an amplification selection switch, the second capacitor and the resistor are connected in parallel, one end of the second capacitor and one end of the resistor are both connected to the amplification selection switch, and the other ends are both connected to the output end of the comparison / amplification module, and the amplification selection switch, the first capacitor, the self-test selection switch and an input end of the comparison / amplification module are all connected; The first capacitor and the self-test selection switch are both connected to the charge and discharge unit, and are both connected to the reference capacitor through the reference switch.

[0015] Further, when the comparison / amplification module includes a first comparator / amplifier and a second comparator / amplifier: the amplification selection switch, the first capacitor, the self-test selection switch, and one input end of the first comparator / amplifier and the second comparator / amplifier are all connected; the other end of the second capacitor and the other end of the resistor are all connected to the output ends of the first comparator / amplifier and the second comparator / amplifier.

[0016] Furthermore, the ultrasonic transducer array includes a linear array ultrasonic transducer and a planar array ultrasonic transducer.

[0017] The beneficial effects of the present application are as follows: the self-test device for ultrasonic transducer arrays described in the present application calculates the size of the capacitance to be measured by the rise time and fall time of the charging and discharging of the capacitance to be measured, thereby measuring the array elements in the transducer array; at the same time, a reference capacitor is introduced to reduce the current error and the inaccuracy caused by the circuit parasitic capacitance. The self-test device can measure the electrical parameters of all mainstream transducers, greatly improving the development speed of the transducer array integration process. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the schematic diagram of the electrical model of the transducer; Figure 2a It is a schematic diagram of an existing self-test circuit; Figure 2b for Figure 2a The timing diagram of the charging and discharging process corresponding to the self-test circuit; Figure 2c for Figure 2a An embodiment in which the discharge unit is replaced by a reset switch, only one measurement is required; Figure 2d for Figure 2a Another embodiment, in which the charging unit is replaced by a setting switch, only one measurement is required; Figure 3 This is a schematic diagram of the structure of a capacitor self-test device according to Embodiment 1 of the present application; Figure 4 This is a schematic diagram of the structure of a differential capacitor self-test device according to Embodiment 2 of the present application; Figure 5 This is a schematic structural diagram of a differential capacitor self-test device according to Embodiment 3 of the present application; Figure 6 This is a schematic diagram of the structure of a differential capacitor self-test device according to Embodiment 4 of the present application. DETAILED DESCRIPTION

[0019] The technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0020] The self-test device for ultrasonic transducer array described in the present application includes a charge-discharge module and a comparison / amplification module. The charge-discharge module is used to charge and discharge the reference capacitor, the capacitor module to be tested and the circuit parasitic capacitor; the comparison / amplification module is used to obtain the charge-discharge time of the reference capacitor, the capacitor module to be tested and the circuit parasitic capacitor; and finally the size of the capacitor module to be tested is obtained according to the charge-discharge time of the reference capacitor, the capacitor module to be tested and the circuit parasitic capacitor.

[0021] The comparison / amplification module includes at least one comparator or at least one amplifier, each of which includes two input terminals and one output terminal, one input terminal is connected to the charge and discharge module, and the other input terminal is connected to the reference voltage.

[0022] As a specific embodiment, the charge and discharge module includes at least one charge and discharge unit. In the embodiment of the present application, the specific implementation of the charge and discharge unit is as follows: Figure 2a , Figure 2c and Figure 2d shown. Figure 2a In the embodiment, each charging and discharging unit includes a charging unit and a discharging unit; Figure 2c In the embodiment, each charging and discharging unit includes a charging unit and a reset switch; Figure 2d In the embodiment, each charge and discharge unit includes a discharge unit and a setting switch.

[0023] Figure 3 This is an embodiment of the self-test device described in this application, in order to eliminate Figure 2a The error of the reference current in the self-test circuit shown and the inaccuracy caused by the circuit parasitic capacitance, a reference capacitor is introduced in this application .

[0024] in addition, Figure 2a After the discharge unit in the charge and discharge unit is replaced by a reset switch, only one measurement is required. The schematic diagram and the corresponding charge and discharge process timing diagram are shown in Figure 2c shown.

[0025] Figure 2a After the charging unit in the charging and discharging unit is replaced by a setting switch, only one measurement is required. The schematic diagram and the corresponding timing diagram of the charging and discharging process are shown in Figure 2d shown.

[0026] Embodiment 1:

[0027] Figure 3 The corresponding capacitance measurement is for a single-port transducer or sensor, and the measurement process includes: 1) Close the switch cal-en, the switch in-en is closed, the current source For reference capacitor Charge and discharge. Figure 2b The timing diagram shown in the figure measures the reference capacitance The required charge and discharge time is: (2) 2) Open the switch cal-en, close the switch in-en, current source Capacitor to be tested Charge and discharge, measure the capacitance to be tested The required charge and discharge time is: (3) Disconnect switch cal-en and switch in-en, current source Parasitic capacitance of the circuit Charge and discharge, measure circuit parasitic capacitance The required charge and discharge time is: (4) 4) By subtracting formulas (2), (3), and (4) from each other, we can obtain the error with the reference current and the circuit parasitic capacitance. The ratio is irrelevant to the size, and the capacitance to be measured is finally calculated by the ratio The size of this ratio is expressed as: (5) For a dual-port transducer or sensor, the present application proposes a differential BIST circuit, such as Figure 4 and Figure 5 shown.

[0028] Embodiment 2: Figure 5 middle, is the circuit parasitic capacitance, , is the parasitic capacitance of the transducer. In order to be able to measure , and , this application uses two-way BIST to measure three capacitors through switches S0, S1 and S2 respectively, including: 1) When S1 is closed, is shorted to ground, BIST measures + , get: (6) 2) When S2 is closed, is shorted to ground, BIST measures + , get: (7) 3) When S0 is closed, is shorted to ground, BIST measures + , get: (8) 4) By solving formulas (6), (7) and (8), we can measure , and .

[0029] Embodiment three: Figure 4 The corresponding differential BIST circuit has no Figure 5 The measurement process of switch S0 in the example includes: 1) Disconnect switches S1 and S2 and measure the capacitance of node (1) to obtain: (9) 2) Close switch S2, open switch S1, and measure the capacitance of node (1) to obtain: (10) 3) Disconnect switches S1 and S2 and measure the capacitance of node (2) to obtain: (11) 4) Close switch S1, open switch S2, and measure the capacitance of node (2) to obtain: (12) 5) According to formulas (9), (10), (11) and (12), we get: (13) according to And formula (10) to get ,according to And formula (12) to get .

[0030] Embodiment 4: like Figure 6 As shown, the self-test device further includes a self-test selection module and an amplification selection module.

[0031] The self-test selection module includes a capacitor Cin and a self-test selection switch BIST_EN connected in parallel. The amplification selection module includes a capacitor CF, a resistor RF and an amplification selection switch AMP_EN. When the self-test selection switch BIST_EN is closed and the amplification selection switch AMP_EN is disconnected, the self-measurement device is in a BIST self-test mode. When the self-test selection switch BIST_EN is disconnected and the amplification selection switch AMP_EN is closed, the self-measurement device is in an amplifier mode for amplifying a received signal of the ultrasonic transducer array.

[0032] Through the above-mentioned self-measurement device of the present application, it is possible to measure the electrical parameters of all mainstream transducers, greatly improving the development speed of the transducer array integration process.

[0033] The above are exemplary embodiments of the present application, and the protection scope of the present application is defined by the claims and their equivalents.

Claims

1. A self-testing device for an ultrasonic transducer array, characterized in that: include: A charge-discharge module for charging and discharging a reference capacitor, a capacitor module to be measured, and a circuit parasitic capacitor; A comparison / amplification module for obtaining the charge and discharge time of the reference capacitor, the capacitor module to be tested, and the circuit parasitic capacitor; The size of the capacitor module to be measured is obtained according to the charge and discharge time of the reference capacitor, the capacitor module to be measured and the circuit parasitic capacitance; The comparison / amplification module includes at least one comparator or at least one amplifier, each of which includes two input terminals and one output terminal, one input terminal is connected to the charge and discharge module, and the other input terminal is connected to the reference voltage.

2. The self-test device according to claim 1, characterized in that: The charging and discharging module includes at least one charging and discharging unit, each of which includes a charging unit and a discharging unit; or each charging and discharging unit includes a charging unit and a reset switch; Or each charge and discharge unit includes a discharge unit and a setting switch.

3. The self-test device according to claim 2, characterized in that: The capacitance module to be measured includes a capacitance to be measured, the comparison / amplification module includes a comparator / amplifier, and the charge-discharge module includes a charge-discharge unit; One end of the circuit parasitic capacitor is grounded; the other end is connected to the charge and discharge unit, and is connected to the reference capacitor through a reference switch; One end of the reference capacitor is grounded, and the other end is connected to the charge and discharge unit and the circuit parasitic capacitance through a reference switch; One end of the capacitor to be tested is grounded; the other end is connected to the charge and discharge unit through the switch to be tested, and is connected to the reference capacitor through the switch to be tested and the reference switch; When the charge-discharge unit includes a charge unit and a discharge unit, the charge unit and the discharge unit are both connected to a reference capacitor through a reference switch, connected to a capacitor to be tested through a switch to be tested, connected to a circuit parasitic capacitor, and connected to an input terminal of a comparator / amplifier; When the charge-discharge unit includes a charging unit and a reset switch, the charging unit and the reset switch are connected to the reference capacitor through the reference switch, connected to the capacitor to be tested through the switch to be tested, connected to the circuit parasitic capacitance, and connected to an input terminal of the comparator / amplifier; When the charge and discharge unit includes a discharge unit and a set switch, the discharge unit and the set switch are connected to the reference capacitor through the reference switch, connected to the capacitor to be tested through the test switch, connected to the circuit parasitic capacitance, and connected to an input terminal of the comparator / amplifier.

4. The self-test device according to claim 2, characterized in that: The charge and discharge module includes a first charge and discharge unit and a second charge and discharge unit, the comparison / amplification module includes a first comparator / amplifier and a second comparator / amplifier, the capacitance module to be tested includes a first capacitance to be tested, a second capacitance to be tested, a first switch and a second switch, and the switch to be tested includes a first switch to be tested and a second switch to be tested; One input end of the first comparator / amplifier and the second comparator / amplifier are both connected to a reference voltage, another input end of the first comparator / amplifier is connected to the output of the first charge and discharge unit, another input end of the second comparator / amplifier is connected to the output of the second charge and discharge unit, and the output ends of the first comparator / amplifier and the second comparator / amplifier are both connected to a logic gate module; When the first charge-discharge unit and the second charge-discharge unit both include a charging unit and a discharging unit, the charging unit and the discharging unit of the first charge-discharge unit are both connected to the reference capacitor through a reference switch, and connected to the first capacitor to be measured and the circuit parasitic capacitance through a first switch to be measured; the charging unit and the discharging unit of the second charge-discharge unit are connected to the second capacitor to be measured through a second switch to be measured; When the first charge-discharge unit and the second charge-discharge unit both include a charging unit and a reset switch, the charging unit and the reset switch of the first charge-discharge unit are connected to the reference capacitor through the reference switch, and connected to the first capacitor to be measured and the circuit parasitic capacitance through the first switch to be measured; the charging unit and the reset switch of the second charge-discharge unit are connected to the second capacitor to be measured through the second switch to be measured; When the first charge and discharge unit and the second charge and discharge unit both include a discharge unit and a set switch, the discharge unit and the set switch of the first charge and discharge unit are connected to the reference capacitor through the reference switch, and connected to the first capacitor to be measured and the circuit parasitic capacitance through the first switch to be measured; the discharge unit and the set switch of the second charge and discharge unit are connected to the second capacitor to be measured through the second switch to be measured.

5. The self-test device according to claim 4, characterized in that: One end of the first capacitor to be tested is grounded; the other end is grounded through a first switch, connected to the first charge and discharge unit through the first switch to be tested, and connected to the reference capacitor through the first switch to be tested and the reference switch; One end of the second capacitor to be tested is grounded; the other end is grounded through a second switch and connected to the second charge and discharge unit through the second switch to be tested; One end of the circuit parasitic capacitor is grounded through a first switch, connected to the first charge-discharge unit through a first switch to be tested, and connected to a reference capacitor through the first switch to be tested and a reference switch; the other end is grounded through a second switch, and connected to the second charge-discharge unit through a second switch to be tested; One end of the first switch is grounded, and the other end is connected to the first charge and discharge unit through the first switch to be tested, and is connected to the reference capacitor through the first switch to be tested and the reference switch; One end of the second switch is grounded, and the other end is connected to the second charge and discharge unit through the second switch to be tested.

6. The self-test device according to claim 5, characterized in that: The capacitor module to be tested also includes a third switch; one end of the third switch is connected to the first charge and discharge unit, connected to the first switch, the first capacitor to be tested and one end of the circuit parasitic capacitance through the first switch to be tested, and connected to the reference capacitor through the reference switch; the other end of the third switch is connected to the second charge and discharge unit, and connected to the second switch, the second capacitor to be tested and the other end of the circuit parasitic capacitance through the second switch to be tested.

7. The self-test device according to any one of claims 4 to 6, characterized in that: The first switch, the second switch, the first switch to be tested, and the second switch to be tested are all MOS switches.

8. The self-test device according to any one of claims 2 to 6, characterized in that: The self-test device further comprises a self-test selection module and an amplification selection module; the self-test selection module comprises a first capacitor and a self-test selection switch connected in parallel; the amplification selection module comprises a second capacitor, a resistor and an amplification selection switch, the second capacitor and the resistor are connected in parallel, one end of the second capacitor and one end of the resistor are both connected to the amplification selection switch, and the other ends are both connected to the output end of the comparison / amplification module, and the amplification selection switch, the first capacitor, the self-test selection switch and an input end of the comparison / amplification module are all connected; The first capacitor and the self-test selection switch are both connected to the charge and discharge unit, and are both connected to the reference capacitor through the reference switch.

9. The self-test device according to claim 8, characterized in that: When the comparison / amplification module includes a first comparator / amplifier and a second comparator / amplifier: the amplification selection switch, the first capacitor, the self-test selection switch, and one input end of the first comparator / amplifier and the second comparator / amplifier are all connected; the other end of the second capacitor and the other end of the resistor are all connected to the output ends of the first comparator / amplifier and the second comparator / amplifier.

10. The self-test device according to claim 1, characterized in that: The ultrasonic transducer array includes a linear array ultrasonic transducer and a planar array ultrasonic transducer.

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