Optical module and optical module connector

Abstract

The invention provides an optical module and an optical module connector, and belongs to the technical field of optical communication. The optical module comprises a golden finger and a circuit board, the golden finger is electrically connected with the circuit board, the golden finger comprises a first pin, a basic pin group and a second pin, the first pin is located between a first side edge of the top surface of the circuit board and the first basic pin, the first basic pin is located on the top surface of the basic pin group and is adjacent to the first side edge, and the second pin is located between the first side edge and the second basic pin. The second pin is located between a second side edge of the bottom surface of the circuit board and the second basic pin, and the second basic pin is a pin which is located on the bottom surface and is adjacent to the second side edge in the basic pin group. According to the optical module provided by the invention, the first pin and the second pin are added on the basis of the basic pin group, so that the optical module can be compatible with passive optical networks in various modes.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technology, and in particular to an optical module and an optical module connector. Background Art

[0002] With the development of optical communication technology, in passive optical networks (PON), gigabit-capable PON (GPON) and 10Gigabit-capable PON (XGPON) can no longer meet the needs of future broadband business development, and passive optical networks are evolving towards higher bandwidths. For example, passive optical networks are evolving towards 50Gigabit-capable PON (50G PON).

[0003] When passive optical networks evolve towards higher bandwidths, it is inevitable that network devices with multiple bandwidths will coexist in the optical network, requiring optical modules to be compatible with network devices with multiple bandwidths. Summary of the invention

[0004] The present disclosure provides an optical module and an optical module connector, with newly added pins, so that the optical module can support network devices with multiple bandwidths.

[0005] In a first aspect, the present disclosure provides an optical module, which includes a gold finger and a circuit board. The gold finger is electrically connected to the circuit board. The gold finger includes a first pin, a basic pin group and a second pin. The first pin is located between a first side edge of a top surface of the circuit board and a first basic pin. The first basic pin is a pin in the basic pin group that is located on the top surface and adjacent to the first side edge. The second pin is located between a second side edge of a bottom surface of the circuit board and a second basic pin. The second basic pin is a pin in the basic pin group that is located on the bottom surface and adjacent to the second side edge.

[0006] In the solution shown in the present disclosure, based on the basic pin group, two new pins are added to the vacant positions on the top and bottom surfaces of the circuit board, and the number of pins is increased, so that the optical module can support network devices with multiple bandwidths.

[0007] In an example, the basic pin group includes 38 pins, and the number of pins located on the top surface and the number of pins located on the bottom surface of the 38 pins are the same.

[0008] In one example, the optical module is used to support data transmission of at least one of a Gigabit passive optical network, a 10 Gigabit passive optical network, and a 50 Gigabit passive optical network.

[0009] In one example, the control or indication pins in the gold finger include the 8th pin, the 11th pin, the 12th pin and the 20th pin from the left of the top surface along the insertion direction, and the 1st pin, the 2nd pin, the 8th pin, the 9th pin, the 12th pin to the 14th pin and the 20th pin from the left of the bottom surface. The power pins in the gold finger include the 9th pin and the 10th pin from the left of the top surface along the insertion direction, and the 10th pin from the left of the bottom surface, or the power pins in the gold finger include the 9th pin and the 10th pin from the left of the top surface along the insertion direction, and the 10th pin and the 11th pin from the left of the bottom surface. The pins in the gold finger include the first pin, the fourth pin, the seventh pin, the thirteenth pin, the sixteenth pin and the nineteenth pin from the left of the top surface along the insertion direction and the fifth pin and the seventeenth pin from the left of the bottom surface.

[0010] In an example, the first pin and the second pin are control or indication pins of the Gigabit Passive Optical Network. In this way, the newly added pins are used for the Gigabit Passive Optical Network.

[0011] In one example, the first pin is a signal check pin of the gigabit passive optical network, and the second pin is a reset pin of the gigabit passive optical network, or the first pin is a reset pin of the gigabit passive optical network, and the second pin is a signal check pin of the gigabit passive optical network.

[0012] In one example, when the basic pin group includes three power pins, the basic pin group includes a rate selection pin for a 50 Gigabit passive optical network. In this way, when the number of power pins is relatively small, the rate selection function of the 50 Gigabit passive optical network can occupy a single pin.

[0013] In one example, when the basic pin group includes 4 power pins, in the uplink time division scenario, the first pin is the rate selection pin of the 50 Gigabit passive optical network, the second pin is the signal check pin of the Gigabit passive optical network, and the reset signal of the Gigabit passive optical network and the reset signal of the 50 Gigabit passive optical network reuse the same pin among the 38 pins. In this way, when the number of power pins is relatively large, the reset signal of the Gigabit passive optical network and the reset signal of the 50 Gigabit passive optical network reuse one pin.

[0014] In one example, since the pins on the top surface are suitable for high-speed pins, the signal transmitting pins and the signal receiving pins of the 50 Gigabit passive optical network are located on the top surface of the circuit board.

[0015] In an example, the width of the first pin and the second pin is greater than or equal to 0.4 mm and less than or equal to 0.6 mm. In this way, the width of the pin is relatively large and the implementation difficulty is low.

[0016] In one example, the width of the first end of the circuit board is 16.4±0.1 mm, and the thickness is 1 mm, and the first end is the end where the gold finger is located. In this way, the width of the first end of the circuit board is the same as the width of the circuit board with 38 pins, and can also adapt to the original optical module connector.

[0017] In one example, the first side and the second side are located on both sides of the circuit board, the interval between the first side and the first basic pin is greater than the interval between the third side and the third basic pin, the third basic pin is a pin in the basic pin group that is located on the top surface and adjacent to the third side, and the third side and the second side are located on the same side of the circuit board.

[0018] In one example, the interval between the first pin and the first base pin is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm, and the interval between the second pin and the second base pin is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm.

[0019] In one example, the optical module is used to support data transmission in a passive optical network at least at a transmission rate higher than 10 Gbps.

[0020] In a second aspect, the present disclosure provides an optical module connector, which includes a pin slot for plugging in an optical module, the inner wall of the pin slot is provided with a first extension pin, a first basic pin group and a second extension pin, the first extension pin is located between the first side of the top of the inner wall and the first edge pin, the first edge pin is a pin in the first basic pin group that is located at the top and adjacent to the first side, the second extension pin is located between the second side of the bottom of the inner wall and the second edge pin, the second edge pin is a pin in the first basic pin group that is located at the bottom and adjacent to the second side.

[0021] In the solution shown in the present disclosure, when two pins are added to the optical module, two pins are also added to the pin slot for inserting the optical module, so as to adapt to the optical module.

[0022] In an example, the first basic pin group includes 38 pins, and the number of pins located at the top and the number of pins located at the bottom of the 38 pins are the same.

[0023] In one example, the first extension pin, the first basic pin group, and the second extension pin are used to support data transmission of at least one of a Gigabit passive optical network, a 10 Gigabit passive optical network, and a 50 Gigabit passive optical network.

[0024] In one example, the control or indication pins in the pin slot include the 8th pin, the 11th pin, the 12th pin and the 20th pin from the top left and the 1st pin, the 2nd pin, the 8th pin, the 9th pin, the 12th pin to the 14th pin and the 20th pin from the bottom left along the insertion direction. The power pins in the pin slot include the 9th and 10th pins from the left at the top and the 10th pin from the left at the bottom along the insertion direction, or the power pins in the pin slot include the 9th and 10th pins from the left at the top and the 10th and 11th pins from the left at the bottom along the insertion direction, and the ground pins in the pin slot include the 1st, 4th, 7th, 13th, 16th and 19th pins from the left at the top and the 5th and 17th pins from the left at the bottom along the insertion direction.

[0025] In an example, the first extension pin and the second extension pin are control or indication pins of the Gigabit passive optical network.

[0026] In one example, the first extension pin is a signal check pin of the gigabit passive optical network, and the second extension pin is a reset pin of the gigabit passive optical network, or the first extension pin is a reset pin of the gigabit passive optical network, and the second extension pin is a signal check pin of the gigabit passive optical network.

[0027] In an example, when the first basic pin group includes three power pins, the first basic pin group includes a rate selection pin of a 50 Gigabit passive optical network.

[0028] In one example, when the first basic pin group includes 4 power pins, in an uplink time division scenario, the first extended pin is a rate selection pin of a 50 Gigabit passive optical network, the second extended pin is a signal check pin of the Gigabit passive optical network, and the reset signal of the Gigabit passive optical network and the reset signal of the 50 Gigabit passive optical network multiplex the same pin among the 38 pins.

[0029] In one example, the signal transmission pin and the signal reception pin of the 50 Gigabit passive optical network are located at the top.

[0030] In one example, the inner wall width of the pin slot is 16.6±0.1 mm, and the minimum height of the inner wall is 1.14 mm.

[0031] In one example, the first side and the second side are located on both sides of the pin slot, the interval between the first side and the first edge pin is greater than the interval between the third side and the third edge pin, the third edge pin is a pin in the first basic pin group located at the top and adjacent to the third side, and the third side and the second side are located on the same side of the pin slot.

[0032] In one example, the spacing between the first extension pin and the first edge pin is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm, and the spacing between the second extension pin and the second edge pin is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of a PON provided by an exemplary embodiment of the present disclosure;

[0034] Figure 2 is a schematic diagram of three modes of PON provided by an exemplary embodiment of the present disclosure;

[0035] Figure 3 This is a schematic diagram of the traditional arrangement of gold fingers on a printed circuit board;

[0036] Figure 4 is a schematic diagram of the structure of an optical module provided by an exemplary embodiment of the present disclosure;

[0037] Figure 5 It is a structural schematic diagram of a gold finger located on a circuit board provided by an exemplary embodiment of the present disclosure;

[0038] Figure 6 It is a structural schematic diagram of a gold finger located on a circuit board provided by an exemplary embodiment of the present disclosure;

[0039] Figure 7 is a schematic structural diagram of a transition pin provided by an exemplary embodiment of the present disclosure;

[0040] Figure 8 It is a structural schematic diagram of a gold finger located on a circuit board provided by an exemplary embodiment of the present disclosure;

[0041] Fig. 9 It is a structural schematic diagram of a gold finger located on a circuit board provided by an exemplary embodiment of the present disclosure;

[0042] Fig.10 It is a structural schematic diagram of a gold finger located on a circuit board provided by an exemplary embodiment of the present disclosure;

[0043] Fig.11 is a structural schematic diagram of an optical module connector provided by an exemplary embodiment of the present disclosure;

[0044] Fig.12 is a structural schematic diagram of an optical module connector provided by an exemplary embodiment of the present disclosure;

[0045] Fig.13 is a structural schematic diagram of an optical module connector provided by an exemplary embodiment of the present disclosure;

[0046] Fig.14 It is a schematic diagram of the structure of an optical module connector provided by an exemplary embodiment of the present disclosure.

[0047] Illustration

[0048] 1. Gold finger; 2. Circuit board; 03. Optical device; 4. Optical digital signal processing (ODSP) device; 5. Electric chip; 11. First pin; 12. Basic pin group; 13. Second pin; 031. Sub-optical device; 032. Wavelength division multiplexing (WDM) device; 51. Sub-chip; 121. First basic pin; 122. Second basic pin; 123. Third basic pin; 124. Fourth basic pin;

[0049] 3. Pin slot; 31. First extension pin; 32. First basic pin group; 33. Second extension pin; 321. First edge pin; 322. Second edge pin; 323. Third edge pin. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0051] In the field of optical access PON, the optical line terminal (OLT) is connected to multiple optical network units (ONUs) through a passive optical splitter. The OLT is connected to the Public Switched Telephone Network (PSTN), the Internet, and community antenna television (CATV) to provide data transmission services. Figure 1 Schematic diagram of PON shown.

[0052] With the development of optical communication technology, the optical modules plugged into OLT have undergone a series of evolutions, from the early small form-factor pluggable optical modules (SFP) to the miniaturized and accelerated SFP+. The future evolution of 50GPON optical modules has always been a topic of discussion in the industry. In the 10G PON era, SFP+ became the mainstream of optical modules, and SFP+ can support the combination of XGS-PON and GPON (combo). In the future, as the amount of data transmission increases, optical modules will inevitably evolve towards large bandwidth and high speed. The current is an important evolutionary moment for the development of 50G PON. Considering factors such as performance improvement and dispersion cost optimization, 50G PON needs to integrate ODSP in the optical module. However, SFP is small in size and has a small layout space, making it difficult to support the application of 50G PON.

[0053] In order to be compatible with the network devices in the existing PON, the OLT needs to be compatible with three types of PON (GPON, 10G PON and 50G PON), so the optical module also needs to adapt to three types of ONU, namely GPON ONU, 10G PON ONU and 50G PON ONU, see Figure 2 The OLT shown in the figure is connected to ONUs in three modes. Among them, 10G PON is divided into symmetric 10G PON and asymmetric 10G PON. Symmetric 10G PON means that the transmission rate of upstream transmission and downstream transmission is 10Gbps, and asymmetric 10G PON means that the transmission rate of upstream transmission is 2.5Gbps and the transmission rate of downstream transmission is 10Gbps.

[0054] exist Figure 1 and Figure 2 In the network architecture shown, there are two ways to transmit data between OLT and ONU, one is wavelength division and the other is time division. In the downstream transmission of wavelength division, the wavelength used by 50G PON is 1342nm, the wavelength used by 10GPON is 1577nm, and the wavelength used by GPON is 1490nm. In the upstream transmission of wavelength division, the wavelength used by 50G PON is 1286nm, the wavelength used by 10G PON is 1270nm, and the wavelength used by GPON is 1310nm.

[0055] In the time-division downlink transmission, the wavelength used by 50G PON is 1342nm, the wavelength used by 10G PON is 1577nm, and the wavelength used by GPON is 1490nm. In the time-division uplink transmission, the wavelength used by 50G PON is 1300nm, the wavelength used by 10G PON is 1270nm, and the wavelength used by GPON is 1310nm.

[0056] In order to obtain an optical module compatible with the three types of PON, the gold finger in the optical module must first support 50G PON, XG PON and GPON. The gold finger is composed of multiple golden conductive contacts, which are called gold fingers because of their gold-plated surface and the arrangement of the conductive contacts like fingers. The conductive contacts are relatively thin metal sheets, called pins or pins.

[0057] At present, 28G quad small form-factor pluggable optical modules (QSFP28) are mostly used in data communication scenarios. From the appearance point of view, the width of the optical module is 18.35mm, and the width of the internal printed circuit board (PCB) is greater than 14mm, which makes the layout space of the optical module sufficient to realize most ODSP applications, especially large-size, low-cost and low-process ODSP. In addition, from the perspective of external interfaces, the number of gold finger pins is 38, which is relatively small, making the optical module incompatible with 50G PON, XG PON and GPON.

[0058] In addition, the package size of the next generation small form factor pluggables (NGSFP) has not changed much compared to DSFP. The gold finger adds two rows of pins along the insertion direction of the optical communication device. The two rows of pins are located on the top and bottom of the PCB, respectively, referred to as the top of the board and the bottom of the board. The number of gold finger pins has increased from 22 to 44, which can support the coexistence of 50GPON, XG PON and GPON modes. Figure 3 A schematic diagram of the arrangement of gold fingers on a printed circuit board is provided. In this way, since the package size has not changed significantly, the space reserved for the layout of optical devices and ODSP devices in the optical module is small, and the implementation is difficult. The optical devices include photoelectric conversion devices and electro-optical conversion devices.

[0059] Among them, the printed circuit board is referred to as the circuit board for short, the top surface of the circuit board refers to the surface of the circuit board seen from top to bottom when the optical module is inserted into the optical communication equipment, and the bottom surface of the circuit board refers to the surface of the circuit board seen from bottom to top when the optical module is inserted into the optical communication equipment.

[0060] The optical module in the embodiment of the present disclosure may be any one of an optical receiving module, an optical transmitting module and an integrated optical transceiver module. The following description will be made by taking the optical module as an integrated optical transceiver module as an example.

[0061] In the embodiment of the present disclosure, on the basis of the existing optical module, pins in the gold finger are added so that the optical module can realize the required functions. The structure of the optical module, the definition of the pins and the optical module connector are described in turn below.

[0062] 1. Structure of optical module

[0063] Figure 4 Provides a schematic diagram of the optical module structure. Figure 4 The optical module includes a gold finger 1, a circuit board 2, an optical device 03, an ODSP device 4 and an electrical chip 5.

[0064] Among them, the gold finger 1 is electrically connected to the circuit board 2, and electrical signals can be transmitted between the two. The gold finger 1 is located on the surface of the circuit board 2 and is close to the first end of the circuit board 2. The first end is the end of the optical module inserted into the optical communication device. The length direction of the gold finger 1 is the same as the insertion direction of the optical module into the optical communication device. After the optical module is inserted into the optical communication device, the pins in the gold finger 1 are electrically connected to the optical communication device.

[0065] The optical device 03 is used to convert optical signals into electrical signals, and to convert electrical signals into optical signals. One end of the optical device 03 is electrically connected to the electrical chip 5, and the other end is connected to the transmission optical fiber connected to the optical module.

[0066] One end of the ODSP device 4 is electrically connected to the circuit board 2, and the other end is electrically connected to the electrical chip 5. The ODSP device 4 is used to process the complex digital signal of the 50G PON, so that the signal quality is relatively good.

[0067] The electric chip 5 is electrically connected to the circuit board 2. For example, the electric chip 5 is integrated on the circuit board 2, and the electric chip 5 is electrically connected to the gold finger 1 through the circuit board 2. The electric chip 5 is used to process the electric signal, such as amplifying it.

[0068] During the signal transmission process, the optical module receives the electrical signal sent by the optical communication device through the gold finger 1, the electrical chip 5 processes the electrical signal and transmits it to the optical device 03, and the optical device 03 converts the electrical signal into an optical signal and transmits it through the connected transmission optical fiber.

[0069] During the signal receiving process, the optical module receives the optical signal through the connected transmission optical fiber, the optical device 03 converts the optical signal into an electrical signal, the electrical chip 5 processes the electrical signal and transmits it to the gold finger 1, and the gold finger 1 transmits the electrical signal to the optical communication device.

[0070] 1. Gold Finger 1

[0071] Figure 5 A schematic diagram of the structure of the gold finger 1 located on the circuit board 2 is provided. Figure 5The gold finger 1 includes a first pin 11, a basic pin group 12, and a second pin 13. The basic pin group 12 includes a first basic pin 121 and a second basic pin 122. The first basic pin 121 is a pin in the basic pin group 12 adjacent to a first side edge of the top surface of the circuit board 2, and the second basic pin 122 is a pin in the basic pin group 12 adjacent to a second side edge of the bottom surface of the circuit board 2. Here, the first side edge and the second side edge are both board edges of the circuit board 2, and are different sides.

[0072] The first pin 11 is located between the first side of the top surface of the circuit board 2 and the first basic pin 121 , the second pin 13 is located between the bottom surface of the circuit board 2 and the second basic pin 122 , and the first pin 11 , the basic pin group 12 and the second pin 13 are parallel to each other.

[0073] In one example, the basic pin group 12 includes 38 pins, and the number of pins located on the top and bottom surfaces of the circuit board 2 is the same, that is, 19 pins are located on the top surface of the circuit board 2, and the other 19 pins are located on the bottom surface of the circuit board 2. The optical module in the implementation of the present disclosure is equivalent to adding a first pin 11 and a second pin 13 in the idle area on the basis of the QSFP series, and the QSFP series includes QSFP+, QSFP28, QSFP56 and QSFP112, etc.

[0074] In one example, when the basic pin group 12 includes 38 pins, in order to enable the optical module to be inserted into an existing optical communication device, the width of the first end of the circuit board 2 is 16.4±0.1 mm, the thickness is 1 mm, and the first end is the end where the gold finger 1 is located. The width of the first end describes the width of the circuit board 2 at the location of the gold finger 1.

[0075] In one example, the positions of the pins on the top and bottom surfaces of the circuit board 2 in the gold finger 1 are asymmetrical, so that the intervals between the two edge pins on the top surface in the basic pin group 12 and the adjacent side edges are different, and the intervals between the two edge pins on the bottom surface in the basic pin group 12 and the adjacent side edges are different. Therefore, in order to make the design difficulty of the first pin 11 and the second pin 13 relatively low, the first side edge and the second side edge are located on different sides of the circuit board 2, and the first pin 11 is located on the side with a larger free area, and the second pin 13 is located on the side with a larger free area.

[0076] For example, see Figure 6In the case where the basic pin group 12 includes 38 pins, the width of the first end of the circuit board 2 is 16.4±0.1 mm, the two edge pins located on the top surface of the basic pin group 12 include the first basic pin 121 and the third basic pin 123, and the two edge pins located on the bottom surface of the basic pin group 12 include the second basic pin 122 and the fourth basic pin 124. The interval between the first basic pin 121 and the third basic pin 123 is 14.40 mm, and the interval between the second basic pin 122 and the fourth basic pin 124 is 14.40 mm. The interval between two pins is the distance between the central axes of the two pins. The distance between the central axis of the circuit board 2 and the first basic pin 121 is equal to 7.00 mm, the distance between the central axis of the circuit board 2 and the third basic pin 123 is equal to 7.40 mm, the distance between the central axis of the circuit board 2 and the second basic pin 122 is equal to 7.00 mm, and the distance between the central axis of the circuit board 2 and the fourth basic pin 124 is equal to 7.40 mm. The width of the pins in the basic pin group 12 is 0.6 mm, and the distance between the pins is 0.8 mm. The distance between the first basic pin 121 and the first side is equal to 1.2 mm, the distance between the second basic pin 122 and the second side is equal to 1.2 mm, the distance between the third basic pin 123 and the third side is equal to 0.8 mm, and the distance between the fourth basic pin 124 and the fourth side is equal to 0.8 mm. The first side and the second side are located on both sides of the circuit board 2, the first side and the third side are located on both sides of the circuit board 2, the second side and the third side are located on the same side of the circuit board 2, and the first side and the fourth side are located on the same side of the circuit board 2. It should be noted here that the interval between the pin and the side refers to the distance from the center axis of the pin to the side.

[0077] The first pin 11 and the second pin 13 are close to the side of the circuit board 2, so that the gold finger 1 is closer to the side of the circuit board 2. Compared with the spacing of the pins in the basic pin group 12, the spacing between the first pin 11 and the first basic pin 121 is allowed to be changed to a certain extent, and the spacing between the second pin 13 and the second basic pin 122 is allowed to be changed to a certain extent, but the change deviation will not be relatively large, such as usually not greater than 0.2mm. For example, the first spacing between the first pin 11 and the first basic pin 121 is 0.8mm. Alternatively, the first spacing is greater than or equal to 0.6mm and less than or equal to 1mm. The second spacing between the second pin 13 and the second basic pin 122 is 0.8mm. Alternatively, the second spacing is greater than or equal to 0.6mm and less than or equal to 1mm.

[0078] Optionally, the first interval and the second interval are the same, or different. If they are the same, it can be easier to design.

[0079] In another example, the first pin 11 and the second pin 13 are set on different sides in consideration of the process difficulty in the foregoing text. With the optimization of the process, the first pin 11 and the second pin 13 can also be set on the same side, so that the first side and the second side are also located on the same side of the circuit board 2.

[0080] In one example, the first pin 11 and the second pin 13 are close to the side of the circuit board 2, so that the gold finger 1 is close to the side of the circuit board 2, and the width is allowed to be changed in design, but the width should not be too small. The width of the first pin 11 is greater than or equal to 0.4 mm and less than or equal to 0.6 mm, and the width of the second pin 13 is greater than or equal to 0.4 mm and less than or equal to 0.6 mm.

[0081] Optionally, the width of the first pin 11 and the width of the second pin 13 may be the same or different.

[0082] Optionally, the first pin 11 has the same width as the pins in the basic pin group 12, and the second pin 13 has the same width as the pins in the basic pin group 12. For example, the width of the pins in the basic pin group 12 is 0.6 mm, and the widths of the first pin 11 and the second pin 13 are both 0.6 mm. In this way, when manufacturing an optical module, there is no need to set pins of various widths, and the design complexity is low.

[0083] It should be noted that when the width of the pin is set to 0.6 mm, a certain error is usually allowed so that the width of the pin is 0.60±0.03 mm.

[0084] In one example, the lengths of the first pin 11, the pins in the basic pin group 12, and the second pin 13 are set according to their uses, that is, they are set according to their definitions. For example, the length of the pin used for power supply is greater than the length of the pin used for signal transmission. For another example, the length of the pin used for signal transmission is equal to the length of the pin used for signal reception.

[0085] In one example, a transition pin is provided at the top of the first pin 11 to prevent wear when the optical module is inserted into the optical module connector. The top is the end of the first pin 11 that first contacts the optical module connector when the optical module is inserted into the optical module connector. The transition pin can also be called a transition pin. Figure 7 There is a 45-degree chamfer at the top of the transition pin, with a horizontal distance of 0.3mm and a width of 0.36mm at the top.

[0086] In another example, a transition pin is provided at the top of the second pin 13 to prevent wear when the optical module is inserted into the optical module connector. The top is the end where the second pin 13 first contacts the optical module connector when the optical module is inserted into the optical module connector.

[0087] 2. Optical Devices 03

[0088] In the case where the optical module supports multiple modes of PON, the optical device 03 includes three sub-optical devices 031 and a wavelength division multiplexing device 32. Each mode of PON corresponds to a sub-optical device 031, which is used to support the photoelectric conversion of the PON of this mode. The WDM device 32 is used to combine the optical signals of the three modes of PON into one optical signal, output from the transmission optical fiber connected to the optical module, and in the wavelength division scenario, divide the one optical signal received upstream into the optical signals of the three modes of PON and transmit them to the corresponding sub-optical device 031, and in the time division scenario, divide the one optical signal received upstream into the optical signals of the two modes of PON and transmit them to the corresponding sub-optical device 031, see Figure 4 The structural diagram of the optical module is shown.

[0089] 3. Electric chip 5

[0090] In the case where the optical module supports multiple modes of PON, the electrical chip 5 includes multiple sub-chips 51, which correspond to the multiple modes of PON one by one, that is, the multiple sub-chips 51 include three sub-chips 51, and the three sub-chips 51 correspond to 50G PON, 10GPON and GPON respectively, see Figure 4 The structural diagram of the optical module is shown.

[0091] Figure 4 The optical module shown can at least support data transmission of a passive optical network with a transmission rate of 10Gbps. For example, it supports data transmission of a 50G passive optical network. For another example, it supports data transmission of a 50G passive optical network and data transmission of a 10G passive optical network. Here, 10Gpbs is not strictly 10Gbps, but people use 9.98Gbps as 10Gpbs.

[0092] 2. Definition of pins in Gold Finger 1

[0093] If the optical module is compatible with three modes of PON, namely GPON, 10G PON and 50G PON, the pins of Gold Finger 1 include at least 41 functional pins. In terms of categories, the 41 functional pins include control or indication pins, serial deserialization signal pins, power pins and ground pins. The control or indication pins include common control or indication pins and control or indication pins of three modes of PON. The serial deserialization signal pins include signal transceiver pins of three modes of PON. For details, see Table 1. Among them, the control or indication pins are used for control or indication signals.

[0094] Table 1

[0095]

[0096] Among them, in Table 1, regarding the control or indication pins, TX_dis indicates whether the pin of the transmitter is turned off, RSSITrigger indicates the pin of the received signal strength detection request, and ModprsL indicates whether the optical module is in place. G_Rx_SD is the signal check pin of GPON, and G_reset is the reset pin of GPON. 10G_Rx_SD is the signal check pin of 10G PON, 10G_reset is the reset pin of 10G PON, and 10G_rate_sel is the rate selection pin of 10G PON, which is used to select whether the upstream transmission rate is 2.5Gbps or 10Gbps. 50G_Rx_SD is the signal check pin of 50G PON, 50G_reset is the reset pin of 50G PON, and 50G_rate_sel is the rate selection pin of 50G PON, which is used to select whether the upstream transmission rate is 50Gbps or 25Gbps.

[0097] Regarding the serial deserialization signal pins, GPON Txp and GPON Txn are the positive signal transmission pin and negative signal transmission pin of GPON, respectively, and GPON Rxp and GPON Rxn are the positive signal receiving pin and negative signal receiving pin of GPON, respectively. 10GPON Txp and 10G PON Txn are the positive signal transmission pin and negative signal transmission pin of 10G PON, respectively, and 10G PON Rxp and 10G PON Rxn are the positive signal receiving pin and negative signal receiving pin of 10G PON, respectively, which can be used to receive signals with a transmission rate of 10Gbps, and can also be used to receive signals with a transmission rate of 2.5Gbps. 50G PON Tx1p and 50G PONTx1n are a pair of signal transmission pins of 50G PON, which are positive signal transmission pins and negative signal transmission pins respectively. 50G PONTx2p and 50G PON Tx2n are another pair of signal transmission pins of 50G PON, which are positive signal transmission pins and negative signal transmission pins respectively. The pair of signal transmission pins are used to transmit signals with a transmission rate of 25Gbps, and the other pair of signal transmission pins are used to transmit signals with a transmission rate of 25Gbps, which is equivalent to the optical module transmitting a signal with a transmission rate of 50Gbps. Alternatively, the pair of signal transmission pins are used to transmit signals with a transmission rate of 50Gbps, and the other pair of signal transmission pins are used as redundant backup. 50G PON Rx1p and 50G PON Rx1n are a pair of signal receiving pins of 50G PON, which are respectively a positive signal receiving pin and a negative signal receiving pin. 50G PON Rx2p and 50G PON Rx2n are another pair of signal receiving pins of 50G PON, which are respectively a positive signal receiving pin and a negative signal receiving pin.

[0098] Wherein, in the case of receiving a signal with a transmission rate of 50 Gbps, the pair of signal receiving pins is used to receive a signal with a transmission rate of 25 Gbps, and the other pair of signal receiving pins is used to receive a signal with a transmission rate of 25 Gbps. Alternatively, the pair of signal receiving pins is used to receive a signal with a transmission rate of 50 Gbps, and the other pair of signal receiving pins is used as a redundant backup.

[0099] In the case of receiving a signal with a transmission rate of 25 Gbps, the pair of signal receiving pins is used to receive a signal with a transmission rate of 12.5 Gbps, and the other pair of signal receiving pins is used to receive a signal with a transmission rate of 12.5 Gbps. Alternatively, the pair of signal receiving pins is used to receive a signal with a transmission rate of 25 Gbps, and the other pair of signal receiving pins is used as a redundant backup.

[0100] Regarding the power pins, VCC Tx and VCC Rx are the transmitting power and receiving power respectively.

[0101] In the embodiment of the present disclosure, when the basic pin group 12 includes 38 pins, if the first pin 11 and the second pin 13 are both 1, the gold finger 1 includes 40 pins, and the optical module in the embodiment of the present disclosure is equivalent to adding two pins in the idle area on the basis of the QSFP series. It can be seen from Table 1 that if the gold finger 1 is compatible with three modes of PON, GPON, 10G PON and 50G PON, then at least 41 functional pins are required, which requires the existence of pins with multiplexed functions.

[0102] When defining the pins of the gold finger 1, the correspondence between the 40 pins in the gold finger 1 and the standard 38 pins is provided, see Table 2. In Table 2, the 38 pins in the QSFP are used as an example for explanation.

[0103] For the convenience of description, along the insertion direction, the 20 pins of the gold finger 1 located on the bottom surface of the circuit board 2 are numbered from 1 to 20 from left to right, and the 20 pins of the gold finger 1 located on the top surface of the circuit board 2 are numbered from 21 to 40 from right to left, the first pin 11 is numbered 21, and the second pin 13 is numbered 1. The insertion direction is the direction in which the optical module is inserted into the optical module connector. And along the insertion direction, the 19 pins of the QSFP located on the bottom surface of the circuit board 2 are numbered from 1 to 19 from left to right, and the 19 pins of the QSFP located on the top surface of the circuit board 2 are numbered from 20 to 38 from right to left.

[0104] Table 2

[0105]

[0106]

[0107] In Table 2, the 10th pin in Gold Finger 1 is used as a control or indication pin, or as a power pin, so that the 40 pins in Gold Finger 1 can provide 41 functions. Tx1~Tx4 and Rx1~Rx4 are used to transmit serial deserialization signals, and the specific positions can be adjusted according to the actual design.

[0108] In one example, the first pin and the 21st pin are two newly added pins, which are used for the control or indication signal of GPON, and can be flexibly compatible with 38-pin 10G PON and 50G PON optical modules of two modes, as well as 38-pin 50G PON optical modules. For example, the first pin 11 is a signal check pin of GPON, and the second pin 13 is a reset pin of GPON. For another example, the first pin 11 is a reset pin of GPON, and the second pin 13 is a signal check pin of GPON.

[0109] In one example, the pins located on the top surface of the circuit board 2 are more suitable for high-speed signal transmission and can ensure signal integrity as much as possible. Therefore, the signal transmission pins and signal receiving pins of the 50G PON are located on the top surface of the circuit board 2. For example, the pins numbered 23, 24, 26, 27, 35, 36, 38 and 39 are used as the signal transmission pins and signal receiving pins of the 50G passive optical network. Here, in the 50G PON, it is not limited to whether the transmission rate of a pair of signal transmission pins is 50Gbps or the transmission rates of two pairs of signal transmission pins are 25Gbps respectively, nor is it limited to whether the transmission rate of a pair of signal receiving pins is 50Gbps or the transmission rates of two pairs of signal receiving pins are 25Gbps respectively, which can be set as needed.

[0110] In one example, the power supply reserves 4 pins, and the pins numbered 10, 11, 31, and 32 are power pins, and each pin is designed to have a current capacity of 1 A. Among them, the pin numbered 10 can also be set as a control or indication signal pin. The number of power pins can be adjusted according to the power consumption of the optical module.

[0111] For example, the wavelength used for 50G PON upstream transmission is 1300nm, and the wavelength used for GPON upstream transmission is 1310nm. In upstream transmission, the wavelengths of 50G PON and GPON are close, which is equivalent to sharing a band. The wavelength isolation is low and they will interfere with each other. Therefore, 50G PON and GPON are set to time division multiplexing, that is, 50G PON and GPON will not transmit upstream at the same time. The reset signals of 50GPON and GPON will not be transmitted at the same time. Therefore, the reset signals of 50G PON and GPON can share a pin. The first pin 11 is the rate selection pin of 50G PON, and the second pin 13 is the signal check pin of GPON. The reset signal of GPON and the reset signal of 50G PON reuse the same pin in the basic pin group 12. The same pin is the pin numbered 33, see Figure 8 The schematic diagram of the golden finger 1 shown in the figure, Figure 8 The definition of each pin in the gold finger 1 shown is shown in Table 3.

[0112] Table 3

[0113]

[0114] In the low-power optical module, the power supply reserves 3 pins, and a pin in the basic pin group 12 is used as a 50G PON rate selection pin. For example, the pin numbered 10 can be used as a 50G PON rate selection pin. In this case, the first pin 11 is the GPON reset pin, and the second pin 13 is the GPON signal check pin, see Fig. 9 The schematic diagram of the gold finger 1 shown, or, the first pin 11 is a signal check pin of GPON, and the second pin 13 is a reset pin of GPON. Fig. 9 The definition of each pin in the gold finger 1 shown is shown in Table 4.

[0115] Table 4

[0116]

[0117]

[0118] In Tables 3 and 4, the positions of the signal transmitting pins can be interchanged according to actual needs, and the positions of the signal receiving pins can also be interchanged according to actual needs. For example, the positions of the signal transmitting pins of 10G PON and the signal transmitting pins of GPON are interchanged, and the positions of the signal receiving pins of 10G PON and the signal receiving pins of GPON are interchanged. In addition, the positions of the control or indication pins can also be interchanged according to actual needs. For example, the positions of the pin indicating whether the pin is in place and the pin of the reset signal of 10G PON are interchanged, and the positions of the ModPrsL pin and the 10G_reset pin are interchanged. See the definitions of the various pins in the gold finger 1 shown in Table 5, corresponding to Fig.10 .

[0119] Table 5

[0120]

[0121]

[0122] It should be noted that Tables 3 to 5 are only exemplary examples of three possible definition methods. There are too many definition methods to be exhaustive.

[0123] Through the above description, one pin is added to the upper and lower layers of the gold finger free area of ​​the standard QSFP, and the positions of the other pins remain unchanged. The optical module connector corresponding to the standard QSFP can be inserted, and the optical module connector with 40 pins can also be inserted. However, when the optical module connector corresponding to the standard QSFP is inserted, the first pin 11 and the second pin 13 are in a suspended state. Therefore, it can support 50G PON, 50G PON and 10G PON, 50GPON and GPON, and 50G PON, 10G PON and GPON.

[0124] 3. Optical module connector

[0125] The optical module connector is a connector for plugging the optical module on the optical communication equipment. The optical module is the optical module mentioned above. The optical module connector can also be called a socket. Fig.11 A cross-sectional diagram of an optical module connector is shown.

[0126] See also Fig.12 The optical module connector shown in the figure comprises a pin slot 3 for inserting the optical module. The inner wall of the pin slot 3 is provided with a first extension pin 31 , a first basic pin group 32 and a second extension pin 33 .

[0127] Among them, the first basic pin group 32 includes a first edge pin 321 and a second edge pin 322, the first edge pin 321 is the pin in the first basic pin group 32 adjacent to the first side of the top of the inner wall, and the second edge pin 322 is the pin in the first basic pin group 32 adjacent to the second side of the bottom of the inner wall.

[0128] The first extension pin 31 is located between the first side and the first edge pin 321 , the second extension pin 33 is located between the second side and the second edge pin 322 , and the first extension pin 31 , the first basic pin group 32 and the second extension pin 33 are parallel to each other.

[0129] In an example, the first basic pin group 32 includes 38 pins, among which the number of pins located at the top of the inner wall and the number of pins located at the bottom of the inner wall are the same, that is, 19 pins are located at the top of the inner wall and the other 19 pins are located at the bottom of the inner wall.

[0130] In one example, when the first basic pin group 32 includes 38 pins, in order to enable the pin slot 3 to be inserted into a QSFP optical module including 38 pins and the optical module mentioned in the embodiment of the present disclosure, the width of the pin slot 3 is set to 16.6±0.1mm, and the minimum height of the pin slot 3 is set to 1.14mm, see Fig.13 .

[0131] In addition, the specific dimensions of the pin slot 3 refer to the provisions in the standard of the QSFP protocol. For example, the distance between the top of the pin slot 3 and the bottom of the optical module connector is 5.35±0.13mm, the distance between the horizontal center axis of the pin slot 3 and the bottom of the optical module connector is 3.50±0.10mm, the distance between the bottom end of the pin slot 3 and the bottom of the optical module connector is 1.65±0.08mm, and the height of the base of the pin slot 3 is 0.95±0.13mm, see Fig.14 .

[0132] In one example, the positions of the pins at the top of the inner wall and the pins at the bottom of the inner wall are asymmetrical, so that the intervals between the two edge pins at the top of the inner wall in the first basic pin group 32 and the adjacent side edges are different, and the intervals between the two edge pins at the bottom of the inner wall in the first basic pin group 32 and the adjacent side edges are different. For example, the two edge pins at the top of the inner wall include the first edge pin 321 and the third edge pin 323, and the interval between the third edge pin 323 and the adjacent third side edge is greater than the interval between the first edge pin 321 and the first side edge. Therefore, in order to make the design difficulty of the first extension pin 31 and the second extension pin 33 relatively low, the first side edge and the second side edge are located on different sides of the circuit board 2, and the first extension pin 31 is located on the side with a larger idle area, and the second extension pin 33 is located on the side with a larger idle area.

[0133] For example, when the first basic pin group 32 includes 38 pins, the first extension pin 31 and the second extension pin 33 are close to the side of the circuit board 2. Compared with the spacing of the pins in the first basic pin group 32, the spacing between the first extension pin 31 and the first edge pin 321 is allowed to be changed to a certain extent, and the spacing between the second extension pin 33 and the second edge pin 322 is allowed to be changed to a certain extent, but the deviation of this change will not be relatively large, such as usually not greater than 0.2mm. For example, the first spacing between the first extension pin 31 and the first edge pin 321 is 0.8mm. Alternatively, the first spacing is greater than or equal to 0.6mm and less than or equal to 1mm. The second spacing between the second extension pin 33 and the second edge pin 322 is 0.8mm. Alternatively, the second spacing is greater than or equal to 0.6mm and less than or equal to 1mm. It should be noted that the spacing between the pins needs to match the spacing of the pins in the gold finger 1.

[0134] Optionally, the first interval and the second interval are the same, or different. If they are the same, it can be easier to design.

[0135] In one example, the first extension pin 31 and the second extension pin 33 are close to the side of the circuit board 2, so that the gold finger 1 is close to the side of the circuit board 2, and the width is allowed to be changed in design, but the width should not be too small. The width of the first extension pin 31 and the second extension pin 33 may be set the same for different manufacturers and can be set according to actual needs.

[0136] Optionally, the width of the first extension pin 31 and the width of the second extension pin 33 may be the same or different.

[0137] Optionally, the first extension pin 31 has the same width as the pins in the first basic pin group 32, and the second extension pin 33 has the same width as the pins in the first basic pin group 32. For example, the widths of the first extension pin 31 and the second extension pin 33 are both 0.37 mm, and the width of the pins in the first basic pin group 32 is 0.37 mm. In this way, when manufacturing the pin slot 3, the widths of the pins are the same, and there is no need to set pins of various widths, and the design complexity is low.

[0138] In an example, the lengths of the first extension pin 31 , the pins in the first basic pin group 32 , and the second extension pin 33 are set according to their uses, that is, according to their definitions.

[0139] In an example, the optical module connector further includes a circuit board, and the circuit board is electrically connected to the pins in the pin slot 3 .

[0140] It should be noted that Figure 12 to Figure 14Only part of the structure of the optical module connector is shown in the figure. For the rest of the structure, see Fig.11 .

[0141] 4. Definition of pins in pin slot 3

[0142] When defining the pins of the pin slot 3, for the convenience of description, the 20 pins located at the bottom of the inner wall are numbered 1 to 20 from left to right along the insertion direction, and the 20 pins located at the top of the inner wall are numbered 21 to 40 from right to left along the insertion direction, that is, the first extended pin 31 is numbered 21, and the second extended pin 33 is numbered 1.

[0143] The 20 pins at the top of the inner wall correspond one-to-one with the 20 pins at the top of the circuit board 2 in the gold finger 1, so the definitions of the corresponding pins are exactly the same. The 20 pins at the bottom of the inner wall correspond one-to-one with the 20 pins at the bottom of the circuit board 2 in the gold finger 1, so the definitions of the corresponding pins are exactly the same. See the definition of the pins in the gold finger 1 in the previous text, which will not be repeated here.

[0144] In the disclosed embodiment, the optical module can use a 40-pin QSFP package to achieve compatibility with three modes of PON. Moreover, the key dimensions of the circuit board 2 and the position of the gold finger 1 in the optical module are consistent with the QSFP protocol, and can be compatible with 38-pin QSFP series applications. Moreover, through the reasonable pin definition of the gold finger 1, the optical module can be compatible with optical modules that support 50G PON and 10G PON and optical modules that support single-mode 50G PON.

[0145] Moreover, compared with SFP optical modules, there is a wider layout space, which can adapt to ODSP devices with lower process, reduce the process difficulty of ODSP devices, thereby reducing the cost of ODSP devices, and then reduce the cost of optical modules.

[0146] It should be noted that the above description is based on the first pin 11 and the second pin 13 being one each. With the improvement of the process, the first pin 11 and the second pin 13 may also be multiple. The more pins are added, the more functions can be realized. For example, there are two first pins 11 and two second pins 13, the two first pins 11 are located on both sides of the top surface of the circuit board 2, and the two second pins 13 are located on both sides of the bottom surface of the circuit board 2.

[0147] In the present disclosure, the terms "first" and "second" and the like are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first and second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first pin may be referred to as a second pin, and similarly, a second pin may be referred to as a first pin. Both the first pin and the second pin may be pins, and in some cases, may be separate and different pins.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An optical module, characterized in that: The optical module comprises a gold finger (1) and a circuit board (2), wherein the gold finger (1) is electrically connected to the circuit board (2); The gold finger (1) comprises a first pin (11), a basic pin group (12) and a second pin (13); The first pin (11) is located between a first side edge of the top surface of the circuit board (2) and a first basic pin (121), and the first basic pin (121) is a pin in the basic pin group (12) that is located on the top surface and adjacent to the first side edge; The second pin (13) is located between the second side edge of the bottom surface of the circuit board (2) and the second basic pin (122); the second basic pin (122) is a pin in the basic pin group (12) located on the bottom surface and adjacent to the second side edge.

2. The optical module according to claim 1, characterized in that: The basic pin group (12) includes 38 pins, and the number of pins located on the top surface and the number of pins located on the bottom surface of the 38 pins are the same.

3. The optical module according to claim 1 or 2, characterized in that: The optical module is used to support data transmission of at least one of a Gigabit passive optical network, a 10 Gigabit passive optical network and a 50 Gigabit passive optical network.

4. The optical module according to claim 3, characterized in that: The control or indication pins in the gold finger (1) include the 8th pin, the 11th pin, the 12th pin and the 20th pin from the left of the top surface along the insertion direction and the 1st pin, the 2nd pin, the 8th pin, the 9th pin, the 12th pin to the 14th pin and the 20th pin from the left of the bottom surface; The power pins in the gold finger (1) include the 9th and 10th pins from the left of the top surface along the insertion direction and the 10th pin from the left of the bottom surface; or, the power pins in the gold finger (1) include the 9th and 10th pins from the left of the top surface along the insertion direction and the 10th and 11th pins from the left of the bottom surface; The pins in the gold finger (1) include the first pin, the fourth pin, the seventh pin, the thirteenth pin, the sixteenth pin and the nineteenth pin from the left of the top surface along the insertion direction and the fifth pin and the seventeenth pin from the left of the bottom surface.

5. The optical module according to claim 4, characterized in that: The first pin (11) and the second pin (13) are control or indication pins of the gigabit passive optical network.

6. The optical module according to claim 5, characterized in that: The first pin (11) is a signal check pin of the Gigabit passive optical network, and the second pin (13) is a reset pin of the Gigabit passive optical network; or, The first pin (11) is a reset pin of the gigabit passive optical network, and the second pin (13) is a signal check pin of the gigabit passive optical network.

7. The optical module according to claim 5 or 6, characterized in that: In the case where the basic pin group (12) includes three power pins, the basic pin group (12) includes a rate selection pin for a 50 Gigabit passive optical network.

8. The optical module according to claim 3 or 4, characterized in that: When the basic pin group (12) includes 4 power pins, in an uplink time division scenario, the first pin (11) is a rate selection pin of the 50 Gigabit passive optical network, the second pin (13) is a signal check pin of the Gigabit passive optical network, and the reset signal of the Gigabit passive optical network and the reset signal of the 50 Gigabit passive optical network multiplex the same pin among the 38 pins.

9. The optical module according to any one of claims 1 to 8, characterized in that: The signal transmission pin and the signal receiving pin of the 50 Gigabit passive optical network are located on the top surface of the circuit board (2).

10. The optical module according to any one of claims 1 to 9, characterized in that: The width of the first pin (11) and the second pin (13) is greater than or equal to 0.4 mm and less than or equal to 0.6 mm.

11. The optical module according to any one of claims 1 to 10, characterized in that: The width of the first end of the circuit board (2) is 16.4±0.1 mm, and the thickness is 1 mm. The first end is the end where the gold finger (1) is located.

12. The optical module according to any one of claims 1 to 11, characterized in that: The first side edge and the second side edge are located on two sides of the circuit board (2); The interval between the first side and the first basic pin (121) is greater than the interval between the third side and the third basic pin (123); the third basic pin (123) is a pin in the basic pin group (12) located on the top surface and adjacent to the third side; the third side and the second side are located on the same side of the circuit board (2).

13. The optical module according to claim 12, characterized in that: The interval between the first pin (11) and the first base pin (121) is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm; The interval between the second pin (13) and the second base pin (122) is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm.

14. The optical module according to any one of claims 1, 2 and 4 to 13, characterized in that: The optical module is used to support data transmission in a passive optical network with a transmission rate at least higher than 10 Gbps.

15. An optical module connector, characterized in that: The optical module connector comprises a pin slot (3) for plugging in the optical module; The inner wall of the pin slot (3) is provided with a first extended pin (31), a first basic pin group (32) and a second extended pin (33); The first extended pin (31) is located between the first side of the top of the inner wall and the first edge pin (321), and the first edge pin (321) is a pin in the first basic pin group (32) located at the top and adjacent to the first side; The second extended pin (33) is located between the second side of the inner wall bottom and the second edge pin (322), and the second edge pin (322) is a pin in the first basic pin group (32) located at the bottom and adjacent to the second side.

16. The optical module connector according to claim 15, characterized in that: The first basic pin group (32) includes 38 pins, and the number of pins located at the top and the number of pins located at the bottom of the 38 pins are the same.

17. The optical module connector according to claim 15 or 16, characterized in that: The first extension pin (31), the first basic pin group (32) and the second extension pin (33) are used to support data transmission of at least one of a Gigabit passive optical network, a 10 Gigabit passive optical network and a 50 Gigabit passive optical network.

18. The optical module connector according to claim 17, characterized in that: The control or indication pins in the pin slot (3) include the 8th pin, the 11th pin, the 12th pin and the 20th pin from the top left along the insertion direction and the 1st pin, the 2nd pin, the 8th pin, the 9th pin, the 12th pin to the 14th pin and the 20th pin from the bottom left; The power pins in the pin slot (3) include the 9th pin and the 10th pin from the left at the top along the insertion direction and the 10th pin from the left at the bottom; or, the power pins in the pin slot (3) include the 9th pin and the 10th pin from the left at the top along the insertion direction and the 10th pin and the 11th pin from the left at the bottom; The pins in the pin slot (3) include the first pin, the fourth pin, the seventh pin, the thirteenth pin, the sixteenth pin and the nineteenth pin from the left at the top along the insertion direction and the fifth pin and the seventeenth pin from the left at the bottom.

19. The optical module connector according to claim 18, characterized in that: The first extension pin (31) and the second extension pin (33) are control or indication pins of the Gigabit passive optical network.

20. The optical module connector according to claim 19, characterized in that: The first extension pin (31) is a signal check pin of the Gigabit passive optical network, and the second extension pin (33) is a reset pin of the Gigabit passive optical network; or, The first extension pin (31) is a reset pin of the gigabit passive optical network, and the second extension pin (33) is a signal check pin of the gigabit passive optical network.

21. The optical module connector according to claim 19 or 20, characterized in that: In the case where the first basic pin group (32) includes three power pins, the first basic pin group (32) includes a rate selection pin for a 50 Gigabit passive optical network.

22. The optical module connector according to claim 17 or 18, characterized in that: When the first basic pin group (32) includes 4 power pins, in an uplink time division scenario, the first extension pin (31) is a rate selection pin of the 50 Gigabit passive optical network, the second extension pin (33) is a signal check pin of the Gigabit passive optical network, and the reset signal of the Gigabit passive optical network and the reset signal of the 50 Gigabit passive optical network multiplex the same pin among the 38 pins.

23. The optical module connector according to any one of claims 15 to 22, characterized in that: The signal transmitting pin and the signal receiving pin of the 50 Gigabit passive optical network are located at the top.

24. The optical module connector according to any one of claims 15 to 13, characterized in that: The inner wall width of the pin slot (3) is 16.6±0.1 mm, and the minimum inner wall height is 1.14 mm.

25. The optical module connector according to any one of claims 15 to 24, characterized in that: The first side edge and the second side edge are located on two sides of the pin slot (3); The interval between the first side and the first edge pin (321) is greater than the interval between the third side and the third edge pin (323), the third edge pin (323) is a pin in the first basic pin group (32) located at the top and adjacent to the third side, and the third side and the second side are located on the same side of the pin slot (3).

26. The optical module connector according to claim 25, characterized in that: The interval between the first extension pin (31) and the first edge pin (321) is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm; The interval between the second extension pin (33) and the second edge pin (322) is 0.8 mm, or greater than or equal to 0.6 mm and less than or equal to 1 mm.

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