Optical module working method based on I3C communication and optical module

Abstract

The invention belongs to the technical field of communication, and relates to an optical module working method based on I3C communication and an optical module. The method comprises the following steps that: an optical module MCU (Microprogrammed Control Unit) continuously monitors whether a dynamic address is allocated by an I3C controller or not by monitoring dynamic address update interruption generated by an I3C peripheral; when it is monitored that the dynamic address is successfully allocated, the I3C peripheral, a receiving end DMA channel bound with the I3C peripheral and a sending end DMA channel bound with the I3C peripheral are configured, and after configuration is completed, the I3C controller is waited to send an operation instruction; and when an operation instruction is received, the optical module MCU responds to a private read operation or a private write operation initiated by the I3C controller. The optical module performs data processing work by using the method. According to the method, the optical module can greatly improve the communication rate, the equipment management efficiency and the like by means of the characteristics of the I3C communication based on the functions of dynamic address allocation, interruption and the like of the I3C communication.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and specifically discloses an optical module working method and an optical module based on I3C communication. Background Art

[0002] With the rapid development of modern electronic devices, the demand for communication interfaces is increasing continuously. Due to its simple and efficient characteristics, the traditional communication bus such as I2C (Inter-Integrated Circuit) is widely used in many embedded systems.

[0003] The I2C protocol was released by Philips in 1982 and was initially used to achieve low-speed and low-cost communication between chips on a circuit board. It adopts a two-wire design, namely SDA (Serial Data Line) and SCL (Serial Clock Line), supports the master-slave mode and multi-master architecture, and provides multiple communication bandwidth modes. When using the I2C protocol for optical module control and communication, the optical module receives read and write operations of the master device through the SCL and SDA buses of I2C to achieve the reading of the I2C optical module status and the configuration and control of parameters. And the I2C data parsing adopts a single-byte interrupt processing method. The existing communication method of the optical module based on the I2C protocol has the following deficiencies: 1. Bandwidth rate limitation: In practice, the optical module can at most use the "Fast Mode Plus" of I2C, and its maximum bandwidth is only 1Mpbs, which limits the high-bandwidth data transmission.

[0004] 2. Low processing efficiency of the I2C interrupt mode: When the module receives data through I2C, it adopts single-byte interrupt processing, that is, an interrupt is generated every time a byte is received or sent. The frequent entry of the MCU (Microcontroller Unit) into the interrupt has problems such as low efficiency, high MCU occupancy, poor real-time performance, and high power consumption.

[0005] 3. The problem that DMA (Direct Memory Access) can only process fixed-length data: The traditional communication peripheral DMA transmission can only transmit fixed-length data, that is, the slave device must know in advance the length of the data to be sent by the master device, so that the slave device can set a fixed length when initializing the DMA receive and send channels, which cannot meet the requirements of the optical module master for dynamically reading and writing data lengths of the optical module slave.

[0006] In order to improve the communication efficiency of the optical module, the I3C (Improved Inter-Integrated Circuit) protocol is proposed to be used as the communication protocol for the optical module. This application aims to propose a technology for adapting the I3C communication protocol to the optical module. Summary of the Invention

[0007] The purpose of the present invention is to provide a working method and an optical module for the optical module based on I3C communication, and solve the problem of adapting the I3C communication protocol to the optical module; the specific solutions are as follows: In a first aspect, a working method for an optical module based on I3C communication is provided. The method includes: The optical module MCU continuously monitors whether a dynamic address has been assigned by the I3C controller by monitoring the dynamic address update interrupt generated by the I3C peripheral. When it is detected that the dynamic address assignment is successful, the I3C peripheral, the receive DMA channel bound to the I3C peripheral, and the transmit DMA channel bound to the I3C peripheral are configured. After the configuration is completed, wait for an operation instruction issued by the I3C controller; when an operation instruction is received, the optical module MCU responds to the private read operation or the private write operation initiated by the I3C controller.

[0008] Further, when it is detected that the dynamic address assignment is successful, configuring the I3C peripheral, the receive DMA channel bound to the I3C peripheral, and the transmit DMA channel bound to the I3C peripheral includes configuring and enabling the I3C peripheral STOP interrupt to cooperate with the receive DMA channel to receive variable-length data sent by the I3C controller, and configuring the receive DMA channel to respond to the DMA private write operation; specifically configuring the receive DMA channel includes: Setting the source address of the receive DMA to the I3C receive data register in the I3C peripheral; Setting the destination address of the receive DMA to at least two memory areas in the RAM of the optical module MCU as receive buffer areas; Setting the receive byte length of the receive DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receive byte length of the receive DMA > (the maximum byte length of the EPL extended payload page + one byte); Enabling the receive DMA channel; Enabling the receive DMA request.

[0009] Further, when it is detected that the dynamic address allocation is successful, configure the I3C peripheral, the receiving-end DMA channel bound to the I3C peripheral, and the transmitting-end DMA channel bound to the I3C peripheral, including configuring to enable the STOP interrupt of the I3C peripheral to cooperate with the transmitting-end DMA channel to send variable-length data to the I3C controller, and configuring the transmitting-end DMA channel to respond to the DMA private read operation; specifically configuring the transmitting-end DMA channel includes: Set the source address of the transmitting-end DMA to a memory area in the RAM of the optical module MCU as the transmission buffer; Set the destination address of the transmitting-end DMA to the I3C transmit data register in the I3C peripheral; Set the transmitting byte length of the transmitting-end DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the transmitting byte length of the transmitting-end DMA > the maximum byte length of the EPL extended payload page; Enable the transmitting-end DMA channel; Enable the transmitting-end DMA request.

[0010] Further, the working process of the private write is as follows: After the receiving-end DMA is triggered, move the received data from the receiving-end DMA source address into the receiving buffer in the receiving-end DMA destination address; when the private write data transmission is completed, generate an I3C peripheral STOP interrupt based on the stop bit in the data to achieve variable-length data reception of the receiving-end DMA; Calculate the actual received data length in the STOP interrupt of the I3C peripheral; In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the transmitting-end DMA channel bound to the I3C peripheral to enable the optical module to respond to the next private read operation of the I3C controller; In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the receiving-end DMA channel bound to the I3C peripheral to enable the optical module to respond to the next private write operation of the I3C controller; Process the data in the receiving buffer based on the management memory mapping in the CMIS protocol.

[0011] Further, the working process of the private read is as follows: After the transmitting-end DMA is triggered, the transmitting-end DMA moves the data from the currently configured transmitting-end DMA source address to the destination address of the transmitting-end DMA; when the private read data transmission is completed, generate an I3C peripheral STOP interrupt based on the stop bit in the data to achieve variable-length data transmission of the transmitting-end DMA; Calculate the actual transmitted data length in the I3C peripheral STOP interrupt; Configure the I3C peripheral and the transmit DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private read operation of the I3C controller; Process the data in the transmit buffer based on the management memory mapping in the CMIS protocol.

[0012] Furthermore, configure the I3C peripheral and the receive DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private write operation of the I3C controller. Specifically, it includes: Disable the receive DMA request; Disable the receive DMA channel; Empty the RX-FIFO queue of the I3C; Set the receive byte length of the receive DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receive byte length of the receive DMA > (the maximum byte length of the EPL extended payload page + one byte); Modify the destination address of the receive DMA to the memory area in the RAM of the MCU of the optical module as the receive buffer; Enable the receive DMA channel; Enable the receive DMA request.

[0013] Furthermore, configure the I3C peripheral and the transmit DMA channel bound to the I3C peripheral in the STOP interrupt of the I3C peripheral, so that the optical module can respond to the next private read operation of the I3C controller. Specifically, it includes: Disable the transmit DMA request; Disable the transmit DMA channel; Empty the TX-FIFO queue of the I3C; Set the transmit byte length of the transmit DMA based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the transmit byte length of the transmit DMA > the maximum byte length of the EPL extended payload page; Modify the transmit source address based on the optical module register address in the receive buffer and the page mapping value of the 127th byte of the Lower Memory, so that the optical module can respond to the next current read operation; Enable the transmit DMA channel; Enable the transmit DMA request.

[0014] Furthermore, the private write operation is based on the random write frame format, where the random write frame format consists of a start bit, an optical module address, a write flag bit, an optical module acknowledgment bit, an optical module register address, a first check bit, a first data, a second check bit,..., an Nth data bit, an N + 1th check bit, and a stop bit in sequence.

[0015] Further, the private read operation is based on a random read frame format, where the random read frame format consists of a start bit, an optical module address, a write flag bit, an optical module response bit, an optical module register address, a check bit, a repeated start bit, an optical module address, a read flag bit, an optical module response bit, a first data, a first end determination bit, ……, an Nth data, an Nth end determination bit, and a stop bit in sequence.

[0016] Further, the current read operation is based on a current read frame format, where the current read frame format consists of a start bit, an optical module address, a read flag bit, an optical module response bit, a first data, a first end determination bit, ……, an Nth data, an Nth end determination bit, and a stop bit in sequence.

[0017] Further, it is characterized in that it further includes an optical module communication error recovery method, which is specifically as follows: When the I3C peripheral enters an error interrupt, the optical module MCU acquires and records the error source; In the error interrupt of the I3C peripheral, enable the I3C peripheral STOP interrupt and perform the configuration of the transmitter DMA channel; the specific configuration of the transmitter DMA channel includes: Disable the transmitter DMA request; disable the transmitter DMA channel; clear the I3C TX-FIFO queue; set the transmitter DMA transmission byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the transmitter DMA transmission byte length > the maximum byte length of the EPL extended payload page; modify the transmitter DMA source address based on the CMIS memory mapped address where the current communication error occurs; enable the transmitter DMA channel; enable the transmitter DMA request; In the error interrupt of the I3C peripheral, enable the I3C peripheral STOP interrupt and perform the configuration of the receiver DMA channel; the specific configuration of the receiver DMA channel includes: Disable the receiver DMA request; disable the receiver DMA channel; clear the I3C RX-FIFO queue; set the receiver DMA reception byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receiver DMA reception byte length > (the maximum byte length of the EPL extended payload page + one byte); modify the destination address of the receiver DMA to the memory area in the RAM of the optical module MCU as the reception buffer; enable the receiver DMA channel; enable the receiver DMA request.

[0018] In a second aspect, an optical module is provided, and the working method of the optical module adopts the optical module working method based on I3C communication provided in the first aspect.

[0019] The beneficial effects of the present invention are as follows: A working method for optical module data processing combining I3C communication and DMA mechanism is provided. Based on the dynamic address allocation, interruption and other functions of I3C communication, this method enables the optical module to greatly improve the communication rate and the device management efficiency by virtue of the characteristics of I3C communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The hardware structure diagram of the optical module of the present invention; Figure 2 The schematic diagram of the random write frame format in the working method of the optical module of the present invention; Figure 3 The schematic diagram of the random read frame format in the working method of the optical module of the present invention; Figure 4 The schematic diagram of the current read frame format in the working method of the optical module of the present invention; Figure 5 The flowchart of the working method of the optical module of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0022] With the development of optical communication technology, optical modules need to support higher-bandwidth data transmission and lower power consumption. However, existing optical modules generally rely on the I2C protocol and use single-byte interruption to process data. This protocol has problems such as limited bandwidth, low data processing efficiency, high power consumption and insufficient scalability.

[0023] Therefore, the present invention intends to design a working method for an optical module based on the I3C protocol.

[0024] As Figure 1 shown, first, clarify the hardware architecture of the optical module in the present invention, which mainly includes a fiber optic interface, an electrical interface, a transmitting unit, a receiving unit, a DSP (Digital Signal Processing), an MCU and a power supply unit.

[0025] Among them, the fiber optic interface: Connects to the transmitting unit and the receiving unit and is used for receiving and transmitting optical signals. If it is an AEC (Active Electrical Cable) module, the receiving and transmitting units and the fiber optic interface in the above block diagram are not included.

[0026] Electrical Interface: 1. It includes the SCL and SDA signal lines of I3C. The optical module is connected to the SCL and SDA buses of the I3C controller (such as switches, network cards, etc.) through the I3C bus of the electrical interface / golden finger. The optical module acts as a target device to conduct I3C communication with the I3C controller. 2. Multiple low-speed signal control pins, such as ModPrsL (Module Present Low, module presence detection signal (low level effective)), IntL (Interrupt Low, interrupt signal), LPMode (Low Power Mode, low power mode), ModSel (Mode Selection, module selection signal), and ResetL (Reset Low, reset signal), are used to implement functions such as module presence indication, status indication, power consumption mode control, module selection, and reset control. 3. It includes high-speed signal data pins, which are divided into differential signal pairs at the transmitting end of Tx1, Tx2...Txn (representing multiple independent transmission channels of the optical module) and differential signal pairs at the receiving end of Rx1, Rx2...Rxn (representing multiple independent receiving channels of the optical module). 4. Power lines and ground lines are used to supply power to the optical module.

[0027] Transmitting Unit: It mainly includes a laser, a modulator, and a driver, which are responsible for converting electrical signals into optical signals and transmitting them to the receiving unit of the remote optical module through optical fibers. If it is an AEC module, it does not include the receiving and transmitting units and the optical fiber interface in the above block diagram.

[0028] Receiving Unit: It mainly includes a photodetector and a TIA (Transimpedance Amplifier), which are responsible for converting optical signals into electrical signals, amplifying the electrical signals, and then outputting them to the DSP.

[0029] DSP: It is mainly used to process complex signal modulation and transmission problems. It improves the performance and transmission quality of the optical module through efficient digital signal processing algorithms. Some DSPs have integrated the driver in the above transmitting unit and the TIA in the receiving unit.

[0030] MCU: It is the management core of the module, responsible for coordinating and controlling the work of each part of the module to ensure the efficient operation of the module.

[0031] Power Supply Unit: It supplies power to the MCU, DSP, transmitting unit, and receiving unit.

[0032] Before elaborating on the method of the present invention in detail, some professional terms in the context of the present invention are first listed and explained.

[0033] Optical module: A key hardware module in an optical communication system that realizes the mutual conversion between electrical signals and optical signals and is used for high-speed data transmission between network devices. The optical module also has an MCU, which is formed by encapsulating a core, peripherals electrically connected to the core, and storage (Flash / RAM), etc.; the I3C peripheral in the present invention is the aforementioned peripheral that composes the MCU. As the management core of the optical module, the MCU is responsible for coordinating and controlling the work of each part of the module to ensure the efficient operation of the module, and the I3C peripheral is managed by the MCU core. The I3C peripheral is managed by the MCU of the optical module and operates according to the MIPI (Mobile Industry Processor Interface) protocol.

[0034] The I3C controller (I3C Controller), which is the master device, is an I3C peripheral located in hardware devices such as switches or network cards, and this peripheral acts as a controller (Controller) role, while the I3C peripheral of the optical module acts as a target device (Target) role.

[0035] The I3C peripheral in the present invention refers to a hardware module integrated in the MCU and supporting the I3C communication protocol. It can be configured into two roles, Target and Controller. The I3C peripheral of the optical module MCU is usually configured as the role of the target device (Target), called the slave device. The I3C peripherals in hardware devices such as switches or network cards are usually configured as controllers (Controller), called the master device.

[0036] DMA (Direct Memory Access): A technology used for data transfer. In the present invention, it is used to directly transfer data between peripherals and memory without the CPU intervening byte by byte, which can greatly improve efficiency and reduce power consumption.

[0037] DMA channel: Refers to the logical path used to complete a specific data transfer task, just like a "conveyor belt", which automatically transfers data from one location to another based on a specific trigger signal.

[0038] STOP interrupt: An interrupt mechanism in the I3C peripheral. Its name may be different in hardware devices of different manufacturers. For example, in the STM32 series products produced by STMicroelectronics Group, it can also be called a completion interrupt.

[0039] Variable-length data: Refers to data frames or data packets with an unfixed length. Correspondingly, in traditional DMA communication, only data frames with a fixed length can be transmitted, that is, the target device knows in advance the length of the data to be sent or received by the master device.

[0040] Enable: It means that by setting relevant control parameters, register bits or logic signals, a certain functional module, subsystem or signal path is put into an operable, responsive or effective state to execute the predetermined function. It usually means that the system has the permission or conditions to execute a certain function.

[0041] Disable: It is the antonym of Enable. It means that by clearing or modifying the corresponding control parameters, register bits or signal states, a specific function, module or path is put into an inoperable, unresponsive or invalid state to achieve the purpose of closing, pausing or stopping the function.

[0042] EPL (Extended Payload Length): The maximum byte length of the extended payload page. In the optical module management communication based on the CMIS (Common Management Interface Specification) protocol, data is exchanged in the form of command frames through the I2C or I3C bus. The command frame usually includes fields such as the Command Code, Payload Length, and Payload. To adapt to the scenario of large-capacity data transmission, the CMIS protocol introduces the EPL (Extended Payload Length) mechanism on the basis of the standard Payload Length field. This field is enabled when the Payload Length field takes the maximum value of 0xFF (255), and is used to indicate the situation where the actual data payload length exceeds 255 bytes. When the EPL mechanism is enabled, the original Payload field is stored and transmitted immediately after the EPL field. Through this mechanism, large-capacity data interaction scenarios such as EEPROM data block access and firmware download can be supported, significantly improving the protocol's expansion ability and data throughput efficiency.

[0043] Enable the 127th byte of Lower Memory: Lower Memory refers to an address space of 128 bytes in size, ranging from 0x00 to 0x7F. This area contains some global control and module status information. Among them, the 127th byte (address 0x7F) refers to the Page Select byte in CMIS, that is, the page index; the page index value determines which page (or the page in a certain Bank) is accessed when the host accesses a certain byte in the page (address range from 128 to 255). Generally speaking, by writing different values (from 128 to 255) to this byte, different "pages" can be accessed. Each "page" represents a complete 128-byte register mapping area for accessing more information or control functions.

[0044] Based on the above description of professional terms, the method of the present invention is further elaborated as follows: In the present invention, the optical module uses the I3C protocol for communication. Based on the advantages of the I3C protocol, dynamic address allocation for the I3C peripherals in the optical module can be achieved. After the I3C peripherals are assigned dynamic addresses, the I3C peripherals will generate dynamic address update interrupts, and the optical module MCU will monitor in real time whether it receives the dynamic address update interrupts generated by the I3C peripherals to determine whether the I3C peripherals have completed address allocation based on the monitoring results.

[0045] It should be noted that when the optical module MCU monitors the dynamic address allocation of the I3C peripherals, the optical module can perform normal tasks. During dynamic address allocation, the I3C optical module can receive and respond to the ENTDAA (Enter Dynamic Address Assignment) instruction, RSTDAA (Reset Dynamic Address Assignment) instruction, and SETNEWDA (Set New Dynamic Address) instruction sent by the I3C controller to dynamically allocate a 7-bit address to ensure the uniqueness of the dynamic address on the I3C bus; it should be noted that the I3C controller here is the master device, which is an I3C peripheral in hardware devices such as switches or network cards, and this peripheral acts as the controller role, while the I3C peripheral of the optical module acts as the target device role.

[0046] When the dynamic address allocation is successful, the hardware module in the optical module can communicate with the hardware module in the master device (such as a switch or network card) to implement internal system operations, achieving access to and modification of specific functions, configurations, or status information of the device. The operations here mainly include the private read or private write operations of the I3C controller by the optical module MCU based on the operation instructions.

[0047] Before performing the private read or private write operation, it is first necessary to configure the I3C peripheral; specifically, enable the I3C peripheral STOP interrupt (which has different names in different hardware device manufacturers, such as the completion interrupt in STM32 series products), which is used to implement the end flag of the DMA variable-length data transfer between the I3C receive data register or the I3C transmit data register and the memory of the optical module MCU; its working principle is that when the data transfer between the I3C receive data register or the I3C transmit data register and the memory of the optical module MCU (including the optical module MCU sending or receiving data) is completed, the optical module MCU will immediately sense the I3C peripheral STOP interrupt signal on the I3C bus (during the period when SCL is kept high, the process of the SDA level dropping from 1 to 0, that is, the falling edge of the level). Variable-length data means that compared with the traditional DMA method where the data transfer has a fixed length, the variable-length data here means that the data length is not fixed or unique.

[0048] Here, instead of using the traditional DMA method to receive data and judge whether the reception is completed based on a pre-set fixed transfer data length, the I3C peripheral STOP interrupt is used; for easy understanding, taking the actual data written by the control device as 2047 bytes as an example, after the 2047 bytes are transmitted on the I3C hardware bus, an I3C STOP interrupt will be generated, and no transmit-side DMA transfer completion interrupt will be generated (because at this time, the DMA has only transferred 2047 bytes of data, which is less than the maximum receive byte length of 2050 bytes on the receive side); furthermore, relevant processing after the data reading is completed can be further carried out in the I3C STOP interrupt, such as preparing the next transmit-side or receive-side configuration to support the next private read or private write operation.

[0049] After the I3C peripheral is configured, the receiving DMA channel bound to the I3C peripheral is configured to respond to the DMA private write operation; the private write here means that the I3C controller (master device) transfers data to the I3C receive data register in the I3C peripheral of the optical module, and then transfers the data from the I3C receive data register to the receive buffer of the optical module MCU. That is to say, after the data is written into the I3C receive data register, the data is transferred to the optical module MCU memory through the DMA transfer mechanism; therefore, before the data is further transferred to the optical module MCU memory, it is necessary to first configure the DMA channel between the optical module MCU memory and the I3C peripheral in the optical module. Based on the optical module MCU, the DMA channel here is the receiving DMA channel. The specific content of the receiving DMA channel configuration is as follows: Set the source address of the receiving DMA to the I3C receive data register in the I3C peripheral; the source address here can also be understood as: the I3C receive data register in the I3C peripheral is used to receive the data sent by the master device (switch, network card, test card, etc.) through the bus to implement the private write.

[0050] Set the destination address of the receiving DMA to at least two memory areas in the RAM of the optical module MCU as the receive buffer; the purpose of setting multiple receive buffers is that they can be used alternately to receive multiple data; In this embodiment, the receive buffer can be two, named the first receive buffer and the second receive buffer respectively. Among them, the first receive buffer and the second receive buffer are two memory areas in the RAM of the I3C optical module MCU; in subsequent private write operations, the I3C optical module will alternately use the first receive buffer and the second receive buffer to receive data to implement the Ping-Pong mechanism, and the first receive buffer is used here.

[0051] Regarding the Ping-Pong mechanism, that is, in the case of multiple buffers, the first received data to be processed is cached in one of the receive buffers and the data is processed. When there is still new data to be received and processed while the data is being processed, the data is stored in another receive buffer and waits to be processed after the previous data is processed; similarly, when there is new data to be received and processed while the data in the first two buffers has not been processed yet, the data can be cached in the third receive buffer. Generally, setting two receive buffers can basically meet most application scenarios. Therefore, in the embodiments of the present invention, two buffers are used as examples.

[0052] It should also be noted that when there are multiple blocks in the receive buffer, a receive priority can be set for each buffer block. The purpose is that when waiting to receive data, the address of the idle receive buffer with a higher priority is first configured as the destination address to receive data preferentially. When the previous data is still being processed and the occupied receive buffer has not been freed up, the new data will be cached in the receive buffer with the highest priority among the idle receive buffers.

[0053] To cooperate with the I3C peripheral STOP interrupt to achieve variable-length data reception, in the configuration of the receive-end DMA channel, there is also a setting for the receive-end DMA receive byte length; this length setting is based on the maximum byte length of the EPL (Extended Payload Length) extended payload page in the CMIS (Common Management Interface Specification) protocol; it needs to be larger than the maximum byte length of the EPL extended payload page plus one byte; that is, the receive-end DMA receive byte length > (the maximum byte length of the EPL extended payload page + one byte). This one byte refers to the address byte of the data register. For easy understanding, the following is an example: One setting can be that when the current maximum EPL length is 2048 bytes, adding an optical module data register address byte makes it a total of 2049 bytes. Therefore, to achieve DMA variable-length reception, a length value larger than 2049 needs to be set. For example, when the receive-end DMA receive byte length here is set to 2050 bytes, since the maximum EPL length is 2048 bytes and an additional one-byte register length is required, a total of 2049 bytes, so when receiving data, data larger than 2049 bytes will not be received, and thus the DMA transfer complete interrupt will not be triggered. At this time, it is possible to determine whether the reception is complete based on identifying the I3C peripheral STOP interrupt, and thus achieve the reception of variable-length data.

[0054] After the above configuration is set up, the receive-end DMA channel can be enabled and the receive-end DMA request can be enabled, so that the DMA channel and the DMA request are in an available state, so that after the private write data of the master device is transferred to the I3C receive data register in the optical module I3C peripheral, the corresponding DMA channel request of the I3C peripheral is triggered, and the data is transferred from the I3C receive data register to the optical module MCU memory through the receive-end DMA channel.

[0055] After the I3C peripheral is configured, the transmitting DMA channel bound to the I3C peripheral is configured to respond to the DMA private read operation; through the above private write process, it can be known that the private read means that the I3C controller (master device) reads the data transported by the DMA from the memory area of the optical module MCU in the I3C transmit data register of the I3C peripheral of the optical module. That is to say, the data transmission process of the private read is: the optical module MCU transports the data to the I3C transmit data register through the transmitting DMA channel, and the I3C transmit data register then transmits the data to the I3C controller (master device). Similarly, before the optical module MCU transports the data to the I3C transmit data register through the transmitting DMA channel, the transmitting DMA channel in the optical module needs to be configured first; the specific content is as follows: Set the source address of the transmitting DMA to a memory area in the RAM of the optical module MCU as the transmit buffer; in practice, specifically: set the source address of the transmitting DMA to the Management Memory map specified by the CMIS protocol. Here, it is the start address of the Lower Memory specified by the CMIS protocol, which is also a memory area in the RAM (Random Access Memory) of the I3C optical module MCU, named the transmit buffer here. At this time, if the I3C controller performs a Current Read operation, the Lower Memory content can be successfully read out. It should be noted that the Lower Memory in CMIS refers to an address space of 128 bytes in size, with a range of 0x00 to 0x7F. This area contains some global control and module status information. Specifically, for the 127th byte (address 0x7F), in CMIS, it is used for page selection. That is, by writing different values to the 127th byte, different "pages" can be accessed. Each "page" represents a complete 128-byte register mapping area for accessing more information or control functions.

[0056] Set the destination address of the transmitting DMA to the I3C transmit data register in the I3C peripheral; the destination address here can be understood as: the I3C transmit data register in the I3C peripheral is used to send the data for implementing the private read to the master device (switch, network card, test card, etc.) through the bus.

[0057] Similarly, to cooperate with the STOP interrupt of the I3C peripheral to achieve variable-length data transmission, it also includes the setting of the transmission end DMA transmission byte length; this length setting is based on setting the transmission end DMA transmission byte length with the maximum byte length of the EPL extended payload page in the CMIS protocol, and the transmission end DMA transmission byte length can be greater than the maximum byte length of the EPL extended payload page; for easy understanding, the following is an example: One of the settings can be that when the current maximum EPL length is 2048 bytes, in order to achieve DMA variable-length reception, a length value greater than 2048 also needs to be set. Here, it can be set to 2049 bytes, that is, greater than the maximum byte length of the EPL extended payload page. Different from the private read, a register address byte also needs to be carried in the data of the private write. Therefore, the reception end DMA reception byte length is set to 2050 bytes, while in the private read, since there is no register address byte in the data, it can be set to 2049 bytes.

[0058] After the above configuration is set, the transmission end DMA channel can be enabled and the transmission end DMA request can be enabled; so that the DMA channel and the DMA request are in an available state; when a private read request from the master device is received, the corresponding DMA channel request of the I3C peripheral is triggered, and the optical module MCU transports the data to the I3C transmit data register through the transmission end DMA channel; and then the I3C transmit data register transmits the data to the master device through the I3C bus.

[0059] The above content elaborates in detail the hardware device configuration before performing the private read operation or the private write operation and the specific data transmission process during the private read or private write operation. Based on this configuration description and data transmission process description, the following further details the specific operation process and data communication principle when performing the private write or private read operation.

[0060] It should be noted that the triggering of both the private write or private read operation is based on the operation instruction of the I3C controller (master device); that is, after the optical module MCU receives the operation instruction of the I3C controller (master device), the corresponding private write or private read operation will be executed.

[0061] First, the execution process of the private write operation is described: Receive and respond to the private write operation of the I3C controller.

[0062] When the optical module MCU receives a private write operation from the I3C controller, the data for the private write has already been transmitted by the I3C controller to the I3C receive data register. To transfer the private write data in the I3C receive data register to the receive buffer in the optical module MCU, the receive DMA is first triggered to transfer the data received in the I3C receive data register from the receive DMA source address (i.e., the address of the I3C receive data register) to the first receive buffer or the second receive buffer in the receive DMA destination address (the memory area address in the RAM of the optical module MCU). When the transfer of the private write data is complete, an I3C peripheral STOP interrupt is generated based on the stop bit. The stop bit is the last byte in the private write data, as can be seen from the random write frame format defined later.

[0063] In practice, it can be specifically: The receive DMA is triggered by the not-empty flag of the RX-FIFO (Receive First-In-First-Out buffer), and automatically transfers the received data from the receive DMA source address (I3C receive data register) to the receive DMA destination address (the first receive buffer and the second receive buffer in the RAM of the optical module MCU alternate to receive data). The data transferred by the DMA is the optical module register address in the random write frame format, as well as the first data to the Nth data. When the transfer of the private write data is complete, an I3C peripheral STOP interrupt is generated based on the stop bit to achieve the reception of variable-length data.

[0064] Calculate the actual received data length in the I3C peripheral STOP interrupt.

[0065] After completing the data transfer work in the private write operation, it is also necessary to configure the I3C peripheral in the STOP interrupt of the I3C peripheral; and configure the transmit DMA channel bound to the I3C peripheral for the optical module to respond to the next private read operation of the I3C controller; and configure the receive DMA channel bound to the I3C peripheral for the optical module to respond to the next private write operation of the I3C controller.

[0066] Among them, the I3C peripheral configuration is the same as the I3C peripheral configuration before the DMA channel configuration of the aforementioned private read or private write operation, which is also to enable the I3C peripheral STOP interrupt to achieve the transfer of variable-length data between the I3C receive data register or the I3C transmit data register and the memory of the optical module MCU. Then, the corresponding DMA channel is configured.

[0067] Take the private read as an example first: Before configuring the transmit DMA channel again; it is first necessary to disable the transmit DMA request and the transmit DMA channel, that is, before the configuration is completed, the transmit DMA is in an inoperative state.

[0068] Then clear the TX-FIFO (Transmit First-In-First-Out) queue of I3C. Then set the byte length of the DMA sender based on the maximum byte length of the EPL extended load page in the CMIS protocol. The byte length of the DMA sender is greater than the maximum byte length of the EPL extended load page. As above, the byte can be set to 2049 bytes. The principle here is as mentioned above, and there are many principles in the following text that can refer to the above content of DMA channel configuration, so it will not be repeated here and in the following text.

[0069] Based on the optical module register address in the first receiving buffer and / or the second receiving buffer and the page mapping value of LowerMemory byte 127, the source address of the transmitting end is modified so that the optical module responds to the next current read operation; in practice, the source address of the transmitting end is modified, which is based on the Management Memory map management memory mapping specified by the CMIS protocol, and the specific source address is determined according to the optical module register address in the latest received receiving buffer (the first receiving buffer or the second receiving buffer) and the page mapping value of LowerMemory byte 127. After the above work is completed, the transmitting end DMA channel is reconfigured. In order to respond to subsequent private read operations, the transmitting end DMA channel and the transmitting end DMA request are enabled again at this time.

[0070] Similarly, in response to a new private write operation, the specific configuration process is as follows: Before configuring the receiving DMA channel again, you first need to disable the receiving DMA request and the receiving DMA channel, that is, before the configuration is completed, the receiving DMA is in an inoperative state.

[0071] Clear the RX-FIFO queue of I3C. Set the receiving DMA receiving byte length based on the maximum byte length of the EPL extended load page in the CMIS protocol, and the receiving DMA receiving byte length is greater than the maximum byte length of the EPL extended load page plus a byte of register length; as above, the byte here can be set to 2050 bytes. Modify the destination address of the receiving DMA to two memory areas in the RAM of the optical module MCU as the first receiving buffer area and the second receiving buffer area; in subsequent private write operations, the first receiving buffer area and the second receiving buffer area are set alternately. The use of the Ping-pong mechanism can minimize the risk of delay and data loss. After the above work is completed, the receiving DMA channel is reconfigured. In order to respond to subsequent private write operations, the receiving DMA channel and the receiving DMA request are enabled again at this time.

[0072] After completing the above DMA channel configuration, the data in the first receive buffer and / or the second receive buffer is processed based on the management memory mapping in the CMIS protocol. Among them, the received data in the receive buffer is the optical module register address in the random write frame format, and the first data to the Nth data (such as Figure 2 the data 1 to data N therein). Refer to the CMIS protocol to find the optical module control register that the I3C controller wants to control according to the page mapping value of the current lower Memory and the optical module register address, and perform corresponding control.

[0073] Among them, as Figure 2 shown, the random write frame format consists of a start bit, an optical module address, a write flag bit, an optical module acknowledgment bit, an optical module register address, a first parity bit, a first data, a second parity bit,..., an Nth data, an N+1th parity bit, and a stop bit in sequence. For ease of understanding, each component in the frame format will be further described.

[0074] Start bit (START): The start condition on the I3C bus, used to initiate a communication, usually initiated by the master device, indicating the start of a new transaction.

[0075] Optical module address (Address): A 7-bit or dynamically allocated I3C device address, used to uniquely identify the location of the target device (optical module).

[0076] Write flag bit (Write Bit): The value is 0, indicating that the master device will write data to the target device (at this time, writing the register address).

[0077] Optical module acknowledgment bit (ACK): The response bit of the target device to the address and direction bit, pulled low indicating that it has been successfully received and is ready for communication.

[0078] Optical module register address (Register Address): Specifies the register address to be written inside the target device. This address will be used in subsequent reads.

[0079] Parity bit: After the master device writes the optical module register address, an odd parity bit is appended to perform odd parity check on this address byte, that is, it is required that the number of "1"s among all bits including the parity bit is odd. If the odd parity check fails, the target device may not respond or return an error flag, thereby ensuring the reliability of communication.

[0080] Optical module acknowledgment bit (ACK): The target device confirms again that it is ready to send data to the master device.

[0081] First data (Data 1): The first byte of data written to the register address, sent by the I3C controller.

[0082] Data N: The last data byte.

[0083] STOP: Indicates the completion of the current communication and releases the bus.

[0084] The above is the description of the execution process of the private write operation. Next, the working process of the private read is briefly described as follows: Receive and respond to the private read operation of the I3C controller.

[0085] The transmitting DMA transfers the data from the currently configured transmitting DMA source address into the I3C transmit data register in the destination of the transmitting DMA; when the private read data transfer is completed, an I3C peripheral STOP interrupt is generated based on the STOP bit; in practice, the transmitting DMA automatically transfers the data from the configured transmitting DMA source address to the transmitting DMA destination address (the I3C transmit data register of the I3C peripheral). The source address here is determined by the optical module register address and the Lower Memory page mapping value in the first receive buffer and the second receive buffer. The private read operation is based on the above random read frame format; after the private read data transfer is completed, an I3C peripheral STOP interrupt is generated based on the STOP bit.

[0086] Among them, as Figure 3 shown, the random read frame format consists of a start bit, an optical module address, a write flag bit, an optical module acknowledgment bit, an optical module register address, a parity bit, a repeated start bit, an optical module address, a read flag bit, an optical module acknowledgment bit, the first data, the first end judgment bit,..., the Nth data, the Nth end judgment bit, and a STOP bit in sequence. Among them, Repeated START: Restarts a frame of communication without sending STOP, used to switch from a write operation to a read operation.

[0087] Address: Sends the target device address again to prepare for the upcoming read operation.

[0088] Read Bit: A value of 1 indicates that the master device will read data from the target device.

[0089] First End Judgment Bit (T bit): The response bit sent by the target device, used to notify the master device whether the target device itself continues to transmit data. Among them: T bit = 1 indicates: Continue to transmit data, and the transmission is ended by the stop signal.

[0090] T bit = 0 indicates: The target device ends the data transmission.

[0091] Nth End Judgment Bit (T bit): A response bit sent by the target device to notify the master device whether the target device itself continues to transmit data. Among them: T bit = 1 indicates that: continue to transmit data, and the transmission is ended by the stop signal.

[0092] T bit = 0 indicates that: the target device ends data transmission. Calculate the actual transmitted data length in the I3C peripheral STOP interrupt.

[0093] After completing the data transfer work in the private read operation, it is also necessary to configure the I3C peripheral in the STOP interrupt of the I3C peripheral; and configure the transmitting DMA channel bound to the I3C peripheral to enable the optical module to respond to the next private read operation of the I3C controller.

[0094] Among them, the I3C peripheral configuration is the same as the I3C peripheral configuration before the DMA channel configuration of the aforementioned private read or private write operation, which is also to enable the I3C peripheral STOP interrupt to realize the transfer of variable-length data between the I3C transmit data register and the optical module MCU memory. Then configure the corresponding DMA channel.

[0095] The process of reconfiguring the DMA channel for private read is as follows: Before reconfiguring the transmitting DMA channel again; first, it is necessary to disable the transmitting DMA request and the transmitting DMA channel, that is, before the configuration is completed, the transmitting DMA is in an inoperative state.

[0096] Empty the TX-FIFO queue of the I3C. Then set the transmission byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol. The transmitting DMA transmission byte length is greater than the maximum byte length of the EPL extended payload page; similarly, 2049 bytes can be set here for the byte.

[0097] Based on the optical module register address in the first receive buffer and / or the second receive buffer and the LowerMemory byte 127 page mapping value, modify the transmitting source address to enable the optical module to respond to the next current read operation. Among them, as Figure 4 shown, the current read frame format consists of a start bit, an optical module address, a read flag bit, an optical module acknowledgment bit, the first data, the first end judgment bit,..., the Nth data, the Nth end judgment bit, and a stop bit in sequence. After the above work is completed, the transmitting DMA channel is reconfigured. In order to respond to subsequent private read operations, enable the transmitting DMA channel and the transmitting DMA request at this time.

[0098] After completing the above DMA channel configuration, the data in the transmit buffer is processed based on the managed memory mapping in the CMIS protocol. This mainly includes clearing the registers of the Lower memory and the upper page (high page).

[0099] In addition, as Figure 5 shown, before performing the above working method, it also includes: Step 1: Initialize the low-speed control pins of the optical module electrical interface.

[0100] Step 2: Initialize DMA. Specifically, it includes: Step 2.1: Initialize the module I3C transmitter DMA channel.

[0101] Step 2.1.1: Configure the hardware request protocol of the transmitter DMA channel as burst.

[0102] Step 2.1.2: Configure the transmitter DMA direction as memory to peripheral.

[0103] Step 2.1.3: Configure the DMA source address mode as auto-increment mode.

[0104] Step 2.1.4: Configure the DMA destination address mode as fixed mode.

[0105] Step 2.2: Initialize the module I3C receiver DMA channel.

[0106] Step 2.2.1: Configure the hardware request protocol of the receiver DMA channel as burst (burst).

[0107] Step 2.2.2: Configure the receiver DMA direction as peripheral to memory.

[0108] Step 2.2.3: Configure the DMA source address mode as fixed mode.

[0109] Step 2.2.4: Configure the DMA destination address mode as auto-increment mode.

[0110] Step 3: Initialize the I3C peripheral, which mainly includes the following configurations: Step 3.1: Configure the optical module as an I3C target device (Target).

[0111] Step 3.2: Configure the Provisioned ID (pre-configured identifier).

[0112] Step 3.3: Set the maximum read data length to 2048 bytes to support the reading of the EPL extended payload page with a maximum length of 2048 bytes specified in the CMIS protocol.

[0113] Step 3.4: Set the maximum write data length to 2049 to support the simultaneous write of the EPL extended payload page with a maximum length of 2048 bytes specified in the CMIS protocol plus 1 byte of the optical module register address.

[0114] Step 3.5: Configure to support the maximum transmission rate. In SDR (Single Data Rate) mode, it supports a maximum bandwidth of 12.5Mpbs.

[0115] Step 3.6: Enable the I3C transfer complete interrupt and the I3C error interrupt.

[0116] Step 3.7: Enable the event response interrupt of the I3C CCC (Common Command Codes) instructions including the dynamic address allocation instruction ENTDAA.

[0117] Step 4: Initialize the DSP, the transmitting unit, and the receiving unit.

[0118] The above working method of the optical module based on I3C communication transfers data from the I3C peripheral to the RAM of the I3C optical module MCU through DMA after receiving the data sent by the I3C controller from the I3C bus, and transfers the data in the RAM of the I3C optical module MCU to the I3C peripheral through DMA. The method of using DMA transfer can improve the I3C communication throughput and reduce the CPU load.

[0119] According to the maximum length of the EPL extended payload in the CMIS protocol, by setting the transmission length of the data sent and received by DMA to be greater than the actual data length received and sent by the I3C optical module, and combining with the completion interrupt of the I3C peripheral, the variable-length transmission of DMA is achieved.

[0120] During the process of the I3C optical module receiving data, the Ping-Pong mechanism is used, that is, the data is received by alternately using the first receiving buffer and the second receiving buffer, which can minimize the risk of delay and data loss. The destination address of the receiving end DMA is two memory areas defined in the RAM of the I3C optical module MCU, which are named receiving buffer 1 and receiving buffer 2 here. In the private write operation, the I3C optical module will alternately use the first receiving buffer and the second receiving buffer to receive data to implement the Ping-Pong mechanism.

[0121] The above method has the following advantages: 1. Improve the communication rate of the optical module and meet the high-bandwidth requirements; Optical modules need to handle high-speed data transmission in modern communication. The I3C protocol can support the SDR mode with a maximum bandwidth of 12.5 Mbps and the HDR-DDR mode with a communication bandwidth of 25 Mbps, significantly improving the bus communication rate and meeting the requirements of optical modules for high bandwidth and high speed. Compared with the Fast Mode Plus (1 Mbps) used in traditional I2C modules in practice, I3C has achieved an order-of-magnitude improvement in data throughput, thus accelerating the data transmission and control command processing efficiency between the optical module and the host device. It is particularly suitable for application scenarios that require high-speed and large-volume data exchange, such as firmware updates of optical module MCUs and DSPs. For firmware downloads of the same size, it takes 20.34 s to update the firmware using I2C as the master device test board and an I2C optical module, while it only takes 6.28 s to update the firmware using I3C as the controller test board and an I3C optical module.

[0122] 2. Use DMA to transfer data, reduce MCU occupancy, and improve real-time performance; Using DMA to transfer data reduces the MCU occupancy rate, avoids frequently entering the interrupt to process data reception and transmission, enables the rest of the tasks of the optical module to run more smoothly, and improves the real-time performance of the optical module.

[0123] 3. Low-power operation; The present invention utilizes the low-power characteristics of the I3C protocol to enable the I3C bus of the optical module to automatically enter the low-power mode in the non-communication state, thereby reducing the overall energy consumption of the optical module. Especially in scenarios where a large number of devices are densely deployed, this optimization can significantly reduce the overall power consumption, extend the service life of the optical module, and reduce the maintenance cost.

[0124] 4. Improve the stability of the optical module and reduce signal interference; The improved design of the I3C protocol includes better signal integrity and bus arbitration mechanisms, which can reduce communication conflicts and signal interference inside the optical module. Through these characteristics, the present invention improves the stability and reliability of the optical module, ensuring the long-term stable operation of the system.

[0125] In addition to disclosing the above working method process, the present invention also proposes an optical module communication error recovery method, which is as follows: When the I3C peripheral enters an error interrupt, the optical module MCU obtains and records the error source; In the error interrupt of the I3C peripheral, enable the I3C peripheral STOP interrupt and configure the transmit DMA channel; the specific configuration of the transmit DMA channel includes: First, it is necessary to disable the transmitter DMA request and the transmitter DMA channel, that is, before the configuration is completed, the transmitter DMA is in an inoperative state; then clear the TX-FIFO (Transmit First-In-First-Out) queue of I3C; then set the transmitter DMA transmission byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, and the transmitter DMA transmission byte length is greater than the maximum byte length of the EPL extended payload page; similarly, 2049 bytes can be set here; then modify the transmitter DMA source address based on the CMIS memory mapping address where the current communication error occurs; then enable the transmitter DMA channel and the transmitter DMA request; among them, modifying the transmitter DMA source address is specifically: modifying the transmitter DMA source address, which is based on the Management Memory map specified in the CMIS protocol, and the specific source address is the CMIS memory mapping address where the current communication error occurs. Enable the I3C controller to read out the data that caused a communication error during the previous "random read" operation during the next "current read" operation.

[0126] Configure and enable the I3C peripheral completion interrupt and configure the receiver DMA channel in the error interrupt of the I3C peripheral; the specific configuration of the receiver DMA channel includes: Before configuring the receiver DMA channel again, it is first necessary to disable the receiver DMA request and the receiver DMA channel, that is, before the configuration is completed, the receiver DMA is in an inoperative state; clear the RX-FIFO queue of I3C; set the receiver DMA reception byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, and the receiver DMA reception byte length is greater than the maximum byte length of the EPL extended payload page plus the register length of one byte; similarly, 2050 bytes can be set here; modify the destination address of the receiver DMA to the memory area in the RAM of the MCU of the optical module as the receive buffer; then enable the receiver DMA channel and the receiver DMA request.

[0127] Based on the above optical module working method, an optical module is also provided, and the working method of this optical module adopts the above optical module working method based on I3C communication.

[0128] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An optical module working method based on I3C communication, characterized in that: Methods include: The optical module MCU continuously monitors whether it has been assigned a dynamic address by the I3C controller by monitoring the dynamic address update interrupts generated by the I3C peripheral; When the dynamic address allocation is detected to be successful, the I3C peripheral, the receiving DMA channel bound to the I3C peripheral, and the transmitting DMA channel bound to the I3C peripheral are configured. After the configuration is completed, wait for the I3C controller to issue an operation instruction; when the operation instruction is received, the optical module MCU responds to the private read operation or private write operation initiated by the I3C controller.

2. The optical module working method based on I3C communication as claimed in claim 1, characterized in that: When the dynamic address allocation is detected to be successful, the I3C peripheral, the receiving DMA channel bound to the I3C peripheral, and the transmitting DMA channel bound to the I3C peripheral are configured, including enabling the I3C peripheral STOP interrupt to cooperate with the receiving DMA channel to receive the variable-length data sent by the I3C controller, and configuring the receiving DMA channel to respond to the DMA private write operation; Configuring the receiving DMA channel specifically includes: Set the source address of the receiving DMA to the I3C receive data register in the I3C peripheral; Set the destination address of the receiving end DMA to at least two memory areas in the RAM of the optical module MCU as the receiving buffer area; The receiving DMA receiving byte length is set based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receiving DMA receiving byte length> (the maximum byte length of the EPL extended payload page + one byte); Enable the receiving DMA channel; Enable receive DMA request.

3. The optical module working method based on I3C communication as claimed in claim 1, characterized in that: When the dynamic address allocation is detected to be successful, the I3C peripheral, the receiving DMA channel bound to the I3C peripheral, and the transmitting DMA channel bound to the I3C peripheral are configured, including enabling the I3C peripheral STOP interrupt to cooperate with the transmitting DMA channel to send variable-length data to the I3C controller, and configuring the transmitting DMA channel to respond to the DMA private read operation; Configuring the transmitting DMA channel specifically includes: Set the source address of the transmitting DMA to a memory area in the RAM of the optical module MCU as the sending buffer area; Set the destination address of the sending DMA to the I3C send data register in the I3C peripheral; The byte length of the DMA sent by the transmitting end is set based on the maximum byte length of the EPL extended load page in the CMIS protocol, wherein the byte length of the DMA sent by the transmitting end is greater than the maximum byte length of the EPL extended load page; Enable the transmitting DMA channel; Enable outgoing DMA requests.

4. The optical module working method based on I3C communication as claimed in claim 2, characterized in that: The working process of the private write is as follows: After the receiving end DMA is triggered, the received data is moved from the receiving end DMA source address to the receiving buffer area in the receiving end DMA destination address; when the private write data transmission is completed, the I3C peripheral STOP interrupt is generated based on the stop bit in the data to realize the receiving end DMA indefinite length data reception; Calculate the actual received data length in the I3C peripheral STOP interrupt; In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the transmitting DMA channel bound to the I3C peripheral so that the optical module responds to the next private read operation of the I3C controller; In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the receiving end DMA channel bound to the I3C peripheral so that the optical module responds to the next private write operation of the I3C controller; The data in the receive buffer is processed based on the management memory mapping in the CMIS protocol.

5. The optical module working method based on I3C communication as claimed in claim 3, characterized in that: The working process of the private read is as follows: After the sender DMA is triggered, the sender DMA moves the data from the currently configured sender DMA source address to the sender DMA destination address; when the private read data transmission is completed, the I3C peripheral STOP interrupt is generated based on the stop bit in the data to realize the sender DMA indefinite length data transmission; Calculate the actual length of the transmitted data in the STOP interrupt of the I3C peripheral; In the STOP interrupt of the I3C peripheral, configure the I3C peripheral and the transmitting DMA channel bound to the I3C peripheral so that the optical module responds to the next private read operation of the I3C controller; The data in the send buffer is processed based on the management memory mapping in the CMIS protocol.

6. The optical module working method based on I3C communication as claimed in claim 4, characterized in that: The configuration of the I3C peripheral and the receiving end DMA channel bound to the I3C peripheral is performed in the STOP interrupt of the I3C peripheral, so that the optical module responds to the next private write operation of the I3C controller, specifically including: Disable receiving end DMA request; Disable the receiving DMA channel; Clear the I3C RX-FIFO queue; The receiving DMA receiving byte length is set based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receiving DMA receiving byte length> (the maximum byte length of the EPL extended payload page + one byte); Modify the destination address of the receiving end DMA to the memory area in the RAM of the optical module's MCU as the receiving buffer area; Enable the receiving DMA channel; Enable receive DMA request.

7. The optical module working method based on I3C communication as described in claim 4 or 5, characterized in that: The configuration of the I3C peripheral and the transmitting DMA channel bound to the I3C peripheral is performed in the STOP interrupt of the I3C peripheral, so that the optical module responds to the next private read operation of the I3C controller, specifically including: Disable outgoing DMA requests; Disable the sending DMA channel; Clear the I3C TX-FIFO queue; The byte length of the DMA sent by the transmitting end is set based on the maximum byte length of the EPL extended load page in the CMIS protocol, wherein the byte length of the DMA sent by the transmitting end is greater than the maximum byte length of the EPL extended load page; Based on the optical module register address in the receiving buffer and the page mapping value of the 127th byte of the Lower Memory, the source address of the transmitting end is modified so that the optical module responds to the next current read operation; Enable the transmitting DMA channel; Enable outgoing DMA requests.

8. The optical module working method based on I3C communication as claimed in claim 6, characterized in that: The private write operation is based on a random write frame format, wherein the random write frame format is composed of a start bit, an optical module address, a write flag bit, an optical module response bit, an optical module register address, a first check bit, first data, a second check bit, ..., an Nth data bit, an N+1th check bit, and a stop bit.

9. The optical module working method based on I3C communication as claimed in claim 7, characterized in that: The private read operation is based on a random read frame format, wherein the random read frame format is sequentially composed of a start bit, an optical module address, a write flag bit, an optical module response bit, an optical module register address, a check bit, a repeated start bit, an optical module address, a read flag bit, an optical module response bit, a first data, a first end judgment bit, ..., an Nth data, an Nth end judgment bit, and a stop bit.

10. The optical module working method based on I3C communication as claimed in claim 7, characterized in that: The current read operation is based on the current read frame format, wherein the current read frame format is sequentially composed of a start bit, an optical module address, a read flag bit, an optical module response bit, a first data, a first end judgment bit, ..., an Nth data, an Nth end judgment bit, and a stop bit.

11. The optical module working method based on I3C communication according to any one of claims 1 to 5, characterized in that: It also includes an optical module communication error recovery method, as follows: When the I3C peripheral enters an error interrupt, the optical module MCU obtains and records the error source; Enable the I3C peripheral STOP interrupt in the I3C peripheral error interrupt and configure the DMA channel at the transmitting end; The transmitting end DMA channel configuration specifically includes: Disable the sender DMA request; disable the sender DMA channel; clear the I3C TX-FIFO queue; set the sender DMA send byte length based on the maximum byte length of the EPL extended load page in the CMIS protocol, where the sender DMA send byte length> the maximum byte length of the EPL extended load page; modify the sender DMA source address based on the CMIS memory mapping address of the current communication error; enable the sender DMA channel; enable the sender DMA request; In the error interrupt of the I3C peripheral, the I3C peripheral STOP interrupt is enabled and the receiving end DMA channel configuration is performed; the receiving end DMA channel configuration specifically includes: Disable the receiving DMA request; disable the receiving DMA channel; clear the I3C RX-FIFO queue; set the receiving DMA receiving byte length based on the maximum byte length of the EPL extended payload page in the CMIS protocol, where the receiving DMA receiving byte length > (the maximum byte length of the EPL extended payload page + one byte); modify the receiving DMA destination address to the memory area in the RAM of the optical module's MCU as the receiving buffer area; enable the receiving DMA channel; enable the receiving DMA request.

12. An optical module, characterized in that: The working method of the optical module adopts the working method of the optical module based on I3C communication according to any one of claims 1 to 11.

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