Optical module

Abstract

The invention provides an optical module, and belongs to the technical field of optical communication. The optical module comprises a circuit board and a plurality of golden fingers, the circuit board is electrically connected with the plurality of golden fingers, the plurality of golden fingers are located on the surface of the circuit board and close to the end portion of the circuit board, and the length direction of the plurality of golden fingers is the same as the insertion direction of the optical module inserted into the optical communication equipment. By adopting the optical module provided by the invention, the plurality of golden fingers can provide more pins, so that the optical module can be compatible with network equipment with various transmission rates.

Description

Technical Field

[0001] The present disclosure relates to the field of optical communication technology, and in particular to an optical module. Background Art

[0002] With the development of optical communication technology, in passive optical networks (PON), gigabit-capable PON (GPON) and 10Gigabit-capable PON (XGPON) can no longer meet the needs of future broadband business development, and passive optical networks are evolving towards higher transmission rates. For example, passive optical networks are evolving towards 50Gigabit-capable PON (50G PON).

[0003] When passive optical networks evolve towards higher transmission rates, it is inevitable that network devices with multiple transmission rates will coexist in the optical network, requiring optical modules to be compatible with network devices with multiple transmission rates. Summary of the invention

[0004] The present disclosure provides an optical module, which includes a plurality of gold fingers. The plurality of gold fingers can provide more pins, so that the optical module can be compatible with network devices with various transmission rates.

[0005] The present disclosure provides an optical module, which includes a circuit board and a plurality of gold fingers; the circuit board is electrically connected to the plurality of gold fingers; the plurality of gold fingers are located on the surface of the circuit board and close to the end of the circuit board, the plurality of gold fingers are flush with the end of the circuit board, and the length direction of the plurality of gold fingers is the same as the insertion direction of the optical module into an optical communication device.

[0006] In the solution shown in the present disclosure, the optical module includes multiple gold fingers, and the multiple gold fingers can provide more pins. More pins can support network devices with more transmission rates, so that the optical module can support network devices with more transmission rates.

[0007] In one example, the plurality of gold fingers include a first gold finger and a second gold finger, each of the first gold finger and the second gold finger includes 22 pins, the number of pins located on the top and bottom surfaces of the circuit board of the 22 pins of the first gold finger is the same, and the number of pins located on the top and bottom surfaces of the circuit board of the 22 pins of the second gold finger is the same. In this way, the number of pins of the gold finger is the same as the number of pins of the existing gold finger, so that the architecture of the gold finger does not need to be redesigned, simplifying the design.

[0008] In one example, the first golden finger and the second golden finger are used to support at least one of a Gigabit passive optical network, a 10 Gigabit passive optical network, and a 50 Gigabit passive optical network. In this way, the coexistence of three modes of passive optical networks can be supported.

[0009] In one example, the signal transmission pin of the 10 Gigabit passive optical network is located on the bottom surface of the circuit board, and the signal transmission pin includes the first pin and the second pin from the left of the first gold finger along the insertion direction, or the first pin and the second pin from the left of the second gold finger along the insertion direction. The position of the signal transmission pin is the same as the position of the signal transmission pin of the existing gold finger GPON, which simplifies the design.

[0010] In one example, the signal receiving pins of the 10 Gigabit passive optical network are located on the bottom surface of the circuit board, and the signal receiving pins include the seventh pin and the eleventh pin from the left along the insertion direction of the first gold finger, or the seventh pin and the eleventh pin from the left along the insertion direction of the second gold finger. The position of the signal receiving pin is the same as the position of the signal receiving pin of the existing gold finger GPON, which simplifies the design.

[0011] In one example, the signal transmission pins of the 50 Gigabit passive optical network include a first pair of signal transmission pins and a second pair of signal transmission pins of 25 Gigabit, the first pair of signal transmission pins and the second pair of signal transmission pins are both located on the top surface of the circuit board, the first pair of signal transmission pins include the second pin and the third pin from the left of the first gold finger along the insertion direction, and the second pair of signal transmission pins include the second pin and the third pin from the left of the second gold finger along the insertion direction. Two pairs of 25 Gigabit signal transmission pins are used to achieve 50G transmission, and the position of the signal transmission pins is the same as that of the signal transmission pins of the existing gold finger 10G PON, which simplifies the design.

[0012] In one example, the 50 Gigabit passive optical network is a symmetrical passive optical network, and the signal receiving pins of the 50 Gigabit passive optical network include a first pair of 25 Gigabit signal receiving pins and a second pair of signal receiving pins, the first pair of signal receiving pins and the second pair of signal receiving pins are both located on the top surface of the circuit board, the first pair of signal receiving pins include the eighth pin and the ninth pin from the left of the first gold finger along the insertion direction, and the second pair of signal receiving pins include the eighth pin and the ninth pin from the left of the second gold finger along the insertion direction. Two pairs of 25 Gigabit signal receiving pins are used to achieve 50G reception, and the position of the signal receiving pins is the same as that of the signal receiving pins of the existing gold finger 10G PON, simplifying the design.

[0013] In one example, the 50 Gigabit passive optical network is a symmetric passive optical network, and the control or indication pins of the 50 Gigabit passive optical network include a reset pin, a signal check pin and a rate selection pin, the reset pin and the signal check pin are both located on the bottom surface of the circuit board, the rate selection pin is located on the top surface of the circuit board, the reset pin is the eighth pin from the left of the first golden finger or the second golden finger along the insertion direction, the signal check pin is the ninth pin from the left of the first golden finger or the second golden finger along the insertion direction, and the rate selection pin is the eleventh pin from the left of the first golden finger or the second golden finger along the insertion direction. The position of the control or indication pin is the same as that of the control or indication pin of the existing golden finger 10GPON, which simplifies the design.

[0014] In one example, the 50 Gigabit passive optical network is an asymmetric passive optical network, and the signal receiving pins of the 50 Gigabit passive optical network include a pair of 25 Gigabit signal receiving pins, and the pair of signal receiving pins include the eighth pin and the ninth pin from the left of the first gold finger along the insertion direction, or the eighth pin and the ninth pin from the left of the second gold finger along the insertion direction. The position of the signal receiving pin is the same as the position of the signal receiving pin of the existing gold finger 10G PON, which simplifies the design.

[0015] In one example, the 50 Gigabit passive optical network is an asymmetric passive optical network, and the control or indication pin of the 50 Gigabit passive optical network includes a reset pin and a signal check pin, the reset pin and the signal check pin are both located on the bottom surface of the circuit board, the reset pin is the eighth pin from the left of the first gold finger or the second gold finger along the insertion direction, and the signal check pin is the ninth pin from the left of the first gold finger or the second gold finger along the insertion direction. The position of the control or indication pin is the same as that of the control or indication pin of the existing gold finger 10G PON, simplifying the design.

[0016] In one example, the spacing between the multiple gold fingers matches the spacing between the multiple connectors of the optical communication device, so that the multiple gold fingers are inserted into the multiple connectors of the optical communication device. In this way, the multiple gold fingers of the optical module are adapted to the existing multiple connectors without changing the structure of the multiple connectors of the optical communication device.

[0017] In an example, the optical module further includes an optical device and an electrical chip, the optical device is electrically connected to the electrical chip, and the electrical chip is electrically connected to the plurality of gold fingers through the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a PON provided by an exemplary embodiment of the present disclosure;

[0019] Figure 2This is a schematic diagram of the arrangement of gold fingers in the next generation small form factor pluggable (NGSFP);

[0020] Figure 3 is a schematic diagram of the structure of an optical module provided by an exemplary embodiment of the present disclosure;

[0021] Figure 4 is a schematic diagram of the structure of an optical module provided by an exemplary embodiment of the present disclosure;

[0022] Figure 5 is a schematic diagram of the structure of an optical module provided by an exemplary embodiment of the present disclosure;

[0023] Figure 6 It is a schematic diagram of the pin arrangement in the gold finger of DSFP provided by an exemplary embodiment of the present disclosure;

[0024] Figure 7 It is a schematic diagram of the pin arrangement of a gold finger provided by an exemplary embodiment of the present disclosure;

[0025] Figure 8 It is a schematic diagram of the pin arrangement of a gold finger provided by an exemplary embodiment of the present disclosure;

[0026] Fig. 9 It is a schematic diagram of the pin arrangement of the gold finger provided by an exemplary embodiment of the present disclosure.

[0027] Illustration

[0028] 1. Circuit board; 2. Gold finger; 3. Optical device; 4. Electric chip;

[0029] 31. Sub-optical devices; 32. Wavelength division multiplexing (WDM) devices;

[0030] 41. Sub-chip; 5. Optical digital signal processing (ODSP) device. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0032] In the field of optical communications, the packaging format of optical modules in passive optical networks is 10G small form-factor pluggable optical modules (10Gigabit small form-factor pluggable, SPF+), also known as dual small form-factor pluggable optical modules (dual small form-factor pluggable, DSFP). The transmission rate of optical modules with this packaging format has been increased from 2.5Gbps to 10Gbps, and supports the coexistence of 2.5G PON and XG PON modes. With the evolution of optical communication technology, optical modules are evolving towards high transmission rates, large bandwidths, and miniaturization. During the evolution process, it is inevitable that network devices with multiple transmission rates coexist in optical networks, which requires optical modules to be compatible with network devices with multiple transmission rates. For example, Figure 1 A schematic diagram of PON is provided, see Figure 1 In PON, the optical line terminal (OLT) is connected to multiple optical network units (ONUs) through a passive optical splitter. The multiple ONUs include 50G PON network equipment, XG PON network equipment and GPON network equipment. Therefore, the optical module supports 50G PON and supports the coexistence of 50G PON, XG PON and GPON, which has become a problem that needs to be solved. Before solving this problem, we must first solve the problem that the gold finger in the optical module supports 50GPON, XG PON and GPON. Among them, the gold finger is composed of multiple golden conductive contacts. Because its surface is gold-plated and the conductive contacts are arranged like fingers, it is called a gold finger. The conductive contact is a relatively thin metal sheet, called a pin or a pin.

[0033] Figure 1 In the Internet, OLT is connected to the Public Switched Telephone Network (PSTN), the Internet and community antenna television (CATV) to provide data transmission services.

[0034] At present, compared with DSFP, the package size of NGSFP has not changed much. The gold finger adds two rows of pins along the insertion direction of the optical communication equipment. The two rows of pins are located on the top and bottom of the printed circuit board (PCB), respectively, referred to as the top of the board and the bottom of the board. The number of gold finger pins has increased from 22 to 44, which can support the coexistence of 50G PON, XG PON and GPON modes. Figure 2 A schematic diagram of the layout of the gold fingers on the printed circuit board is provided. In this way, the number of pins of NGSFP increases, and the space occupied becomes more, while the package size does not change significantly compared to SFP+, so the space reserved for the layout of optical devices and ODSP devices in the optical module is small, and the implementation is difficult. Optical devices include photoelectric conversion devices and electro-optical conversion devices.

[0035] Among them, the printed circuit board is referred to as the circuit board for short, the top surface of the circuit board refers to the surface of the circuit board seen from top to bottom when the optical module is inserted into the optical communication equipment, and the bottom surface of the circuit board refers to the surface of the circuit board seen from bottom to top when the optical module is inserted into the optical communication equipment.

[0036] The optical module in the embodiment of the present disclosure may be any one of an optical receiving module, an optical transmitting module and an integrated optical transceiver module. The following description will be made by taking the optical module as an integrated optical transceiver module as an example.

[0037] Figure 3 Provides a schematic diagram of the optical module structure. Figure 3 The optical module includes a circuit board 1, a plurality of gold fingers 2, an optical device 3 and an electrical chip 4.

[0038] Among them, the circuit board 1 is electrically connected with multiple gold fingers 2. Multiple gold fingers 2 are located on the surface of the circuit board 1 and close to the end of the circuit board 1. Multiple gold fingers 2 are flush with the end of the circuit board 1 (equivalent to the multiple gold fingers 2 being at the same distance from the end after being projected onto the circuit board 1). The end is the end of the optical module inserted into the optical communication device. Specifically, the pins in the multiple gold fingers 2 are respectively located on the top and bottom surfaces of the circuit board 1. The length direction of the multiple gold fingers 2 is the same as the insertion direction of the optical module into the optical communication device. After the optical module is inserted into the optical communication device, it is electrically connected to the optical communication device through multiple gold fingers 2.

[0039] The optical device 3 is used to convert optical signals into electrical signals, and to convert electrical signals into optical signals. One end of the optical device 3 is electrically connected to the electrical chip 4, and the other end is connected to the transmission optical fiber connected to the optical module.

[0040] The electric chip 4 is electrically connected to the circuit board 1. For example, the electric chip 4 is integrated on the circuit board 1, and the electric chip 4 is electrically connected to the plurality of gold fingers 2 through the circuit board 1. The electric chip 4 is used to process the electric signal, such as amplifying it.

[0041] During the signal transmission process, the optical module receives the electrical signal sent by the optical communication device through the gold finger 2, the electrical chip 4 processes the electrical signal and transmits it to the optical device 3, and the optical device 3 converts the electrical signal into an optical signal and transmits it through the connected transmission optical fiber.

[0042] During the signal reception process, the optical module receives the optical signal through the connected transmission optical fiber, the optical device 3 converts the optical signal into an electrical signal, the electrical chip 4 processes the electrical signal and transmits it to the gold finger 2, and the gold finger 2 transmits the electrical signal to the optical communication device.

[0043] exist Figure 3 In the optical module shown, the optical module includes a plurality of gold fingers 2 , and the number of pins in the optical module is increased, so that it can support multiple modes of PON and is compatible with a single mode of PON.

[0044] In one example, when the optical module supports multiple modes of PON, the optical device 3 includes multiple sub-optical devices 31 and a wavelength division multiplexing device 32. Each mode of PON corresponds to a sub-optical device 31, which is used to support the photoelectric conversion of the PON of that mode. The WDM device 32 is used to merge the optical signals of the PONs of multiple modes into one optical signal, output from the transmission optical fiber connected to the optical module, and divide the optical signal received upstream into optical signals of the PONs of multiple modes, and transmit them to multiple sub-optical devices 31, see Figure 4 The structural diagram of the optical module is shown.

[0045] In one example, when the optical module supports multiple modes of PON, the electrical chip 4 includes multiple sub-chips 41, which correspond to the multiple modes of PON one by one, that is, the multiple sub-chips 41 include a 50G PON sub-chip 41, a 10G PON sub-chip 41, and a GPON sub-chip 41, see Figure 4 The structural diagram of the optical module is shown.

[0046] In one example, since the transmission rate of 50G PON is high and the digital signal processing is complex, an ODSP can be separately set in the optical module. Then, when the optical module supports 50G PON, the optical module also includes an ODSP5, which is set between the sub-chip 41 of the 50G PON and the gold finger 2 to process complex digital signals so that the signal quality is better. Figure 4 The structural diagram of the optical module is shown.

[0047] In one example, in order to keep the appearance structure of the connector of the optical communication device unchanged, the spacing between the plurality of gold fingers 2 is matched with the spacing between the plurality of connectors of the optical communication device, so that the plurality of gold fingers 2 can be inserted into the plurality of connectors, and the plurality of gold fingers 2 correspond to the plurality of connectors one by one. Figure 5 The schematic diagram of the optical module corresponding to the connector of the optical communication device shown, the multiple gold fingers 2 include a first gold finger and a second gold finger, the optical communication device illustrates two connectors, the spacing between the first gold finger and the second gold finger is a first spacing, the spacing between the slots in the two connectors into which the first gold finger and the second gold finger are inserted is a second spacing, the first spacing is the same as the second spacing, so that when the first gold finger is inserted into the left connector, the second gold finger is simultaneously inserted into the right connector.

[0048] use Figure 5 The optical module shown enables the optical communication device to be flexibly plugged in. For example, the optical communication device includes 8 connectors, and the optical communication device can be plugged in 2 optical modules of the embodiment of the disclosure, and can also be plugged in 4 optical modules including a single gold finger 2 .

[0049] In one example, the plurality of gold fingers 2 include two gold fingers 2, namely, a first gold finger and a second gold finger, and the first gold finger and the second gold finger each include 22 pins. Eleven pins of the first gold finger are located on the top surface of the circuit board 1, and the other 11 pins are located on the bottom surface of the circuit board 1. Eleven pins of the second gold finger are located on the top surface of the circuit board 1, and the other 11 pins are located on the bottom surface of the circuit board 1. Figure 5 Provides two schematic diagrams of gold fingers, Figure 5 In the figure, the first gold finger is on the left side of the second gold finger. This is just an example. The first gold finger can also be on the right side of the second gold finger. The top surface of the circuit board 1 refers to the surface of the circuit board 1 seen from top to bottom when the optical module is inserted into the optical communication device, and the bottom surface of the circuit board 1 refers to the surface of the circuit board 1 seen from bottom to top when the optical module is inserted into the optical communication device.

[0050] In an example, when the plurality of golden fingers 2 include a first golden finger and a second golden finger, the pins of the first golden finger and the second golden finger can support at least one of GPON, XG PON and 50G PON. For example, the first golden finger and the second golden finger support GPON, XG PON and 50G PON. For another example, the first golden finger and the second golden finger support GPON and XGPON. For another example, the first golden finger and the second golden finger support GPON and 50G PON.

[0051] In one example, when the first gold finger and the second gold finger include 22 gold fingers, the first gold finger and the second gold finger are equivalent to the gold finger of DSFP, and the pin positions of the three gold fingers are arranged in the same way. In DSFP, the gold finger can support XG PON and GPON. For the pin arrangement in the gold finger, see Figure 6 .exist Figure 6 In the figure, along the insertion direction, the 1st to 11th pins of the gold finger are arranged from left to right on the bottom surface of the circuit board, and the 12th to 22nd pins are arranged from right to left on the top surface of the circuit board. Table 1 gives the names and meanings of each pin.

[0052] Table 1

[0053]

[0054]

[0055] In Table 1, when XG PON is a symmetric passive optical network, the transmission rate of upstream and downstream transmission is 10Gbps, and the transmission rate that is compatible with upstream transmission is 2.5Gbps. The 12th pin is a rate selection pin, which is used to select whether the transmission rate of upstream transmission is 2.5Gbps or 10Gbps. The two upstream transmission rates work in a time-division manner. When XG PON is a symmetric passive optical network, it is expressed as a 10-Gigabit symmetric passive optical network (10-Gigabit symmetric PON, XGS PON). When XG PON is an asymmetric passive optical network, the transmission rate of upstream transmission is 2.5Gbps, and the transmission rate of downstream transmission is 10Gbps. The 12th pin is an unconnected pin, also known as an undefined pin. Figure 1 In the scenario shown, upstream transmission refers to transmission from the ONU to the OLT, and downstream transmission refers to transmission from the OLT to the ONU.

[0056] In the disclosed embodiment, in order to support the coexistence of three modes of PON, namely GPON, XG PON and 50G PON, the optical module defines the pins of the first golden finger and the second golden finger. Since the number and position arrangement of the pins of the first golden finger, the second golden finger and the golden finger in DSFP are the same, and the golden finger in DSFP supports GPON and XG PON, it can be considered that some pins of the first golden finger and the second golden finger are redefined so that the first golden finger and the second golden finger can also support 50G PON.

[0057] When defining the pins of the first gold finger and the second gold finger, the pins required for the symmetric passive optical network and the asymmetric passive optical network are different. Therefore, when describing the pin definition below, the symmetric passive optical network and the asymmetric passive optical network are explained separately. Here, the symmetric passive optical network and the asymmetric passive optical network are for 50G PON. When 50G PON is a symmetric passive optical network, the transmission rate of the upstream transmission and the downstream transmission are both 50Gbps, and the transmission rate of the upstream transmission is also compatible with 25Gbps. When 50G PON is an asymmetric passive optical network, the transmission rate of the upstream transmission is 25Gbps, and the transmission rate of the downstream transmission is 50Gbps.

[0058] Before defining the pins of the first and second gold fingers, the pins in the first and second gold fingers are first numbered, and the 22 pins included in the first gold finger are numbered from 1 to 22, and the 22 pins included in the second gold finger are numbered from 1 to 22. Along the insertion direction, the first to 11th pins of the first gold finger are arranged from left to right on the bottom surface of the circuit board 1, and the 12th to 22nd pins are arranged from right to left on the top surface of the circuit board 1. Along the insertion direction, the first to 11th pins of the second gold finger are arranged from left to right on the bottom surface of the circuit board 1, and the 12th to 22nd pins are arranged from right to left on the top surface of the circuit board 1.

[0059] 1. Symmetric passive optical network.

[0060] In a symmetric passive optical network, the first golden finger and the second golden finger include a 50G PON signal transmission pin and a signal receiving pin as well as a 50G PON control or indication pin. There are many ways to define the pins of the first golden finger and the second golden finger, and three optional ways are given below.

[0061] a) The first definition, see Figure 7 Provided schematic diagram of the gold finger pin arrangement.

[0062] a1. Signal transmission pin of 50G PON.

[0063] The signal transmission pins include two pairs of 25G signal transmission pins, namely the first pair of signal transmission pins and the second pair of signal transmission pins. The first pair of signal transmission pins and the second pair of signal transmission pins each include two pins, one of the two pins is used to transmit the positive signal of 25G, and the other pin is used to transmit the negative signal of 25G, which are respectively represented as 25G_TX+ and 25G_TX-. The two pairs of 25G signal transmission pins can transmit a total of 50G signals.

[0064] The first pair of signal transmitting pins and the second pair of signal transmitting pins are both located on the top surface of the circuit board 1. The first pair of signal transmitting pins includes the second pin and the third pin from the left of the first gold finger along the insertion direction. The second pair of signal transmitting pins includes the second pin and the third pin from the left of the second gold finger along the insertion direction. The second pin is 25G_TX-, and the third pin is 25G_TX+. In this case, it is equivalent to speeding up XG_TX+ in DSFP to 25G_TX+, and speeding up XG_TX- to 25G_TX-. When speeding up, signal simulation can be used to obtain it.

[0065] It should be noted that “the i-th pin from the left” refers to the i-th pin arranged from left to right along the insertion direction, which will not be described in detail in the following text.

[0066] a2, 50G PON signal receiving pin.

[0067] The signal receiving pins include two pairs of 25G signal receiving pins, namely the first pair of signal receiving pins and the second pair of signal receiving pins. The first pair of signal receiving pins and the second pair of signal receiving pins each include two pins, one of the two pins is used to receive the positive signal of 25G, and the other pin is used to receive the negative signal of 25G, which are represented as 25G_RX+ and 25G_RX- respectively. The two pairs of 25G signal receiving pins can receive a total of 50G signals.

[0068] The first pair of signal receiving pins and the second pair of signal receiving pins are both located on the top surface of the circuit board 1. The first pair of signal receiving pins includes the third pin and the fourth pin from the right of the first gold finger along the insertion direction. The second pair of signal receiving pins includes the third pin and the fourth pin from the right of the second gold finger along the insertion direction. The third pin is 25G_RX-, and the fourth pin is 25G_RX+. In this case, it is equivalent to speeding up XG_RX+ in DSFP to 25G_RX+, and speeding up XG_RX- to 25G_RX-. When speeding up, signal simulation can be used to obtain it.

[0069] It should be noted that “the i-th pin from the right” refers to the i-th pin arranged from right to left along the insertion direction, which will not be described in detail in the following text.

[0070] a3, 50G PON control or indication pin.

[0071] The control or indication pins include a reset pin, a signal check pin and a rate selection pin. The reset pin is represented as 50G_Reset, the signal check pin is represented as 50G_SD, and the rate selection pin is represented as 50G_Rate_sel.

[0072] The reset pin is used to control the reset of the 50G sub-chip 41, and the signal check pin is used to check whether the 50GPON optical signal is received. The rate selection pin is used to select the transmission rate (i.e., the receiving rate) of the uplink transmission, and select whether the receiving rate is 25Gbps or 50Gbps. The two receiving rates work in a time-division manner.

[0073] The reset pin and the signal check pin are both located on the bottom surface of the circuit board 1. The reset pin is the fourth pin from the right of the first gold finger along the insertion direction, or the reset pin is the fourth pin from the right of the second gold finger along the insertion direction.

[0074] The signal check pin is the third pin from the right of the first gold finger along the insertion direction, or the signal check pin is the third pin from the right of the second gold finger along the insertion direction.

[0075] The rate selection pin is located on the top surface of the circuit board 1. The rate selection pin is the first pin from the right of the first gold finger along the insertion direction, or the rate selection pin is the first pin from the right of the second gold finger along the insertion direction.

[0076] This is equivalent to upgrading XG_Reset to 50G_Reset, upgrading XG_SD to 50G_SD, and upgrading XG Rate_sel to 50G_Rate_sel.

[0077] a4, XG PON signal transmission pin.

[0078] The signal transmission pin includes two pins, one of which is used to transmit a positive signal of 10G PON, and the other pin is used to transmit a negative signal of 10G PON, which are respectively represented as XG_TX+ and XG_TX-.

[0079] The signal transmitting pin is located on the bottom surface of the circuit board 1. The signal transmitting pin includes the first pin and the second pin from the left of the first gold finger along the insertion direction. Alternatively, the signal transmitting pin includes the first pin and the second pin from the left of the second gold finger along the insertion direction. The first pin is XG_TX+ and the second pin is XG_TX-. In this case, since the original XG_TX+ is accelerated to 25G_TX+ and the original XG_TX- is accelerated to 25G_TX-, G_TX+ and G_TX- need to be accelerated to XG_TX+ and XG_TX-. Therefore, it is equivalent to speeding up G_TX+ in DSFP to XG_TX+ and speeding up G_TX- to XG_TX-. When speeding up, signal simulation can be used to obtain it.

[0080] a5, XG PON signal receiving pin.

[0081] The signal receiving pin includes two pins, one of which is used to receive a positive signal of the 10G PON, and the other pin is used to receive a negative signal of the 10G PON, which are respectively represented as XG_RX+ and XG_RX-.

[0082] The signal receiving pins are located on the bottom surface of the circuit board 1. The signal receiving pins include the first pin and the fifth pin from the right of the first gold finger along the insertion direction. Alternatively, the signal receiving pins include the first pin and the fifth pin from the right of the second gold finger along the insertion direction. The first pin is XG_RX+, and the fifth pin is XG_RX-. In this case, since the original XG_RX+ is accelerated to 25G_RX+, and the original XG_RX- is accelerated to 25G_RX-, G_RX+ and G_RX- need to be accelerated to XG_RX+ and XG_RX- respectively. Therefore, it is equivalent to speeding up G_RX+ in DSFP to XG_RX+, and speeding up G_RX- to XG_RX-. When speeding up, signal simulation can be used to obtain it.

[0083] When the pins are defined in the first manner, the definitions of the pins in the first gold finger and the second gold finger refer to Table 2.

[0084] Table 2

[0085]

[0086]

[0087] It can be seen from Table 2 that in a symmetric passive optical network, only some pins of the first golden finger and the second golden finger are redefined, which can simplify the definition process.

[0088] It should be noted that there are two G_SD in Table 2, one of which can be set to a null pin. Figure 7 This is only an example, and there may be other definition methods, for example, setting the 50G control or indication pins in the same gold finger.

[0089] The above is to upgrade the relevant pins of 10G PON to the pins of 50G PON. In another way, the relevant pins of GPON can also be upgraded to the pins of 50G PON. For example, the signal transmission pins of GPON are upgraded to the signal transmission pins of 50G PON.

[0090] b) The second definition.

[0091] b1, 50G PON signal transmission pin.

[0092] The signal transmission pin includes two pins, one of which is used to transmit a positive signal of 50G PON, and the other pin is used to transmit a negative signal of 50G PON, which are respectively represented as 50G_TX+ and 50G_TX-.

[0093] The two pins are both located on the top surface of the circuit board 1. The two pins include the second pin and the third pin from the left of the first gold finger along the insertion direction, or include the second pin and the third pin from the left of the second gold finger along the insertion direction, the second pin is 50G_TX-, and the third pin is 50G_TX+. In this case, it is equivalent to speeding up one XG_TX+ in the DSFP to 50G_TX+, and speeding up one XG_TX- to 50G_TX-. When speeding up, signal simulation can be used to obtain it. Set another XG_TX+ and another XG_TX- to empty pins. Alternatively, keep another XG_TX+ and another XG_TX-, and set one G_TX+ and one G_TX- in the first gold finger and the second gold finger to empty pins.

[0094] b2, 50G PON signal receiving pin.

[0095] The signal receiving pin includes two pins, one of which is used to receive a positive signal of 50G PON, and the other pin is used to receive a negative signal of 50G PON, which are respectively represented as 50G_RX+ and 50G_RX-.

[0096] The two pins are both located on the top surface of the circuit board 1. The two pins include the third pin and the fourth pin from the right of the first gold finger along the insertion direction, or include the third pin and the fourth pin from the right of the second gold finger along the insertion direction, the fourth pin is 50G_RX+, and the third pin is 50G_RX-. In this case, it is equivalent to speeding up one XG_RX+ in the DSFP to 50G_RX+, and speeding up one XG_RX- to 50G_RX-. When speeding up, signal simulation can be used to obtain it. Set another XG_RX+ and another XG_RX- to empty pins. Alternatively, keep another XG_RX+ and another XG_RX-, and set one G_RX+ and one G_RX- in the first gold finger and the second gold finger to empty pins.

[0097] For the definitions of the remaining pins, refer to the first definition method.

[0098] When the pins are defined in the second manner, the definitions of the pins in the first gold finger and the second gold finger refer to Table 3.

[0099] Table 3

[0100]

[0101]

[0102] It can be seen from Table 3 that in a symmetric passive optical network, only some pins of the first golden finger and the second golden finger are redefined, which can simplify the definition process.

[0103] It should be noted that the above-mentioned symmetric passive optical network is for 50G PON. For 10G PON, it can be an asymmetric passive optical network (the transmission rate of upstream transmission is 2.5Gbps, and the transmission rate of downstream transmission is 10Gbps), or it can be a symmetric passive optical network (the upstream transmission rate and the downstream transmission rate are both 10Gbps). Tables 2 and 3 give examples of 10GPON being a symmetric passive optical network, and the 12th pin in the first gold finger is set to the rate selection pin of 10G PON. In another example, when 10G PON is an asymmetric passive optical network, the 12th pin in the first gold finger can also be set to NC.

[0104] c) The third definition.

[0105] Without referring to the definition of the gold finger in DSFP, the pins in the first gold finger and the second gold finger are directly defined to support the coexistence of three modes of PON. The third definition method can be understood as the position rearrangement of the pins with various meanings in the first definition method or the second definition method.

[0106] 2. Asymmetric passive optical network.

[0107] In an asymmetric passive optical network, the first gold finger and the second gold finger include the signal transmission pin and the signal receiving pin of the 50G PON and the control or indication pin of the 50G PON. Two definition methods are provided below.

[0108] a) The first definition, see Figure 8 and Fig. 9 The pin layout diagram of the gold finger is provided. Figure 8 Corresponding to Table 4, Fig. 9 Corresponding Table 5.

[0109] a1. Signal transmission pin of 50G PON.

[0110] The signal transmission pins of 50G PON in the asymmetric passive optical network are the same as those of 50G PON in the symmetric passive optical network, and are not described here.

[0111] a2, 50G PON signal receiving pin.

[0112] In an asymmetric passive optical network, a 25G signal is received upstream, so the signal receiving pin includes a pair of 25G signal receiving pins. The pair of signal receiving pins includes two pins, one of the two pins is used to receive a positive signal of 25G, and the other pin is used to receive a negative signal of 25G, which are respectively represented as 25G_RX+ and 25G_RX-.

[0113] The pair of signal receiving pins are both located on the top surface of the circuit board 1. The pair of signal receiving pins includes the third pin and the fourth pin from the right of the first gold finger along the insertion direction. Or the pair of signal receiving pins includes the third pin and the fourth pin from the right of the second gold finger along the insertion direction. The fourth pin is 25G_RX+, and the third pin is 25G_RX-. In this case, it is equivalent to speeding up XG_RX+ in DSFP to 25G_RX+, and speeding up XG_RX- to 25G_RX-. When speeding up, signal simulation can be used to obtain it.

[0114] a3, 50G PON control or indication pin.

[0115] The control or indication pins include a reset pin and a signal check pin, the reset pin is represented by 50G_Reset, and the signal check pin is represented by 50G_SD. The reset pin is used to control the reset of the electrical chip of the 50G PON, and the signal check pin is used to check whether the optical signal is received.

[0116] The reset pin and the signal check pin are both located on the bottom surface of the circuit board 1. The reset pin and the signal check pin can be both located on the first golden finger, can be both located on the second golden finger, or can be located on the first golden finger and the second golden finger respectively.

[0117] Exemplarily, the reset pin is the fourth pin from the right of the first gold finger along the insertion direction, or the reset pin is the fourth pin from the right of the second gold finger along the insertion direction.

[0118] The signal check pin is the third pin from the right of the first gold finger along the insertion direction, or the signal check pin is the third pin from the right of the second gold finger along the insertion direction.

[0119] This is equivalent to upgrading XG_Reset to 50G_Reset and upgrading XG_SD to 50G_SD.

[0120] a4, XG PON signal transmission pin.

[0121] The signal transmission pin includes two pins, one of which is used to transmit a positive signal of 10G PON, and the other pin is used to transmit a negative signal of 10G PON, which are respectively represented as XG_TX+ and XG_TX-.

[0122] The signal transmitting pin is located on the bottom surface of the circuit board 1. The signal transmitting pin includes the first pin and the second pin from the left of the first gold finger along the insertion direction. Alternatively, the signal transmitting pin includes the first pin and the second pin from the left of the second gold finger along the insertion direction. The first pin is XG_TX+ and the second pin is XG_TX-. In this case, since the original XG_TX+ is accelerated to 25G_TX+ and the original XG_TX- is accelerated to 25G_TX-, G_TX+ and G_TX- need to be accelerated to XG_TX+ and XG_TX-. Therefore, it is equivalent to speeding up G_TX+ in DSFP to XG_TX+ and speeding up G_TX- to XG_TX-. When speeding up, signal simulation can be used to obtain it.

[0123] a5, XG PON signal receiving pin.

[0124] The signal receiving pin includes two pins, one of which is used to receive a positive signal of the 10G PON, and the other pin is used to receive a negative signal of the 10G PON, which are respectively represented as XG_RX+ and XG_RX-.

[0125] The signal receiving pins are located on the bottom surface of the circuit board 1. The signal receiving pins include the first pin and the fifth pin from the right of the first gold finger along the insertion direction. Alternatively, the signal receiving pins include the first pin and the fifth pin from the right of the second gold finger along the insertion direction. The first pin is XG_RX+, and the fifth pin is XG_RX-. In this case, since the original XG_RX+ is accelerated to 25G_RX+, and the original XG_RX- is accelerated to 25G_RX-, G_RX+ and G_RX- need to be accelerated to XG_RX+ and XG_RX-. Therefore, it is equivalent to speeding up G_RX+ in DSFP to XG_RX+, and speeding up G_RX- to XG_RX-. When speeding up, signal simulation can be used to obtain it.

[0126] Alternatively, the signal receiving pin is located on the top surface of the circuit board 1. The signal receiving pin includes the third pin and the fourth pin from the right of the first gold finger along the insertion direction. Alternatively, the signal receiving pin includes the third pin and the fourth pin from the right of the second gold finger along the insertion direction. The fourth pin is XG_RX+, and the third pin is XG_RX-. In this case, it is equivalent to using XG_RX+ in DSFP as XG_RX+ in the embodiment of the present disclosure, and using XG_RX- in DSFP as XG_RX- in the embodiment of the present disclosure. It should be noted that in this case, both the first gold finger and the second gold finger include G_RX+ and G_RX-, so G_RX+ and G_RX- in the first gold finger or the second gold finger can be made into empty pins, or upgraded to XG_RX+ and XG_RX for redundant backup.

[0127] When the pins are defined in the first manner, the definitions of the pins in the first gold finger and the second gold finger refer to Table 4 and Table 5.

[0128] Table 4

[0129]

[0130]

[0131] In Table 4, there are two pairs of 10G PON signal receiving pins, which can be considered as redundant backup. The 14th and 15th pins in the second gold finger can also be accelerated to 25G_RX- and 25G_RX+ respectively, and the 14th and 15th pins in the first gold finger are redundant backups.

[0132] Table 5

[0133]

[0134] It can be seen from Table 4 and Table 5 that in an asymmetric passive optical network, only some pins of the first golden finger and the second golden finger are redefined, which can simplify the definition process.

[0135] It should be noted that the above-mentioned asymmetric passive optical network is for 50G PON. For 10G PON, it can be an asymmetric passive optical network or a symmetric passive optical network. Tables 4 and 5 give examples of 10G PON being a symmetric passive optical network, in which the 12th pin in the first gold finger is set to the rate selection pin of 10G PON, and the 12th pin in the second gold finger is set to NC. In another example, the 12th pin in the second gold finger can also be set to the rate selection pin of 10G PON, and the 12th pin in the first gold finger can be set to NC.

[0136] b) The second definition.

[0137] b1, 50G PON signal transmission pin.

[0138] The signal transmission pin includes two pins, one of which is used to transmit a positive signal of 50G PON, and the other pin is used to transmit a negative signal of 50G PON, which are respectively represented as 50G_TX+ and 50G_TX-.

[0139] The two pins are both located on the top surface of the circuit board 1. The two pins include the second pin and the third pin from the left of the first gold finger along the insertion direction, or include the second pin and the third pin from the left of the second gold finger along the insertion direction, the second pin is 50G_TX-, and the third pin is 50G_TX+. In this case, it is equivalent to speeding up one XG_TX+ in the DSFP to 50G_TX+, and speeding up one XG_TX- to 50G_TX-. When speeding up, signal simulation can be used to obtain it. Set another XG_TX+ and another XG_TX- to empty pins. Alternatively, keep another XG_TX+ and another XG_TX-, and set one G_TX+ and one G_TX- in the first gold finger and the second gold finger to empty pins.

[0140] For the definitions of the remaining pins, refer to the first definition method.

[0141] c) The third definition.

[0142] Without referring to the gold finger in DSFP, the pins in the first gold finger and the second gold finger are directly defined to support the coexistence of three modes of PON. The third definition method can be understood as the position rearrangement of the pins with various meanings in the first definition method or the second definition method.

[0143] It should be noted that in symmetric passive optical networks and asymmetric passive optical networks, downlink transmission adopts the form of broadcasting, and uplink transmission adopts the mode of time division multiple access (TDMA).

[0144] It should also be noted that the definition of the pins in the connector in the optical communication device will also be updated to adapt to the optical module in the embodiment of the present disclosure.

[0145] In the disclosed embodiment, a new pin layout method is provided to solve the problem of insufficient number of single gold finger pins, which can not only support 50G PON, but also be backward compatible with 10G PON and GPON.

[0146] In addition, the optical module in the embodiment of the present disclosure can be plugged into the optical communication device together with the original DSFP, without upgrading the optical communication device, to achieve smooth system upgrade. For example, the optical communication device includes 16 connectors, and the 16 connectors can be plugged into 16 DSFPs. When the optical module includes two gold fingers, 8 optical modules provided by the embodiment of the present disclosure can be plugged in.

[0147] In addition, by using the packaging size advantage of the gold finger provided by the embodiment of the present disclosure, there is space to accommodate optical devices and ODSP, so that ODSP is integrated in the optical module and the signal quality is better.

[0148] In the present disclosure, the terms "first" and "second" and the like are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first and second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first golden finger may be referred to as the second golden finger, and similarly, the second golden finger may be referred to as the first golden finger. Both the first golden finger and the second golden finger may be golden fingers, and in some cases, may be separate and different golden fingers.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An optical module, characterized in that: The optical module comprises a circuit board (1) and a plurality of gold fingers (2); The circuit board (1) is electrically connected to the plurality of gold fingers (2); The plurality of gold fingers (2) are located on the surface of the circuit board (1) and close to the end of the circuit board (1); The plurality of gold fingers (2) are flush with the ends of the circuit board (1); The length direction of the plurality of gold fingers (2) is the same as the insertion direction of the optical module into the optical communication device.

2. The optical module according to claim 1, characterized in that: The plurality of golden fingers (2) include a first golden finger and a second golden finger; The first gold finger and the second gold finger each include 22 pins; Among the 22 pins of the first gold finger, the number of pins located on the top surface and the bottom surface of the circuit board (1) is the same; Among the 22 pins of the second gold finger, the number of pins located on the top surface and the bottom surface of the circuit board (1) is the same.

3. The optical module according to claim 2, characterized in that: The first golden finger and the second golden finger are used to support at least one of a Gigabit passive optical network, a 10 Gigabit passive optical network, and a 50 Gigabit passive optical network.

4. The optical module according to claim 2 or 3, characterized in that: The signal transmission pins of the 10 Gigabit passive optical network are located on the bottom surface of the circuit board (1); The signal transmitting pins include the first pin and the second pin from the left of the first gold finger along the insertion direction, or the first pin and the second pin from the left of the second gold finger along the insertion direction.

5. The optical module according to any one of claims 2 to 4, characterized in that: The signal receiving pin of the 10 Gigabit passive optical network is located on the bottom surface of the circuit board (1); The signal receiving pins include the seventh pin and the eleventh pin from the left of the first gold finger along the insertion direction, or the seventh pin and the eleventh pin from the left of the second gold finger along the insertion direction.

6. The optical module according to any one of claims 2 to 5, characterized in that: The signal transmission pins of the 50 Gigabit passive optical network include a first pair of signal transmission pins and a second pair of signal transmission pins of 25 Gigabit; The first pair of signal transmitting pins and the second pair of signal transmitting pins are both located on the top surface of the circuit board (1); The first pair of signal transmitting pins includes the second pin and the third pin from the left of the first gold finger along the insertion direction; The second pair of signal transmitting pins includes the second pin and the third pin from the left of the second gold finger along the insertion direction.

7. The optical module according to any one of claims 2 to 6, characterized in that: The 50 Gigabit passive optical network is a symmetric passive optical network; The signal receiving pins of the 50 Gigabit passive optical network include a first pair of signal receiving pins and a second pair of signal receiving pins of 25 Gigabit; The first pair of signal receiving pins and the second pair of signal receiving pins are both located on the top surface of the circuit board (1); The first pair of signal receiving pins includes the eighth pin and the ninth pin from the left of the first gold finger along the insertion direction; The second pair of signal receiving pins includes the eighth pin and the ninth pin from the left of the second gold finger along the insertion direction.

8. The optical module according to any one of claims 2 to 7, characterized in that: The 50 Gigabit passive optical network is a symmetric passive optical network; The control or indication pins of the 50 Gigabit passive optical network include a reset pin, a signal check pin and a rate selection pin; The reset pin and the signal check pin are both located on the bottom surface of the circuit board (1); The rate selection pin is located on the top surface of the circuit board (1); The reset pin is the eighth pin from the left of the first golden finger or the second golden finger along the insertion direction; The signal check pin is the ninth pin from the left of the first golden finger or the second golden finger along the insertion direction; The rate selection pin is the eleventh pin from the left of the first golden finger or the second golden finger along the insertion direction.

9. The optical module according to any one of claims 2 to 6, characterized in that: The 50 Gigabit passive optical network is an asymmetric passive optical network; The signal receiving pins of the 50 Gigabit passive optical network include a pair of 25 Gigabit signal receiving pins; The pair of signal receiving pins are located on the top surface of the circuit board (1); The pair of signal receiving pins includes the eighth pin and the ninth pin from the left of the first gold finger along the insertion direction, or the eighth pin and the ninth pin from the left of the second gold finger along the insertion direction.

10. The optical module according to any one of claims 2 to 6, characterized in that: The 50 Gigabit passive optical network is an asymmetric passive optical network; The control or indication pins of the 50 Gigabit passive optical network include a reset pin and a signal check pin; The reset pin and the signal check pin are both located on the bottom surface of the circuit board (1); The reset pin is the eighth pin from the left of the first golden finger or the second golden finger along the insertion direction; The signal check pin is the ninth pin from the left of the first golden finger or the second golden finger along the insertion direction.

11. The optical module according to any one of claims 1 to 10, characterized in that: The spacing between the plurality of gold fingers (2) matches the spacing between the plurality of connectors of the optical communication device, so that the plurality of gold fingers (2) can be inserted into the plurality of connectors of the optical communication device.

12. The optical module according to any one of claims 1 to 11, characterized in that: The optical module also includes an optical device (3) and an electrical chip (4); The optical device (3) is electrically connected to the electrical chip (4); The electric chip (4) is electrically connected to the plurality of gold fingers (2) via the circuit board (1).

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