A method for fabricating a waveguide-integrated tri-layer graphene electro-optic modulator

Abstract

This invention discloses a method for fabricating a waveguide-integrated tri-layer graphene electro-optic modulator. The method employs a tri-layer graphene capacitor structure to enhance the interaction between graphene and light, thereby improving the modulation efficiency and reducing insertion loss of the device within the same device size. The first and third graphene layers are interconnected. After the third graphene layer is transferred, a vacuum annealing process is used to remove residual water, ensuring that the third graphene layer can adhere to the surfaces of the first graphene layer and the dielectric layer. This simplifies the device control circuit and facilitates device miniaturization.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, and in particular relates to a method for fabricating a waveguide-integrated tri-layer graphene electro-optic modulator. Background Technology

[0002] Optical modulators are key functional components in microwave photonics signal generation and processing systems. Exploring high-speed, high-bandwidth, and compact integrated optical modulators for on-chip optical device interconnection has become a development trend in modulators. In recent years, integrated photonics, aiming at on-chip functional integration systems, has developed rapidly. In the process of chip-based optical signal processing systems, developing efficient modulators is an important research area.

[0003] Graphene, a two-dimensional material that has been extensively studied in recent years, possesses numerous superior properties compared to traditional electro-optic materials, including excellent mechanical properties, high thermal conductivity, ultra-wideband optical response spectrum, extremely high carrier mobility, and high current density carrying capacity. It holds promise for simultaneously meeting the requirements of small size, low power consumption, and large bandwidth in modulators, making it an ideal material for integrated microwave photonics. Because single-layer graphene suffers from insufficient light absorption, combining graphene with waveguides, utilizing evanescent waves around the waveguide to enhance the interaction between graphene and light and increase the interaction distance, is an important way to improve the efficiency of graphene optoelectronic devices. These excellent properties give graphene a unique advantage in the field of novel optical and optoelectronic devices.

[0004] Research on graphene-based electro-optic modulators is progressing rapidly. They generally adopt a structural design that combines graphene with waveguides in a capacitor-like manner. The active region of the device exhibits the advantage of small size. However, graphene electro-optic modulators also have many problems, such as the difficulty in achieving high modulation bandwidth and high extinction ratio at the same time, and the need for further optimization of device modulation efficiency. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a waveguide-integrated triple-layer graphene electro-optic modulator, which improves modulation efficiency, reduces insertion loss, and simplifies device control circuitry.

[0006] To achieve the objective of this invention, a method for fabricating a waveguide-integrated tri-layer graphene electro-optic modulator is provided, comprising the following steps:

[0007] Step 1: Fabrication of Si waveguide on SOI substrate: The Si waveguide pattern is obtained using planar photolithography and development technology, and the Si waveguide is etched using a dry etching process.

[0008] Step 2, Si waveguide surface planarization: A SiO2 layer is grown on the surface of the Si waveguide using plasma-enhanced chemical vapor deposition, and then the surface of the Si waveguide is polished to be flat using chemical mechanical polishing technology.

[0009] Step 3, Transfer of the first graphene layer: The first graphene layer is transferred to the SiO2 surface using a wet transfer process;

[0010] Step 4: Patterning of the first graphene layer: An isolation pattern is prepared on the surface of the first graphene layer using planar photolithography, and then the first graphene layer outside the isolation pattern area is removed by dry oxidation.

[0011] Step 5, Dielectric layer growth: A dielectric layer is grown on the surface of the first graphene layer using atomic layer deposition (ALD) technology;

[0012] Step 6: Transfer and patterning of the second graphene layer, the process of which is the same as steps 3 and 4;

[0013] Step 7: Preparation of the first metal electrode: An electrode pattern is prepared on the surface of the second graphene layer using planar photolithography. The electrode pattern is located in the edge region of the second graphene layer pattern. After evaporation, metallization is completed, and the first metal electrode is prepared by sol-gel peeling technology.

[0014] Step 8, Dielectric layer growth: A dielectric layer is grown on the surface of the second graphene layer using atomic layer deposition (ALD) technology;

[0015] Step 9, Dielectric layer opening: An opening pattern is prepared on the surface of the dielectric layer using planar photolithography and development technology. The opening pattern is located above the first graphene layer. The dielectric layer under the opening pattern is removed by wet etching process until the surface of the first graphene layer is exposed.

[0016] Step 10, Transfer and patterning of the third graphene layer: The process is the same as step 3. After the third graphene layer is transferred, a vacuum high-temperature annealing process is used, and the subsequent process is the same as step 4.

[0017] Step 11: Preparation of the second metal electrode: An electrode pattern is prepared on the surface of the third graphene layer using planar photolithography. The electrode pattern is located in the edge region of the third graphene layer pattern. After evaporation, metallization is completed. With the aid of sol-gel exfoliation technology, the second metal electrode is prepared, thus completing the preparation of the graphene electro-optic modulator.

[0018] Compared with the prior art, the significant progress of the present invention is as follows: (1) The present invention adopts a three-layer graphene design, which enhances the interaction between graphene and light compared with the traditional two-layer graphene electro-optic modulator, and can improve the device modulation efficiency and reduce insertion loss under the same device size; (2) The first graphene layer and the second graphene layer of the present invention adopt an interconnected design, and the third graphene layer is transferred by vacuum annealing process to remove residual water, ensuring that the third graphene layer can be attached to the surface of the first graphene layer and the dielectric layer, simplifying the device control circuit and facilitating device miniaturization.

[0019] To more clearly illustrate the functional characteristics and structural parameters of the present invention, further explanation is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0021] Figure 1 This is a schematic diagram of the tri-layered graphene electro-optic modulator of the present invention;

[0022] Figure 2 This is a schematic diagram of the waveguide structure of the present invention;

[0023] Figure 3 This is a schematic diagram of waveguide surface planarization according to the present invention;

[0024] Figure 4 This is a schematic diagram of the first graphene layer structure of the present invention;

[0025] Figure 5 This is a schematic diagram of the alumina growth medium of the present invention;

[0026] Figure 6 This is a schematic diagram of the second graphene layer and the first metal electrode of the present invention;

[0027] Figure 7 This is a schematic diagram of the alumina growth medium and the opening of the present invention. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The present invention discloses a method for fabricating a waveguide-integrated tri-layer graphene electro-optic modulator, comprising the following steps:

[0030] Step 1: Fabrication of Si waveguide on SOI substrate: The Si waveguide pattern is obtained using planar photolithography, and the Si waveguide is etched using a dry etching process. Figure 2 ;

[0031] Step 2, Si waveguide surface planarization: A SiO2 layer is grown on the Si waveguide surface using plasma-enhanced chemical vapor deposition, followed by chemical mechanical polishing to achieve a flat surface. Figure 3 ;

[0032] Step 3, Transfer of the first graphene layer: The first graphene layer is transferred to the SiO2 surface using a wet transfer process;

[0033] Step 4: Patterning of the first graphene layer: An isolation pattern is prepared on the surface of the first graphene layer using planar photolithography. Then, dry oxidation and oxygen plasma are used to remove the first graphene layer outside the isolation pattern area, and then... Figure 4 ;

[0034] Step 5, Dielectric Layer Growth: A dielectric layer is grown on the surface of the first graphene layer using atomic layer deposition (ALD) technology, combined with... Figure 5 ;

[0035] Step 6: Transfer and patterning of the second graphene layer, the process of which is the same as steps 3 and 4;

[0036] Step 7: Fabrication of the first metal electrode: An electrode pattern is fabricated on the surface of the second graphene layer using planar photolithography. The electrode pattern is located at the edge region of the second graphene layer pattern. After evaporation, metallization is completed, and a sol-gel lift-off technique is used to prepare the first metal electrode. Figure 6 ;

[0037] Step 8, Dielectric layer growth: A dielectric layer is grown on the surface of the second graphene layer using atomic layer deposition (ALD) technology;

[0038] Step 9, Dielectric Layer Aperture: An aperture pattern is fabricated on the surface of the dielectric layer using planar photolithography. The aperture pattern is located above the first graphene layer. A wet etching process is used to remove the dielectric layer beneath the aperture pattern until the surface of the first graphene layer is exposed. Figure 7 ;

[0039] Step 10, Transfer and patterning of the third graphene layer: The process is the same as step 3. In view of the possibility of water residue in the bonding of the third graphene layer in the dielectric pores during wet transfer, a vacuum high-temperature annealing process is used after the transfer of the third graphene layer to ensure that the third graphene layer is bonded to the surface of the first graphene layer and the dielectric layer. The process is then repeated as in step 4.

[0040] Step 11: Fabrication of the second metal electrode: An electrode pattern is fabricated on the surface of the third graphene layer using planar photolithography. The electrode pattern is located at the edge region of the third graphene layer pattern. After evaporation, metallization is completed, and a sol-gel lift-off technique is used to fabricate the second metal electrode, thus completing the fabrication of the graphene electro-optic modulator. Figure 1 .

[0041] Furthermore, in step 10, a vacuum high-temperature annealing process is adopted, with an annealing temperature of 200-300℃, a pressure of less than 1Pa, and a time of 2-4 hours.

[0042] Furthermore, the SiO2 layer in step 2 has a thickness of 1-2 μm, and then the surface is polished by chemical mechanical polishing until the remaining SiO2 layer is 50-100 nm.

[0043] Furthermore, the dielectric layer in steps 5 and 8 is a high-k dielectric with a thickness of 10-30 nm.

[0044] Furthermore, the high-k medium is Al2O3 or HfO2.

[0045] Furthermore, the metal electrode material in steps 7 and 11 is Au, with a thickness of 200 nm to 1 μm.

[0046] Furthermore, the Si waveguide step height in step 1 is 200-300nm, and the Si waveguide width is 400-600nm.

[0047] When electro-optic modulation is achieved using a capacitor structure with four or more graphene layers, the manufacturing process becomes more difficult, the distance from the waveguide is greater, and the modulation efficiency is reduced.

[0048] In the attached diagram, graphene 1 is the first graphene layer, graphene 2 is the second graphene layer, and graphene 3 is the third graphene layer; electrode 1 is the first metal electrode, and electrode 2 is the second metal electrode.

[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0050] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a waveguide-integrated tri-layer graphene electro-optic modulator, characterized in that, Includes the following steps: Step 1: Fabrication of Si waveguide on SOI substrate: The Si waveguide pattern is obtained using planar photolithography and development technology, and the Si waveguide is etched using a dry etching process. Step 2, Si waveguide surface planarization: A SiO2 layer is grown on the surface of the Si waveguide using plasma-enhanced chemical vapor deposition, and then the surface of the Si waveguide is polished to be flat using chemical mechanical polishing technology. Step 3, Transfer of the first graphene layer: The first graphene layer is transferred to the SiO2 surface using a wet transfer process; Step 4: Patterning of the first graphene layer: An isolation pattern is prepared on the surface of the first graphene layer using planar photolithography, and then the first graphene layer outside the isolation pattern area is removed by dry oxidation. Step 5, Dielectric layer growth: A dielectric layer is grown on the surface of the first graphene layer using atomic layer deposition (ALD) technology; Step 6: Transfer and patterning of the second graphene layer, the process of which is the same as steps 3 and 4; Step 7: Preparation of the first metal electrode: An electrode pattern is prepared on the surface of the second graphene layer using planar photolithography. The electrode pattern is located in the edge region of the second graphene layer pattern. After evaporation, metallization is completed, and the first metal electrode is prepared by sol-gel peeling technology. Step 8, Dielectric layer growth: A dielectric layer is grown on the surface of the second graphene layer using atomic layer deposition (ALD) technology; Step 9, Dielectric layer opening: An opening pattern is prepared on the surface of the dielectric layer using planar photolithography and development technology. The opening pattern is located above the first graphene layer. The dielectric layer under the opening pattern is removed by wet etching process until the surface of the first graphene layer is exposed. Step 10, Transfer and patterning of the third graphene layer: The process is the same as step 3. After the third graphene layer is transferred, a vacuum high-temperature annealing process is used, and the subsequent process is the same as step 4. Step 11: Preparation of the second metal electrode: An electrode pattern is prepared on the surface of the third graphene layer using planar photolithography. The electrode pattern is located in the edge region of the third graphene layer pattern. After evaporation, metallization is completed. With the aid of sol-gel exfoliation technology, the second metal electrode is prepared, thus completing the preparation of the graphene electro-optic modulator.

2. The method for fabricating a waveguide-integrated triple-layered graphene electro-optic modulator according to claim 1, characterized in that, In step 10, a vacuum high-temperature annealing process is used to remove residual water and ensure that the third graphene layer can adhere to the surface of the first graphene layer and the dielectric layer. The annealing temperature is 200-300℃, the pressure is less than 1Pa, and the time is 2-4 hours.

3. The method for fabricating a waveguide-integrated tri-layered graphene electro-optic modulator according to claim 1, characterized in that, The SiO2 layer in step 2 has a thickness of 1-2 μm, and then the surface is polished by chemical mechanical polishing until the remaining SiO2 layer is 50-100 nm.

4. The method for fabricating a waveguide-integrated triple-layered graphene electro-optic modulator according to claim 1, characterized in that, The dielectric layer in steps 5 and 8 is a high-k dielectric with a thickness of 10-30 nm.

5. The method for fabricating a waveguide-integrated triple-layered graphene electro-optic modulator according to claim 4, characterized in that, The high-K medium is Al2O3 or HfO2.

6. The method for fabricating a waveguide-integrated triple-layered graphene electro-optic modulator according to claim 1, characterized in that, The metal electrode material used in steps 7 and 11 is Au, with a thickness of 200 nm to 1 μm.

7. The method for fabricating a waveguide-integrated triple-layered graphene electro-optic modulator according to claim 1, characterized in that, The Si waveguide step height in step 1 is 200-300nm, and the Si waveguide width is 400-600nm.

Images