Array substrate and display screen

Abstract

The embodiment of the application provides an array substrate and a display screen, wherein the electrical test metal wiring, the outer common electrode and the inner common electrode are arranged on the side of the first insulating layer away from the conductive layer; the inner common electrode is arranged on the side close to the display area, and the outer common electrode is arranged on the side away from the display area; the electrical test metal wiring is arranged between the outer common electrode and the inner common electrode; at least one first via hole and at least one second via hole are arranged on the first insulating layer, so that the conductive layer can be connected together with the inner Com metal and the outer Com metal through the first insulating layer via hole, and then the outer Com signal is introduced into the inner Com, the attenuation of the inner Com signal is compensated, and the display performance of the screen is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display screen. Background Technology

[0002] TFT (Thin Film Transistor) and LCD (Liquid Crystal Display) achieve their display effects by deflecting liquid crystals through an electric field formed between pixel electrodes and the Com (common) electrode.

[0003] Typically, display substrates are designed with inner and outer rings of Com traces, such as... Figure 1 As shown, generally speaking, the array substrate includes an external common electrode (external Com) and an internal common electrode (internal Com). The internal common electrode is located on the side closer to the display area, and the external common electrode is located on the side farther away from the display area. Electrical test metal traces (ET signal lines) are also included. Figure 1 The display substrate also includes PLG (Propel Link Gate) traces, Source IC, and Gate IC.

[0004] The inner Com is used to form the electric field required for liquid crystal deflection with the pixel electrodes, while the outer Com surrounds the outer edge of the substrate for shielding and protection. The inner Com voltage signal is usually provided by an IC (integrated circuit), while the outer Com voltage signal is provided by an FPC (flexible printed circuit).

[0005] For internal COM signals, due to the larger resistance of ITO (Indium Tin Oxide) and the greater voltage division, the signal attenuation is greater than that of external COM signals during the transmission from the IC output to the farthest pixel. When the internal COM signal strength attenuates to a certain level, it will affect the display effect, and this effect is more pronounced for vertically elongated screens.

[0006] Therefore, conventional panel designs connect the metal layers of the inner and outer Coms together away from the IC, using the voltage signal of the outer Com to compensate for the signal attenuation of the inner Com.

[0007] However, for panels with separate Gate ICs (gate driver chips, row driver chips) and Source ICs (source driver chips, column driver chips), there are metal traces for ET (Electric Test) signals between the inner Com and the outer Com, so the metal layers of the inner and outer Com cannot be directly connected together. Summary of the Invention

[0008] The purpose of this application is to provide an array substrate and a display screen. The specific technical solution is as follows:

[0009] The first aspect of this application provides an array substrate, comprising:

[0010] Outer common electrode, inner common electrode, first insulating layer, conductive layer, electrical test metal trace;

[0011] The electrical test metal trace, the outer common electrode, and the inner common electrode are disposed on the side of the first insulating layer away from the conductive layer; the inner common electrode is disposed on the side closer to the display area, and the outer common electrode is disposed on the side away from the display area; the electrical test metal trace is disposed between the outer common electrode and the inner common electrode.

[0012] At least one first via and at least one second via are provided in the first insulating layer; the conductive layer connects the outer common electrode and the inner common electrode through at least one first via and at least one second via.

[0013] In one possible implementation, the array substrate further includes a second insulating layer and a first metal layer; the first metal layer is disposed between the second insulating layer and the first insulating layer.

[0014] The electrical test metal trace, the outer common electrode, and the inner common electrode are disposed on the side of the second insulating layer away from the first insulating layer.

[0015] In one possible implementation, the first metal layer includes: a first sub-metal layer and a second sub-metal layer; the first sub-metal layer and the second sub-metal layer are separated by the first insulating layer, the second sub-metal layer is disposed on the side closer to the display area, and the first sub-metal layer is disposed on the side away from the display area;

[0016] The first sub-metal layer includes a first outer common electrode, and the second sub-metal layer includes a first inner common electrode;

[0017] At least one third via and at least one fourth via are provided in the first insulating layer; wherein the depth of the third via is less than the depth of the first via, and the depth of the fourth via is less than the depth of the second via, and the conductive layer connects the first outer common electrode and the first inner common electrode through at least one third via and at least one fourth via.

[0018] In one possible implementation, the conductive layer comprises a block structure, and / or the conductive layer comprises at least one strip structure;

[0019] The block structure connects the outer common electrode and the inner common electrode through at least one first through hole and at least one second through hole;

[0020] and / or

[0021] The strip structure connects the outer common electrode and the inner common electrode through at least one first through hole and at least one second through hole;

[0022] The angle between the strip structure and the electrical test metal trace is greater than a preset angle threshold.

[0023] In one possible implementation, the strip structure is perpendicular to the electrical test metal trace.

[0024] In one possible implementation, the conductive layer includes a plurality of strip structures, the plurality of strip structures having the same width.

[0025] In one possible implementation, the array substrate further includes a plurality of transition structures disposed between the bonding area and the switching area of ​​the array substrate;

[0026] The transition structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer;

[0027] The second insulating layer is disposed on one side of the second metal layer, the first metal layer is disposed on the side of the second insulating layer away from the second metal layer, the first insulating layer is disposed on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is disposed on the side of the first insulating layer away from the second metal layer;

[0028] The length of the first metal layer extending in the second direction of the transition structure is less than a preset length;

[0029] The conductive layer includes an ET conductive portion and an IC conductive portion. The first insulating layer has a fifth via, and the first and second insulating layers have a sixth via. The first metal layer is connected to the ET conductive portion through the fifth via, and the ET conductive portion is connected to the ET signal line in the second metal layer through the sixth via. The first and second insulating layers have a plurality of seventh vias, and the IC conductive portion is connected to the IC signal line in the second metal layer through the seventh vias.

[0030] In one possible implementation, the array substrate further includes a plurality of transition structures disposed between the bonding area and the switching area of ​​the array substrate;

[0031] The transition structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer;

[0032] The second insulating layer is disposed on one side of the second metal layer, the first metal layer is disposed on the side of the second insulating layer away from the second metal layer, the first insulating layer is disposed on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is disposed on the side of the first insulating layer away from the second metal layer;

[0033] The length of the first metal layer extending in the second direction of the transition structure is less than a preset length;

[0034] The conductive layer includes an ET conductive portion and an IC conductive portion;

[0035] The first insulating layer has a fifth via, and the first and second insulating layers have a sixth via. The first metal layer is connected to the ET conductive part through the fifth via, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via. The first and second insulating layers have through holes, and the IC conductive part is connected to the IC signal line in the second metal layer through the through holes.

[0036] In one possible implementation, multiple transition structures form multiple rows of transition structures in a first direction, and the transition structures between adjacent rows of transition structures are staggered in a second direction.

[0037] A second aspect of this application provides a display screen including the array substrate described in the first aspect above.

[0038] Beneficial effects of the embodiments in this application:

[0039] This application provides an array substrate and display screen. Electrical test metal traces, an outer common electrode, and an inner common electrode are disposed on the side of a first insulating layer away from the conductive layer. The inner common electrode is disposed on the side closer to the display area, and the outer common electrode is disposed on the side away from the display area. The electrical test metal traces are disposed between the outer common electrode and the inner common electrode. At least one first via and at least one second via are provided in the first insulating layer, so that the conductive layer can be connected to the inner Com metal and the outer Com metal through the first insulating layer via, thereby introducing the outer Com signal into the inner Com and compensating for the attenuation of the inner Com signal to improve the display performance of the screen.

[0040] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0042] Figure 1 This is a schematic diagram of an array substrate structure in related technologies;

[0043] Figure 2-1 This is a schematic diagram of the first structure of the array substrate provided in the embodiments of this application;

[0044] Figure 2-2 This is a schematic diagram of a second structure of the array substrate provided in the embodiments of this application;

[0045] Figure 2-3 This is a schematic diagram of a third structure of the array substrate provided in the embodiments of this application;

[0046] Figure 2-4 This is a schematic diagram of the fourth structure of the array substrate provided in the embodiments of this application;

[0047] Figure 3 This is a schematic diagram of the fifth structure of the array substrate provided in the embodiments of this application;

[0048] Figure 4 This is a schematic diagram of the sixth structure of the array substrate provided in the embodiments of this application;

[0049] Figure 5 This is a schematic diagram of a process of an array substrate provided in an embodiment of this application;

[0050] Figure 6-1 A schematic diagram of a chip coating structure for an array substrate provided in related technologies;

[0051] Figure 6-2 for Figure 6-1 A cross-sectional view of line A-A';

[0052] Figure 7-1 This is a schematic diagram of the first structure of chip coating on the array substrate provided in the embodiments of this application;

[0053] Figure 7-2 for Figure 7-1 Cross-sectional view of B-B';

[0054] Figure 8-1 This is a schematic diagram of a second structure for chip coating on an array substrate provided in an embodiment of this application.

[0055] Figure 8-2 for Figure 8-1Cross-sectional view of B-B'. Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0057] like Figure 2-1 As shown, this application provides an array substrate, including:

[0058] Outer common electrode 01, inner common electrode 03, first insulating layer 05, conductive layer 06, electrical test metal trace 02;

[0059] The electrical test metal trace 02, the outer common electrode 01, and the inner common electrode 03 are disposed on the side of the first insulating layer 05 away from the conductive layer 06; the inner common electrode 03 is disposed on the side closer to the display area, and the outer common electrode 01 is disposed on the side away from the display area; the electrical test metal trace 02 is disposed between the outer common electrode 01 and the inner common electrode 03.

[0060] At least one first via 110 and at least one second via 120 are provided in the first insulating layer 05; the conductive layer 06 connects the outer common electrode 01 and the inner common electrode 03 through at least one first via 110 and at least one second via 120.

[0061] The first insulating layer can be a protective layer (PVX). An electrical test metal trace (ET signal metal trace) 02 is set between the inner Com and the outer Com. The inner and outer Com metals cannot be directly connected together. At least one first via 110 and at least one second via 120 are set in the first insulating layer (PVX) 05. The first via 110 is located on the outer Com side and the second via 120 is located on the inner Com side. That is, the projection of the first via on the first insulating layer overlaps with the projection of the outer common electrode 01 on the first insulating layer; the projection of the second via on the first insulating layer overlaps with the projection of the inner common electrode 03 on the first insulating layer.

[0062] The number of vias can be one or more. In one example, a first via 110 and a second via 120 are provided in the first insulating layer 05, wherein the first via 110 is provided on the outer COM side and the second via 120 is provided on the inner COM side.

[0063] In one example, the number of the first via is n, and the number of the second via is m, where n and m are both integers not less than 1. m and n can be equal or not equal, and can be set according to the actual situation, without limitation here.

[0064] When there are multiple first vias and / or multiple second vias, the dimensions of each first via can be the same or different. The dimensions of each second via can also be the same or different.

[0065] In other words, the conductive layer can be directly connected to the outer Com metal through the first via 110, and the conductive layer can be directly connected to the inner Com metal through the second via 120. In one example, conductive material is deposited in the first via 110 and the second via 120. Thus, a conductive bridging layer is designed between the inner and outer Com metals. That is, the conductive layer can be connected to the inner and outer Com metals through the vias of the first insulating layer, thereby introducing the outer Com signal into the inner Com and compensating for the attenuation of the inner Com signal to improve the display performance of the screen.

[0066] The conductive layer can be made of ITO (Indium Tin Oxide). The conductive material deposited in the first via 110 and the second via 120 can be the same as or different from the material of the conductive layer. In one example, the conductive material deposited in the first via 110 and the second via 120 is the same as the material of the conductive layer. This effectively connects the external Com signal to the internal Com signal at the far end of the IC without increasing manufacturing costs or affecting the process complexity, compensating for the attenuation of the internal Com signal and improving the display effect.

[0067] In one example, the distance between the second via and the farthest pixel is no greater than a first preset distance threshold. The first preset distance threshold can be determined based on the actual situation.

[0068] Because the internal Com signal is used to form the electric field required for liquid crystal deflection with the pixel electrodes, the voltage drop is greater for the internal Com signal due to the higher resistance of ITO (indium tin oxide). From the IC output to the farthest pixel, the signal attenuation is greater than that of the external Com signal. Therefore, to ensure sufficient magnetic field for the farthest pixel, compensation is needed for the internal Com signal near the farthest pixel. Thus, the position of the second via can be determined based on the position of the farthest pixel. The external Com signal is introduced into the internal Com signal to compensate for the attenuation of the internal Com signal and improve the screen's display performance. The preset distance threshold can be set based on actual conditions.

[0069] based on Figure 2-1 The illustrated embodiments, such as Figure 2-2As shown, in one possible implementation, the array substrate further includes a second insulating layer 04 and a first metal layer 07; the first metal layer 07 is disposed between the second insulating layer 04 and the first insulating layer 05.

[0070] The electrical test metal trace 02, the outer common electrode 01, and the inner common electrode 03 are disposed on the side of the second insulating layer 04 away from the first insulating layer 05.

[0071] In one possible implementation, the array substrate further includes a second metal layer, wherein the outer common electrode 01, the inner common electrode 03, and the electrical test metal trace 02 are all disposed on the second metal layer.

[0072] like Figure 2-3 As shown, the array substrate includes a second metal layer 00, which includes three regions: 001, 002, and 003. An outer common electrode 01 is disposed in 001, an electrical test metal trace 02 is disposed in 002, and an inner common electrode 01 is disposed in 003.

[0073] based on Figure 2-2 The illustrated embodiments, such as Figure 2-4 As shown, in one possible implementation, the first metal layer 07 includes: a first sub-metal layer 071 and a second sub-metal layer 072; the first sub-metal layer 071 and the second sub-metal layer 072 are separated by the first insulating layer, the second sub-metal layer 072 is disposed on the side closer to the display area, and the first sub-metal layer 071 is disposed on the side away from the display area.

[0074] The first sub-metal layer 071 includes a first external common electrode, and the second sub-metal layer 072 includes a first internal common electrode;

[0075] At least one third via 130 and at least one fourth via 140 are provided in the first insulating layer 05; wherein the depth of the third via 130 is less than the depth of the first via 110, and the depth of the fourth via 140 is less than the depth of the second via 120, and the conductive layer connects the first outer common electrode and the first inner common electrode through at least one third via 130 and at least one fourth via 140.

[0076] The first sub-metal layer 071 and the second sub-metal layer 072 are separated by the first insulating layer 05. The first external common electrode is disposed in the first sub-metal layer 071 and the first internal common electrode is disposed in the second sub-metal layer 072. At least one third via 130 and at least one fourth via 140 can be disposed in the first insulating layer 05. The first external common electrode and the first internal common electrode are connected by the conductive layer 06 through the third via 130 and the fourth via 140.

[0077] In other words, a common electrode can be set in either the second metal layer or the first metal layer. If a common electrode is set in the second metal layer, the first metal layer away from the display area can be designated as the first sub-metal layer 071, and the first metal layer closer to the display area can be designated as the second sub-metal layer 072. The third via 130 is located on the side of the first sub-metal layer 071, and the fourth via 140 is located on the side of the second sub-metal layer 072. That is, the projection of the third via on the first insulating layer 05 overlaps with the projection of the first sub-metal layer 071 on the first insulating layer 05; the projection of the fourth via on the first insulating layer 05 overlaps with the projection of the second sub-metal layer 072 on the first insulating layer 05.

[0078] The number of third vias 130 and fourth vias 140 can be one or more. In one example, a third via 130 and a fourth via 140 are provided in the first insulating layer 05.

[0079] In one example, the number of the third via is x, and the number of the fourth via is y, where x and y are both integers greater than 1. x and y can be equal or unequal, and can be set based on the actual situation, without limitation here.

[0080] When there are multiple third vias and / or multiple fourth vias, the dimensions of each third via can be the same or different. The dimensions of each fourth via can also be the same or different.

[0081] Conductive material is deposited in the third via 130 and the fourth via 140, thus creating a conductive bridging layer between the first outer COM and the first inner COM. Specifically, the conductive layer can be connected to both the first outer COM and the first inner COM through the via 05 of the first insulating layer. This allows the outer COM signal to be introduced into the inner COM, compensating for the attenuation of the inner COM signal and improving the screen's display performance.

[0082] The conductive layer can be made of ITO (Indium Tin Oxide). The conductive material deposited in the first via 110 and the second via 120 can be the same as or different from the material of the conductive layer. In one example, the conductive material deposited in the third via 130 and the fourth via 140 is the same as the material of the conductive layer. This effectively connects the external Com signal to the internal Com signal at the far end of the IC without increasing manufacturing costs or affecting the process complexity, compensating for the attenuation of the internal Com signal and improving the display effect.

[0083] In one example, the distance between the second via and the farthest pixel is no greater than a first preset distance threshold. The first preset distance threshold can be determined based on the actual situation.

[0084] In one possible implementation, the conductive layer comprises a block structure, and / or the conductive layer comprises at least one strip structure;

[0085] The block structure connects the outer common electrode and the inner common electrode through at least one first through hole and at least one second through hole;

[0086] and / or

[0087] The strip structure connects the outer common electrode and the inner common electrode through at least one first through hole and at least one second through hole;

[0088] The angle between the strip structure and the electrical test metal trace is greater than a preset angle threshold.

[0089] In one example, the conductive layer can be designed as a block structure, such as... Figure 3 As shown, a large conductive layer partially covers the inner and outer Com metal layers at the far end of the IC. Through perforations in the first insulating layer 05, the conductive layer is connected to the inner and outer Com metal layers, thereby achieving the connection between the inner and outer Com signals. The outer Com signal compensates for the inner Com signal, improving the screen display effect. This method effectively connects the outer Com signal to the inner Com at the far end of the IC without increasing manufacturing costs or affecting the process complexity, compensating for the attenuation of the inner Com signal and improving the display effect.

[0090] In one example, the bulk conductive layer used for bridging is replaced with at least one strip-shaped structure. For example... Figure 4 As shown, the area of ​​the strip structure is smaller than that of the block structure, and the overlap area between the strip structure and the ET signal metal line is smaller, thus reducing the coupling capacitance formed by the two. A smaller coupling capacitance means that the attenuation of the external Com signal can be reduced when the bridging ITO crosses the ET signal metal line, ensuring that the external Com signal can exert its maximum effect when compensating for the internal Com signal, which helps improve the display effect.

[0091] Each strip structure is provided with at least one first through hole 110 and at least one second through hole 120.

[0092] In one example, the conductive layer comprises multiple strip structures. Because the bridging conductive layer is located on the outermost layer of the array substrate process and is close to the substrate edge, if a foreign object scratches the conductive layer, moisture can easily enter and corrode, spreading throughout the entire film layer and causing the bridging function to fail. Multiple strip structures in the bridging conductive layer design can each perform their bridging function independently. If one or more strips are scratched and corroded, it will not affect the normal operation of the others, thus improving the reliability of the bridging function.

[0093] The angle between the strip structure and the electrical test metal trace must be greater than a preset angle threshold to minimize the overlap area between the bridging conductive layer and the ET metal line, thus minimizing the coupling capacitance. A smaller coupling capacitance means less attenuation of the external Com signal as the bridging ITO crosses the ET metal trace, ensuring the external Com signal maximizes its compensation effect on the internal Com signal and improves display quality.

[0094] In one possible implementation, the strip structure is perpendicular to the electrical test metal trace.

[0095] The strip structure, perpendicular to the electrical test metal trace, minimizes the overlap area between the bridging conductive layer and the ET metal line, thus reducing the coupling capacitance. A smaller coupling capacitance means less attenuation of the external Com signal as the bridging ITO crosses the ET metal trace, ensuring the external Com signal maximizes its compensation effect on the internal Com signal and improving display quality.

[0096] In one possible implementation, the conductive layer includes a plurality of strip structures, the plurality of strip structures having the same width.

[0097] The strip structures have the same width, which simplifies the process and does not affect the manufacturing difficulty.

[0098] In one example, the line width and gap between adjacent strip structures are made as equal as possible to ensure that the overlap area between the bridging conductive layer and the ET metal line is minimized, and the coupling capacitance formed by the two is also minimized.

[0099] Based on the above embodiments, see Figure 5 , Figure 5 A schematic diagram of a process for fabricating an array substrate, including the following steps:

[0100] Fabrication of the second metal layer: A conductive metal layer (Mo or Al) is deposited on a transparent glass substrate. The thickness is adjusted appropriately based on the actual situation, process capability, and electrical requirements. For example, the thickness is 300nm-500nm. The required pattern is then created through processes such as photolithography, development, and etching.

[0101] Fabrication of the second insulating layer: An insulating layer (silicon nitride) is deposited on the substrate on which the gate layer pattern has been fabricated. The thickness is adjusted appropriately based on the actual situation, process capability, and electrical requirements. For example, the thickness is 300nm-500nm.

[0102] Fabrication of the Active Layer: A semiconductor layer (amorphous silicon) is deposited on the substrate on which the second insulating layer has been deposited. The thickness is determined based on the actual situation, for example, 180nm. The required pattern is then created through processes such as photolithography, development, and etching.

[0103] Depositing the first ITO layer (1st_ITO): On the substrate with the active layer pattern, another oxide semiconductor layer (indium tin oxide) is deposited. The thickness is determined based on the actual situation, for example, the thickness is 40nm. The required pattern is then created through photolithography, development, etching and other processes.

[0104] Fabrication of the first metal layer: On the substrate with the ITO layer pattern, another conductive metal layer (Mo or Al) is deposited. The thickness is adjusted appropriately based on the actual situation, process capability, and electrical requirements. For example, the thickness is 300nm-500nm. The required pattern is then fabricated through processes such as photolithography, development, and etching.

[0105] Fabrication of the first insulating layer: On the substrate with the SD layer pattern, another insulating layer (silicon nitride) is deposited. The thickness is adjusted appropriately based on the actual situation, process capability, and electrical requirements. For example, the thickness is 400nm-500nm. The required pattern is then fabricated through photolithography, development, etching, and other processes.

[0106] Depositing the second ITO layer (2st_ITO): On the substrate where the first insulating layer pattern has been fabricated, another oxide semiconductor layer (indium tin oxide) is deposited. The thickness is determined based on the actual situation, for example, the thickness is 80nm. The required pattern is then fabricated through processes such as photolithography, development, and etching.

[0107] TFT-LCD achieves its display effect by sending electrical signals from an IC to a substrate, causing the liquid crystal inside the substrate (panel) to deflect. Therefore, for a TFT-LCD to display correctly, the IC (chip) and the panel must be packaged together with very high precision.

[0108] COG (Chip on Glass) packaging technology is currently the most widely used IC packaging technology in the TFT-LCD industry. It involves creating panel pins on the glass of the panel array that correspond one-to-one with the IC pins, and then packaging the IC and panel together in a pin-to-pin manner using a thermoforming process.

[0109] To prevent IC bonding failure due to panel defects, an ET test is required on the panel before IC bonding in the module process to intercept defective panels.

[0110] The ET signal needs to be transferred from the first metal layer to the second metal layer before passing through the Panel Pin after exiting the Switch structure.

[0111] Traditional designs integrate the ET signal conversion structure and panel pin together, specifically as follows: Figures 6-1 to 6-2 As shown, Figure 6-1 It includes an adapter structure and a switch structure, among which Figure 6-2 for Figure 6-1 The cross-sectional view of A-A' shows that a is the IC signal transmission path and b is the ET signal transmission path.

[0112] The ET test structure is only used during the testing phase and is discarded after the module process is completed. However, this design causes the adapter structure to reduce the effective contact area between the Panel Pin and the IC Pin, resulting in a decrease in the number of effective vias for IC signal transmission to the Panel Pin. For example, Figure 6-2 As shown in the figure, assuming the resistance of a single via is R, the total resistance of the vias is R / 5. The reduction in the number of effective vias for IC signal transmission to the Panel Pin leads to an increase in resistance during IC signal transmission and a decrease in the fault tolerance rate in each process, which in turn reduces the reliability of the display module.

[0113] In one possible implementation, the array substrate further includes a plurality of transition structures disposed between the bonding area and the switching area of ​​the array substrate;

[0114] The transition structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; the second insulating layer is disposed on one side of the second metal layer, the first metal layer is disposed on the side of the second insulating layer away from the second metal layer, the first insulating layer is disposed on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is disposed on the side of the first insulating layer away from the second metal layer.

[0115] The length of the first metal layer extending in the second direction of the adapter structure is less than a preset length. The conductive layer includes an ET conductive part and an IC conductive part. The first insulating layer has a fifth via 150. The first insulating layer and the second insulating layer have a sixth via 160. The first metal layer is connected to the ET conductive part through the fifth via 150. The ET conductive part is connected to the ET signal line in the second metal layer through the sixth via 160. The first insulating layer and the second insulating layer have a plurality of seventh vias 170. The IC conductive part is connected to the IC signal line in the second metal layer through the seventh via 170.

[0116] like Figure 7-1and Figure 7-2 As shown, where Figure 7-2 for Figure 7-1 The cross-sectional view of line B-B' shows the ET signal transmission path (c) and the IC signal transmission path (d). Shortening the first metal layer allows for more space to be reserved for bonding the IC pin and the Panel pin. That is, the adapter structure does not encroach on the effective contact area between the Panel pin and the IC pin, thus increasing the number of effective vias for IC signal transmission to the Panel pin. Assuming the resistance of a single via is R, then... Figure 7-2 The optimized via design shown has a total resistance of R / 7, which is higher than the previous design. Figure 6-2 The design scheme reduces resistance by nearly 30%, decreasing resistance during IC signal transmission and improving the reliability of the display module. By separating the ET signal adapter structure from the Panel Pin, the number of vias for IC signal transmission to the Panel is increased. This reduces resistance during IC signal transmission while also improving fault tolerance in each process, thus enhancing display reliability.

[0117] The preset length can be determined based on the actual situation, for example, the preset length is 15μ-20μm.

[0118] like Figures 8-1 to 8-2 As shown, in one possible implementation, the array substrate further includes a plurality of transition structures disposed between the bonding area and the switching area of ​​the array substrate;

[0119] The transition structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; the second insulating layer is disposed on one side of the second metal layer, the first metal layer is disposed on the side of the second insulating layer away from the second metal layer, the first insulating layer is disposed on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is disposed on the side of the first insulating layer away from the second metal layer.

[0120] The length of the first metal layer extending in the second direction of the transition structure is less than a preset length, and the conductive layer includes an ET conductive portion and an IC conductive portion;

[0121] The first insulating layer has a fifth via 150, and the first and second insulating layers have a sixth via 160. The first metal layer is connected to the ET conductive part through the fifth via 150, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via 160. The first and second insulating layers have through holes 180, and the IC conductive part is connected to the IC signal line in the second metal layer through the through holes 180.

[0122] The multiple parallel vias of the Panel Pin are further optimized into a single large through-hole design, which further reduces the via resistance and thus improves the display effect. This design can effectively increase the contact area between the Panel Pin and the IC Pin without increasing manufacturing costs or affecting the process complexity. The single large through-hole design for IC signal transmission to the Panel Pin can further reduce the resistance during IC signal transmission, which helps to improve the pixel charging rate and thus improve the display effect.

[0123] In one possible implementation, multiple transition structures form multiple rows of transition structures in a first direction, and the transition structures between adjacent rows of transition structures are staggered in a second direction.

[0124] The layout of the transition structure can be set based on the actual situation, and no restrictions are imposed here.

[0125] This application also proposes a display screen including an array substrate of any of the above embodiments.

[0126] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0127] The various embodiments in this specification are described in a related manner. For the same or similar parts between the various embodiments, please refer to each other. Each embodiment focuses on describing the differences from other embodiments.

[0128] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An array substrate, characterized in that, include: External common electrode, internal common electrode, first insulating layer, conductive layer, electrical test metal traces, multiple transition structures; The electrical test metal trace, the outer common electrode, and the inner common electrode are disposed on the side of the first insulating layer away from the conductive layer; the inner common electrode is disposed on the side closer to the display area, and the outer common electrode is disposed on the side away from the display area; the electrical test metal trace is disposed between the outer common electrode and the inner common electrode. At least one first via and at least one second via are provided in the first insulating layer; the conductive layer connects the outer common electrode and the inner common electrode through at least one first via and at least one second via; The adapter structure is disposed between the bonding area and the switching area of ​​the array substrate; The transition structure includes a second metal layer, a second insulating layer, a first metal layer, a first insulating layer, and a conductive layer; The second insulating layer is disposed on one side of the second metal layer, the first metal layer is disposed on the side of the second insulating layer away from the second metal layer, the first insulating layer is disposed on the side of the first metal layer and the second insulating layer away from the second metal layer, and the conductive layer is disposed on the side of the first insulating layer away from the second metal layer; The length of the first metal layer extending in the second direction of the transition structure is less than a preset length; The conductive layer includes an ET conductive portion and an IC conductive portion; The first insulating layer has a fifth via, and the first insulating layer and the second insulating layer have a sixth via. The first metal layer is connected to the ET conductive part through the fifth via, and the ET conductive part is connected to the ET signal line in the second metal layer through the sixth via. The first insulating layer and the second insulating layer are provided with a plurality of seventh vias, through which the IC conductive part is connected to the IC signal line in the second metal layer; or, the first insulating layer and the second insulating layer are provided with through holes, through which the IC conductive part is connected to the IC signal line in the second metal layer.

2. The array substrate according to claim 1, characterized in that, The array substrate further includes a second insulating layer and a first metal layer; the first metal layer is disposed between the second insulating layer and the first insulating layer. The electrical test metal trace, the outer common electrode, and the inner common electrode are disposed on the side of the second insulating layer away from the first insulating layer.

3. The array substrate according to claim 2, characterized in that, The first metal layer includes: a first sub-metal layer and a second sub-metal layer; the first sub-metal layer and the second sub-metal layer are separated by the first insulating layer, the second sub-metal layer is disposed on the side closer to the display area, and the first sub-metal layer is disposed on the side farther away from the display area; The first sub-metal layer includes a first outer common electrode, and the second sub-metal layer includes a first inner common electrode; At least one third via and at least one fourth via are provided in the first insulating layer; wherein the depth of the third via is less than the depth of the first via, and the depth of the fourth via is less than the depth of the second via, and the conductive layer connects the first outer common electrode and the first inner common electrode through at least one third via and at least one fourth via.

4. The array substrate according to claim 1, characterized in that, The conductive layer includes a block structure, and / or the conductive layer includes at least one strip structure; The block structure connects the outer common electrode and the inner common electrode through at least one first through hole and at least one second through hole; and / or The strip structure connects the outer common electrode and the inner common electrode through at least one first through hole and at least one second through hole; The angle between the strip structure and the electrical test metal trace is greater than a preset angle threshold.

5. The array substrate according to claim 4, characterized in that, The strip structure is perpendicular to the electrical test metal trace.

6. The array substrate according to claim 4, characterized in that, The conductive layer includes multiple strip structures, all of which have the same width.

7. The array substrate according to claim 1, characterized in that, Multiple transition structures form multiple rows of transition structures in the first direction, and the transition structures between adjacent rows of transition structures are staggered in the second direction.

8. A display screen, characterized in that, The display screen includes the array substrate as described in any one of claims 1 to 7.

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