Voltage regulator

Abstract

The invention relates to a voltage regulator. An apparatus includes a first MOS transistor connected between a first node and a second node, a selectively activatable current source connected between the second node and a third node, and circuitry configured to control the first transistor to regulate a voltage at the second node to a first setpoint value. The apparatus also includes a second MOS transistor connected between the first node and the fourth node and having a gate connected to a gate of the first MOS transistor, a third MOS transistor connected between the third node and the fourth node, a switch connected between the second node and a fourth node; and another circuit configured to control the third transistor to regulate the voltage at the fourth node to a second setpoint value.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French patent application No. 2309122 filed on August 30, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure generally relates to electronic circuits, such as integrated electronic circuits, and more particularly to circuits configured to receive a first supply voltage and deliver a second supply voltage based on the first supply voltage, such circuits being referred to as, for example, voltage regulators. Background Art

[0004] Many known electronic systems are powered by a first direct current (DC) voltage received, for example, on a power pad of the system. In order to power all or part of the internal circuits they include with a second DC supply voltage having a value lower than the first voltage, these known systems include a voltage regulator configured to generate a second DC voltage based on the first DC voltage.

[0005] During stages of use of these known systems, for example during a development phase and / or during a testing phase at the end of manufacturing, it may be desirable to know the current drawn by these systems from a voltage source delivering a first voltage, for example in order to estimate the power consumption of internal circuits of the system powered by a second voltage.

[0006] During other use phases of these known systems, such as during the phase in which the system is used by an end user and / or during the phase in which the system is deployed in its application environment, it may be desirable that the current drawn by these systems from the voltage source delivering the first voltage is constant, for example in order to mask the power consumption of the internal circuits of the system powered by the second voltage. This makes it possible, for example, to avoid an attacker from accessing confidential information based on knowledge of the power consumption of the circuits powered by the second voltage (a process sometimes referred to in the art as a side channel attack).

[0007] There exists a need to overcome all or part of the disadvantages of known voltage regulators.

[0008] For example, there is a need to overcome all or part of the disadvantages of known voltage regulators configured to receive a first supply DC voltage and deliver a second supply DC voltage based on the first DC supply voltage, the second voltage having a value lower than the first voltage.

[0009] For example, there is a need for a voltage regulator that can operate alternately in a first mode in which a current drawn from a voltage source delivering a first voltage varies with a current drawn by a powered circuit, and in a second mode in which the current drawn from the voltage source is constant.

[0010] For example, there exists a need to overcome all or part of the disadvantages of known regulators capable of operating alternately according to the above-mentioned first and second modes.

[0011] There exists a need to overcome all or part of the disadvantages of known voltage regulators. Summary of the invention

[0012] An embodiment provides a device comprising: a first MOS transistor connected between a first node and a second node configured to receive a first power supply voltage; a selectively activatable current source connected between the second node and a third node configured to receive a reference potential; a first circuit configured to control the first transistor to adjust the voltage of the second node to a first set point value at least partially determined by the first set point voltage; a second MOS transistor connected between the first node and a fourth node, and a gate thereof connected to the gate of the first transistor; a third MOS transistor connected between the fourth node and the third node; a switch connected between the second node and the fourth node; and a second circuit configured to control the third transistor to adjust the voltage of the fourth node to a second set point value at least partially determined by the second set point voltage.

[0013] According to an embodiment, the fourth node is configured to deliver a second supply voltage whose value is determined by the first set point value when the switch is turned on and whose value is determined by the second set point value when the switch is turned off.

[0014] According to an embodiment, the first circuit includes: a first resistive voltage divider bridge connected between a second node and a third node; and an error amplifier configured to receive a first set point voltage and a voltage at an intermediate node of the first bridge, and to supply a voltage determined by a difference between the two received voltages to the gate of the first transistor.

[0015] According to an embodiment, the second circuit includes: a second resistance bridge connected between a fourth node and a third node; and an error amplifier configured to receive a second set point voltage and a voltage of an intermediate node of the second bridge and supply a voltage determined by a difference between the two received voltages to the gate of the third transistor.

[0016] According to an embodiment, a ratio of an aspect ratio of the first transistor to an aspect ratio of the second transistor is larger than 1, preferably larger than 100, for example approximately 300.

[0017] According to an embodiment, the device further comprises a control circuit configured to: in a first operation mode, deactivate the second circuit and the current source and control the switch to an on state; and in a second operation mode, activate the second circuit and the current source and control the switch to an off state.

[0018] According to an embodiment, the first circuit and the second circuit are configured such that a first set point value in the first mode in a stable state is equal to a second set point value in the second mode in a stable state.

[0019] According to an embodiment, the control circuit is also configured to perform the following in sequence during a transition from a first operating mode to a second operating mode: controlling the second circuit so that the second set point value is higher than the first set point value; activating a current source; controlling the switch to switch to an off state to switch from the first operating mode to the second operating mode; and controlling the second circuit so that the second set point value is equal to the first set point value.

[0020] According to an embodiment: the first transistor and the second transistor have the same type of channel; and the third transistor has a channel of a type opposite to the channel types of the first transistor and the second transistor.

[0021] According to an embodiment, the first power supply voltage and the second power supply voltage are positive with respect to a reference potential, and the first transistor has a P channel.

[0022] According to an embodiment, the current source includes a resistive element connected in series with the switch between the second node and the third node.

[0023] Another embodiment provides an integrated circuit chip comprising: a device such as described above; a pad configured to receive a first power supply voltage, which corresponds to the power supply voltage of the chip; and an integrated circuit connected to a fourth node, which is configured to be powered by a voltage available on the fourth node of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of this disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0025] Figure 1 An example of an integrated circuit chip including a voltage regulator is schematically shown in block form;

[0026] Figure 2 An example of a voltage regulator is shown; and

[0027] Figure 3 An example of an embodiment of a voltage regulator is shown. DETAILED DESCRIPTION

[0028] Similar features in the various figures are denoted by similar reference numerals. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the embodiments are illustrated and described in detail. In particular, various known electronic circuits that can be used with the voltage regulator for supplying the supply voltage thereto are not described in detail, and the embodiments of the voltage regulator described below are compatible with these known circuits.

[0030] Unless otherwise indicated, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0031] In the following description, when terms that define absolute positions, such as terms "edge", "back", "top", "bottom", "left", "right", etc., or terms that define relative positions, such as terms "above", "below", "upper", "lower", etc., or terms that define directions, such as terms "horizontal", "vertical", etc., are mentioned, unless otherwise specified, they refer to the orientation of the drawing.

[0032] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "around" mean plus or minus 10%, preferably plus or minus 5%.

[0033] Figure 1 An example of an integrated circuit chip 1 including a voltage regulator REG is schematically shown in block form.

[0034] The chip 1 includes input / output pads, each of which is configured to receive a signal originating from outside the chip 1 and / or to transmit a signal to the outside of the chip 1. Figure 1 In the embodiment, the pad 100 is configured to receive a DC power supply voltage VCC. The voltage VCC is provided by a device external to the chip 1 and at Figure 1 A voltage source not shown in the figure is supplied to the pad 100 .

[0035] The chip 1 includes at least one integrated circuit IC configured to be powered by a DC power supply voltage VDD, the value of the voltage VDD being lower than the value of the voltage VCC.

[0036] To this end, chip 1 includes a voltage regulator REG. Regulator REG is configured to receive voltage VCC and deliver voltage VDD based on voltage VCC. Therefore, regulator REG includes: node 102, which corresponds to the input end of circuit REG and is configured to receive voltage VCC; and node 104, which corresponds to the output end of circuit REG and is configured to deliver voltage VDD. For example, input end 102 of circuit REG is connected to pad 100 of chip 1. For example, output end 104 of circuit REG is connected to input end 106 of circuit IC, and input end 106 is configured to receive voltage VDD for powering circuit IC.

[0037] As an example, the chip 1 further comprises a pad 107 configured to receive a reference potential GND (eg ground).

[0038] The voltages VCC and VDD are, for example, referenced to the potential GND. For example, the circuit REG includes a node 108, which corresponds to the input terminal of the circuit REG and is configured to receive the potential GND, and the node 108 is, for example, connected to the pad 107. For example, the circuit IC includes a node 110, which corresponds to the input terminal of the circuit IC and is configured to receive the potential GND, and the node 110 is, for example, connected to the pad 107.

[0039] In this example, voltages VCC and VDD are positive.

[0040] As previously described, it is desirable that, in the first operating mode of REG, the current drawn by circuit REG from pad 100 for delivering voltage VDD varies with the power consumption of circuit IC; that is, varies with the current drawn by circuit IC powered by voltage VDD from output 104 of circuit REG. It is also desirable that, in the second operating mode of circuit REG, the current drawn by circuit REG from pad 100 for providing voltage VDD is constant and therefore has nothing to do with the power consumption of circuit IC powered by voltage VDD. In other words, it is desirable that circuit REG can operate according to the first mode during the first operating phase and according to the second operating mode during the second operating phase. In yet other words, it is desirable that circuit REG can operate alternately according to the first and second operating modes.

[0041] Although in Figure 1 Only two input / output pads 100 and 107 are shown in the example of FIG. 1 , but in practice, the chip 1 may include many other input / output pads.

[0042] In addition, although Figure 1 In the example shown, only one circuit IC is powered by the voltage VDD, but in other examples not shown, multiple integrated circuits of chip 1 are powered by the same voltage VDD, and then all of these circuits are coupled (eg, connected) to the node 104 of the circuit REG.

[0043] Figure 2 An example of a voltage regulator REG1 that can be used as the regulator REG in the chip 1 is shown.

[0044] Therefore, circuit REG1 includes node 102 configured to receive voltage VCC, node 104 configured to deliver voltage VDD, and node 108 configured to receive reference potential GND. As an example, nodes 102, 104 and 108 correspond to an input terminal, an output terminal and an input terminal of circuit REG1, respectively.

[0045] Circuit REG1 also includes a first voltage regulator 200, for example referred to herein as a series regulator. Regulator 200 is configured to deliver voltage VDD based on voltage VCC when it is activated (for example, by a control circuit not shown and forming part of circuit REG1). Thus, regulator 200 is connected to nodes 102 and 108 to receive voltage VCC, and is connected to node 104 to deliver voltage VDD.

[0046] More specifically, regulator 200 includes a MOS transistor P1 and a control circuit 202 configured to control transistor P1. Transistor P1 is connected between nodes 102 and 104. For example, a source of transistor P1 is connected to node 102, and a drain thereof is connected to node 104. In this example where voltages VCC and VDD are positive, transistor P1 has a P channel, or in other words, transistor P1 is a PMOS transistor.

[0047] The circuit 202 for controlling the transistor P1 is configured to control the transistor P1 (ie, to deliver a control voltage on the gate of the transistor P1 ) such that the voltage VDD is at a value equal to the set point value when the regulator 200 is active.

[0048] For regulator 200, the set point value of voltage VDD is at least partially determined by set point voltage V1. Voltage V1 is a DC voltage.

[0049] In this example, circuit 202 includes a resistor bridge 204 connected between nodes 104 and 108. Resistor bridge 204 is configured to deliver a feedback voltage V1fb, the value of which is determined by the value of voltage VDD. Figure 2 In the example of FIG. 1 , the resistor bridge 204 includes two resistor elements R1 and R2 connected in series between nodes 104 and 108, element R1 is connected to node 104, and voltage V1fb is available at the node connecting element R1 to element R2. In other examples not shown, bridge 204 may include more than two resistor elements. When circuit 202 includes Figure 2When the resistor divider bridge 204 is used, the resistance value of the resistor elements of the bridge 204 and the middle node of the bridge 204 (i.e., the node connected between the two resistor elements of the bridge 204 where the voltage V1fb is obtained) together with the voltage V1 determine the set point value of the voltage VDD of the regulator 200.

[0050] In another example not shown, the voltage VDD may be used directly as the voltage V1fb, and the circuit 202 does not include the bridge 204. In this case, the set point value of the voltage VDD of the regulator 200 is determined only by the voltage V1.

[0051] In addition, still Figure 2 In the example of , the circuit 202 includes an error amplifier 206 configured to deliver a voltage Vg1 whose value is determined by the difference between the voltages V1 and V1fb, or, more generally, to deliver a voltage Vg1 whose value is determined by the difference between the voltage VDD and its set point value. The voltage Vg1 is a control voltage applied to the gate of the transistor P1 by the circuit 202. For example, the circuit 206 is implemented by an operational amplifier having an inverting input terminal (-) receiving the voltage V1, a non-inverting input terminal (+) receiving the voltage V1fb, and an output terminal delivering the voltage Vg1.

[0052] When the regulator 200 is inactive, ie controlled to be inactive or disabled, the circuit 202 is configured such that the transistor P1 is turned off.

[0053] Circuit REG1 also includes a second voltage regulator 208, for example, referred to herein as a shunt regulator. Regulator 208 is configured to deliver voltage VDD based on voltage VCC when it is activated (e.g., by a control circuit not shown). Thus, regulator 208 is connected to nodes 102 and 108 to receive voltage VCC, and is connected to node 104 to deliver voltage VDD.

[0054] More specifically, regulator 208 includes MOS transistor N1 , control circuit 210 configured to control transistor N1 , and circuit 212 for delivering a constant current to node 104 based on voltage VCC.

[0055] Circuit 212 includes transistor P2 connected between nodes 102 and 104. For example, the source of transistor P2 is connected to node 102, and its drain is connected to node 104. In this example where voltages VCC and VDD are positive, transistor P2 has a P channel, or in other words, transistor P2 is a PMOS transistor.

[0056] Circuit 212 is configured to bias the gate of transistor P2 when regulator 208 is active (e.g., when it is activated by a control circuit not shown) so that current I1 in transistor P2 (corresponding to the current drawn from node 102) is constant. For example, circuit 212 is configured so that current I1 is equal to K times reference current Iref, where K is a positive factor. Thus, Figure 2 , transistor P2 corresponds to the second transistor of the current mirror, transistor P2 delivers the output current of the mirror, and the other transistor P3 of the mirror receives the current Iref supplied by the current source 214 of the circuit 212. The factor K is then defined by the ratio of the aspect ratio of transistor P2 to the aspect ratio of transistor P3. Of course, transistors P2 and P3 have the same type of channel, in this example a P-type channel.

[0057] More specifically, in Figure 2 In the circuit 212, the source of the transistor P3 is connected to the node 102, the gate thereof is connected to the gate of the transistor P2, and the drain thereof is connected to its gate and to a terminal of the current source 214, the other terminal of the current source 214 being connected to the node 108. In other words, the transistors P2 and P3 are assembled into a current mirror, the transistor P3 and the current source 214 are connected in series between the nodes 102 and 108, and the gate and the drain of the transistor P3 are connected to each other.

[0058] Transistor N1 is connected between node 104 and node 108. For example, the source of transistor N1 is connected to node 108, and the drain thereof is connected to node 104. The type of the channel of transistor N1 is opposite to the type of the channel of transistor P2. Therefore, in this example where voltages VCC and VDD are positive, transistor N1 has an N channel, or in other words, transistor N1 is an NMOS transistor.

[0059] Control circuit 210 of transistor N1 is configured to control transistor N1 (ie, deliver a control voltage on the gate of transistor N1 ) when regulator 208 is active such that voltage VDD is at a value equal to a set point value.

[0060] For regulator 208, the set point value of voltage VDD is at least partially determined by set point voltage V2. Voltage V2 is a DC voltage.

[0061] In this example, circuit 210 includes a resistor bridge 216 connected between nodes 104 and 108. Resistor bridge 216 is configured to deliver a feedback voltage V2fb, the value of which is determined by the value of voltage VDD. Figure 2In the example of FIG. 1 , the resistor bridge 216 includes two resistor elements R3 and R4 connected in series between nodes 104 and 108, element R3 is connected to node 104, and voltage V2fb is available at the node connecting element R3 to element R4. In other examples not shown, bridge 216 may include more than two resistor elements. When circuit 210 includes Figure 2 When the resistor divider bridge 216 is used, the resistance value of the resistor elements of the bridge 216 and the middle node of the bridge 216 (i.e., the node connected between the two resistor elements of the bridge 216 where the voltage V2fb is obtained) together with the voltage V2 determine the set point value of the voltage VDD of the regulator 208.

[0062] In another example not shown, the voltage VDD may be used directly as the voltage V2fb, and the circuit 210 does not include the bridge 216. In this case, the set point value of the voltage VDD of the regulator 208 is determined only by the voltage V2.

[0063] In addition, still Figure 2 In the example of , the circuit 210 includes an error amplifier 218 configured to deliver a voltage Vg2 whose value is determined by the difference between the voltages V2 and V2fb, or, more generally, to deliver a voltage Vg2 whose value is determined by the difference between the voltage VDD and its set point value. The voltage Vg2 is a control voltage applied to the gate of the transistor N1 by the circuit 210. For example, the circuit 218 is implemented by an operational amplifier having an inverting input terminal (-) receiving the voltage V2, a non-inverting input terminal (+) receiving the voltage V2fb, and an output terminal delivering the voltage Vg2.

[0064] When the regulator 208 is inactive, ie controlled to be inactive or disabled, the circuit 212 is configured such that the transistor N1 is turned off and further, the current source 214 is disabled, or in other words, turned off.

[0065] A circuit not shown forming part of regulator REG1 for controlling regulators 200 and 208 is configured to: activate regulator 200 and deactivate regulator 208 when circuit REG1 is in a first operating mode, in which the current drawn from node 102 varies as the power consumption of the load connected to node 104 varies; and activate regulator 208 and deactivate regulator 200 when circuit REG1 is in a second operating mode, in which the current drawn from node 102 must be constant regardless of how the power consumption of the load connected to node 104 varies.

[0066] Therefore, circuit REG1 effectively enables voltage VDD to be delivered based on voltage VCC, so that in the first operating mode the current drawn from node 102 varies with the power consumption of the load powered by voltage VDD, and so that in the second operating mode the current drawn from node 102 is constant and independent of the power consumption of the load powered by voltage VDD.

[0067] However, for this purpose, the regulator comprises two transistors P1 and P2 which are relatively large and bulky with respect to the transistor P3. In fact, these transistors P1 and P2 must be able to conduct between their terminals the maximum current that the voltage source VCC can deliver to the node 102 and therefore to the node 104. For example, for a given application, this maximum current may be of the order of 20 mA at maximum.

[0068] Therefore, it is desirable to have a voltage regulator REG2 that allows the same operation as regulator REG1 but with a reduced size.

[0069] Figure 3 An example of an embodiment of such a voltage regulator REG2 is shown.

[0070] Regulator REG2 consists of Figure 2 Therefore, unless otherwise indicated, for the same element forming part of each of regulators REG1 and REG2, all information indicated for that element when it forms part of regulator REG1 applies to that element when it forms part of regulator REG2. In addition, only the differences between regulators REG1 and REG2 are emphasized here.

[0071] Thus, regulator RGE2 includes nodes 102 , 108 and 104 .

[0072] The regulator REG2 includes a series voltage regulator 300 that is the same as the aforementioned regulator 200. Therefore, the regulator 300 includes a MOS transistor P1 and a circuit 302 for controlling the transistor P1. The circuit 302 is, for example, the same as the aforementioned circuit 202. For example, the circuit 302 includes a resistor divider bridge 204 and a circuit 206.

[0073] However, while transistor P1 is connected between nodes 102 and 104 in regulator 200 , in this embodiment, transistor P1 of regulator 300 is connected between node 102 and an intermediate node 350 .

[0074] Additionally, although circuit 302 includes bridge 204, bridge 204 is connected between nodes 350 and 108, rather than between nodes 104 and 108 as is the case in circuit REG1.

[0075] Regulator REG2 also includes a shunt voltage regulator 308, which is similar to regulator 208 in that it includes: a transistor P2, connected between nodes 102 and 104; a transistor N1, connected between nodes 104 and 108; a circuit 310 for controlling transistor N1, for example the same as control circuit 210, delivering a voltage Vg2 to the gate of transistor N1; and a current source 314.

[0076] However, regulator 308 differs from regulator 208 in that: current source 314 is connected between nodes 350 and 108; regulator 308 does not include transistor P3; and current source 314 is configured to deliver current Iref′ when it is activated (e.g., by control circuit CTRL that forms part of circuit REG2 and is configured to control regulators 300 and 308).

[0077] In practice, when the regulator 308 is active, the arrangement here uses the current source and reuses the regulator 300 to bias the gate of the transistor P2 so that a constant current I1 flows between the terminals of the transistor P2.

[0078] To this end, the regulator REG2 further includes a switch IT coupling the node 350 to the node 104. In other words, the switch IT has a conductive terminal connected to the node 350 and another conductive terminal connected to the node 104. The switch IT is controlled, for example, by the circuit CTRL. For example, when the regulator 308 is inactive, the switch IT is controlled to be in the on state, and when the regulator 308 is active, the switch IT is controlled to be in the off state.

[0079] In addition, the current source 314 is selectively activatable. In other words, the current source is alternately controlled to: a state in which the current source delivers the current Iref', when the current source 314 is turned on or activated; and a state in which the current source does not deliver the current Iref', when the current source 314 is called deactivated or turned off. As an example, the current source 314 is controlled by the circuit CTRL. For example, when the regulator 308 is active, the current source 314 is controlled to be in an active state, and when the regulator 308 is inactive, the current source 314 is controlled to be in an inactive state.

[0080] In regulator REG2, when regulator 300 is active, regulator 308 is inactive, i.e., circuit 310 is disabled, thereby controlling transistor N1 to be off, and thus current source 314 is controlled to be disabled. In this first operation mode where regulator 300 is active and regulator 308 is inactive, switch IT is controlled to be on.

[0081] As an example, in this first operating mode, in order to limit the current leakage in the bridge 216, the resistance element R4 of the bridge 216 is set to have a controllable resistance value, and then the element R4 is controlled to have its maximum resistance value, preferably making the element R4 equivalent to an open circuit.

[0082] As a variant, when the regulator 308 is inactive, a switch may be provided, which is controlled to be in an off state when the regulator 308 is inactive and to be in an on state when the regulator 308 is active. The switch may be arranged between the node 104 and the transistor N1. However, when the regulator 308 is active, this may result in a significant voltage drop across the switch, which is not desirable. The switch may also be arranged in series with the bridge 216 between the nodes 104 and 108. However, here again, this may result in a significant voltage drop across the switch, which is not desirable.

[0083] In addition, in the regulator REG2, when the regulator 308 is active, the regulator 300 is inactive. In this second operation mode in which the regulator 308 is active, the current source 314 is controlled to be in an active state, and the switch IT is controlled to be in an off state. However, in contrast to the circuit REG1 in which the circuit 202 controls the transistor P1 to be in an off state when the regulator 200 is inactive, in the circuit REG2, the control circuit 302 continues to operate and controls the transistor P1 so that the voltage on the node 350 is regulated to the set point value of the regulator 300.

[0084] In the first mode of operation, transistors P1 and P2 are connected in parallel between nodes 102 and 104, 350. Thus, both transistors P1 and P2 together deliver current to node 104, and circuit 302 controls transistor P1, and thus transistor P2, such that voltage VDD is regulated to a set point value of regulator 300, the latter being determined at least in part by the value of voltage V1.

[0085] In the second operating mode, when the set point value of the voltage VDD of the regulator 308 is equal to the set point value of the voltage VDD of the regulator 300, i.e. the situation in the steady state, for example by setting the voltages V1 and V2 to be equal and the ratio R1 / R2 to be equal to the ratio R3 / R4, the voltage at the node 350 is regulated to the same value as the voltage VDD at the node 104. Since the transistors P1 and P2 have the same gate voltage Vg1 and have the same source voltage VCC, the transistor P2 delivers a current I1 at a value determined by the current flowing through the transistor P1 and by the ratio of the aspect ratio of the transistor P2 to the aspect ratio of the transistor P1. Now, when the regulator 300 is inactive, i.e. it does not directly regulate the voltage VDD at the node 104, the current in the transistor P1 is equal to the current Iref' (if the current in the bridge 204 is neglected), or is equal to the sum of the current Iref' and the current in the bridge 204 (if the current in the bridge 204 is not neglected), then Figure 3 In the example of , this current is substantially equal to VDD / (R1+R2). Therefore, the current I1 in transistor P2 is substantially equal to K times the current in transistor P1, where K is determined by the ratio of the dimensions between transistors P1 and P2.

[0086] For example, the ratio of the aspect ratio of transistor P1 to the aspect ratio of transistor P2 is positive, e.g., greater than 100, preferably greater than or equal to 300, e.g., equal to approximately 300. Thus, when regulator 308 is active, current I1 in transistor P2 is greater than the current in transistor P1, e.g., greater than 100 times the current in transistor P1, preferably greater than or equal to 300 times the current in transistor P1, e.g., equal to approximately 300 times the current in transistor P1.

[0087] Thus, in circuit REG2, for the same value of current I1, the dimensions of transistor P2 are similar or even identical to those of transistor P2 of circuit REG1, whereas transistor P1 is smaller than transistor P1 of circuit REG1 and smaller than transistor P2 of circuit REG 2. Circuit REG2 thus includes one less large transistor than circuit REG1 and is therefore smaller in size.

[0088] According to an embodiment, due to the fact that in the second operation mode, the voltage on the node 350 is equal to the regulation voltage VDD on the node 104, the current source 314 can be implemented by a resistor R, and the current Iref' is equal to VDD / R. As an example, the resistor is connected in series with a switch, and when the source 314 is controlled to be on and off, respectively, the switch is controlled to be on and off, respectively. As an alternative example, the resistor R is a resistor with a controllable value, and when the source 314 is controlled to be inactive, the resistor R is controlled to its maximum value, which preferably corresponds to an open circuit.

[0089] According to an embodiment, in order to avoid cross conduction between the two regulators 300 and 308 during the transition from the first operation mode to the second operation mode, the following method is implemented, for example, by the circuit CTRL.

[0090] In an initial step, the regulator 300 is active and the regulator 308 is inactive. Therefore, the switch IT is on, the current source 314 is inactive or off, and the circuit 310 controls the transistor N1 to be in the on state.

[0091] In the next step, the set point value of the voltage VDD of the regulator 310 is modified so that when the regulator 308 is to be switched to the active state, it will attempt to regulate the value of the voltage on the node 104 to a value that is higher than the value to which the regulator 300 regulates the voltage VDD on the node 104. In other words, the set point value of the voltage VDD of the regulator 308 is set to a value that is higher than the set point value of the voltage VDD of the regulator 300. Therefore, the transistor N1 is then controlled by the circuit 310 to the off state.

[0092] As an example, the set point value of the voltage VDD of the regulator 308 is modified by correspondingly modifying the value of the voltage V2 .

[0093] As an alternative example, in an embodiment where the two bridges 204 and 216 are identical and the voltage V1fb is taken from the middle node of the bridge 204 (corresponding to the middle node of the bridge 216 from which the voltage V2fb is taken), in order to avoid having to generate two different set point voltages V1 and V2, the set point value of the voltage VDD of the regulator 308 is modified by modifying the resistance value of one of the resistance elements of the bridge 216. For example, when the voltages V1 and V2 are equal and the elements R1 and R3 have the same resistance value, if the elements R2 and R4 have the same resistance value, then the set point value of the voltage VDD of the two regulators 300 and 308 is the same, and if the resistance value of the resistance element R4 is less than the resistance value of the resistance element R2, then the set point value of the voltage VDD of the regulator 308 will be higher than the set point value of the voltage VDD of the regulator 300.

[0094] In the next step, the current source 314 is switched to the active state and starts delivering the current Iref′.

[0095] In the next step, the regulator 308 is switched to the active state. Since the set point value of its voltage VDD is higher than the set point value of the voltage VDD of the regulator 300, as described above, the transistor N1 remains controlled to the off state.

[0096] Then, the regulator 300 is switched to the deactivated state by turning off the switch IT. As a result, the voltage VDD on the node 104 increases to reach the set point value of the voltage VDD of the regulator 308.

[0097] Before or when the voltage VDD reaches the set point value, the set point value of the voltage VDD of the regulator 308 is modified again to be equal to the set point value of the voltage VDD of the regulator 300 .

[0098] It should be noted that embodiments of the method for transitioning from the first operating mode to the second operating mode described for circuit REG2 may be implemented in connection with Figure 2 The described circuit REG1 is adapted and implemented in an example, for example, as follows.

[0099] In an initial step, regulator 200 is active and regulator 208 is inactive.

[0100] In the next step, the set point value of the voltage VDD of the regulator 208 is set to a value higher than the set point value of the voltage VDD of the regulator 200 .

[0101] In the next step, the regulator 208 is switched to the active state. Due to the fact that the set point value of the voltage VDD of the regulator 208 is higher than the set point value of the voltage VDD of the regulator 200 , the transistor N1 is kept off by the circuit 210 .

[0102] In the next step, the regulator 200 is switched to the inactive state. Thus, the voltage VDD at the node 104 increases to reach the set point value of the voltage VDD of the regulator 208.

[0103] Before or when the voltage VDD reaches the set point value, the set point value of the voltage VDD of the regulator 208 is modified again to be equal to the set point value of the voltage VDD of the regulator 200 .

[0104] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that those skilled in the art will appreciate other variations. In particular, although examples have been described in which voltages VCC and VDD are positive and transistors P1 and P2 have P channels and transistor N1 has an N channel, in other examples not shown, voltages VDD and VCC are negative, and the absolute value of voltage VDD is less than the absolute value of voltage VCC. In this case, transistors P1 and P2 have N channels and transistor N1 has a P channel. If necessary, those skilled in the art will be able to adjust the implementation of circuits 302 and 310, for example, by inverting the voltages entering the inverting and non-inverting inputs of circuits 206 and 218, if necessary.

[0105] In addition, although not described in detail, according to the embodiment, the regulator REG2 is implemented in the chip 1 instead of the regulator REG.

[0106] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A device comprising: a first MOS transistor connected between a first node configured to receive a first power supply voltage and a second node; a selectively activatable current source connected between the second node and a third node configured to receive a reference potential; a first circuit configured to control the first transistor to regulate the voltage of the second node to a first set point value determined at least in part by a first set point voltage; a second MOS transistor connected between the first node and the fourth node; wherein the gate of the second MOS transistor is connected to the gate of the first MOS transistor; a third MOS transistor connected between the fourth node and the third node; a switch connected between the second node and the fourth node; as well as The second circuit is configured to control the third transistor to adjust the voltage of the fourth node to a second set point value determined at least in part by the second set point voltage.

2. The apparatus of claim 1 , wherein the fourth node is configured to deliver a second supply voltage, the value of the second supply voltage being determined by the first set point value when the switch is turned on, and the value of the second supply voltage being determined by the second set point value when the switch is turned off.

3. The apparatus of claim 1 , wherein the first circuit comprises: A first resistor divider bridge connected between the second node and the third node; as well as The error amplifier is configured to receive the first set point voltage and the voltage of the middle node of the first resistor divider bridge and supply a voltage determined by a difference between the two received voltages to the gate of the first MOS transistor.

4. The apparatus of claim 1 , wherein the second circuit comprises: A second resistor divider bridge is connected between the fourth node and the third node; as well as The error amplifier is configured to receive the second set point voltage and the voltage of the middle node of the second resistor divider bridge and supply a voltage determined by a difference between the two received voltages to the gate of the third MOS transistor. 5 . The device of claim 1 , wherein a ratio of an aspect ratio of the first MOS transistor to an aspect ratio of the second MOS transistor is greater than 1. 6 . The device of claim 1 , wherein a ratio of an aspect ratio of the first MOS transistor to an aspect ratio of the second MOS transistor is greater than 100. 7 . The device of claim 1 , wherein a ratio of an aspect ratio of the first MOS transistor to an aspect ratio of the second MOS transistor is approximately 300.

8. The apparatus according to claim 1, further comprising a control circuit, wherein the control circuit is configured to: In the first operation mode, the second circuit and the current source are disabled, and the switch is controlled to be in an on state; and In the second operation mode, the second circuit and the current source are activated, and the switch is controlled to be in an off state. 9 . The apparatus of claim 8 , wherein the first circuit and the second circuit are configured such that a first set point value in the first mode in a stable state is equal to a second set point value in the second mode in a stable state.

10. The apparatus of claim 9, wherein the control circuit is further configured to sequentially perform the following during transition from the first operation mode to the second operation mode: controlling the second circuit so that the second set point value is higher than the first set point value; Activate the current source; Controlling the switch to switch to an off state to switch from the first operation mode to the second operation mode; as well as The second circuit is controlled so that the second set point value is equal to the first set point value.

11. The device according to claim 1, wherein: The first MOS transistor and the second MOS transistor have the same type of channel; and The third MOS transistor has a channel of a type opposite to those of the first MOS transistor and the second MOS transistor.

12. The device of claim 11, wherein the first power supply voltage and the second power supply voltage are positive with respect to a reference potential, and the first MOS transistor has a P channel.

13. The apparatus of claim 1, wherein the selectively activatable current source comprises a resistive element connected in series with the switch between the second node and the third node.

14. An integrated circuit chip, comprising: The device according to claim 1; a pad configured to receive a first power supply voltage, the first power supply voltage corresponding to a power supply voltage of the integrated circuit chip; as well as An integrated circuit is connected to the fourth node, the integrated circuit being configured to be powered by a voltage available at the fourth node of the apparatus.

15. An apparatus comprising: a series regulator circuit having a first input terminal coupled to a power supply voltage node, a first output node outputting a first regulated voltage, and a second input node coupled to a ground node; A shunt regulator circuit having an input terminal coupled to a power supply voltage node, a second output node outputting a second regulated voltage, and a second input node coupled to a ground node; a switch that selectively connects the first output node to the second output node; a selectively activatable current source coupled between the first output node and a ground node; as well as A control circuit is configured to control the operation of the device by: enabling the series regulator circuit, enabling the selectively activatable current source and closing the switch to provide a regulated output voltage of the device from the series regulator circuit; as well as The shunt regulator circuit is enabled and the switch is opened to provide a regulated output voltage of the device from the shunt regulator circuit.

16. The device according to claim 15: wherein the series regulator circuit includes a first MOS transistor coupled between a power supply voltage node and a first output node; wherein the shunt regulator circuit includes a second MOS transistor coupled between the power supply voltage node and the second output node; as well as The gate of the second MOS transistor is connected to the gate of the first MOS transistor.

17. The apparatus of claim 16, wherein the first regulation voltage is controlled by a voltage applied to a gate of the first MOS transistor by a first error amplifier circuit.

18. The device according to claim 17: The shunt regulator circuit further includes a third second MOS transistor coupled between the second output node and the ground node; and The second regulation voltage is controlled by a voltage applied to the gate of the third MOS transistor by the second error amplifier circuit.

19. The device of claim 16, wherein a ratio of an aspect ratio of the first MOS transistor to an aspect ratio of the second MOS transistor is greater than 1. 20 . The device of claim 16 , wherein a ratio of an aspect ratio of the first MOS transistor to an aspect ratio of the second MOS transistor is greater than 100.

21. The device of claim 16, wherein a ratio of an aspect ratio of the first MOS transistor to an aspect ratio of the second MOS transistor is approximately 300.

22. The apparatus of claim 15, wherein the selectively activatable current source comprises a resistive element connected in series with the switch between the first output node and a ground node.

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