IMA system and method for realizing deterministic large-capacity high-speed storage

Abstract

The present invention relates to an integrated modular avionics IMA system comprising a main computing module comprising: a plurality of IMA partitions, where each IMA partition comprises an application; the hardware resources comprise a processor and a memory; the IMA system also includes a storage module configured outside the main computing module and communicatively coupled with the main computing module, where a memory of the main computing module and the storage module form a memory mapping, where the memory mapping is defined by the memory of the main computing module and the storage module. And the operation of the main calculation module on the memory can cause the storage module to execute the corresponding operation.

Description

Technical Field

[0001] The present invention generally relates to an integrated modular avionics (IMA) system, and more particularly, to an IMA system implementing deterministic large-capacity high-speed storage and a method of implementing deterministic large-capacity high-speed storage in an IMA system. Background Art

[0002] Since its birth, avionics systems have gone through a development process from discrete, joint, integrated to highly integrated, from independent subsystems to a modular and highly integrated hierarchical architecture. The Integrated Modular Avionics (IMA) system architecture is the mainstream architecture model of today's avionics systems. The use of reconfigurable universal modules to build complex avionics systems helps to improve system availability, increase system robustness, and significantly reduce system size, power consumption, and life cycle costs. The design concept of standardized modules puts forward new requirements for avionics systems, that is, in terms of software design, it needs to comply with the ARINC 653 standard.

[0003] With the rapid development of avionics technology, the resolution and sampling rate have been greatly improved, which has brought about the need for high-speed storage and reading and writing of large-capacity data. Based on the current market storage technology, when considering the storage and reading and writing needs of large files, NAND Flash is generally considered as the storage medium. However, when the NAND Flash-based storage system is running in a system based on the ARINC653 standard, the following problems may occur:

[0004] 1. Write and erase operations on NAND Flash, because of its bus and Flash characteristics, will affect the certainty and integrity of the partition operation based on the ARINC653 standard;

[0005] 2. NAND Flash has bad block problems. Bad block management and block movement required during normal programming will also affect the time of each operation, causing uncertainty in the operation of ARINC 653 partitions.

[0006] 3. Directly operating and maintaining NAND Flash in the ARINC 653 partition may cause blocking due to waiting for the completion response from NAND Flash, thus affecting the operating efficiency of the ARINC 653 system.

[0007] The article "Design of an Airborne High-Security and High-Reliability Data Storage Module" published in the journal "Electronic Optics and Control" introduces a design of data storage in an IMA system based on NAND Flash. Specifically, Figure 1A schematic diagram of the system architecture of "A Design of an Airborne High-Security and High-Reliability Data Storage Module" is shown. The IMA computing module 102 may, for example, comply with the ARINC 653 standard. The IMA computing module 103 may include multiple partitions, such as partition 1 104a, partition 2 104b, ..., partition n 104n). Each partition may include an application. These applications may constitute the application layer of the IMA computing module 102. Each partition is in the user mode 104 of the IMA core computing module 102. The IMA computing module 102 may also include an operating system layer 108, a module support layer 112, and an OEM hardware platform layer 116, which are in the kernel mode 106 of the IMA computing module 102. NAND Flash 118 resides in the OEM hardware platform layer 116. The module support layer 112 includes a Flash driver 114, which is the lowest-level driver that directly operates the OEM hardware chip. The operating system layer 108 includes a FlashFX layer 110, which may, for example, be used to implement bad block management and wear leveling of NAND Flash.

[0008] However, this design does not solve the determinism and high integrity issues of the NAND Flash-based storage system when it runs in the IMA system based on the ARINC 653 standard. In addition, this design directly operates and maintains the NAND Flash in the system partition, so as mentioned above, in this case, it may be blocked due to waiting for the completion response of the Flash, which can seriously affect the operating efficiency of the system. Summary of the invention

[0009] Some embodiments of the present invention relate to an integrated modular avionics IMA system, comprising: a main computing module, the main computing module comprising: multiple IMA partitions, each IMA partition comprising an application; hardware resources, the hardware resources comprising a processor and a memory; the IMA system further comprises: a storage module, the storage module is configured outside the main computing module and is communicatively coupled to the main computing module, wherein the memory of the main computing module forms a memory mapping with the storage module, so that the operations performed by the main computing module on its memory can cause the storage module to perform corresponding operations.

[0010] Some embodiments of the present invention relate to a method for memory operation of an integrated modular avionics IMA system, comprising: an application in a partition of a main computing module sends an operation request to the memory of the main computing module, the operation request causing the memory of the main computing module to change; a storage module that communicates with the main computing module and is located outside the main computing module detects corresponding changes in the memory of the storage module, wherein the memory of the main computing module forms a memory mapping with the storage module; and the storage module performs corresponding operations on a flash memory installed on the storage module in response to the changes in its memory.

[0011] Some embodiments of the present invention relate to a method for memory operations of an integrated modular avionics IMA system, comprising: scanning, by a storage module located outside a main computing module of the IMA system, a memory of the storage module to obtain an operation request in the memory of the storage module that is mapped from a memory of the main computing module, and executing, by the storage module, a corresponding operation on a flash memory mounted on the storage module in response to detecting the operation request in the memory of the storage module.

[0012] Some embodiments of the present invention relate to a machine-readable storage medium having instructions stored thereon, which, when executed, cause an integrated modular avionics IMA system to perform any of the methods described above.

[0013] Some embodiments of the present invention relate to an integrated modular avionics IMA system, comprising a device for executing any of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to further illustrate the various features and advantages of various embodiments of the present invention, a more specific description of the preferred embodiments of the present invention will be presented with reference to the accompanying drawings. It should be understood that these drawings may only describe typical embodiments of the present invention and are therefore not to be considered as limiting the scope of protection claimed by the present invention.

[0015] In addition, the drawings show main connection relationships or relative positional relationships of the components, rather than all of these relationships, and the components and connections in the drawings are not necessarily drawn according to actual proportions.

[0016] Figure 1 A structural block diagram of a typical IMA computing module based on NAND Flash is shown.

[0017] Figure 2 A schematic diagram of an IMA system capable of implementing deterministic high-speed storage according to an embodiment of the present invention is shown.

[0018] Figure 3 The embodiment according to the present invention is shown Figure 2 Schematic diagram of the details between the IMA main computing module and the storage modules residing outside it.

[0019] Figure 4 A timing diagram of a main computing module and a storage module block according to an embodiment of the present invention is shown.

[0020] Figure 5 A method for implementing deterministic high-speed storage in an IMA system according to an embodiment of the present invention is shown.

[0021] Figure 6 Another method for implementing deterministic high-speed storage in an IMA system according to an embodiment of the present invention is shown.

[0022] Figure 7 A machine-readable medium according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0023] The following detailed description is made with reference to the accompanying drawings. The accompanying drawings illustrate by way of example specific embodiments in which the claimed subject matter may be practiced. It should be understood that the following specific embodiments are intended to provide a specific description of typical examples for the purpose of illustration, but should not be understood as limiting the present invention; those skilled in the art may make appropriate modifications and adjustments to the disclosed embodiments on the premise of fully understanding the spirit and purpose of the present invention without departing from the spirit and scope of the claimed subject matter of the present invention.

[0024] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of each described embodiment. However, it will be apparent to one of ordinary skill in the art that the various embodiments described can be practiced without these specific details. In other instances, well-known structures are not described in detail to avoid unnecessarily obscuring aspects of the embodiments. Unless otherwise defined, the terms used herein shall have the same meanings as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs.

[0025] The IMA architecture is widely used in aircraft avionics systems. The IMA architecture is a layered architecture in which the program part including code and data is partitioned to ensure the reliability of the entire system operation.

[0026] Spatial partitioning ensures that applications in a partition cannot write to the memory or data of applications running in different partitions. Each partition is isolated from each other through an isolation mechanism, so that each partition has independent memory space, can independently use the processing resources of the IMA computing module, and has an independent running context, that is, the data and operations of each partition are independent of each other.

[0027] Time partitioning consists in ensuring that activity in one partition does not affect the timing of activities in other partitions. In ARINC 653 compliant systems, time partitioning is ensured by fixed, cycle-based scheduling. The operating system maintains a Master Time Frame (MAF) of fixed duration that repeats periodically during the runtime operation of the module. Partitions are activated by allocating one or more partition windows within this Master Time Frame. The order of partition activation is defined off-line at configuration time using configuration tables. This provides a deterministic scheduling approach as partitions are provisioned with a predefined amount of time to access processor resources.

[0028] The rapidly developing Flash Memory has gradually become a solution for many storage system designs due to its small size, low cost, low power consumption, long life, vibration resistance and wide temperature adaptability. Currently, Flash chips are mainly divided into NOR Flash and NAND Flash. NOR Flash has the advantages of high reliability and fast random read speed. NAND Flash is a linear storage device suitable for storing large-capacity data and files. Therefore, NAND Flash is widely used in the development of large-capacity and high-speed storage devices.

[0029] NAND Flash uses a nonlinear macro-cell mode to read and write data in pages and erase data in blocks. Data must be erased before writing. NAND Flash chips have advantages such as large storage capacity and fast writing speed, but they also have problems such as bit flipping, limited service life, and bad blocks. NAND Flash chips will have bad blocks randomly distributed inside when they leave the factory. A bad block refers to a data unit with one or more bits in a block that cannot be operated, and new bad blocks will inevitably be added during the long-term use of the chip. Erasing and programming operations on bad blocks are not allowed because this will cause data storage errors.

[0030] The safety of avionics systems is very important. Considering the high safety of avionics systems, it is necessary to ensure the high determinism of partition operation in IMA systems. One aspect of the determinism requirement of IMA systems is that the timing of partition applications is deterministic. However, due to the above-mentioned characteristics of NAND Flash (such as bad blocks, etc.), when a NAND Flash-based storage system is running in an avionics system based on the ARINC 653 standard, it may affect the determinism and integrity of the avionics system. Therefore, corresponding measures need to be taken to ensure the determinism and integrity of the avionics system; in addition, the operating efficiency of the avionics system will also be affected by some of the above-mentioned characteristics of NAND Flash.

[0031] Based on the characteristics of the above-mentioned IMA architecture and the characteristics of NAND Flash, the present invention designs a deterministic large-capacity high-speed storage system based on the ARINC 653 operating system. The system designed by the present invention can perform fast storage operations of large-capacity data while meeting the integrity and determinism of the ARINC 653 system, and can improve the operating efficiency of the system. The following will be specifically introduced in conjunction with the accompanying drawings.

[0032] Figure 2 FIG. 4 is a schematic diagram of an IMA system capable of implementing deterministic high-speed storage according to an embodiment of the present invention. Figure 2 As shown, the solution of the present invention designs the storage module 206 to reside outside the IMA main computing module 202.

[0033] In a specific exemplary embodiment, the IMA main computing module 202 can, for example, run an ARINC 653 operating system. The IMA main computing module 202 can communicate with a storage module 206 residing outside thereof through a bus 204. A suitable bus can be used to communicatively couple the IMA main computing module 202 with the storage module 206 residing outside thereof. In a preferred embodiment of the present invention, the bus 204 may include a PCIE (PCI-Express, peripheral component interconnect express) bus, which can be used to achieve efficient and fast communication between the main computing module 202 and the storage module 206. In order to achieve such communication with the storage module 206, the IMA main computing module 202 may include a driver and an interface associated with the external storage module 206.

[0034] In a specific and preferred embodiment of the present invention, the storage module 206 can be implemented as an MCU (Microcontroller Unit). In this embodiment, the storage module 206 may include the basic structure or circuit of the MCU, however, for the purpose of brevity and convenience of description, only the part associated with the memory operation is shown in this article and the drawings. The solution of the present invention places the storage medium (including flash memory (Flash)) and all the underlying operations on Flash on the storage module 206 equipped with Flash. When the main computing module 202 needs to perform memory operations, it only needs to perform its own specific memory operations, and the rest of the underlying memory operations can be completed by the storage module 206. The storage module 206 can be plugged into the IMA main computing module 202 as an independent hardware.

[0035] The storage module 206 may be configured to execute a storage program to read the memory operation request of the main computing module 202 and complete the related operations on the Flash based on the request when necessary, as described in more detail below.

[0036] Figure 3 The embodiment according to the present invention is shown Figure 2 Schematic diagram of details between the IMA main computing module 202 in FIG. 2 and the storage module 206 residing outside the IMA main computing module 202. The IMA main computing module 202 may include multiple partitions, such as partition 1 208a, partition 2 208b, ..., partition n 208n. Among them, each partition 208a-208n is in the user mode of the IMA main computing module 202. Each partition may include a corresponding application. The applications corresponding to each partition may constitute the application layer of the IMA main computing module 202. As described above, each partition 208a, 208b, ..., 208n is isolated from each other through an isolation mechanism. The isolation of partitions from each other means that a separate memory space of the IMA main computing module 202 can be allocated to each partition, and each partition has exclusive timing of the processing resources (e.g., processor) of the IMA main computing module 202; at the same time, the operating environment (e.g., operating system) and operating context of the application in the partition may also be independent of each other. This partition isolation mechanism of the IMA main computing module 202 ensures the stability and reliability of the operation of the IMA main computing module 202 and the entire avionics system.

[0037] The IMA main computing module 202 may also include a module support layer. The module support layer is in the kernel mode of the IMA main computing module 202. The module support layer may include a storage system kernel driver 212 and some hardware resources, including processing resources (not shown), a host computer memory 214, and input / output (I / O) resources. The input / output resources may include necessary communication configurations, such as interfaces, etc. In one embodiment, the communication configuration may include PCIE and DMA (Direct Memory Access) 216 configurations. PCIE and DMA (preferably QDMA, Quick DMA) configurations may enable high-speed communication of large data between the IMA main computing module 202 and the storage module 206.

[0038] The applications in each partition 208a-208n can manage and schedule the host computer memory 214 at the module support layer through the storage system interface 218. In one embodiment, the storage system interface 218 can be an API (Application Programming Interface).

[0039] In an embodiment of the present invention, the memory 214 of the IMA main computing module 202 can be configured as a memory mapping of the storage module 206, wherein the storage module 206 is outside the IMA main computing module 202. In other words, the operation of the IMA main computing module 202 on its memory 214 can be synchronized to the memory 220 of the storage module 206 residing outside the IMA main computing module 202. The IMA main computing module 202 can form a memory mapping for the storage module 206 through PCIE and DMA configuration, so that the data mapping between the memory 220 of the storage module 206 and the memory 214 of the main computing module 202 can be realized at high speed, and the operation of the IMA main computing module 202 on its memory 214 can be synchronously mapped to the memory 220 of the storage module 206 at high speed. More specifically, the storage system kernel driver 212 of the IMA main computing module 202 can form a memory mapping for the "flash shadow" area 220 of the storage module 206 through PCIE and DMA configuration.

[0040] Figure 3 Also shown is an independent storage module 206 residing outside the IMA main computing module 202. The storage module 206 may include a control logic 224, a memory 220, and a Flash 222.

[0041] As combined Figure 2 As described, the storage module 206 may be implemented as an MCU. The MCU 206 may be equipped with a flash memory (preferably, a NAND flash memory or NAND Flash) 222. The MCU 206 may also include an MCU memory 220. The MCU memory 220 may be configured to be a shadow of the NAND Flash 222, that is, the MCU memory 220 may be a logical mapping of the NAND Flash 222. The MCU memory 220 may have data of the NAND Flash 222.

[0042] In the present invention, the memory mapping formed by the memory 214 of the main computing module 202 and the storage module 206 can be a full flash mapping or a partial mapping based on partitions (for example, mapping of partition flash memory is performed when each partition is switched). In a preferred embodiment of the present invention, a full flash mapping method can be adopted to ensure the certainty and work efficiency of the system.

[0043] In the case of full flash mapping, when the storage module 206 is initialized, for example, by powering on, the storage module 206 can read all the data of the NAND Flash 222 into the memory 220 of the storage module 206, so that the memory 220 of the storage module 206 forms an area that can be called a "flash shadow". In addition, as described above, the memory 214 of the IMA main computing module 202 can map the memory (i.e., flash shadow) 220 of the storage module 206 through the PCIE and DMA interfaces, and preferably perform full mapping. Therefore, the memory 214 of the IMA main computing module 202 can have all the data of the NAND Flash 222 outside it. The memory 220 of the storage module 206 can map the partition application of the IMA main computing module 202 to the memory 214 operation or change. If necessary, the control logic 224 of the storage module 206 can further perform related operations on the NAND Flash 222 based on the changes in the memory 220.

[0044] The control logic 224 of the storage module 206 can be configured to execute a program to detect whether there is a change in the memory 220 in its memory (flash shadow) 220 that reflects the memory operation request from the main computing module 202. Preferably, the control logic 222 of the storage module 206 can be configured to cyclically scan the changes in its memory (flash shadow) 220 to detect whether there is an operation request from the main computing module 202. The control logic 224 of the storage module 206 can be further configured to, if such a change is detected, perform corresponding operations on the NAND Flash 222 according to the changes in the memory (flash shadow) 220. In addition, the control logic 224 of the storage module 206 can be further configured to perform other underlying operations related to the flash memory, such as flash memory maintenance operations, flash memory block management, data integrity processing (such as verification), etc. In a specific embodiment, flash memory block management may include: NAND Flash initialization full data read mapping, data status polling, read and write operations, etc.; flash memory maintenance may include: NAND Flash bad block management, data erase maintenance and handling, and other general maintenance functions of NAND Flash. Therefore, in an embodiment of the present invention, all underlying operations on NAND Flash 222 can be performed by an independent storage module 206 outside the IMA main computing module 202. The underlying operations may include reading, writing, erasing, etc. of the NAND Flash 222 in the storage module 206. In addition, the underlying operations may also include additional underlying operations associated with flash memory maintenance as described above.

[0045] In a preferred embodiment, the control logic 224 of the storage module 206 may be configured to cyclically execute one or more of the above scanning memory 220 , operating Flash 222 , and performing additional underlying operations on Flash 222 in response to instructions stored in the storage module 206 .

[0046] If the corresponding applications in each partition on the IMA main computing module 202 need to perform memory operations (i.e., operate the NAND Flash 222 in the storage module 206), they can access the associated host computer memory 214, for example, by calling. The host computer memory 214 can change accordingly to reflect the operation request of the specific application. Correspondingly, the memory 220 of the storage module 206 can reflect this change of the host computer memory 214, so that the storage module 206 can receive the request from the specific application of the IMA main computing module 202 to operate the NAND Flash 222, and perform the operation on the Nand Flash 222 according to the received operation request. As an exemplary embodiment, a partition application of the IMA main computing module 202 can perform a write operation on the host computer memory 214. Since memory mapping can be performed through the bus 204, the change of this write operation of the host computer memory 214 can be synchronized to the memory 220 of the storage module 206. The storage module 206 may detect the change of its memory 220 (ie, receiving a write request), and further perform a write operation on the NAND Flash 222 according to the change. For example, the storage module 206 may perform a write operation on the NAND Flash 222 based on the storage management table of the NAND Flash.

[0047] In an embodiment of the present invention, the storage module 206 can run in parallel with the IMA main computing module 202. The applications in the partition of the IMA main computing module 202 only need to directly operate the internal host computer memory 214, without directly operating the external NAND Flash. After the applications in the partition of the IMA main computing module 202 finish the related operations on the host computer memory 214, they can continue to execute the next instruction without blocking and waiting for the NAND Flash to reply or waiting for the NAND Flash operation to complete. Therefore, in the invented solution, the IMA main computing module 202 no longer needs to allocate overhead for the operation, maintenance and management of the NAND Flash. Therefore, compared with the prior art, the solution of the present invention greatly improves the system operation efficiency.

[0048] In addition, in the solution of the present invention, NAND Flash operations that affect determinism and integrity are all completed on the storage module 206. The system only needs to configure a sufficient time window for the partition to access the main computer memory 214, without waiting for the reaction or reply of NAND Flash. This makes the time spent on memory operations (e.g., read, write, erase, etc.) of different partition applications of the IMA main computing module 202 or different memory operations of the same application basically consistent and deterministic, thereby improving the determinism of the avionics system. In the case where NAND Flash is set inside the main computing module, due to the characteristics of NAND Flash (e.g., the existence of bad blocks, etc.), the time spent on each memory operation (e.g., write operation) may be different or cannot be completed within the preset time threshold, thereby affecting the determinism of the system.

[0049] The embodiments of the present invention are mainly described in conjunction with NAND Flash. In the case where the data capacity requirement is not high, NOR Flash can also be used. The capacity of NOR Flash is smaller than that of NAND Flash. In addition, NOR Flash is limited by, for example, the CPU bus under a specific architecture. Therefore, the present invention preferably uses NAND Flash to achieve large-capacity data storage while being less restricted by the system.

[0050] Figure 4 402 is a timing diagram of a main computing module and a storage module according to an embodiment of the present invention. Timing 410 indicates an example of a timing diagram of the main computing module 402. The main computing module 402 may be Figure 2 or Figure 3 The IMA main computing module 202. Timing 420 indicates a timing diagram associated with the operation of the storage module 406. The storage module 406 may be Figure 2 or Figure 3 The storage module 206.

[0051] Timing 410 shows two memory operations of a partition application 412 of the main computing module 402. The partition application 412 may be Figure 3 The two memory operations of the partition application 412 are both to operate the memory of the main computing module 402 (for example, Figure 3 After the main computing module 402 stores the memory 214 of the host computer, the application instruction continues to be executed without waiting for the NAND Flash on the storage module 406 to reply or wait for the NAND Flash operation to complete. After receiving the memory operation request from the main computing module 402, the storage module 406 can execute the requested memory operation in parallel with the operation executed by the main computing module 402.

[0052] In the embodiment of the present invention, as described above, PCIE and DMA can be used to implement the communication between the IMA main computing module 402 and the external storage module 406, so the operation of the main computing module 402 on its memory (e.g., the main computer memory 214) will be quickly mapped to the memory of the storage module 406 (e.g., the memory 220). Therefore, the storage module 406 can receive the operation request at the same time as the partition application 412 of the main computing module 402 requests the memory operation or only after a very short time interval. In the read operation of the IMA main computing module 402 on the storage module 406, it is only necessary to directly read the memory mapping area on the main computing module 402 (e.g., Figure 3 The main computer memory 214 in the IMA main computing module 402 is affected by the speed of reading the memory (e.g., DDR), and therefore can be ignored. In the write operation of the IMA main computing module 402 to the storage module 406, it is mainly affected by the DDR write rate and the PCIE transmission rate. Among them, the PCIE transmission rate accounts for a large proportion. Taking the LS1046A CPU as an example, if the PCIE 3.0 / LANE1 configuration is used, its transmission rate can reach 984.6MB / s. Therefore, the design of the present invention can complete fast read and write operations.

[0053] The timing diagram 410 shows two memory operations applied by one of the partitions of the main computing module 402; accordingly, the timing diagram 520 shows two corresponding flash operations performed by the storage module 406. However, it should be understood that this is only exemplary and not limiting, and the main computing module 402 and the storage module 406 can perform more operations respectively. In addition, the main computing module 402 can continue to execute other instructions except the storage instruction after performing the operation on its memory without waiting for the reply of the flash memory on the storage module 406.

[0054] In the traditional solution where NAND Flash resides in the main computing module, after the partition application of the main computing module issues a memory operation request, it needs to wait for the memory operation on the NAND Flash to be completed before continuing to execute the next instruction. Figure 5 It can be seen that in the embodiment of the present invention, the operation on the NAND Flash can be independently completed by the storage module 406, and the main computing module 402 and the storage module 406 can be executed in parallel. Therefore, as described above, this not only greatly improves the operating efficiency of the system, but also improves the certainty and integrity of the system operation.

[0055] Figure 5A method 500 for implementing deterministic high-speed memory operations in an IMA system according to an embodiment of the present invention is shown. The method 500 can be executed in an IMA system. The method 500 includes, at step 502, sending an operation request to the memory of the main computing module by an application in a partition of the main computing module, so that the memory of the main computing module changes based on the request.

[0056] The method 500 also includes, at step 504, a storage module in communication with the main computing module and located outside the main computing module detecting a corresponding change in the memory of the storage module, wherein the memory of the main computing module forms a memory mapping to the storage module. The memory of the main computing module can form a memory mapping to the memory of the storage module through PCIE and DMA configuration.

[0057] In one embodiment, the storage module can be implemented as a microcontroller unit MCU. The MCU may include an MCU memory and a flash memory. The MCU memory and the flash memory may be communicatively coupled, and the memory of the main computing module may be configured to map the MCU memory. The mapping may be a full mapping or a partition-based mapping. In a preferred embodiment, a full mapping may be adopted. In one embodiment, when the storage module is initialized, the data of the flash memory may be read into the MCU memory in full, so that the MCU memory is configured as a flash shadow. Furthermore, since the memory of the main computing module is configured to fully map the MCU memory, the memory of the main computing module may have all the data of the flash memory, and the operations of the main computing module on its own memory may be quickly mapped to the MCU memory, so that the control logic of the MCU may implement the memory operations desired by the main computing module based on the changes in the MCU memory.

[0058] In a preferred embodiment, step 504 may include the storage module cyclically scanning its memory to timely obtain the operation requests from the memory mapping of the main computing module in its memory.

[0059] The method 500 may further include, at step 506, the storage module performing corresponding operations on the flash memory mounted on the storage module in response to the change in its memory. In some embodiments, the operations may be low-level operations on the flash memory, including reading, writing, erasing, etc. In additional embodiments, the method 500 may include the storage module further performing one or more low-level operations of flash block management, flash memory maintenance, and data integrity processing.

[0060] Figure 6Another method for implementing deterministic high-speed memory operations in an IMA system according to an embodiment of the present invention is shown. Method 600 can be performed by a storage module located outside the main computing module of the IMA system. Method 600 may include, at step 602, scanning the memory of the storage module by the storage module located outside the main computing module of the IMA system to obtain a memory operation request from the memory of the main computing module in the memory of the storage module. The memory of the main computing module can form a memory mapping to the memory of the storage module through PCIE and DMA configuration.

[0061] In one embodiment, the storage module can be implemented as a microcontroller unit MCU. The MCU may include an MCU memory and a flash memory. The MCU memory and the flash memory may be communicatively coupled, and the memory of the main computing module may be configured to map the MCU memory. The mapping may be a full mapping or a partition-based mapping. In a preferred embodiment, a full mapping may be adopted. In one embodiment, when the storage module is initialized, the data of the flash memory may be read into the MCU memory in full, so that the MCU memory is configured as a flash shadow. Furthermore, since the memory of the main computing module is configured to fully map the MCU memory, the memory of the main computing module may have all the data of the flash memory, and the operations of the main computing module on its own memory may be quickly mapped to the MCU memory, so that the control logic of the MCU may implement the memory operations desired by the main computing module based on the changes in the MCU memory.

[0062] In a preferred embodiment, step 602 may include the storage module cyclically scanning its memory to timely obtain the operation requests from the memory mapping of the main computing module in its memory.

[0063] The method 600 may also include, at step 604, the storage module, in response to detecting the operation request of the memory of the storage module, performing a corresponding operation on the flash memory installed on the storage module. In some embodiments, the operation may be a low-level operation on the flash memory, including reading, writing, erasing, etc. In additional embodiments, the method 600 may include the storage module further performing one or more low-level operations of flash block management, flash memory maintenance, and data integrity processing.

[0064] In method 500 or 600, the main computing module and the storage module can run in parallel. In addition, after the application in the partition of the IMA system ends the operation on the memory of the main computing module, it can continue to execute the next instruction without waiting for the reply of the flash memory residing on the storage module.

[0065] The present invention also provides a machine-readable medium. Figure 7A machine readable medium 700 is shown according to an embodiment of the present invention. The machine readable medium 700 may include instructions 710. The instructions 710, when executed, may cause the method 500 or 600 of deterministic high-speed memory operation to be implemented in an IMA system.

[0066] Therefore, it can be seen from the above description of the embodiments of the present invention that the technical solution of the present invention has the following advantages over the prior art:

[0067] Higher determinism and integrity: ARINC 653 system partition applications only need to operate the relevant memory mapping area in the main computing module, and NAND Flash operations that affect determinism and integrity are all completed on the storage module. The ARINC 653 system only needs to configure enough time windows for partitions to access memory. Therefore, the system's determinism and integrity are greatly improved;

[0068] Performance improvement: The ARINC 653 system in the main computing module no longer needs to allocate overhead for the operation, maintenance and management of NAND Flash, thus improving the system operation efficiency;

[0069] Strong maintainability: The storage module is connected to the main computing module using the PCIE interface, which is easy to plug and unplug for data maintenance and hardware replacement;

[0070] Strong scalability: The main computing module can easily and flexibly encapsulate and build storage frameworks such as file systems on the NAND Flash memory mapping operation.

[0071] Without departing from the spirit and purpose of the present invention, those skilled in the art may make appropriate modifications and adjustments to the embodiments specifically described above. Therefore, it is intended that the subject matter claimed for protection is not limited to the specific examples disclosed, and these subject matters claimed for protection may also include all implementations falling within the scope of the attached claims and their equivalents.

[0072] Some examples of the present invention are shown below:

[0073] Example 1. An integrated modular avionics IMA system, comprising:

[0074] A main computing module, the main computing module comprising:

[0075] A plurality of IMA partitions, wherein each IMA partition includes an application;

[0076] Hardware resources, including processors and memory;

[0077] a storage module, the storage module being configured outside the main computing module and communicatively coupled to the main computing module,

[0078] The memory of the main computing module forms a memory mapping with the storage module, so that the operation performed by the main computing module on its memory can cause the storage module to perform corresponding operations.

[0079] Example 2. In the IMA system of Example 1, the main computing module and the storage module are configured to be able to run in parallel.

[0080] Example 3. In the IMA system as described in any one of the above examples, the storage module is implemented as a microcontroller unit MCU, the MCU includes an MCU memory and a flash memory, the MCU memory is communicatively coupled to the flash memory, and

[0081] Among them, the memory of the main computing module is configured to map the MCU memory.

[0082] Example 4. In an IMA system as described in any of the above examples, the storage module is configured to read all the data of the flash memory into the MCU memory when initialized, so that the MCU memory is configured as a flash memory shadow, and the memory of the main computing module is configured to fully map the MCU memory.

[0083] Example 5. In an IMA system as described in any of the above examples, the MCU includes control logic, which is configured to cyclically scan the MCU memory to obtain operation requests from the memory mapping of the main computing module in the MCU memory, and perform corresponding operations on the flash memory according to the operation requests.

[0084] Example 6. In an IMA system as described in any of the above examples, the main computing module is configured to enable the application within the IMA partition to continue executing the next instruction after completing the operation on the memory of the main computing module without waiting for the flash memory of the storage module to reply.

[0085] Example 7. In the IMA system as described in any of the above examples, the flash memory comprises NAND flash memory.

[0086] Example 8. In the IMA system as described in any of the above examples, the main computing module communicates with the storage module via a PCIE bus and QDMA configuration.

[0087] Example 9. An IMA system as described in any of the above examples, wherein the operation includes reading, writing, and erasing.

[0088] Example 10. In the IMA system as described in any one of the above examples, the storage module is further configured to perform low-level operations including one or more of the following: flash block management, flash maintenance, and data integrity processing.

[0089] Example 11. A method for integrated modular avionics IMA system memory operations, comprising:

[0090] An application in a partition of a main computing module sends an operation request to a memory of the main computing module, wherein the operation request causes a change in the memory of the main computing module;

[0091] A storage module in communication with the main computing module and located outside the main computing module detects a corresponding change in a memory of the storage module, wherein the memory of the main computing module forms a memory mapping with the storage module; and

[0092] The storage module performs corresponding operations on the flash memory installed on the storage module in response to the changes in the memory thereof.

[0093] Example 12. A method for memory operations of an integrated modular avionics IMA system, comprising:

[0094] Scanning the memory of the storage module by a storage module located outside the main computing module of the IMA system to obtain an operation request from the memory mapping of the main computing module in the memory of the storage module, and

[0095] In response to detecting an operation request of the memory of the storage module, the storage module executes a corresponding operation on the flash memory mounted on the storage module.

[0096] Example 13. In the method as described in any of the above examples, the main computing module and the storage module are configured to be able to run in parallel.

[0097] Example 14. A method as described in any of the above examples, wherein the storage module is implemented as a microcontroller unit MCU, the MCU includes an MCU memory and a flash memory, the MCU memory is communicatively coupled to the flash memory, and

[0098] Among them, the memory of the main computing module is configured to map the MCU memory.

[0099] Example 15. In the method as described in any of the above examples, when the storage module is initialized, all the data in the flash memory are read into the MCU memory, so that the MCU memory is configured as a flash memory shadow, and the memory of the main computing module is configured to fully map the MCU memory.

[0100] Example 16. The method as described in any of the above examples further includes: the control logic of the MCU cyclically scans the MCU memory to obtain operation requests from the memory mapping of the main computing module in the MCU memory, and performs corresponding operations on the flash memory according to the operation requests.

[0101] Example 17. In the method as described in any of the above examples, the application within the partition of the IMA system continues to execute the next instruction after completing the operation on the memory of the main computing module without waiting for the reply of the flash memory of the storage module.

[0102] Example 18. A method as described in any of the above examples, wherein the flash memory comprises NAND flash memory.

[0103] Example 19. In the method as described in any of the above examples, the main computing module communicates with the storage module via a PCIE bus and QDMA configuration.

[0104] Example 20. A method as described in any of the above examples, wherein the operation includes reading, writing, and erasing.

[0105] Example 21. The method as described in any of the above examples further includes: the storage module performs underlying operations including one or more of the following: flash block management, flash maintenance, and data integrity processing.

[0106] Example 22. A machine-readable storage medium having instructions stored thereon, which when executed, cause an integrated modular avionics IMA system to perform the method as described in any one of Examples 11-21.

[0107] Example 23. An integrated modular avionics IMA system, comprising means for performing the method of any of Examples 11-21.

Claims

1. An integrated modular avionics IMA system, comprising: A main computing module, the main computing module comprising: A plurality of IMA partitions, wherein each IMA partition includes an application; Hardware resources, including processors and memory; a storage module, the storage module being configured outside the main computing module and communicatively coupled to the main computing module, The memory of the main computing module forms a memory mapping with the storage module, so that the operation performed by the main computing module on its memory can cause the storage module to perform corresponding operations.

2. The IMA system according to claim 1, characterized in that: The main computing module and the storage module are configured to be able to run in parallel.

3. The IMA system according to claim 1 or 2, characterized in that: The storage module is implemented as a micro control unit MCU, the MCU includes an MCU memory and a flash memory, the MCU memory is communicatively coupled to the flash memory, and Among them, the memory of the main computing module is configured to map the MCU memory.

4. The IMA system according to claim 3, characterized in that: The storage module is configured to read all the data of the flash memory into the MCU memory when initialized, so that the MCU memory is configured as a flash memory shadow, and the memory of the main computing module is configured to fully map the MCU memory.

5. The IMA system according to claim 3, characterized in that: The MCU includes control logic, which is configured to cyclically scan the MCU memory to obtain operation requests from the memory mapping of the main computing module in the MCU memory, and perform corresponding operations on the flash memory according to the operation requests.

6. The IMA system according to claim 3, characterized in that: The main computing module is configured to enable the application in the IMA partition to continue to execute the next instruction after completing the operation on the memory of the main computing module without waiting for the reply of the flash memory of the storage module.

7. The IMA system according to claim 3, characterized in that: The flash memory includes a NAND flash memory.

8. The IMA system according to claim 1 or 2, characterized in that: The main computing module communicates with the storage module via a PCIE bus and QDMA configuration.

9. The IMA system according to claim 1 or 2, characterized in that: The operations include reading, writing, and erasing.

10. The IMA system according to claim 9, characterized in that: The storage module is further configured to perform low-level operations including one or more of the following: flash block management, flash maintenance, and data integrity processing.

11. A method for memory operation of an integrated modular avionics IMA system, comprising: An application in a partition of a main computing module sends an operation request to a memory of the main computing module, wherein the operation request causes a change in the memory of the main computing module; A storage module in communication with the main computing module and located outside the main computing module detects a corresponding change in a memory of the storage module, wherein the memory of the main computing module forms a memory mapping with the storage module; as well as The storage module performs corresponding operations on the flash memory installed on the storage module in response to the changes in the memory thereof.

12. A method for memory operation of an integrated modular avionics IMA system, comprising: Scanning the memory of the storage module by a storage module located outside the main computing module of the IMA system to obtain an operation request from the memory mapping of the main computing module in the memory of the storage module, and In response to detecting an operation request of the memory of the storage module, the storage module executes a corresponding operation on the flash memory mounted on the storage module.

13. The method according to claim 11 or 12, characterized in that The main computing module and the storage module are configured to be able to run in parallel.

14. The method according to claim 11 or 12, characterized in that: The storage module is implemented as a micro control unit MCU, the MCU includes an MCU memory and a flash memory, the MCU memory is communicatively coupled to the flash memory, and Among them, the memory of the main computing module is configured to map the MCU memory.

15. The method according to claim 14, characterized in that When the storage module is initialized, all the data in the flash memory are read into the MCU memory, so that the MCU memory is configured as a flash memory shadow, and the memory of the main computing module is configured to fully map the MCU memory.

16. The method of claim 14, further comprising: The control logic of the MCU cyclically scans the MCU memory to obtain operation requests from the memory mapping of the main computing module in the MCU memory, and performs corresponding operations on the flash memory according to the operation requests.

17. The method according to claim 14, characterized in that The application in the partition of the IMA system continues to execute the next instruction after completing the operation on the memory of the main computing module without waiting for the reply of the flash memory of the storage module.

18. The method of claim 14, wherein: The flash memory includes a NAND flash memory.

19. The method according to claim 11 or 12, characterized in that: The main computing module communicates with the storage module via a PCIE bus and QDMA configuration.

20. The method according to claim 11 or 12, characterized in that The operations include reading, writing, and erasing.

21. The method of claim 20, further comprising: The storage module performs one or more of the following underlying operations: flash memory block management, flash memory maintenance, and data integrity processing.

22. A machine-readable storage medium having instructions stored thereon, which, when executed, cause an integrated modular avionics IMA system to perform the method according to any one of claims 11-21.

23. An integrated modular avionics IMA system, comprising means for executing the method according to any one of claims 11-21.

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