Storage device, storage method, chip, and electronic device

Abstract

The invention relates to the technical field of storage, and provides a storage device, a storage method, a chip and electronic equipment. The storage device comprises a data storage module, a hit judgment module and a request control module, the request control module judges the type of a memory access request, sends the memory access request of a cache type to the hit judgment module to judge the hit condition, then determines a memory access address according to the hit condition, and sends the memory access request and the memory access address to the data storage module; sending the memory access request of the direct access type and the memory access address to a data storage module; and the data storage module accesses the memory access address. According to the storage device, the data storage module is divided into the cache region and the direct access region, and the response modes of different types of access requests are controlled through the request control module, so that the storage device can realize a cache function and can also realize convenient, efficient and accurate storage space control and access, and the performance of the storage device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage device, a storage method, a chip, and an electronic device. Background Art

[0002] In a computer system, when software applications are working, the data movement cost and time cost of accessing the memory are usually relatively large. Therefore, a cache is usually set up in the system to accelerate memory access. When a software application wants to read / write data, a memory access request is generated. First, it is determined whether the memory access request hits the cache. If it hits, it means that the data to be read / written is already stored in the cache, and the data can be directly read / written to the same location in the cache. If it misses (misses), it means that the data to be read / written is not stored in the cache, and the data needs to be read from the memory and then written to the cache, or the data to be written is written to a new storage location in the cache. In this way, the data movement cost and time cost of software application memory access can be reduced.

[0003] Software programmers have a clear perception and control over the memory access behavior of software applications. They often hope to obtain a storage space that can be conveniently and accurately controlled and accessed. However, the cache in the existing technology is not convenient enough and has low memory access efficiency due to the necessary hit judgment steps. The cache has limited capacity and needs to replace the cache lines in a timely manner, which makes it difficult to achieve precise control and access. However, it is difficult to achieve the cache function when a separate storage space is opened up that can be conveniently and efficiently controlled and accessed.

[0004] Therefore, designing a storage device with better performance so that the storage device can not only realize the cache function but also realize convenient, efficient and accurate storage space control and access has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0005] In view of this, the present disclosure proposes a storage device, a storage method, a chip, and an electronic device. The storage device divides a data storage module into a cache area and a direct access area, and controls the response mode of different types of memory access requests through a request control module, so that the storage device can realize both a cache function and convenient, efficient, and accurate storage space control and access, thereby improving the performance of the storage device.

[0006] According to one aspect of the present disclosure, a storage device is provided, including a data storage module, a hit judgment module, and a request control module, wherein the data storage module includes a cache area and a direct access area, wherein the request control module is used to, in response to receiving a memory access request, judge the type of the memory access request, send the cache type memory access request to the hit judgment module, and send the direct access type memory access request and the corresponding memory access address to the data storage module, wherein the memory access address corresponding to the direct access type memory access request belongs to the direct access area; the hit judgment module is used to, in response to receiving a cache type memory access request, judge whether the memory access request hits the cache area, and send the hit status of the memory access request to the request control module; the request control module is also used to, in response to receiving a hit status of any cache type memory access request, determine the memory access address corresponding to the memory access request in the cache area, send the memory access request and the corresponding memory access address to the data storage module, wherein the memory access address corresponding to the cache type memory access request belongs to the cache area; the data storage module is used to, in response to receiving any memory access request and the corresponding memory access address, access the memory address corresponding to the memory access request according to the memory access type included in the memory access request.

[0007] In one possible implementation, a direct access type memory access request includes a first identifier, and the request control module is specifically used to, in response to receiving the memory access request, detect whether the memory access request includes the first identifier; in response to the memory access request including the first identifier, determine that the memory access request is a direct access type; in response to the memory access request not including the first identifier, determine that the memory access request is a cache type.

[0008] In one possible implementation, the memory access request also includes a request address, and the address space of the cache area and the direct access area are different. The request control module is specifically used to, in response to receiving the memory access request, detect the address space corresponding to the request address included in the memory access request; in response to the request address included in the memory access request corresponding to the address space of the direct access area, determine that the memory access request is a direct access type; in response to the request address included in the memory access request corresponding to the address space of the cache area, determine that the memory access request is a cache type.

[0009] In a possible implementation, the data storage module includes S rows and W columns of cache lines. W cache lines in each row form a group, and S cache lines in each column form a way. W and S are positive integers. When the allocation method of the data storage module is group-based allocation, the direct access area includes X rows and W columns of cache lines, and the cache area includes (S - X) rows and W columns of cache lines, where 0 < X < S and X is an integer. When the allocation method of the data storage module is way-based allocation, the direct access area includes S rows and Y columns of cache lines, and the cache area (direct access area) includes S rows and (W - Y) columns of cache lines, where 0 < Y < W and Y is an integer.

[0010] In a possible implementation, the memory access request further includes a request address. When the allocation method of the data storage module is group-based allocation, the request control module is specifically configured to, in response to the memory access request being of the cache type, parse out the group number where the cache line corresponding to the memory access request is located according to the request address, and send the group number and the memory access request to the hit determination module. The hit determination module is specifically configured to, in response to receiving a memory access request of the cache type, determine whether the memory access request hits a group of cache lines corresponding to the group number in the cache area according to the group number where the cache line corresponding to the memory access request is located, and send the hit situation of the memory access request to the request control module.

[0011] In a possible implementation, when the memory access request hits a cache line in a group of cache lines corresponding to the group number in the cache area, the hit situation of the memory access request includes the way number where the hit cache line is located. When the memory access request does not hit a group of cache lines corresponding to the group number in the cache area, the hit situation of the memory access request includes information indicating that the memory access request does not hit.

[0012] In a possible implementation, the request control module is specifically configured to, in response to the information indicating that the memory access request does not hit, select another group of cache lines from the cache area; detect whether there is data to be written to another storage device in the selected group of cache lines; in response to detecting data to be written to another storage device, write the data to another storage device and then use the selected group of cache lines to replace the group of cache lines corresponding to the group number; in response to not detecting data to be written to another storage device, directly use the selected group of cache lines to replace the group of cache lines corresponding to the group number.

[0013] In one possible implementation, the memory access request also includes a request address. When the allocation method of the data storage module is allocation by way, the request control module is specifically used to, in response to the memory access request being a cache type, parse out the way number of the cache line corresponding to the memory access request according to the request address, and send the way number and the memory access request to the hit judgment module; the hit judgment module is specifically used to, in response to receiving a cache type memory access request, determine whether the memory access request hits a cache line corresponding to the way number in the cache area according to the way number of the cache line corresponding to the memory access request, and send the hit status of the memory access request to the request control module.

[0014] In one possible implementation, when the memory access request hits one cache line in a cache line corresponding to the way number in the cache area, the hit status of the memory access request includes the group number of the hit cache line; when the memory access request misses a cache line in the cache area corresponding to the way number, the hit status of the memory access request includes information indicating that the memory access request misses.

[0015] In one possible implementation, the request control module is specifically used to, in response to information indicating that the memory access request missed, select another cache line from the cache area; detect whether the selected cache line contains data to be written to other storage devices; in response to detecting the data to be written to other storage devices, write the data to other storage devices, and then use the selected cache line to replace the cache line corresponding to the number; in response to not detecting the data to be written to other storage devices, use the selected cache line to directly replace the cache line corresponding to the number.

[0016] In a possible implementation, the memory access request also includes a request address, and the request control module is specifically used to, in response to the memory access request being a direct access type, detect an allocation method of the data storage module, and determine whether the addressing methods of the data storage module and the memory access request are the same; in response to the addressing methods of the data storage module and the memory access request being the same, use the request address as the memory access address; in response to the addressing methods of the data storage module and the memory access request being different, decode the request address to obtain the memory access address according to the addressing methods of the data storage module and the memory access request and the allocation method of the data storage module.

[0017] In a possible implementation, the memory access request also includes a request address, and the request control module is specifically used to, in response to the memory access request being a direct access type, detect an allocation method of the data storage module, and determine whether the addressing methods of the data storage module and the memory access request are the same; use the request address to subtract the starting address of the address space of the direct access area to obtain an intermediate address; in response to the addressing methods of the data storage module and the memory access request being the same, use the intermediate address as the memory access address; in response to the addressing methods of the data storage module and the memory access request being different, decode the intermediate address to obtain the memory access address according to the addressing methods of the data storage module and the memory access request and the allocation method of the data storage module.

[0018] In one possible implementation, the request control module includes a register group, which is used to configure the allocation method of the data storage module according to the user's instructions. The request control module is also used to, in response to a reduction in the cache lines included in the cache area, suspend receiving new memory access requests and write the data stored in the reduced cache lines to other storage devices; after the writing of the data stored in the reduced cache lines is completed, continue to receive new memory access requests.

[0019] According to another aspect of the present disclosure, a storage method is provided, the method being applied to a storage device, the storage device comprising a data storage module, the data storage module comprising a cache area and a direct access area, the method comprising: in response to receiving a memory access request, determining a type of the memory access request, the type comprising a cache type and a direct access type; in response to the type of the memory access request being a cache type, determining whether the memory access request hits the cache area, and determining a memory access address corresponding to the memory access request based on the hit condition of the memory access request, the memory access address corresponding to the memory access request of the cache type belonging to the cache area; in response to the type of the memory access request being a direct access type, parsing the memory access address corresponding to the memory access request based on the memory access request, the memory access address corresponding to the memory access request of the direct access type belonging to the direct access area; and accessing the memory address corresponding to the memory access request based on the memory access type included in the memory access request.

[0020] In one possible implementation, a direct access type memory access request includes a first identifier, and in response to receiving the memory access request, determining the type of the memory access request includes: in response to receiving the memory access request, detecting whether the memory access request includes the first identifier; in response to the memory access request including the first identifier, determining that the memory access request is a direct access type; in response to the memory access request not including the first identifier, determining that the memory access request is a cache type.

[0021] In a possible implementation, the memory access request further includes a request address. The address spaces of the cache region and the direct access region are different. In response to receiving a memory access request, determining the type of the memory access request includes: in response to receiving the memory access request, detecting the address space corresponding to the request address included in the memory access request; in response to the request address included in the memory access request corresponding to the address space of the direct access region, determining that the memory access request is of the direct access type; in response to the request address included in the memory access request corresponding to the address space of the cache region, determining that the memory access request is of the cache type.

[0022] In a possible implementation, the data storage module includes S rows and W columns of cache lines. W cache lines in each row form a group, and S cache lines in each column form a way. W and S are positive integers. When the allocation method of the data storage module is group-based allocation, the direct access region includes X rows and W columns of cache lines, and the cache region includes (S - X) rows and W columns of cache lines, where 0 < X < S and X is an integer. When the allocation method of the data storage module is way-based allocation, the direct access region includes S rows and Y columns of cache lines, and the cache region includes S rows and (W - Y) columns of cache lines, where 0 < Y < W and Y is an integer.

[0023] In a possible implementation, the memory access request further includes a request address. When the allocation method of the data storage module is group-based allocation, in response to the type of the memory access request being the cache type, determining whether the memory access request hits the cache region includes: in response to the memory access request being of the cache type, parsing out the group number where the cache line corresponding to the memory access request is located according to the request address; determining whether the memory access request hits the group of cache lines corresponding to the group number in the cache region according to the group number where the cache line corresponding to the memory access request is located.

[0024] In a possible implementation, when the memory access request hits a cache line in a group of cache lines corresponding to the group number in the cache region, the hit situation of the memory access request includes the way number where the hit cache line is located. When the memory access request does not hit the group of cache lines corresponding to the group number in the cache region, the hit situation of the memory access request includes information indicating that the memory access request does not hit.

[0025] In one possible implementation, the method further includes: in response to information indicating that the memory access request missed, selecting another group of cache lines from the cache area; detecting whether there is data to be written to other storage devices in the selected group of cache lines; in response to detecting the data to be written to other storage devices, after writing the data to other storage devices, using the selected group of cache lines to replace a group of cache lines corresponding to the group number; in response to not detecting the data to be written to other storage devices, using the selected group of cache lines to directly replace a group of cache lines corresponding to the group number.

[0026] In one possible implementation, the memory access request also includes a request address. When the allocation method of the data storage module is allocation by way, the type of response to the memory access request is a cache type, and judging whether the memory access request hits the cache area includes: in response to the memory access request being a cache type, parsing the way number of the cache line corresponding to the memory access request according to the request address; judging whether the memory access request hits a cache line corresponding to the way number in the cache area according to the way number of the cache line corresponding to the memory access request.

[0027] In one possible implementation, when the memory access request hits one cache line in a cache line corresponding to the way number in the cache area, the hit status of the memory access request includes the group number of the hit cache line; when the memory access request misses a cache line in the cache area corresponding to the way number, the hit status of the memory access request includes information indicating that the memory access request misses.

[0028] In one possible implementation, the method further includes: in response to information indicating that the memory access request missed, selecting another cache line from the cache area; detecting whether the selected cache line contains data to be written to other storage devices; in response to detecting the data to be written to other storage devices, after writing the data to other storage devices, using the selected cache line to replace the cache line corresponding to the number; in response to not detecting the data to be written to other storage devices, using the selected cache line to directly replace the cache line corresponding to the number.

[0029] In a possible implementation, the memory access request also includes a request address, and in response to the type of the memory access request being a direct access type, a memory access address corresponding to the memory access request is parsed according to the memory access request, including: in response to the memory access request being a direct access type, detecting an allocation method of the data storage module, and determining whether the addressing method of the data storage module and the memory access request are the same; in response to the addressing method of the data storage module and the memory access request being the same, using the request address as the memory access address; in response to the addressing method of the data storage module and the memory access request being different, decoding the request address to obtain the memory access address according to the addressing method of the data storage module and the memory access request and the allocation method of the data storage module.

[0030] In a possible implementation, the memory access request also includes a request address, and in response to the type of the memory access request being a direct access type, a memory access address corresponding to the memory access request is parsed according to the memory access request, including: in response to the memory access request being a direct access type, detecting an allocation method of the data storage module, and determining whether the addressing methods of the data storage module and the memory access request are the same; using the request address to subtract the starting address of the address space of the direct access area to obtain an intermediate address; in response to the addressing methods of the data storage module and the memory access request being the same, using the intermediate address as the memory access address; in response to the addressing methods of the data storage module and the memory access request being different, decoding the intermediate address to obtain the memory access address according to the addressing methods of the data storage module and the memory access request and the allocation method of the data storage module.

[0031] In one possible implementation, the storage device also includes a request control module, the request control module includes a register group, and the register group is used to configure the allocation method of the data storage module according to the user's instructions. The method also includes: in response to a reduction in the cache lines included in the cache area, suspending the reception of new memory access requests, and writing the data stored in the reduced cache lines to other storage devices; after the writing of the data stored in the reduced cache lines is completed, continuing to receive new memory access requests.

[0032] According to another aspect of the present disclosure, a chip is provided, comprising the above-mentioned storage device.

[0033] According to another aspect of the present disclosure, an electronic device is provided, comprising the chip described above.

[0034] According to the storage device of the embodiment of the present disclosure, it includes a data storage module, a hit judgment module, and a request control module. The data storage module includes a cache area and a direct access area, so the storage device can realize both cache function and direct access function. The request control module can respond to receiving a memory access request, judge the type of memory access request, send the cache type memory access request to the hit judgment module, and send the direct access type memory access request and the corresponding memory access address to the data storage module. The hit judgment module can respond to receiving a cache type memory access request, judge whether the memory access request hits the cache area, and send the hit situation of the memory access request to the request control module, so the direct access type memory access request does not need to judge the hit situation; the request control module can also respond to receiving the hit situation of any cache type memory access request, determine the memory access address corresponding to the memory access request in the cache area, and send the memory access request and the corresponding memory access address to the data storage module; the data storage module can respond to receiving any memory access request and the corresponding memory access address, and access the memory address corresponding to the memory access request according to the memory access type included in the memory access request. Since direct access type memory access requests do not need to judge the hit situation, the storage device of the present disclosure responds to direct access type memory access requests more conveniently and efficiently. And the memory access address corresponding to the direct access type memory access request belongs to the direct access area, and the replacement operation of the cache area will not affect the direct access area. Therefore, the storage device of the present disclosure responds to direct access type memory access requests more accurately. In other words, the storage device can achieve convenient, efficient and accurate storage space control and access. And the cache area supports the cache function. In summary, the storage device of the present disclosure divides the data storage module into a cache area and a direct access area, and controls the response method of different types of memory access requests through the request control module, so that the storage device can not only achieve the cache function, but also achieve convenient, efficient and accurate storage space control and access, thereby improving the performance of the storage device.

[0035] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0037] Figure 1a An exemplary application scenario of the storage device according to an embodiment of the present disclosure is shown.

[0038] Figure 1b An exemplary application scenario of the storage device according to an embodiment of the present disclosure is shown.

[0039] Figure 2a A schematic diagram showing the structure of a storage device according to an embodiment of the present disclosure.

[0040] Figure 2b An example of a communication method among a data storage module, a hit judgment module, a request control module, an upstream interface, and a downstream interface according to an embodiment of the present disclosure is shown.

[0041] Figure 3 A schematic diagram showing an allocation method of data storage modules according to an embodiment of the present disclosure.

[0042] Figure 4 A schematic diagram showing an allocation method of data storage modules according to an embodiment of the present disclosure.

[0043] Figure 5 A schematic diagram showing a working process of a storage device according to an embodiment of the present disclosure.

[0044] Figure 6 The diagram shows how the request control module responds when the number of cache lines included in the cache area decreases according to an embodiment of the present disclosure.

[0045] Figure 7 A schematic diagram showing the process of the storage method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0047] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0048] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0049] The following are terms that may appear in this article.

[0050] Cache line: The smallest unit used to store data in the cache.

[0051] Set associative strategy: One of the mapping methods of cache and memory. The set associative strategy divides the cache into multiple groups, each of which contains multiple cache lines. A memory block can be mapped to a cache line in a group.

[0052] Replacement strategy: When a request misses the cache, another cache line is selected to replace the missed cache line to store the data corresponding to the request, which can increase the probability of the cache being hit by the request.

[0053] The hardware caches in the prior art all use hardware-implemented group associative strategies and replacement strategies to accelerate the memory access of software applications, so as to provide greater memory access bandwidth and smaller memory access latency. With the continuous development of software applications, a single fixed replacement strategy can no longer meet the diverse memory access requirements of various software applications. Therefore, the prior art proposes to meet different memory access requirements by carrying identifiers in memory access requests (such as the replacement priority of memory access requests in the cache, whether the memory access request needs to pre-fetch the next cache line, etc.), and by dynamically configuring replacement strategies. Although these means can control and adjust the memory access mode in a more fine-grained manner, these controls and adjustments are not separated from the characteristics of the cache itself, that is, when accessing the cache, it is still necessary to judge the hit status of the memory access request, so the time cost of memory access is difficult to reduce and is not convenient enough. In addition, affected by the replacement strategy, it is relatively difficult to achieve completely accurate control of the memory access mode.

[0054] In emerging software applications, especially software applications for artificial intelligence computing, since software programmers have a clear perception and control over the memory access behavior of software applications, they often hope to obtain a storage space close to the processor that can be easily and precisely controlled and accessed, so as to use this storage space to optimize the processor performance at the operator level. At the same time, they hope to reserve a portion of space to provide a cache function for memory access requests whose behavior is difficult to clearly define (such as some random address access or instruction reading, etc.). However, the cache of the prior art is not convenient enough due to the necessary hit judgment steps and has low memory access efficiency. The cache has limited capacity and needs to replace the cache lines in it in a timely manner, which makes it difficult to achieve precise control and access. However, it is difficult to achieve the cache function when a separate storage space is opened up that can be easily and efficiently controlled and accessed.

[0055] In view of this, the present disclosure proposes a storage device, a storage method, a chip, and an electronic device. The storage device divides a data storage module into a cache area and a direct access area, and controls the response mode of different types of memory access requests through a request control module, so that the storage device can realize both a cache function and convenient, efficient, and accurate storage space control and access, thereby improving the performance of the storage device.

[0056] Figure 1a and Figure 1bAn exemplary application scenario of the storage device according to an embodiment of the present disclosure is shown.

[0057] like Figure 1a and Figure 1b As shown, the chip may include a processor, and the storage device may be arranged in the processor (see Figure 1a ), or set outside the processor (see Figure 1b ). The storage device may include a cache area and a direct access area, wherein when the storage device is disposed outside the processor, the direct access area may be disposed on a side closer to the processor. The cache area may realize a cache function, and the direct access area may realize convenient and accurate storage space control and access.

[0058] The processor can run the software application to generate a memory access request. The storage device can parse the corresponding memory access address according to the memory access request, and access the memory access address according to the memory access type (read access / write access) included in the memory access request.

[0059] The storage device can configure the size of the cache area and the direct access area in response to the user's instructions. When the cache lines included in the cache area are reduced, the storage device can automatically write the data stored in the reduced cache lines to other storage devices (such as memory or off-chip memory) without software intervention.

[0060] Figure 2a A schematic diagram showing the structure of a storage device according to an embodiment of the present disclosure.

[0061] like Figure 2a As shown, in a possible implementation, the present disclosure proposes a storage device, including a data storage module, a hit judgment module, and a request control module. The data storage module includes a cache area and a direct access area.

[0062] The request control module is used for, in response to receiving a memory access request, determining the type of the memory access request, sending the cache type memory access request to the hit determination module, and sending the direct access type memory access request and the corresponding memory access address to the data storage module, wherein the memory access address corresponding to the direct access type memory access request belongs to the direct access area;

[0063] The hit judgment module is used to, in response to receiving a cache type memory access request, judge whether the memory access request hits the cache area, and send the hit status of the memory access request to the request control module;

[0064] The request control module is also used to, in response to receiving a hit condition of a memory access request of any cache type, determine a memory access address corresponding to the memory access request in the cache area, send the memory access request and the corresponding memory access address to the data storage module, and the memory access address corresponding to the memory access request of the cache type belongs to the cache area;

[0065] The data storage module is used for, in response to receiving any memory access request and a corresponding memory access address, accessing the memory access address corresponding to the memory access request according to the memory access type included in the memory access request.

[0066] For example, the storage device may include Figure 2a The data storage module, hit judgment module, and request control module shown. The request control module can communicate with the data storage module and the hit judgment module respectively. The request control module can also be connected to the upstream interface (not shown) of the storage device, and the data storage module can also be connected to the upstream interface and downstream interface (not shown) of the storage device respectively. Figure 2b An example of a communication method among a data storage module, a hit judgment module, a request control module, an upstream interface, and a downstream interface according to an embodiment of the present disclosure is shown.

[0067] like Figure 2b As shown, the upstream interface can be used to receive memory access requests, and the downstream interface can be used to transmit data to other storage devices (such as memory or off-chip memory).

[0068] The data storage module may include a cache area and a direct access area, so the storage device may support a cache function and a direct access function. An exemplary allocation method of the cache area and the direct access area may be found in the following text and Figure 3 , Figure 4 The software application may generate different types of memory access requests if it is known that the storage device supports the above two functions. Among them, a cache type memory access request may be generated when accessing the cache area, and a direct access type memory access request may be generated when accessing the direct access area.

[0069] The memory access request is received from the upstream interface and transmitted to the request control module. The request control module is used to determine the type of the memory access request in response to receiving the memory access request. If it is determined to be a cache type, the memory access request can be sent to the hit judgment module to determine the hit situation. If it is determined to be a direct access type, the memory access request and the corresponding memory access address can be sent to the data storage module. The memory access address can be obtained by parsing the request address included in the memory access request, and the memory access address parsed for the direct access type memory access request can be the address of a cache line belonging to the direct access area. The present disclosure does not limit the parsing method of the memory access address corresponding to the direct access type memory access request, and an exemplary parsing method is given later.

[0070] For cache-type memory access requests, the hit judgment module determines whether the memory access request hits the cache area, and can send the hit status of the memory access request to the request control module. The cache-type memory access request may include a tag. If the cache area stores the data to be read / written by the memory access request, the hit judgment module also stores the tag included in the cache-type memory access request. Therefore, the hit judgment module can determine whether the memory access request hits the cache area by comparing the tags. The present disclosure does not limit the method for judging the hit situation, and an exemplary judgment method is given later.

[0071] In this case, only cache-type memory access requests will perform hit judgment, and direct access-type memory access requests do not need to perform hit judgment, making access to the direct access area in response to direct access-type memory access requests more convenient and efficient, with greater bandwidth and reduced power consumption.

[0072] After the request control module receives the hit status of the cache type memory access request, it can determine the memory access address corresponding to the memory access request in the cache area according to the hit status, and the determined memory access address can be the address of a cache line belonging to the cache area. The request control module can send the memory access request and the corresponding memory access address to the data storage module. The present disclosure does not limit the method for determining the memory access address corresponding to the cache type memory access request, and an exemplary determination method is given later.

[0073] In response to receiving any memory access request and the corresponding memory access address, the data storage module can access the memory access address corresponding to the memory access request according to the memory access type included in the memory access request. If the memory access type is read access, the memory access address corresponding to the memory access request is accessed, and after reading the data stored in the memory access address, the read data can be returned to the initiator of the memory access request (such as a software application) through the upstream interface. If the memory access type is write access, the memory access request can further include data to be written, and the memory access address corresponding to the memory access request can be accessed, and the data to be written can be written to the memory access address for storage.

[0074] A storage device according to an embodiment of the present disclosure includes a data storage module, a hit determination module, and a request control module. The data storage module includes a cache area and a direct access area. Therefore, the storage device can implement both cache functions and direct access functions. Among them, the request control module can respond to a memory access request, determine the type of the memory access request, send the memory access request of the cache type to the hit determination module, and send the memory access request of the direct access type and the corresponding memory access address to the data storage module. The hit determination module can respond to the received memory access request of the cache type, determine whether the memory access request hits the cache area, and send the hit situation of the memory access request to the request control module. Therefore, the memory access request of the direct access type does not need to be judged for the hit situation; the request control module can also respond to the hit situation of any received memory access request of the cache type, determine the memory access address corresponding to the memory access request in the cache area, and send the memory access request and the corresponding memory access address to the data storage module; the data storage module can respond to any received memory access request and the corresponding memory access address, and access the memory access address corresponding to the memory access request according to the memory access type included in the memory access request. Since the memory access request of the direct access type does not need to be judged for the hit situation, the storage device of the present disclosure responds to the memory access request of the direct access type more conveniently and efficiently. And the memory access address corresponding to the memory access request of the direct access type belongs to the direct access area, and the replacement operation of the cache area does not affect the direct access area. Therefore, the storage device of the present disclosure responds to the memory access request of the direct access type more accurately. That is, the storage device can achieve convenient, efficient, and accurate storage space control and access. And the cache area supports cache functions. In summary, the storage device of the present disclosure divides the data storage module into a cache area and a direct access area, and controls the response methods of different types of memory access requests through the request control module, so that the storage device can not only implement cache functions, but also achieve convenient, efficient, and accurate storage space control and access, improving the performance of the storage device.

[0075] Two exemplary allocation methods of the data storage module are introduced below. Figure 3 and Figure 4 A schematic diagram showing an allocation method of the data storage module according to an embodiment of the present disclosure.

[0076] In a possible implementation manner, the data storage module includes S rows and W columns of cache rows. Each row of W cache rows is a group, and each column of S cache rows is a way. W and S are positive integers.

[0077] When the allocation method of the data storage module is group-based allocation, the direct access area includes X rows and W columns of cache rows, and the cache area includes S - X rows and W columns of cache rows, where 0 < X < S and X is an integer;

[0078] When the allocation method of the data storage module is allocation by way, the direct access area includes S rows and Y columns of cache lines, and the cache area includes S rows and W - Y columns of cache lines, where 0 < Y < W and Y is an integer.

[0079] For example, as Figure 3 and Figure 4 shown, assuming S = 16 and W = 4, the data storage module may include 16 rows and 4 columns of cache lines. The 4 cache lines in each row form a group, and the 4 cache lines in each column form a way. Then there are a total of 16 groups of cache lines (group 0 to group 15) and 4 ways of cache lines (way 0 to way 3). Each cache line is sequentially addressed from address 0 to address 63.

[0080] As Figure 3 shown, one allocation method of the data storage module is allocation by group, that is, allocating the complete X groups of cache lines (X rows and W columns of cache lines) to the direct access area, where 0 < X < S and X is an integer, and the remaining S - X groups of cache lines (S - X rows and W columns of cache lines) are allocated to the cache area. In the Figure 3 example, X can be equal to 8. If it is further set that the cache lines with lower group numbers are preferentially allocated to the direct access area, then the cache lines from group 0 to group 7 can be allocated to the direct access area, and the cache lines from group 8 to group 15 can be allocated to the cache area. If it is further set that the cache lines with higher group numbers are preferentially allocated to the direct access area, then the cache lines from group 8 to group 15 can be allocated to the direct access area, and the cache lines from group 0 to group 7 can be allocated to the cache area.

[0081] Those skilled in the art should understand that when allocating by group, the allocation priorities of each group of cache lines should not be limited to the above examples. For example, it is also possible to preferentially allocate the cache lines with middle group numbers to the direct access area, as long as the complete X groups of cache lines (X rows and W columns of cache lines) are allocated to the direct access area, and the remaining S - X groups of cache lines (S - X rows and W columns of cache lines) are allocated to the cache area. The present disclosure does not limit the allocation priorities of each group of cache lines.

[0082] As Figure 4 shown, one allocation method of the data storage module is allocation by way, that is, allocating the complete Y ways of cache lines (S rows and Y columns of cache lines) to the direct access area, where 0 < Y < W and Y is an integer, and the remaining W - Y ways of cache lines (S rows and W - Y columns of cache lines) are allocated to the cache area. In the Figure 4 example, Y can be equal to 1. If it is further set that the cache lines with lower way numbers are preferentially allocated to the direct access area, then the cache line of way 0 can be allocated to the direct access area, and the cache lines of way 1 to way 3 can be allocated to the cache area. If it is further set that the cache lines with higher way numbers are preferentially allocated to the direct access area, then the cache line of way 3 can be allocated to the direct access area, and the cache lines of way 0 to way 2 can be allocated to the cache area.

[0083] Those skilled in the art should understand that the allocation priority of each cache line when allocating by way should be more than the above example. For example, the cache line with the middle way number can also be preferentially allocated to the direct access area. As long as the complete Y-way cache line (S row and Y column cache line) is allocated to the direct access area, and the remaining WY-way cache lines (S row and WY column cache lines) are allocated to the cache area, the present disclosure does not limit the allocation priority of each cache line.

[0084] The request control module may include a register group for configuring the allocation method of the data storage module according to the user's instructions. In one example, when the allocation method is allocation by group, the register group may store allocation identifiers corresponding to each group of cache lines, and the allocation identifier may indicate whether the current group of cache lines is locked or valid, which can be used when the cache line is replaced in the cache area. Among them, locked or invalid means that the current group of cache lines is allocated to the direct access area, and unlocked or valid means that the current group of cache lines is allocated to the cache area. Similarly, when the allocation method is allocation by way, the register group may store allocation identifiers corresponding to each way of cache lines, and the allocation identifier may indicate whether the current way of cache lines is locked or valid, which can be used when the cache line is replaced in the cache area. Among them, locked or invalid means that the current way of cache lines is allocated to the direct access area, and unlocked or valid means that the current way of cache lines is allocated to the cache area. An exemplary method for replacing cache lines in a cache area is given later.

[0085] In this way, users can dynamically adjust the cache line ratio of the cache area and the direct access area in the data storage module according to application requirements, and conveniently use the storage space of the data storage module as more cache area or more direct access area according to actual needs, so as to realize dynamic configuration of cache lines and realize a storage device with a hybrid working mode of cache function and direct access function. In addition, dynamic adjustment can also reduce the use of hardware storage resources and reduce hardware costs.

[0086] Those skilled in the art should understand that although the smallest storage unit of the direct access area is also referred to as a cache line herein, in fact, the cache line does not need to assume the cache function when it is located in the direct access area.

[0087] In this way, the allocation mode of the data storage module is made more flexible.

[0088] Figure 5 A schematic diagram showing the working process of the storage device according to an embodiment of the present disclosure is shown. Figure 5 This section describes the specific functions of each module of the storage device.

[0089] like Figure 5 As shown, after the storage device receives a memory access request, the request control module first determines the type of the memory access request.

[0090] An exemplary manner in which the request control module determines the type of a memory access request is described below.

[0091] In a possible implementation, a direct access type memory access request includes a first identifier, and the request control module is specifically configured to:

[0092] In response to receiving a memory access request, detecting whether the memory access request includes a first identifier;

[0093] In response to the memory access request including the first identifier, determining that the memory access request is a direct access type;

[0094] In response to the memory access request not including the first identifier, it is determined that the memory access request is of a cache type.

[0095] For example, when a software application generates a direct access type memory access request, a first identifier may be added, but when a cache type memory access request is generated, the first identifier does not need to be added. In this case, the type of memory access request can be distinguished by whether the memory access request includes the first identifier. The request control module can detect whether the memory access request includes the first identifier in response to receiving the memory access request; when the memory access request includes the first identifier, the memory access request is judged to be a direct access type, and when the memory access request does not include the first identifier, the memory access request is judged to be a cache type.

[0096] Similarly, the software application may also add the second identifier when generating a cache type memory access request, and may not need to add the second identifier when generating a cache type memory access request, or may add the first identifier. The request control module may detect whether the memory access request includes the first identifier or the second identifier in response to receiving the memory access request; when the memory access request includes the first identifier, the memory access request is judged to be a direct access type; when the memory access request does not include the first identifier or includes the second identifier, the memory access request is judged to be a cache type.

[0097] In this case, the request control module can complete the type determination of the memory access request as long as it has the ability to identify the first identifier, which makes the type determination of the memory access request simpler and the subsequent decoding method for obtaining the memory access address of the memory access request simpler.

[0098] Another exemplary manner in which the request control module determines the type of a memory access request is described below.

[0099] In a possible implementation, the memory access request also includes a request address, the address space of the cache area and the address space of the direct access area are different, and the request control module is specifically used to:

[0100] In response to receiving a memory access request, detecting an address space corresponding to a request address included in the memory access request;

[0101] In response to a request address included in the memory access request corresponding to an address space of the direct access area, determining that the memory access request is a direct access type;

[0102] In response to a request address included in the memory access request corresponding to an address space of the cache area, it is determined that the memory access request is of a cache type.

[0103] For example, after the data storage module is allocated, the address space of the cache area and the direct access area can be synchronized to the software application. The address space of the cache area and the direct access area is different. When the software application generates a cache type memory access request, the request address included in the memory access request can be determined according to the address space of the cache area. When a direct access type memory access request is generated, the request address included in the memory access request can be determined according to the address space of the direct access area. In this case, the type of memory access request can be distinguished by which area of ​​address space the request address included in the memory access request corresponds to. In response to receiving a memory access request, the request control module can detect the address space corresponding to the request address included in the memory access request. When the request address corresponds to the address space of the direct access area, the memory access request is judged to be a direct access type. When the request address corresponds to the address space of the cache area, the memory access request is judged to be a cache type.

[0104] Since there is no need to add an identifier for distinguishing different types of memory access requests, the data volume of the memory access request is smaller.

[0105] In this way, the request control module is more flexible in determining the type of memory access request.

[0106] Combine the following Figure 5 The response process of a storage device to a cache type memory access request is introduced.

[0107] like Figure 5 As shown, after determining the type of memory access request, for cache type memory access requests, the hit situation can be judged first. Figure 2b According to the relevant description, the hit judgment module judges the hit situation of the memory access request by comparing the tags. If the cache area stores a lot of data, then there will be a lot of tags that need to be compared, resulting in a relatively large data processing cost and time cost for the hit judgment. In this regard, the present disclosure proposes a method for narrowing the scope of hit judgment. Among them, when the allocation method of the data storage module is different, the implementation method of narrowing the scope of hit judgment is different. Accordingly, the specific content of the hit situation determined by the hit judgment module and the replacement method of the cache line when a miss is also different.

[0108] The following first introduces an exemplary implementation method of narrowing the hit judgment range when the data storage module is allocated in groups.

[0109] In a possible implementation, the memory access request further includes a request address. When the allocation mode of the data storage module is group allocation,

[0110] The request control module is specifically used to, in response to the memory access request being a cache type, parse the group number of the cache line corresponding to the memory access request according to the request address, and send the group number and the memory access request to the hit judgment module;

[0111] The hit judgment module is specifically used to, in response to receiving a cache type memory access request, determine whether the memory access request hits a group of cache lines corresponding to the group number in the cache area according to the group number of the cache line corresponding to the memory access request, and send the hit status of the memory access request to the request control module.

[0112] For example, the memory access request also includes a request address A. When the allocation mode of the data storage module is group allocation, after the request control module determines that the memory access request is a cache type, the group number M of the cache line corresponding to the memory access request can be parsed according to the request address A. At this time, the cache line corresponding to the memory access request is a cache line in the Mth group of cache lines.

[0113] Each cache line can be the same size. Assume that the data storage module preferentially allocates cache lines with low group numbers to the direct access area (see example Figure 3 ), the number of groups M is calculated as follows:

[0114] Number of groups M = (request address A / cache line size)% (SX) + X

[0115] Among them, % represents the remainder, S represents the total number of groups of the data storage module, X represents the total number of groups allocated to the direct access area, and SX represents the total number of groups allocated to the cache area. For example, when (request address A / cache line size) = 20, S = 16, X = 8, and SX = 8, the number of groups M = 20% 8 + 8 = 12, indicating that the cache line corresponding to the memory access request is a cache line in the 12th cache line group.

[0116] For comparison, if the data storage module includes S rows and W columns (S groups and W ways) of cache lines, all of which are cache lines in the cache area, then the number of groups M' = (request address A / cache line size) % S = 20 % 16 = 4. However, when the allocation is by group and X = 8, see Figure 3 , the 0th to 7th groups of cache lines have been allocated to the direct access area and no longer support the cache function. Therefore, the 8th group of cache lines is actually equivalent to the 0th group of cache lines in the cache area. Therefore, when the number of groups M'=4, the cache line corresponding to the memory access request should be located in the 12th group (M'+X=M=12) of cache lines.

[0117] In this case, the request control module of the present disclosure may resolve the cache-type memory access request for the M'th group of cache lines into the access to the M'+Xth group of cache lines, thereby ensuring the accuracy of the memory access.

[0118] Those skilled in the art should understand that if the data storage module preferentially allocates cache lines with a high group number to the direct access area, then M may be equal to M′.

[0119] In this way, the accuracy of group number calculation can be guaranteed when allocating by group.

[0120] The data stored in the cache line is usually stored in response to a received historical memory access request. The hit judgment module includes a tag storage area, which may include a storage location of S rows and W columns. When the data read / written in response to a certain memory access request is stored in the cache line of the i-th row and j-th column, the data storage module may write the tag of the memory access request into the storage location of the i-th row and j-th column in the tag storage area. Therefore, the tags stored in the tag storage area and the data stored in the data storage module are in one-to-one correspondence.

[0121] Therefore, in the process of the hit judgment module judging the hit situation, since the group number M of the cache line corresponding to the memory access request has been determined, it is only necessary to judge whether a row corresponding to the group number M in the tag storage area stores the same tag as the newly received memory access request. If the same tag as the newly received memory access request is stored, it means that the memory access request hits a group of cache lines corresponding to the group number M in the cache area, and the number N of the way where the hit cache line is located can be determined. If the same tag as the newly received memory access request is not stored, it means that the memory access request does not hit a group of cache lines corresponding to the group number M in the cache area. The hit judgment module can send the hit situation to the request control module, and the request control module determines the subsequent operation according to the hit situation.

[0122] The following are examples of possible hit scenarios when the data storage module is assigned by group.

[0123] In a possible implementation, when a memory access request hits a cache line in a group of cache lines corresponding to the group number in the cache area, the hit condition of the memory access request includes the way number where the hit cache line is located;

[0124] When a memory access request misses a group of cache lines corresponding to the group number in the cache area, the hit condition of the memory access request includes information indicating that the memory access request misses.

[0125] For example, when the data storage module is allocated by group, when the hit judgment module determines that the memory access request hits a cache line in a group of cache lines corresponding to the group number M in the cache area, it can further determine the way number N where the hit cache line is located, so the hit situation of the memory access request may include the way number N where the hit cache line is located. When the request control module receives the way number N where the cache line hit by the memory access request is located, combined with the group number M determined by itself in response to the same memory access request, it can be determined that the memory access request hits the cache line of the Nth way of the Mth group, and the address of the cache line of the Nth way of the Mth group is determined as the memory access address corresponding to the memory access request.

[0126] Optionally, after the hit judgment module determines the way number N where the hit cache line is located, the address of the cache line of the Nth way of the Mth group can also be directly determined as the memory access address corresponding to the memory access request based on the number of groups M and the number of ways N, and the memory access request, the memory access address, and the information indicating that the memory access request did not hit are sent to the data storage module without using the request control module. The disclosed embodiment does not limit which of the request control module and the hit judgment module determines and sends the memory access address when the memory access request hits the cache area.

[0127] When a memory access request misses a set of cache lines corresponding to the number of sets M in the cache area, such as Figure 5 As shown, the request control module can be used to replace a group of cache lines corresponding to the group number M (replace cache lines). After replacing the cache lines, the request control module can send the memory access address, the memory access request, and the information indicating that the memory access request misses to the data storage module.

[0128] In a possible implementation, the request control module is further configured to:

[0129] In response to information indicating that the memory access request missed, selecting another set of cache lines from the cache area;

[0130] detecting whether there is data to be written into other storage devices in a selected set of cache lines;

[0131] In response to detecting data to be written to the other storage device, after writing the data to the other storage device, replacing a group of cache lines corresponding to the group number with the selected group of cache lines;

[0132] In response to not detecting data to be written to other storage devices, directly replacing a group of cache lines corresponding to the group number with the selected group of cache lines.

[0133] For example, if the request control module receives information indicating that a memory access request misses, the request control module may determine that the Mth group of cache lines needs to be replaced based on the group number M calculated in response to the memory access request. The request control module may select another group of cache lines from the cache area, such as the Pth group of cache lines, and detect whether there is data to be written to other storage devices in the Pth group of cache lines. If data to be written to other storage devices is detected, the data storage module may be notified to write the detected data to other storage devices through the downstream interface, and then use the selected group of cache lines (the Pth group of cache lines) to replace a group of cache lines corresponding to the group number M (the Mth group of cache lines); if data to be written to other storage devices is not detected, the selected group of cache lines may be used to directly replace a group of cache lines corresponding to the group number M.

[0134] See also Figure 3 , assuming that the number of groups M=12, the cache area includes the 8th to 15th groups of cache lines, and the data storage module preferentially allocates the cache lines with lower group numbers to the direct access area, then the request control module queries the register group to determine that the allocation flags of the 0th to 7th groups of cache lines indicate locked or invalid, and the allocation flags of the 8th to 15th groups of cache lines indicate unlocked or valid. A group of cache lines can be selected from the 8th to 11th and 13th to 15th groups of cache lines according to a preset selection strategy to replace the 12th group of cache lines (M=12).

[0135] In this way, reasonable replacement of cache lines can be guaranteed when allocating by group.

[0136] The following describes an exemplary implementation of narrowing the hit determination range when the data storage module is allocated by way.

[0137] In a possible implementation, the memory access request further includes a request address. When the allocation mode of the data storage module is allocation by way,

[0138] The request control module is specifically used to, in response to the memory access request being a cache type, parse the way number of the cache line corresponding to the memory access request according to the request address, and send the way number and the memory access request to the hit judgment module;

[0139] The hit judgment module is specifically used to, in response to receiving a cache type memory access request, determine whether the memory access request hits a cache line corresponding to the way number in the cache area according to the way number of the cache line corresponding to the memory access request, and send the hit status of the memory access request to the request control module.

[0140] For example, when a memory access request includes a request address A and the allocation mode of the data storage module is allocation by way, after the request control module determines that the memory access request is a cache type, it can parse the way number N where the cache line corresponding to the memory access request is located according to the request address A. At this time, the cache line corresponding to the memory access request is a cache line in the cache line of the Nth way.

[0141] The size of each cache line can be the same and equal to L. Assuming that the data storage module preferentially allocates cache lines with high way numbers to the direct access area, the way number N is calculated as follows:

[0142] Number of ways N = (request address A / cache line size L) % (WY)

[0143] Among them, % represents the remainder, W represents the total number of ways of the data storage module, Y represents the total number of ways allocated to the direct access area, and WY represents the total number of ways allocated to the cache area. For example, when (request address A / cache line size L) = 13, W = 4, Y = 1, and WY = 3, the number of ways N = 13%3 = 1, indicating that the cache line corresponding to the memory access request is a cache line in the cache line of way 1.

[0144] In contrast, if the S groups of W-way cache lines included in the data storage module are all cache lines of the cache area, then the number of ways N'=(request address A / cache line size L)%(W)=13%4=1. That is, N' may be equal to N.

[0145] Those skilled in the art should understand that if the data storage module preferentially allocates cache lines with low way numbers to the direct access area, then N=(request address A / cache line size L)%(WY)+Y, ie, N'+Y=N.

[0146] In this way, the accuracy of the road number calculation during road allocation can be guaranteed.

[0147] Refer to the above description of the tag storage area. Since the tags stored in the tag storage area correspond one to one with the data stored in the data storage module, in the process of the hit judgment module judging the hit situation, since the way number N where the cache line corresponding to the memory access request is located has been determined, it is only necessary to judge whether a column corresponding to the way number N in the tag storage area stores the same tag as the newly received memory access request. If the same tag as the newly received memory access request is stored, it means that the memory access request hits a cache line corresponding to the way number N in the cache area, and the group number M where the hit cache line is located can be determined. If the same tag as the newly received memory access request is not stored, it means that the memory access request does not hit a cache line corresponding to the way number N in the cache area. The hit judgment module can send the hit situation to the request control module, and the request control module determines the subsequent operation according to the hit situation.

[0148] The following describes an example of a possible hit situation when data storage modules are allocated by way.

[0149] In a possible implementation, when a memory access request hits a cache line in a cache area corresponding to a way number, the hit condition of the memory access request includes a group number where the hit cache line is located;

[0150] When a memory access request misses a cache line corresponding to the way number in the cache area, the hit status of the memory access request includes information indicating that the memory access request misses.

[0151] For example, when the data storage module is allocated by way, when the hit judgment module determines that the memory access request hits a cache line in a cache line of a way corresponding to the way number N in the cache area, it can further determine the group number M where the hit cache line is located, so the hit situation of the memory access request may include the group number M where the hit cache line is located. When the request control module receives the group number M where the cache line hit by the memory access request is located, combined with the way number N determined by itself in response to the same memory access request, it can be determined that the memory access request hits the cache line of the Nth way of the Mth group, and the address of the cache line of the Nth way of the Mth group is determined as the memory access address corresponding to the memory access request.

[0152] Optionally, after the hit judgment module determines the group number M where the hit cache line is located, the address of the cache line of the Nth way of the Mth group can also be directly determined as the memory access address corresponding to the memory access request based on the group number M and the way number N, and the memory access request, the memory access address, and the information indicating that the memory access request hits are sent to the data storage module without using the request control module. The disclosed embodiment does not limit which of the request control module and the hit judgment module determines and sends the memory access address when the memory access request hits the cache area.

[0153] When a memory access request misses a cache line corresponding to the number N in the cache area, such as Figure 5 As shown, the request control module can be used to replace a cache line corresponding to the number N (replace the cache line). After replacing the cache line, the request control module can send the memory access address, the memory access request, and the information indicating that the memory access request misses to the data storage module.

[0154] In a possible implementation, the request control module is further configured to:

[0155] In response to information indicating that the memory access request misses, selecting another cache line from the cache area;

[0156] Detecting whether there is data to be written into other storage devices in the selected cache line;

[0157] In response to detecting data to be written into other storage devices, after writing the data into other storage devices, replacing a cache line corresponding to the way number with the selected cache line;

[0158] In response to not detecting data to be written into other storage devices, the selected cache line is used to directly replace the cache line corresponding to the way number.

[0159] For example, if the request control module receives information indicating that a memory access request misses, the request control module may determine that the Nth cache line needs to be replaced based on the previously calculated number of ways N. The request control module may select another cache line from the cache area, such as the Qth cache line, and detect whether there is data to be written to other storage devices in the Qth cache line. If data to be written to other storage devices is detected, the data is written to other storage devices through the downstream interface, and then the selected cache line (Qth cache line) is used to replace the cache line corresponding to the number of ways N (the Nth cache line); if no data to be written to other storage devices is detected, the selected cache line may be used to directly replace the cache line corresponding to the number of ways N.

[0160] See also Figure 4 , assuming that N=1, the cache area includes cache lines 0 to 3, and the data storage module preferentially allocates cache lines with high numbers to the direct access area, then the request control module queries the register group to determine that the allocation mark of the cache line 3 indicates locked or invalid, and the allocation marks of the cache lines 0 to 2 indicate unlocked or valid. A cache line can be selected from the cache lines 0 and 2 according to the preset selection strategy to replace the cache line 1 (N=1).

[0161] In this way, reasonable replacement of cache lines can be guaranteed when allocating by way.

[0162] like Figure 5 As shown, when the data storage module executes a cache-type memory access request, if information indicating that the memory access request hits is received, the memory access address (located in the cache area) of the memory access request can be directly accessed, and the corresponding data read / write operation can be completed according to the memory access type, such as reading the data to be read from the memory access address and returning it to the software application through the upstream interface, or writing the data to be written to the memory access address. If information indicating that the memory access request misses is received, the cache line can be filled first, such as obtaining the data to be read through the downstream interface and writing it to the memory access address, or writing the data to be written to other storage devices through the downstream interface first, and then writing it to the memory access address.

[0163] Combine the following Figure 5 The response process of a storage device to a direct access type memory access request is introduced.

[0164] After determining the type of memory access request, for a direct access type memory access request, the request control module can directly parse the memory access address corresponding to the memory access request. The parsing method is related to the determination method of the type of memory access request, the addressing method of the data storage module and the memory access request, and may also be related to the allocation method of the data storage module.

[0165] The following first introduces an exemplary method for determining a memory access address of a direct access type memory access request when the first identifier is used to determine the type of the memory access request.

[0166] In a possible implementation, the memory access request also includes a request address, and the request control module is specifically configured to:

[0167] In response to the memory access request being of a direct access type, detecting an allocation mode of the data storage module, and determining whether the addressing modes of the data storage module and the memory access request are the same;

[0168] In response to the data storage module and the memory access request having the same addressing mode, using the request address as the memory access address;

[0169] In response to different addressing modes of the data storage module and the memory access request, the request address is decoded to obtain the memory access address according to the addressing mode of the data storage module and the memory access request and the allocation mode of the data storage module.

[0170] For example, in response to the memory access request being a direct access type, the request control module can detect the allocation mode of the data storage module and determine whether the addressing mode of the data storage module and the memory access request are the same. There are two addressing modes, namely, the way priority addressing mode and the group priority addressing mode.

[0171] The way-first addressing method means that the addresses of the cache lines are from low to high in the order of (group 0, way 0), (group 0, way 1), ..., (group 0, way W-1), ..., (group S-1, way W-1).

[0172] The group-first addressing method means that the addresses of the cache lines are from low to high (group 0, way 0), (group 1, way 0), ..., (group S-1, way 0), ..., (group S-1, way W-1).

[0173] If the addressing mode of the data storage module and the memory access request are the same, then the request address included in the memory access request does not need to be converted to the address under the addressing mode of the data storage module. Since the first identifier is used to determine the type of the memory access request at this time, the request address is already an accurate address encoded starting from 0, so the request address can be directly used as the memory access address.

[0174] If the addressing modes of the data storage module and the memory access request are different, the request address included in the memory access request needs to be converted to an address under the addressing mode of the data storage module. Since the first identifier is used to determine the type of the memory access request at this time, the request address is already an accurate address encoded starting from 0. Therefore, the request address can be decoded to obtain the memory access address according to the addressing mode of the data storage module and the memory access request and the allocation mode of the data storage module.

[0175] For example, when the memory access request adopts the way-first addressing mode, the data storage module adopts the group-first addressing mode, and the data storage module is allocated by group, the group number U0 and the way number V0 of the cache line corresponding to the memory access request can be calculated according to the request address A. Among them, U0 = (request address A / cache line size) % X, X is the total number of groups allocated to the direct access area, S is the total number of groups in the data storage area, and % represents the remainder. V0 = (request address A / cache line size) / U0. Then, based on the group number U0 and the way number V0, the memory access address B0 = V0×S+U0 is calculated.

[0176] When the memory access request adopts a group-priority addressing method, the data storage module adopts a way-priority addressing method, and the data storage modules are allocated by groups, the exemplary method for determining the memory access address is similar to the method when the memory access request adopts a way-priority addressing method, the data storage module adopts a group-priority addressing method, and the data storage modules are allocated by groups, and will not be repeated here.

[0177] For another example, when the memory access request adopts a group-first addressing method, the data storage module adopts a way-first addressing method, and the data storage module is allocated by way, the way number V1 and the group number U1 of the cache line corresponding to the memory access request can be calculated based on the request address A. Among them, V1 = (request address A / cache line size) % Y + (WY), Y is the total number of ways allocated to the direct access area, W is the total number of ways in the data storage area, and % represents the remainder. U1 = request address A / X. Then, based on the group number U1 and the way number V1, the memory access address B1 = U1×W+V1 is calculated.

[0178] Assume A=10, W=4, Y=1, WY=3, and the cache line size is 1, then V1=10%1+3=3, U1=10 / 1=10, B1=10×4+3=43, so the parsed memory access address is equal to 43, corresponding to Figure 4 The cache line of group 10, way 3.

[0179] When the memory access request adopts a way-first addressing method, the data storage module adopts a group-first addressing method, and the data storage module is allocated by way, the exemplary method for determining the memory access address is similar to the method when the memory access request adopts a group-first addressing method, the data storage module adopts a way-first addressing method, and the data storage module is allocated by way, and will not be repeated here.

[0180] The following describes an exemplary method for determining a memory access address of a direct access type memory access request when the address space is used to determine the type of the memory access request.

[0181] In a possible implementation, the memory access request also includes a request address, and the request control module is specifically configured to:

[0182] In response to the memory access request being of a direct access type, detecting an allocation mode of the data storage module, and determining whether an addressing mode of the data storage module and the memory access request are the same;

[0183] Subtract the starting address of the address space of the direct access area from the request address to get the intermediate address;

[0184] In response to the data storage module and the memory access request having the same addressing mode, the intermediate address is used as the memory access address;

[0185] In response to different addressing modes of the data storage module and the memory access request, the intermediate address is decoded to obtain the memory access address according to the addressing mode of the data storage module and the memory access request and the allocation mode of the data storage module.

[0186] For example, in response to the memory access request being a direct access type, the request control module can detect the allocation mode of the data storage module and determine whether the addressing mode of the data storage module and the memory access request are the same. There are two addressing modes, namely, the way priority addressing mode and the group priority addressing mode. For examples, see the relevant description above.

[0187] Since the address space is used to determine the type of memory access request, the request address is not an address encoded starting from 0. The request address can be subtracted from the start address of the address space of the direct access area to obtain the intermediate address. The memory access address obtained by decoding using the intermediate address is accurate.

[0188] If the addressing mode of the data storage module and the memory access request is the same, then the intermediate address and the addressing mode of the data storage module are also the same, and the intermediate address does not need to be converted to the address under the addressing mode of the data storage module. The intermediate address can be directly used as the memory access address.

[0189] If the addressing methods of the data storage module and the memory access request are different, then the intermediate address and the addressing method of the data storage module are also different, and the intermediate address needs to be converted to the address under the addressing method of the data storage module. The memory access address can be obtained by decoding the intermediate address according to the addressing method of the data storage module and the memory access request and the allocation method of the data storage module.

[0190] For example, when the memory access request adopts the way-first addressing mode, the data storage module adopts the group-first addressing mode, and the data storage module is allocated by group, the group number U2 and the way number V2 of the cache line corresponding to the memory access request can be calculated based on the intermediate address C. Among them, U2 = (intermediate address C / cache line size) % X, X is the total number of groups allocated to the direct access area, S is the total number of groups in the data storage area, and % represents the remainder. V2 = (intermediate address C / cache line size) / U2. Then, based on the group number U2 and the way number V2, the memory access address B2 = V2×S+U2 is calculated.

[0191] When the memory access request adopts a group-priority addressing method, the data storage module adopts a way-priority addressing method, and the data storage modules are allocated by groups, the exemplary method for determining the memory access address is similar to the method when the memory access request adopts a way-priority addressing method, the data storage module adopts a group-priority addressing method, and the data storage modules are allocated by groups, and will not be repeated here.

[0192] For another example, when the memory access request adopts the group-first addressing mode, the data storage module adopts the way-first addressing mode, and the data storage module is allocated by way, the way number V3 and the group number U3 of the cache line corresponding to the memory access request can be calculated based on the intermediate address C. Among them, V3 = (intermediate address C / cache line size) % Y + (WY), Y is the total number of ways allocated to the direct access area, W is the total number of ways in the data storage area, and % represents the remainder. U3 = intermediate address C / X. Then, based on the group number U3 and the way number V3, the memory access address B3 = U3×W+V3 is calculated.

[0193] When the memory access request adopts a way-first addressing method, the data storage module adopts a group-first addressing method, and the data storage module is allocated by way, the exemplary method for determining the memory access address is similar to the method when the memory access request adopts a group-first addressing method, the data storage module adopts a way-first addressing method, and the data storage module is allocated by way, and will not be repeated here.

[0194] Those skilled in the art should understand that if the data storage module itself has computing capabilities, the data storage module can also be used to calculate the memory access address. In this case, the request control module only needs to send a direct access type memory access request to the data storage module without sending the corresponding memory access address at the same time. The disclosed embodiment does not limit whether the request control module sends a request address at the same time when sending a direct access type memory access request.

[0195] When the memory access address of a direct access type memory access request crosses the boundary, that is, exceeds the maximum address of the address space of the direct access area, the request control module can discard the memory access request. If the memory access request is a read access type, an invalid data can be returned to the software application through the upstream interface, and an interrupt can be reported to the processor, which will be handed over to the processor to perform exception handling operations such as chip reset or process termination. Such exception handling operations can be implemented based on existing technologies and will not be repeated here.

[0196] When the data storage module executes a direct access type memory access request, it can directly access the memory access address of the memory access request (located in the direct access area). For write access, the data to be written can be written to the determined memory access address. For read access, the data is read from the determined memory access address and returned to the software application through the upstream interface.

[0197] Combination Figure 5 It can be seen from the relevant description that when using the storage device disclosed in the present invention, a direct access type memory access request will only access the cache line of the direct access area, and a cache type memory access request will only access the cache line of the cache area. The access of different types of requests is reasonably allocated, with no overlap or waste, which ensures the accuracy of memory access while reducing hardware costs.

[0198] In a possible implementation, the request control module includes a register group, and the register group is used to configure the allocation mode of the data storage module according to the user's instruction.

[0199] The request control module is further used to, in response to a reduction in the number of cache lines included in the cache area, suspend receiving new memory access requests, and write data stored in the reduced cache lines into other storage devices;

[0200] After the data stored in the reduced cache line is written, new memory access requests continue to be received.

[0201] For example, when the user instructs to change the allocation mode of the data storage module so that the size of the cache area becomes smaller, it may not be desirable to lose the data stored in the cache lines included in the reduced portion. Therefore, the request control module can also be used to, in response to the reduction of the cache lines included in the cache area, suspend receiving new memory access requests and write the data stored in the reduced cache lines to other storage devices. After the data stored in the reduced cache lines is written, new memory access requests continue to be received. This operation can be automatically triggered by the request control module without user intervention.

[0202] Figure 6 The diagram shows how the request control module responds when the number of cache lines included in the cache area decreases according to an embodiment of the present disclosure.

[0203] like Figure 6As shown, the original direct access area includes the 3rd cache line, and the original cache area includes the 0th to 2nd cache lines. After the user adjusts the allocation configuration, the direct access area is changed to the 2nd to 3rd, and the cache area is changed to the 0th to 1st. For the cache area, the reduced cache line is the 2nd cache line (automatic write-back area). The request control module can suspend receiving new memory access requests and write the data stored in the 2nd cache line to other storage devices. After the data stored in the 2nd cache line is written, it continues to receive new memory access requests.

[0204] In this case, when users perform operations such as out-of-bounds checks and space allocation, they do not need to consider whether they will affect cache replacement and application, which improves user experience. Users can dynamically adjust the allocation method at any time without having to worry about maintaining consistency.

[0205] The storage device disclosed in the present invention has better usability due to the improved functional diversity, so that the on-chip storage space of the chip can be more fully utilized and is applicable to a wider range of application scenarios. At the same time, compared with the existing solutions, the present invention uses a register group as an interface for modifying the configuration, which is more intuitive and easy to use, and can support users to perform more precise storage control.

[0206] Compared to implementing independent direct access memory and cache on the chip at the same time, the storage device disclosed in the present invention can merge the storage space of the two. Under the same area and power consumption, it can provide a larger cache area for software applications that require more cache functions, and can provide a larger direct access area for software applications that require more controllable on-chip independent storage space, thereby expanding the application scenarios of the chip and enabling it to achieve better performance in more scenarios.

[0207] The present disclosure also provides a storage method, Figure 7 A schematic diagram showing the process of the storage method according to an embodiment of the present disclosure.

[0208] In a possible implementation, the storage method is applied to a storage device, the storage device includes a data storage module, the data storage module includes a cache area and a direct access area, and the schematic diagram of the structure of the storage device can be seen in Figure 2a and Figure 2b .

[0209] like Figure 7 As shown, the method includes:

[0210] Step S71, in response to receiving a memory access request, determining a type of the memory access request, the type including a cache type and a direct access type;

[0211] Step S72, in response to the type of the memory access request being a cache type, determining whether the memory access request hits a cache area, and determining a memory access address corresponding to the memory access request according to a hit condition of the memory access request, wherein the memory access address corresponding to the cache type memory access request belongs to the cache area;

[0212] Step S73, in response to the type of the memory access request being a direct access type, parsing a memory access address corresponding to the memory access request according to the memory access request, wherein the memory access address corresponding to the memory access request of the direct access type belongs to the direct access area;

[0213] Step S74: accessing a memory access address corresponding to the memory access request according to the memory access type included in the memory access request.

[0214] Among them, step S71 can be completed by the request control module described above. In step S72, "in response to the type of the memory access request being a cache type, determining whether the memory access request hits the cache area" can be completed by the hit judgment module described above, and "determining the memory access address corresponding to the memory access request based on the hit situation of the memory access request" can be completed by the hit judgment module or the request control module. Step S73 can be completed by the request control module or the data storage module. Step S74 can be completed by the data storage module.

[0215] In a possible implementation, a direct access type memory access request includes a first identifier, and in response to receiving the memory access request, determining the type of the memory access request includes:

[0216] In response to receiving the memory access request, detecting whether the memory access request includes the first identifier;

[0217] In response to the memory access request including the first identifier, determining that the memory access request is a direct access type;

[0218] In response to the memory access request not including the first identifier, it is determined that the memory access request is of a cache type.

[0219] In a possible implementation, the memory access request further includes a request address, the cache area and the direct access area have different address spaces, and in response to receiving the memory access request, determining the type of the memory access request includes:

[0220] In response to receiving the memory access request, detecting an address space corresponding to a request address included in the memory access request;

[0221] In response to a request address included in the memory access request corresponding to an address space of the direct access area, determining that the memory access request is a direct access type;

[0222] In response to the request address included in the memory access request corresponding to the address space of the cache area, it is determined that the memory access request is of the cache type.

[0223] In a possible implementation, the data storage module includes S rows and W columns of cache lines. W cache lines in each row form a group, and S cache lines in each column form a way. W and S are positive integers.

[0224] When the allocation method of the data storage module is group-based allocation, the direct access area includes X rows and W columns of cache lines, and the cache area includes (S - X) rows and W columns of cache lines, where 0 < X < S and X is an integer.

[0225] When the allocation method of the data storage module is way-based allocation, the direct access area includes S rows and Y columns of cache lines, and the cache area direct access area includes S rows and (W - Y) columns of cache lines, where 0 < Y < W and Y is an integer.

[0226] In a possible implementation, the memory access request further includes a request address. When the allocation method of the data storage module is group-based allocation,

[0227] In response to the type of the memory access request being the cache type, determining whether the memory access request hits the cache area includes:

[0228] In response to the memory access request being of the cache type, based on the request address, parsing out the group number where the cache line corresponding to the memory access request is located;

[0229] Based on the group number where the cache line corresponding to the memory access request is located, determining whether the memory access request hits a group of cache lines corresponding to the group number in the cache area.

[0230] In a possible implementation, when the memory access request hits a cache line in a group of cache lines corresponding to the group number in the cache area, the hit situation of the memory access request includes the way number where the hit cache line is located;

[0231] When the memory access request does not hit a group of cache lines corresponding to the group number in the cache area, the hit situation of the memory access request includes information indicating that the memory access request misses.

[0232] In a possible implementation, the method further includes:

[0233] In response to the information indicating that the memory access request misses, selecting another group of cache lines from the cache area;

[0234] Detecting whether there is data to be written to other storage devices in the selected group of cache lines;

[0235] In response to detecting data to be written to the other storage device, after writing the data to the other storage device, replacing a group of cache lines corresponding to the group number with the selected group of cache lines;

[0236] In response to not detecting data to be written to other storage devices, directly replacing a group of cache lines corresponding to the group number with the selected group of cache lines.

[0237] In a possible implementation, the memory access request further includes a request address. When the allocation mode of the data storage module is allocation by way,

[0238] In response to the type of the memory access request being a cache type, determining whether the memory access request hits a cache area includes:

[0239] In response to the memory access request being of a cache type, parsing the way number of the cache line corresponding to the memory access request according to the request address;

[0240] According to the way number of the cache line corresponding to the memory access request, it is determined whether the memory access request hits a cache line in the cache area corresponding to the way number.

[0241] In a possible implementation, when the memory access request hits a cache line in a cache line corresponding to the way number in the cache area, the hit condition of the memory access request includes the group number of the hit cache line;

[0242] When the memory access request misses a cache line in the cache area corresponding to the way number, the hit status of the memory access request includes information indicating that the memory access request misses.

[0243] In a possible implementation, the method further includes:

[0244] In response to information indicating that the memory access request misses, selecting another cache line from the cache area;

[0245] Detecting whether there is data to be written into other storage devices in the selected cache line;

[0246] In response to detecting data to be written into other storage devices, after writing the data into other storage devices, replacing a cache line corresponding to the way number with a selected cache line;

[0247] In response to not detecting data to be written into other storage devices, directly replacing a cache line corresponding to the way number with the selected cache line.

[0248] It should be noted that when the memory access request misses, the cache line replacement can be completed by the request control module, and step S74 can be performed after the cache line replacement is completed.

[0249] In a possible implementation, the memory access request further includes a request address, and in response to the type of the memory access request being a direct access type, parsing the memory access address corresponding to the memory access request according to the memory access request includes:

[0250] In response to the memory access request being a direct access type, detecting an allocation mode of the data storage module, and determining whether an addressing mode of the data storage module and the memory access request are the same;

[0251] In response to the data storage module and the memory access request having the same addressing mode, using the request address as the memory access address;

[0252] In response to different addressing modes of the data storage module and the memory access request, the request address is decoded to obtain the memory access address according to the addressing modes of the data storage module and the memory access request and the allocation mode of the data storage module.

[0253] In a possible implementation, the memory access request further includes a request address, and in response to the type of the memory access request being a direct access type, parsing the memory access address corresponding to the memory access request according to the memory access request includes:

[0254] In response to the memory access request being a direct access type, detecting an allocation mode of the data storage module, and determining whether an addressing mode of the data storage module is the same as that of the memory access request;

[0255] Subtracting the start address of the address space of the direct access area from the request address to obtain an intermediate address;

[0256] In response to the data storage module and the memory access request having the same addressing mode, using the intermediate address as the memory access address;

[0257] In response to different addressing modes of the data storage module and the memory access request, the intermediate address is decoded to obtain the memory access address according to the addressing modes of the data storage module and the memory access request and the allocation mode of the data storage module.

[0258] In a possible implementation, the storage device further includes a request control module, the request control module includes a register group, and the register group is used to configure the allocation mode of the data storage module according to a user's instruction. The method further includes:

[0259] In response to a reduction in the number of cache lines included in the cache area, suspending the reception of new memory access requests, and writing data stored in the reduced cache lines into other storage devices;

[0260] After the data stored in the reduced cache line is written, new memory access requests continue to be received.

[0261] In a possible implementation, the present disclosure further provides a chip, including the storage device described above. A schematic diagram of the structure of the chip can be found in Figure 1a and Figure 1b .

[0262] In a possible implementation, the present disclosure further provides an electronic device, including the chip described above. The electronic device may be a terminal device or a server, and the present disclosure does not limit the specific type of the electronic device.

[0263] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0264] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A storage device, characterized in that: It includes a data storage module, a hit judgment module, and a request control module. The data storage module includes a cache area and a direct access area. The request control module is configured to, in response to receiving a memory access request, determine the type of the memory access request, send the memory access request of the cache type to the hit judgment module, and send the memory access request of the direct access type and the corresponding memory access address to the data storage module. The memory access address corresponding to the memory access request of the direct access type belongs to the direct access area. The hit judgment module is configured to, in response to receiving a memory access request of the cache type, determine whether the memory access request hits the cache area, and send the hit situation of the memory access request to the request control module. The request control module is further configured to, in response to receiving the hit situation of any memory access request of the cache type, determine the memory access address corresponding to the memory access request in the cache area, and send the memory access request and the corresponding memory access address to the data storage module. The memory access address corresponding to the memory access request of the cache type belongs to the cache area. The data storage module is configured to, in response to receiving any memory access request and the corresponding memory access address, access the memory access address corresponding to the memory access request according to the memory access type included in the memory access request.

2. The storage device according to claim 1, characterized in that The memory access request of the direct access type includes a first identifier. Specifically, the request control module is configured to in response to receiving the memory access request, detect whether the memory access request includes the first identifier; in response to the memory access request including the first identifier, determine that the memory access request is of the direct access type; in response to the memory access request not including the first identifier, determine that the memory access request is of the cache type.

3. The storage device according to claim 1, characterized in that: The memory access request further includes a request address. The address spaces of the cache area and the direct access area are different. Specifically, the request control module is configured to in response to receiving the memory access request, detect the address space corresponding to the request address included in the memory access request; in response to the request address included in the memory access request corresponding to the address space of the direct access area, determine that the memory access request is of the direct access type; in response to the request address included in the memory access request corresponding to the address space of the cache area, determine that the memory access request is of the cache type.

4. The storage device according to claim 1, characterized in that: The data storage module includes S rows and W columns of cache lines. Every W cache lines in each row form a group, and every S cache lines in each column form a way. W and S are positive integers. When the allocation method of the data storage module is group-based allocation, the direct access area includes X rows and W columns of cache lines, and the cache area includes (S - X) rows and W columns of cache lines, where 0 < X < S and X is an integer. When the allocation method of the data storage module is way-based allocation, the direct access area includes S rows and Y columns of cache lines, and the cache area and the direct access area include S rows and (W - Y) columns of cache lines, where 0 < Y < W and Y is an integer.

5. The storage device according to claim 4, characterized in that: The memory access request further includes a request address. When the allocation method of the data storage module is group-based allocation, The request control module is specifically configured to, in response to the memory access request being a cache type, parse out the group number of the cache line corresponding to the memory access request according to the request address, and send the group number and the memory access request to the hit determination module; The hit judgment module is specifically used to, in response to receiving a cache type memory access request, determine whether the memory access request hits a group of cache lines corresponding to the group number in the cache area according to the group number of the cache lines corresponding to the memory access request, and send the hit status of the memory access request to the request control module.

6. The storage device according to claim 5, characterized in that: When the memory access request hits a cache line in a group of cache lines corresponding to the group number in the cache area, the hit condition of the memory access request includes the way number where the hit cache line is located; When the memory access request misses a group of cache lines corresponding to the group number in the cache area, the hit status of the memory access request includes information indicating that the memory access request misses.

7. The storage device according to claim 5, characterized in that: The request control module is also used to: In response to information indicating that the memory access request misses, selecting another set of cache lines from the cache area; detecting whether there is data to be written into other storage devices in a selected set of cache lines; In response to detecting data to be written to the other storage device, after writing the data to the other storage device, replacing a group of cache lines corresponding to the group number with the selected group of cache lines; In response to not detecting data to be written to other storage devices, directly replacing a group of cache lines corresponding to the group number with the selected group of cache lines.

8. The storage device according to claim 4, characterized in that: The memory access request also includes a request address. When the allocation mode of the data storage module is allocation by way, The request control module is specifically configured to, in response to the memory access request being a cache type, parse out the way number of the cache line corresponding to the memory access request according to the request address, and send the way number and the memory access request to the hit determination module; The hit judgment module is specifically used to, in response to receiving a cache type memory access request, determine whether the memory access request hits a cache line corresponding to the way number in the cache area according to the way number of the cache line corresponding to the memory access request, and send the hit status of the memory access request to the request control module.

9. The storage device according to claim 8, characterized in that: When the memory access request hits a cache line in a cache line corresponding to the way number in the cache area, the hit condition of the memory access request includes the group number of the hit cache line; When the memory access request misses a cache line in the cache area corresponding to the way number, the hit status of the memory access request includes information indicating that the memory access request misses.

10. The storage device according to claim 8, characterized in that: The request control module is also used to: In response to information indicating that the memory access request misses, selecting another cache line from the cache area; Detecting whether there is data to be written into other storage devices in the selected cache line; In response to detecting data to be written into other storage devices, after writing the data into other storage devices, replacing a cache line corresponding to the way number with a selected cache line; In response to not detecting data to be written into other storage devices, directly replacing a cache line corresponding to the way number with the selected cache line.

11. The storage device according to claim 2, characterized in that: The memory access request also includes a request address, and the request control module is specifically used to: In response to the memory access request being a direct access type, detecting an allocation mode of the data storage module, and determining whether an addressing mode of the data storage module and the memory access request are the same; In response to the data storage module and the memory access request having the same addressing mode, using the request address as the memory access address; In response to different addressing modes of the data storage module and the memory access request, the request address is decoded to obtain the memory access address according to the addressing modes of the data storage module and the memory access request and the allocation mode of the data storage module.

12. The storage device according to claim 3, characterized in that: The memory access request also includes a request address, and the request control module is specifically used to: In response to the memory access request being a direct access type, detecting an allocation mode of the data storage module, and determining whether an addressing mode of the data storage module is the same as that of the memory access request; Subtracting the start address of the address space of the direct access area from the request address to obtain an intermediate address; In response to the data storage module and the memory access request having the same addressing mode, using the intermediate address as the memory access address; In response to different addressing modes of the data storage module and the memory access request, the intermediate address is decoded to obtain the memory access address according to the addressing modes of the data storage module and the memory access request and the allocation mode of the data storage module.

13. The storage device according to claim 1, characterized in that: The request control module includes a register group, and the register group is used to configure the allocation mode of the data storage module according to the user's instructions. The request control module is further configured to, in response to a reduction in the number of cache lines included in the cache area, suspend receiving new memory access requests, and write data stored in the reduced cache lines into other storage devices; After the data stored in the reduced cache line is written, new memory access requests continue to be received.

14. A storage method, characterized in that: The method is applied to a storage device, the storage device includes a data storage module, the data storage module includes a cache area and a direct access area, and the method includes: In response to receiving a memory access request, determining a type of the memory access request, the type comprising a cache type and a direct access type; In response to the type of the memory access request being a cache type, determining whether the memory access request hits a cache area, and determining a memory access address corresponding to the memory access request according to a hit condition of the memory access request, wherein the memory access address corresponding to the cache type memory access request belongs to the cache area; In response to the type of the memory access request being a direct access type, parsing a memory access address corresponding to the memory access request according to the memory access request, wherein the memory access address corresponding to the memory access request of the direct access type belongs to the direct access area; Access a memory access address corresponding to the memory access request according to the memory access type included in the memory access request.

15. A chip, characterized in that: A storage device comprising any one of claims 1-13.

16. An electronic device, characterized in that: Comprising the chip as claimed in claim 15.

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