Communication method of TPM (Trusted Platform Module), TPM, single board and equipment

Abstract

The invention provides a communication method of a TPM (Trusted Platform Module), the TPM, a single board and equipment, and is applied to the technical field of computers, the TPM comprises a TPM logic module, a receiving buffer, a TPM register and a processor, and the TPM register is a storage space divided from a memory of the TPM. The TPM logic module receives a TPM register write command sent by the host and stores the effective load of the write command to the receiving buffer, and the effective load of the TPM register write command is part of or all of the content forming TPM command data; when the data in the receiving buffer reaches a first data volume threshold value, the processor transfers and stores the data in the receiving buffer into a TPM (Trusted Platform Module) register; when all contents of the TPM command data are stored in the TPM register, the processor executes the TPM command data. The problem that TPM hardware cost is high due to the fact that a pure hardware scheme is adopted in TPM communication in the related technology can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a TPM communication method, a TPM, a single board and a device. Background Art

[0002] Trusted Platform Module (TPM) is an independent security chip that can safely store information used to verify the device. The device can be a computer, mobile phone, communication device, etc. The information used to verify the device can be passwords, certificates, encryption keys, etc. As a passive device, TPM will not actively perform operations. The device's business central processing unit (CPU) needs to communicate with TPM as a host and send TPM command data to TPM. Then, TPM executes the task indicated by the TPM command data and returns the task response data to the host.

[0003] Currently, the module used in TPM to communicate with the host is implemented by pure hardware, which increases the overall hardware cost of TPM. Summary of the invention

[0004] The present disclosure provides a TPM communication method, TPM, single board and device, which can solve the problem in the related art that the module used in the TPM for communicating with the host is implemented by pure hardware, resulting in high hardware cost of the TPM. The technical solution is as follows:

[0005] In a first aspect, a communication method of a TPM is provided, wherein the TPM includes a TPM logic module, a receiving buffer, a TPM register, and a processor, wherein the TPM register is a storage space divided in a memory of the TPM, and the method includes:

[0006] The TPM logic module receives the TPM register write command sent by the host, and stores the payload of the TPM register write command in the receiving buffer, wherein the payload of the TPM register write command is part or all of the content constituting the TPM command data. When the data stored in the receiving buffer reaches a first data volume threshold, the processor transfers the data stored in the receiving buffer to the TPM register. When the TPM register has stored all the contents of the TPM command data, the processor executes the task indicated by the TPM command data.

[0007] In the technical solution provided by the present disclosure, the TPM register that needs to store the complete TPM command data is implemented by software simulation (i.e., a storage space is divided in the memory of the TPM, and this storage space is reflected as a TPM register to the outside), and the newly added receiving buffer does not need to be able to store the complete TPM command data, but only needs to be able to store the effective load of a TPM register write command. In the actual implementation, the effective load of a TPM register write command is only a part of the TPM command data. In this case, although the receiving buffer is implemented by hardware, the required chip area is smaller than the chip area required for the TPM register implemented by hardware in the related art, which can effectively save hardware costs. Exemplarily, the TPM register needs to be able to store at least 1k bytes of data, while the receiving buffer only needs to be able to store 128 bytes of data. In terms of hardware implementation, the hardware cost required to implement the receiving buffer is much smaller than the hardware cost required to implement the TPM register.

[0008] In a possible implementation, the TPM further includes a sending buffer, and the method further includes:

[0009] The processor stores the response data of the task in the TPM register, and then transfers the response data stored in the TPM register to the send buffer. The TPM logic module sends the response data stored in the send buffer to the host.

[0010] In the technical solution provided by the present disclosure, a sending buffer is also introduced into the TPM, and the amount of data required to be stored in the sending buffer is similar to the amount of data required to be stored in the receiving buffer. Exemplarily, both the sending buffer and the receiving buffer only need to be able to store 128 bytes of data. In this way, the total amount of data that the sending buffer and the receiving buffer need to be able to store is also much smaller than the amount of data that the TPM register needs to be able to store, that is, the hardware cost will also be much smaller.

[0011] In a possible implementation, the process of storing the response data of the task in the TPM register may include:

[0012] The processor reads data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfers the data to the sending buffer. The TPM logic module receives the TPM register read command sent by the host. The TPM register read command carries indication information of the amount of data to be read. Then, the TPM logic module sends the response data of the amount of data to be read stored in the sending buffer to the host. In addition, the TPM logic module monitors the amount of data stored in the sending buffer, and when the amount of data stored is less than the second data amount threshold, a first interrupt signal is sent to the processor. In response to the first interrupt signal, the processor reads data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfers the data to the sending buffer.

[0013] In the technical solution provided by the present disclosure, the command header of the TPM register read command includes a read data amount field, and the value in the field is the indication information of the amount of data to be read, which is used to indicate the amount of data that the host wants to read. The storage space of the sending buffer is small and may not be able to store the complete response data. In this case, the processor can transfer the response data to the sending buffer in batches.

[0014] In a possible implementation, before the TPM logic module receives the TPM register write command sent by the host, the method further includes:

[0015] The TPM logic module configures the value of the burst count field in the status register to the remaining storage space size of the receiving buffer.

[0016] In the scheme provided by the present disclosure, the value of the burst count field in the status register can be dynamically adjusted by the TPM logic module. The value of the burst count field is provided to the host. In the scenario where the TPM receives command data, the value of this field is used to indicate how much data the TPM can receive without back pressure on the host. In order to make the data sent by the host just be received by the TPM without back pressure on the host, the TPM logic module can configure the value of this field to the remaining storage space size of the receiving buffer in the scenario where the TPM receives command data. In this way, the amount of data of the payload carried in the TPM register write command sent by the host to the TPM can be less than or equal to the remaining storage space size of the receiving buffer, so that the TPM logic module can return a high level signal at the same time as the command header of the TPM register write command is received (when the beat), so that the host can send the payload of the TPM register write command to the TPM without waiting. In this way, the communication method of the TPM provided by the present disclosure can meet the zero delay requirement of the TCG PC Client Platform TPM Profile (TCG PC Client Platform TPM Profile, PTP) specification.

[0017] In a possible implementation, after the processor executes the task indicated by the TPM command data, the method further includes:

[0018] The TPM logic module configures the value of the burst count field in the status register to be the amount of data stored in the send buffer.

[0019] In the solution provided by the present disclosure, in the scenario where the TPM sends data (i.e., the scenario where the host reads the response data of a task from the TPM), the value of the burst count field is used to indicate how much data the TPM can send to the host without back pressure on the host. In order to ensure that the amount of data stored in the sending buffer is not less than the amount of data that the host wants to read, in the scenario where the TPM sends data, the TPM logic module configures the value of the burst count field to the amount of data stored in the sending buffer. In this way, the host can read the response data it wants to read without waiting.

[0020] In a possible implementation, the processor transfers the data stored in the receive buffer to the TPM register, which may be triggered by the TPM logic module and is processed as follows:

[0021] The TPM logic module determines that the data stored in the receiving buffer reaches the first data volume threshold, and sends a second interrupt message to the processor. In response to the second interrupt message, the processor transfers the data stored in the receiving buffer to the TPM register.

[0022] In a second aspect, a TPM is provided, the TPM comprising a TPM logic module, a receiving buffer, a TPM register and a processor, the TPM register being a storage space divided in a memory of the TPM, wherein:

[0023] The TPM logic module is used to receive a TPM register write command sent by a host, and store a payload of the TPM register write command in the receiving buffer, wherein the payload of the TPM register write command is part or all of the content constituting the TPM command data;

[0024] When the data stored in the receiving buffer reaches a first data amount threshold, the processor is used to transfer the data stored in the receiving buffer to the TPM register;

[0025] When all the contents of the TPM command data have been stored in the TPM register, the processor is further configured to execute the task indicated by the TPM command data.

[0026] In a possible implementation, the TPM further includes a sending buffer, and the processor is further configured to store the response data of the task in the TPM register, and transfer the response data stored in the TPM register to the sending buffer;

[0027] The TPM logic module is further configured to send the response data stored in the sending buffer to the host.

[0028] In a possible implementation, the processor is configured to read data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfer the data to the sending buffer;

[0029] The TPM logic module is used for the TPM logic module to receive a TPM register read command sent by the host, wherein the TPM register read command carries indication information of the amount of data to be read;

[0030] Sending the response data of the amount of data to be read stored in the sending buffer to the host;

[0031] The TPM logic module is further configured to determine that the data stored in the sending buffer is less than a second data amount threshold, and send a first interrupt signal to the processor;

[0032] In response to the first interrupt signal, the processor is further configured to read data no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfer the data to the sending buffer.

[0033] In a possible implementation, before the TPM logic module receives the TPM register write command sent by the host, the TPM logic module is further configured to configure the value of the burst count field in the status register as the remaining storage space size of the receiving buffer.

[0034] In a possible implementation, after the processor executes the task indicated by the TPM command data, the TPM logic module is further configured to configure the value of the burst count field in the status register to the data volume of the data stored in the sending buffer.

[0035] In a possible implementation, the TPM logic module is further configured to determine that the data stored in the receiving buffer reaches a first data volume threshold, and send a second interrupt message to the processor;

[0036] In response to the second interrupt message, the processor is configured to transfer the data stored in the receiving buffer to the TPM register.

[0037] In a third aspect, a single board is provided, comprising a processor and a trusted platform module TPM, wherein the processor is used to send register read and write commands to the TPM, and the TPM is used to execute the TPM communication method as described in the first aspect above.

[0038] In a fourth aspect, a device is provided, characterized in that the device includes a CPU and a TPM, wherein the CPU is used to send a TPM register write command to the TPM, and the TPM is used to execute the TPM communication method as described in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a structural schematic diagram of a single board provided by an embodiment of the present disclosure;

[0040] Figure 2 The present disclosure provides a schematic diagram of the structure of a TPM;

[0041] Figure 3 The present disclosure provides a schematic diagram of the structure of a TPM;

[0042] Figure 4 is a schematic diagram of the structure of a TPM provided by an embodiment of the present disclosure;

[0043] Figure 5 is a flow chart of a TPM communication method provided by an embodiment of the present disclosure;

[0044] Figure 6 It is a structural schematic diagram of a device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0046] The present disclosure provides a TPM communication method, which can be applied to a TPM. A TPM can be an independent chip deployed in a device, which can be a computer, a mobile phone, a communication device, etc. Figure 1 , shows a single board of a device, on which a business CPU and a TPM are deployed. The business CPU serves as a host and communicates with the TPM through a serial peripheral interface (SPI).

[0047] The communication between the host and TPM generally includes two processes. One process is: the host sends TPM command data to the TPM through SPI, and the TPM writes the received TPM command data into the TPM register and executes the task indicated by the TPM command data. The other process is: the TPM executes the task indicated by the TPM command data, generates the task response data, writes the task response data into the TPM register, and returns it to the host through SPI.

[0048] In the related art, there are generally two solutions for implementing the above communication process:

[0049] Related technologies 1. Pure hardware implementation

[0050] See also Figure 2 In the pure hardware implementation, the TPM register and TPM logic module are both hardware modules. The following is a brief introduction to the TPM communication process in the pure hardware implementation:

[0051] Step 21, the host's application (Application, app) calls the Trusted Software Stack (Trusted Software Stack, TSS), and calls the TPM driver in the operating system (Operating System, OS) through the TSS, generates TPM command data in the TSS through the TPM driver, and sends the TPM command data to the SPI master module (SPI master).

[0052] Step 22: The SPI master carries the TPM command data in at least one TPM register write command according to the size of the TPM command data, and sends the at least one TPM register write command to the SPI slave module (SPIslave) in the TPM in sequence.

[0053] Step 23: The SPI slave receives the TPM register write command and forwards the TPM register write command to the TPM Logic Module.

[0054] Step 24: The TPM Logic Module parses the TPM register write command and writes the payload of the TPM register write command into the TPM register, wherein the TPM register is used as a data buffer (data FIFO) to store TPM command data and task response data.

[0055] Step 25: When the TPM Logic Module determines that all the contents of the TPM command data have been written into the TPM register, it reports an interrupt to the interrupt handle module.

[0056] Step 26: The Interrupt handle module wakes up the TPM task (TASK) module to execute the task indicated by the TPM command data.

[0057] Step 27: After the TPM TASK module completes the task, it writes the task response data into the TPM register and notifies the TPM Logic Module that the task processing is completed.

[0058] Step 28: The host sends a TPM register read command to the TPM to read the task response data. The TPM LogicModule sends the task response data to the host via the SPI slave.

[0059] In the related art 1, the TPM register is implemented by hardware, and usually the TPM register needs to be able to store at least 1k byte of data. If the TPM needs to support asymmetric encryption algorithm (RSA) 4096, the TPM register needs to be able to store 4k bytes of data. In this case, the area of ​​the hardware-implemented TPM register in the chip will be larger, resulting in higher hardware costs.

[0060] Related Technology 2: Pure Software Implementation

[0061] See also Figure 3 In the pure software implementation, the communication library module (Communicate Lib) is a software module, and the TPM register is implemented by software simulation. Communicate Lib replaces the TPM Logic Module in the pure hardware implementation to implement the relevant functions of the TPM Logic Module. The software simulation implements the TPM register by dividing a storage space in the TPM memory as the TPM register. This storage space is the TPM register for the host. The TPM command data sent by the host and the response data of the task will be stored in this storage space. Among them, RandomAccess Memory can be Random Access Memory (RAM). The following is a brief introduction to the communication process of TPM under the pure software implementation solution:

[0062] Step 31, the host app calls TSS, and calls the TPM driver in the OS through TSS, generates TPM command data in TSS through the TPM driver, and sends the TPM command data to the SPI master.

[0063] Step 32: The SPI master carries the TPM command data in at least one TPM register write command according to the size of the TPM command data, and sends the at least one TPM register write command to the SPI slave in the TPM in sequence.

[0064] Step 33: When the SPI slave receives the TPM register write command, it reports an interrupt to the Interrupt handle module.

[0065] Step 34: The Interrupt handle module notifies Communicate Lib, and Communicate Lib writes the payload of the TPM register write command into the TPM register.

[0066] Step 35: When Communicate Lib determines that all the contents of the TPM command data have been written into TPMregister, it wakes up the TPM TASK module to execute the task indicated by the TPM command data.

[0067] Step 36: After TPM TASK completes the task, it writes the task response data into the TPM register and notifies Communicate Lib that the task processing is completed.

[0068] Step 37: The host sends a TPM register read command to the TPM to read the task response data. CommunicateLib sends the task response data to the host via the SPI slave.

[0069] In the related technology 2, the communication between TPM and host does not meet the zero-delay requirement of the TCG PC Client Platform TPM Profile (PTP) specification. In the PTP specification, it is stipulated that the host needs to be able to read the data returned by TPM at the same time as the host sends the last byte of the command header of the register read / write command to TPM. For the related technology 2, the command header needs to be sent to Communicate Lib by the SPI slave first. After CommunicateLib receives the complete command header, it needs to parse it. Only after parsing can the corresponding data be returned to the host. Therefore, the related technology 2 cannot meet the zero-delay requirement specified by PTP.

[0070] The present disclosure provides a communication method for a TPM, see Figure 4 , TPM includes SPI slave, TPM LogicModule, TPM register, receive buffer (rxFIFO), and transmit buffer (txFIFO). Among them, TPM LogicModule, rxFIFO and txFIFO are hardware modules, and TPM register is implemented by software simulation. In addition, TPM can also include software modules: TPM TASK module, Interrupt handle module and Communicate Lib module, among which Interrupt handle module and Communicate Lib module can be configured in the OS of TPM. These software modules are run by the processor of TPM. Of course, the software modules mentioned here are only exemplary divisions according to the execution functions. These modules can be divided into more software modules or fewer software modules. The specific division of software modules is not limited in the embodiments of the present disclosure.

[0071] Combine the following Figure 4 The TPM shown in the figure illustrates the communication method of the TPM provided by the embodiment of the present disclosure. Figure 5 The communication method provided by the embodiment of the present disclosure may include the following processing flow:

[0072] Step 401: The application program running on the host sends TPM command data to the SPI master.

[0073] In implementation, when the application program running on the host needs to instruct the TPM to perform a task, it can call the TSS, call the TPM driver through the TSS, and generate corresponding TPM command data in the TSS through the TPM driver, and the TPM command data is used to instruct the TPM to perform the corresponding task. Exemplarily, when the TPM needs to be initialized, the TPM command data generated by the host is the initialization (startup) command data, and the initialization command data is used to instruct the TPM to perform the initialization task.

[0074] After generating the TPM command data, the TPM command data is sent to the SPI master through the TPM driver.

[0075] Step 402: The SPI master sends a TPM register write command to the SPI slave module (SPI slave).

[0076] In practice, the host and TPM communicate via SPI, and the SPI protocol that complies with the PTP specification specifies the maximum amount of data in a single transmission of the payload. In addition, there is a burst count field in the TPM status register, which is used to indicate how much data the TPM can receive without back pressure on the host when the TPM receives TPM command data, and how much data the TPM can send to the host without back pressure on the host when the TPM sends task response data.

[0077] Therefore, the SPI master needs to obtain the value of the burst count field in the Status Register. Then, based on the maximum amount of data in the payload of a single transmission specified by the SPI and the value of the burst count field, it determines whether the TPM command data needs to be segmented.

[0078] If the data volume of the TPM command data is greater than the maximum data volume of the payload of a single transmission specified by SPI, or the data volume of the TPM command data is greater than the value of the burst count field, the data slices are cut from the first byte of the TPM command data, and the SPI command header is encapsulated on the data slices to obtain the TPM register write command. The TPM register write command is used to instruct the TPM to write the payload to the specified register. When the data slices are cut, the size of the cut data slices can be MIN (the data volume of the unsent TPM command data, the maximum data volume of the payload of a single transmission specified by SPI, and the data volume indicated by the value of the burst count field), where MIN() means taking the minimum value of the elements in the brackets. Exemplarily, the data volume of the unsent TPM command data is 128 bytes, the maximum data volume of the payload of a single transmission specified by SPI is 64 bytes, and the value of the burst count field is 128, then the cut data slices can be 64 bytes.

[0079] If the amount of TPM command data is less than or equal to the maximum amount of payload data for a single transmission specified by SPI, and the amount of TPM command data is less than or equal to the value of the burst count field, the TPM command data is encapsulated with an SPI command header to obtain a TPM register write command.

[0080] After generating the TPM register write command, the SPI master sends the TPM register write command to the SPI slave. In the process of sending the TPM register write command to the SPI slave, if the SPI master receives a low-level signal returned by the TPM after sending the command header of the TPM register write command, it means that the TPM is not ready to receive the TPM register write command, and the SPI master temporarily does not send the payload in the TPM register write command. If the SPI master receives a high-level signal returned by the TPM, it means that the TPM is ready to receive the TPM register write command, and the SPI master continues to send the payload in the TPM register write command.

[0081] In addition, if the payload in the TPM register write command is a data slice of the TPM command data, after the current TPM register write command is sent, the SPI master continues to split and encapsulate the unsent TPM command data according to the above segmentation rules, generates the corresponding TPM register write command, and sends it to the TPM.

[0082] Step 403: The SPI slave sends a TPM register write command to the TPM Logic Module.

[0083] In implementation, whenever the SPI slave receives data sent by the SPI master, it immediately forwards the received data to the TPM Logic Module.

[0084] Step 404: The TPM Logic Module stores the payload of the TPM register write command into the rxFIFO.

[0085] In implementation, the TPM Logic Module detects whether the remaining storage space of the rxFIFO is sufficient to store the payload in the TPM register write command, and if the remaining storage space of the rxFIFO is sufficient to store the payload in the TPM register write command, the payload in the TPM register write command is stored in the rxFIFO. If the remaining storage space of the rxFIFO is insufficient to store the payload in the TPM register write command, the host is back-pressured.

[0086] Specifically, after receiving the command header of the TPM register write command sent by the SPI slave, the TPM Logic Module parses the command header, determines that the TPM register command currently being received is a TPM register write command through the read / write identification field in the command header, and determines the amount of data to be written (i.e., the amount of data in the payload of the TPM register write command) through the read / write data amount field in the command header. Then, the TPM Logic Module determines whether the amount of data to be written is less than or equal to the remaining storage space size of the rxFIFO.

[0087] If it is determined that the amount of data to be written is less than or equal to the remaining storage space size of the rxFIFO, a high-level signal is returned to the SPI master through the SPI slave to instruct the SPI master to send the payload of the TPM register write command. When the SPI master receives the above high-level signal, it sends the payload of the TPM register write command to the SPI slave. The SPI slave sends the received payload of the TPM register write command to the TPM Logic Module. The TPM Logic Module stores the payload of the TPM register write command in the rxFIFO.

[0088] If it is determined that the amount of data to be written is greater than the remaining storage space size of the rxFIFO, the host is back-pressured. The processing of back-pressure on the host may be: returning a low-level signal to the SPI master through the SPI slave. When the SPI master receives the above low-level signal, it temporarily does not send the payload of the TPM register write command to the SPI slave. The TPM Logic Module stops back-pressure on the host until it detects that the remaining storage space size of the rxFIFO is greater than or equal to the amount of data to be written, and returns a high-level signal to the SPI master through the SPI slave to instruct the SPI master to send the payload of the TPM register write command. When the SPI master receives the above high-level signal, it sends the payload of the TPM register write command to the SPI slave. The SPI slave sends the received payload of the TPM register write command to the TPM Logic Module. The TPM Logic Module stores the payload of the TPM register write command in the rxFIFO.

[0089] In a possible implementation, in order to allow the payload of the TPM register write command sent by the host to be stored in the rxFIFO without generating back pressure, in the disclosed embodiment, the TPM Logic Module can also configure the value of the burst count field in the Status Register according to the current mode of the TPM (receive data mode or send data mode). The following first describes the value of the burst count field configured by the TPM Logic Module in the receive data mode:

[0090] Before the host sends command data to the TPM, it will first notify the TPM. Correspondingly, after the TPM receives the notification, Communicate Lib configures the TPM Logic Module to receive data mode. Then, the TPM Logic Module detects the remaining storage space of the rxFIFO and configures the value of the burst count field in the Status Register to indicate the remaining storage space size of the rxFIFO. For example, if the remaining storage space size of the rxFIFO is 128 bytes, the value of the burst count field can be set to 128.

[0091] Step 405: When the amount of data in the rxFIFO reaches a first data amount threshold, the TPM Logic Module reports a first interrupt signal to the Interrupt handle module.

[0092] In implementation, each time the TPM Logic Module stores the payload of the TPM register write command into the rxFIFO, it detects the amount of data stored in the rxFIFO, and sends a first interrupt signal to the Interrupt handle module if the amount of data stored in the rxFIFO is greater than a first data amount threshold.

[0093] The first data volume threshold may be dynamically configured by Communicate Lib. The configuration of the first data volume threshold is described below:

[0094] Before the host sends command data to the TPM, it will first notify the TPM. Correspondingly, after the TPM receives the notification, Communicate Lib can initialize and configure the first data volume threshold to the command header length of the TPM command data, for example, 10 bytes. After receiving the command header of the TPM command data and transferring the command header of the TPM command data to the TPMRegister, Communicate Lib uses the command header to determine the total data volume of the TPM command data and calculate the remaining data volume of the TPM command data that the current TPM has not yet received. Furthermore, the first data volume threshold is configured as: MIN (the remaining data volume of the TPM command data, the default threshold). For the default threshold, it can be pre-configured according to the actual storage space of the rxFIFO. Exemplarily, the default threshold can be half of the total storage space of the rxFIFO. For example, when the total storage space of the rxFIFO is 128 bytes, the default threshold can be configured as 64 bytes.

[0095] Step 406: The Interrupt handle module sends a first data transfer notification to Communicate Lib.

[0096] In implementation, after receiving the first interrupt signal, the Interrupt handle module sends a first data transfer notification to Communicate Lib through the interrupt processing function, wherein the first data transfer notification is used to instruct Communicate Lib to transfer the data stored in the rxFIFO to the TPM Register.

[0097] Step 407: Communicate Lib transfers the data in the rxFIFO to the TPM Register.

[0098] In implementation, after receiving the first data transfer notification, Communicate Lib transfers the data stored in the rxFIFO to the TPM Register.

[0099] Step 408: After Communicate Lib determines that the TPM command data has been received, it sends a wake-up message to the TPM TASK module.

[0100] In implementation, the command header of the TPM command data includes a data volume indication field, and Communicate Lib can read the value of the data volume indication field and detect whether the data volume of the TPM command data stored in the TPM Register reaches the data volume indicated by the data volume indication field. If the data volume of the TPM command data stored in the TPM Register reaches the data volume indicated by the data volume indication field, it is determined that the TPM command data reception is completed, and a wake-up message is sent to the TPM TASK module.

[0101] Step 409: The TPM TASK module executes the task indicated by the command data and generates task response data.

[0102] In implementation, after receiving the wake-up message, the TPM TASK module obtains the TPM command data stored in the TPM register, parses the TPM command data, executes the task indicated by the TPM command data, and generates the task response data after the task is completed. Exemplarily, if the TPM command data is initialization command data, the TPM TASK module executes the initialization task, and correspondingly, the task response data is the initialization result data.

[0103] Step 410: The TPM TASK module stores the response data of the task in the TPM register, and returns a task completion message to Communicate Lib.

[0104] In implementation, after executing the task indicated by the TPM command data, the TPM TASK module generates task response data, stores the task response data in the TPM register, and returns a task completion message to CommunicateLib.

[0105] Step 411: Communicate Lib transfers the response data of the task to txFIFO.

[0106] In implementation, after receiving the task completion message, Communicate Lib transfers the task response data to the txFIFO. Since the amount of response data may be larger than the storage space of the txFIFO, Communicate Lib may transfer the response data to the txFIFO in multiple times.

[0107] If the response data of the task is transferred only once, after the transfer is completed, the value of the Burst Count field in the status register is set to the amount of data currently stored in the txFIFO, and the value of the available data (dataAvail) field in the Status Register is set to 1. After all task data is read by the HOST, the dataAvail field in the status register is set to 0. The value of the dataAvail field is used to indicate that the host can read the response data of the task from the TPM.

[0108] If the response data of the task is transferred multiple times, after the first transfer is completed, the value of the Burst Count field in the status register is set to the amount of data currently stored in the txFIFO, and the available data (dataAvail) field in the status register is set to 1. After all task data are read by the HOST, the value of the dataAvail field in the status register is set to 0.

[0109] Step 412: The SPI master sends a TPM register read command to the SPI slave.

[0110] In implementation, when the host detects that the value of the dataAvail field in the Status Register of the TPM is 1, it generates a register read command and sends the TPM register read command to the SPI slave through the SPI master. The amount of data to be read indicated by the read data amount field in the command header of the register read command is the amount of data indicated by the value of the Burst Count field.

[0111] Step 413: The SPI slave sends a TPM register read command to the TPM Logic Module.

[0112] In implementation, after receiving the TPM register read command, the SPI slave sends the TPM register read command to the TPM Logic Module.

[0113] Step 414: The TPM Logic Module sends the response data of the task stored in the txFIFO to the SPI slave.

[0114] In implementation, in order to make the amount of data that the host wants to read when reading the response data of the task just the amount of data stored in the txFIFO, in the disclosed embodiment, the TPM Logic Module can configure the value of the burst count field in the StatusRegister. Specifically, after the task is executed, CommunicateLib configures the TPM Logic Module to send data mode, and then the TPM Logic Module detects the amount of data stored in the txFIFO, and configures the value of the burst count field in the Status Register to indicate the amount of data stored in the txFIFO. Exemplarily, if the amount of data stored in the txFIFO is 64 bytes, the value of the burstcount field can be set to 64.

[0115] Based on the above configuration, the TPM Logic Module reads the read data amount field in the command header of the TPM register read command, and determines that the amount of data to be read is the same as the amount of data stored in the txFIFO. In this case, there is no need to backpressure the host, and the data stored in the txFIFO is directly returned to the SPI slave.

[0116] In addition, each time after completing a read operation on the txFIFO, the TPM Logic Module detects the amount of data stored in the txFIFI, and when it is determined that the amount of data stored in the txFIFO is less than the second data amount threshold, it sends a second interrupt signal to the Interrupthandle module. After receiving the second interrupt signal, the Interrupt handle module sends a data supplement notification to Communicate Lib through the interrupt processing function. After receiving the data supplement notification, Communicate Lib reads part or all of the data from the response data of the task stored in the TPM Register that has not yet been transferred and transfers it to the txFIFO. The specific amount of data read and transferred can be MIN (the remaining amount of response data that has not yet been transferred, the remaining storage space size of the txFIFO).

[0117] The second data volume threshold may be dynamically configured by Communicate Lib. The configuration of the second threshold is described below:

[0118] If the response data of the above task only needs to be transferred once, then after the transfer is completed, or while transferring, the second data volume threshold is configured to be less than or equal to the total data volume of the response data. Exemplarily, the second data volume threshold can be configured to be 0.

[0119] If the task result data needs to be transferred multiple times, after the first transfer is completed, or at the same time as the first transfer, the second data volume threshold is configured as the default threshold. Exemplarily, the default threshold can be half of the total storage space of the txFIFO. For example, when the total storage space of the txFIFO is 128 bytes, the default threshold can be configured as 64 bytes. After the last transfer is completed, or at the same time as the last transfer, the second data volume threshold is configured to be less than or equal to the data volume of the current transfer data. Exemplarily, the second data volume threshold can be configured as 0.

[0120] Step 415: The SPI slave sends the response data of the task to the SPI master.

[0121] In the solution provided by the embodiment of the present disclosure, the TPM Register that needs to store complete TPM command data is implemented by software simulation without the need for additional hardware implementation, and the newly introduced rxFIFO does not need to be able to store complete TPM command data, but only needs to be able to store the payload of a TPM register write command. In actual implementation, the payload of a TPM register write command is only a part of the TPM command data. In this way, although the rxFIFO is implemented by hardware, the required chip area is smaller than the chip area required by the TPM Register in the related art, which can effectively save hardware costs. In addition, in the solution provided by the embodiment of the present disclosure, the TPM Logic Module is implemented by hardware, and through cooperation with the rxFIFO, it can return data (i.e., a high-level signal in the embodiment) when receiving the command header of the TPM register write command, so that the host can continue to send the payload of the TPM register write command without waiting, meeting the zero-delay requirement of the PTP specification.

[0122] The present disclosure also provides a device 100. Figure 6 As shown, the device 100 includes: a bus 102, a processor 104, a memory 106, a communication interface 108, and a TPM 110. The processor 104, the memory 106, and the communication interface 108 communicate through the bus 102. The computing device 100 can be a server or a terminal device. It should be understood that the present disclosure does not limit the number of processors and memories in the device 100.

[0123] The bus 102 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 The bus 102 may include a path for transmitting information between various components of the device 100 (eg, the memory 106, the processor 104, and the communication interface 108).

[0124] The processor 104 may include any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). The processor 104 may serve as the host in the above embodiment.

[0125] The memory 106 may include a volatile memory, such as a random access memory (RAM). The memory 106 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0126] The memory 106 stores executable codes, and the processor 104 executes the executable codes to implement relevant functions respectively.

[0127] The communication interface 108 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the device 100 and other devices or a communication network.

[0128] TPM110 may be the TPM mentioned in the above embodiment, and TPM110 and processor 104 communicate with each other via SPI.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication method of a trusted platform module TPM, characterized in that: The TPM includes a TPM logic module, a receiving buffer, a TPM register and a processor, wherein the TPM register is a storage space divided in the memory of the TPM, and the method includes: The TPM logic module receives a TPM register write command sent by a host, and stores a payload of the TPM register write command in the receiving buffer, wherein the payload of the TPM register write command is part or all of the contents constituting the TPM command data; When the data stored in the receiving buffer reaches a first data amount threshold, the processor transfers the data stored in the receiving buffer to the TPM register; When all the contents of the TPM command data have been stored in the TPM register, the processor executes the task indicated by the TPM command data.

2. The method according to claim 1, characterized in that The TPM further includes a sending buffer, and the method further includes: The processor stores the response data of the task in the TPM register; The processor transfers the response data stored in the TPM register to the sending buffer; The TPM logic module sends the response data stored in the sending buffer to the host.

3. The method according to claim 2, characterized in that The processor stores the response data of the task in the TPM register, including: The processor reads data no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfers the data to the sending buffer; The TPM logic module sends the response data stored in the sending buffer to the host, including: The TPM logic module receives a TPM register read command sent by the host, wherein the TPM register read command carries indication information of the amount of data to be read; The TPM logic module sends the response data of the amount of data to be read stored in the sending buffer to the host; The method further comprises: The TPM logic module determines that the data stored in the sending buffer is less than a second data amount threshold, and sends a first interrupt signal to the processor; In response to the first interrupt signal, the processor reads data no larger than the remaining storage space of the sending buffer from the remaining data of the response data stored in the TPM register, and transfers the data to the sending buffer.

4. The method according to any one of claims 1 to 3, characterized in that Before the TPM logic module receives the TPM register write command sent by the host, the method further includes: The TPM logic module configures the value of the burst count field in the status register as the remaining storage space size of the receiving buffer.

5. The method according to any one of claims 1 to 4, characterized in that After the processor executes the task indicated by the TPM command data, the method further includes: The TPM logic module configures the value of the burst count field in the status register to be the data volume of the data stored in the sending buffer.

6. The method according to any one of claims 1 to 5, characterized in that When the data stored in the receiving buffer reaches a first data amount threshold, the processor transfers the data stored in the receiving buffer to the TPM register, including: The TPM logic module determines that the data stored in the receiving buffer reaches a first data volume threshold, and sends a second interrupt message to the processor; In response to the second interrupt message, the processor transfers the data stored in the receiving buffer to the TPM register.

7. A trusted platform module TPM, characterized in that: The TPM includes a TPM logic module, a receiving buffer, a TPM register and a processor, wherein the TPM register is a storage space divided in the memory of the TPM, wherein: The TPM logic module is used to receive a TPM register write command sent by a host, and store a payload of the TPM register write command in the receiving buffer, wherein the payload of the TPM register write command is part or all of the content constituting the TPM command data; When the data stored in the receiving buffer reaches a first data amount threshold, the processor is used to transfer the data stored in the receiving buffer to the TPM register; When all the contents of the TPM command data have been stored in the TPM register, the processor is further configured to execute the task indicated by the TPM command data.

8. The TPM according to claim 7, characterized in that: The TPM further includes a sending buffer, and the processor is further configured to store the response data of the task in the TPM register, and transfer the response data stored in the TPM register to the sending buffer; The TPM logic module is further configured to send the response data stored in the sending buffer to the host.

9. The TPM according to claim 8, characterized in that: The processor is configured to read data that is no larger than the remaining storage space of the sending buffer from the response data stored in the TPM register, and transfer the data to the sending buffer; The TPM logic module is used for the TPM logic module to receive a TPM register read command sent by the host, wherein the TPM register read command carries indication information of the amount of data to be read; Sending the response data of the amount of data to be read stored in the sending buffer to the host; The TPM logic module is further configured to determine that the data stored in the sending buffer is less than a second data amount threshold, and send a first interrupt signal to the processor; In response to the first interrupt signal, the processor is further configured to read data no larger than the remaining storage space of the sending buffer from the remaining data of the response data stored in the TPM register, and transfer the data to the sending buffer.

10. The TPM according to any one of claims 7 to 9, characterized in that: Before the TPM logic module receives the TPM register write command sent by the host, the TPM logic module is further configured to configure the value of the burst count field in the status register as the remaining storage space size of the receiving buffer.

11. The TPM according to any one of claims 7 to 10, characterized in that: After the processor executes the task indicated by the TPM command data, the TPM logic module is further configured to configure the value of the burst count field in the status register to the data amount of the data stored in the sending buffer.

12. The TPM according to any one of claims 7 to 11, characterized in that: The TPM logic module is further configured to determine that the data stored in the receiving buffer reaches a first data volume threshold, and send a second interrupt message to the processor; In response to the second interrupt message, the processor is configured to transfer the data stored in the receiving buffer to the TPM register.

13. A single board, characterized in that: The single board includes a central processing unit (CPU) and a trusted platform module (TPM), wherein the CPU is used to send a register write command to the TPM, and the TPM is used to execute the trusted platform module (TPM) communication method according to any one of claims 1 to 6.

14. A device, characterized in that The device comprises a central processing unit (CPU) and a trusted platform module (TPM), wherein the CPU is used to send a TPM register write command to the TPM, and the TPM is used to execute the trusted platform module (TPM) communication method according to any one of claims 1 to 6.

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