Instruction operation method, instruction operation device, electronic device and storage medium

Abstract

The invention discloses an instruction operation method, an instruction operation device, an electronic device and a storage medium. The instruction operation method comprises the steps that a plurality of operation instructions are received, and each operation instruction comprises an instruction part; in response to the fact that at least one object operation instruction in the multiple operation instructions further comprises a constant operand, performing compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and storing a plurality of operation instructions according to the at least one compressed constant operand. The instruction operation method can reduce wasted instruction storage space through compression processing of constant operands.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction operation method, an instruction operation device, an electronic device, and a storage medium. Background Art

[0002] With the advent of the era of big data and artificial intelligence, the requirements for the processing performance of computer systems are getting higher and higher. In order to improve the processing performance of the processor, the processor front end needs to provide more instructions to the processor for execution faster. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an instruction operation method, which includes receiving a plurality of operation instructions, wherein each of the plurality of operation instructions includes an instruction part; in response to at least one object operation instruction among the plurality of operation instructions also including a constant operand, compressing the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and storing the plurality of operation instructions according to the at least one compressed constant operand.

[0004] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, multiple operation instructions are microinstructions; based on at least one compressed constant operand, storing the multiple operation instructions includes: storing the multiple operation instructions in a microinstruction cache.

[0005] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, storing multiple operation instructions according to at least one compressed constant operand further includes: merging the multiple operation instructions into a logical storage item for arrangement.

[0006] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, a logical storage item is established according to preset constraint rules, and the preset constraint rules are used to respectively determine the arrangement of multiple operation instructions in the logical storage item.

[0007] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, merging multiple operation instructions into a logical storage item for arrangement includes: storing the logical storage item in a corresponding physical cache item in the microinstruction cache.

[0008] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, at least one object operation instruction includes multiple object operation instructions; the logical storage item includes multiple instruction domains and multiple constant storage domains, the instruction parts of the multiple object operation instructions are respectively arranged in the multiple instruction domains, and the compressed constant operands of the multiple object operation instructions are respectively arranged in the multiple constant storage domains.

[0009] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, storing multiple operation instructions based on at least one compressed constant operand also includes: determining the arrangement form of the multiple compressed constant operands in the constant storage domain based on the data size of the compressed constant operands of the multiple object operation instructions and based on the arrangement capacity of each of the multiple constant storage domains.

[0010] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, the arrangement of multiple compressed constant operands in the constant storage domain includes: arranging the multiple compressed constant operands in the same object constant storage domain in the multiple constant storage domains.

[0011] For example, in the instruction operation method provided in at least some embodiments of the present disclosure, multiple operation instructions are stored according to at least one compressed constant operand, and the method also includes: determining the arrangement order of multiple compressed constant operands in the object constant storage field according to the instruction order of the multiple object operation instructions.

[0012] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, the constant operand includes an immediate number and / or a shift number.

[0013] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, compressing the constant operand of at least one object operation instruction includes: removing the sign extension bit of the constant operand to compress the constant operand.

[0014] For example, in the instruction operation method provided by at least some embodiments of the present disclosure, receiving a plurality of operation instructions includes: receiving the plurality of operation instructions from a decoding unit.

[0015] At least some embodiments of the present disclosure also provide an instruction operation device, which includes a receiving module, a compression module and a storage module; the receiving module is configured to receive multiple operation instructions, wherein each of the multiple operation instructions includes an instruction part; the compression module is configured to compress the constant operand of the at least one object operation instruction in response to at least one object operation instruction among the multiple operation instructions also including a constant operand, so as to obtain at least one compressed constant operand; the storage module is configured to store the multiple operation instructions based on the at least one compressed constant operand.

[0016] At least some embodiments of the present disclosure also provide an instruction operation device, which includes at least one storage unit and at least one processing unit; the at least one storage unit stores computer-executable instructions; and the at least one processing unit is configured to execute the computer-executable instructions. When the computer-executable instructions are executed by the at least one processing unit, the instruction operation method provided by any embodiment of the present disclosure is implemented.

[0017] At least some embodiments of the present disclosure also provide an electronic device, which includes a decoding unit and a microinstruction cache, wherein the microinstruction cache is configured to: receive multiple operation instructions from the decoding unit, wherein each of the multiple operation instructions includes an instruction part; in response to at least one object operation instruction among the multiple operation instructions also including a constant operand, compress the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and store the multiple operation instructions based on the at least one compressed constant operand.

[0018] At least some embodiments of the present disclosure also provide a non-transitory storage medium that non-transitory stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, the instruction operation method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0020] Figure 1 A schematic diagram of the basic structural division of a processor is shown;

[0021] Figure 2A A schematic diagram of a scenario in which a processor performs instruction fetching provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 2B A flowchart of an instruction operation method provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 3 A schematic diagram showing the structure of a logical storage item and a physical cache item provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 4 An assembly program corresponding to an operation instruction provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 5 A schematic diagram showing the arrangement of an operation instruction in a logic item;

[0026] Figure 6 A schematic diagram showing the arrangement of an operation instruction in a logical storage item provided by at least one embodiment of the present disclosure;

[0027] Figure 7 A block diagram showing a command operation device provided by at least one embodiment of the present disclosure;

[0028] Figure 8A block diagram showing another instruction operation device provided by at least one embodiment of the present disclosure;

[0029] Fig. 9 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0030] Fig.10 A schematic diagram showing the structure of an electronic device provided by at least one embodiment of the present disclosure; and

[0031] Fig.11 A schematic diagram of a non-transitory storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0035] The terms used in the present disclosure are those common terms currently widely used in the art in consideration of the functions of the present disclosure, but these terms may vary according to the intention of a person of ordinary skill in the art, precedents, or new technologies in the art. In addition, specific terms may be selected by the applicant, and in this case, their detailed meanings will be described in the detailed description of the present disclosure. Therefore, the terms used in the specification should not be understood as simple names, but rather as an overall description based on the meaning of the terms and the present disclosure.

[0036] Flowcharts are used in this disclosure to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the previous or following operations are not necessarily performed precisely in order. On the contrary, various steps can be processed in reverse order or simultaneously as needed. At the same time, other operations can also be added to these processes, or one or more operations can be removed from these processes. The pipeline for processor instruction processing includes multiple pipeline stages, for example, instructions must go through branch prediction (Branch prediction), instruction fetch (Instruction fetch), instruction decoding (Decode), instruction dispatch (Dispatch), instruction execution (Execute), instruction termination (Retire), etc.

[0037] In order to improve the performance of the front end of the processor pipeline in providing instructions to the back end, improvements can be made in two aspects: one is to increase the bandwidth of the processor front end to fetch instructions, and the other is to reduce the delay of the processor to fetch instructions.

[0038] Figure 1 The basic structural division diagram of a processor is shown in FIG. 5 . The processor 500 includes at least one processor core 503 . The processor core 503 includes a pipeline for instruction processing. For example, the pipeline of the processor core 503 includes a front end 501 and a back end 502 .

[0039] For example, the processor can store instructions by setting an instruction cache (Cache) in the front end 501. Since the processor can quickly obtain instructions from the instruction cache in the instruction fetching stage, the front end performance of the processor can be optimized by optimizing the instruction cache; the obtained instructions can be decoded to obtain microinstructions in the instruction decoding stage, and the microinstructions are distributed to wait for execution. For example, in addition to the instruction cache, the processor can also add a microinstruction cache (UopCache) in the front end 501. The microinstruction cache is used to store the microinstructions that are frequently used by the processor recently, so that the processor can directly call the microinstructions that are frequently used recently from the microinstruction cache in the instruction fetching stage, thereby improving the instruction processing speed of the processor and reducing power consumption.

[0040] For storing microinstructions in a microinstruction cache, for example, at least one microinstruction may be first determined based on the frequency of use of microinstructions obtained from the instruction sequence executed by the processor, and then the microinstructions may be stored based on the minimum storage unit of the microinstruction cache. For example, the minimum storage unit of the microinstruction cache is a physical cache item. For example, at least one microinstruction may be arranged in a logic item according to a certain rule, and then each logic item may be stored in a corresponding physical cache item of the microinstruction cache, so as to store at least one microinstruction in the microinstruction cache.

[0041] As the number of processing cores in the processor increases, the way the processor calls microinstructions from the microinstruction cache has a more obvious effect on improving the processor's instruction processing speed and reducing system power consumption. Therefore, storing more microinstructions in the microinstruction cache is very important for improving the processor's instruction fetch performance. However, due to the limited chip size, the storage capacity of the microinstruction cache cannot be expanded indefinitely. Therefore, how to store more microinstructions in the limited instruction storage space of the microinstruction cache is an urgent problem to be solved. For example, when microinstructions are stored in the corresponding physical cache items of the microinstruction cache through logical items, there will be a situation where the microinstructions in the logical items are not fully arranged, resulting in a large number of fragmented logical items.

[0042] The inventors of the present disclosure have noticed that, in response to the above problems, two storage compression methods for storing microinstructions have been proposed to store more microinstructions into the microinstruction cache.

[0043] In the first storage compression method, when microinstructions are arranged into logic items according to certain rules, the instruction items for arranging the instruction part and the constant items for arranging constant operands are distinguished in the logic items. If there is a situation in the fragmented logic item where the arrangement space of the instruction items is not full, and the arrangement space of the constant items is not enough, the storage space of the instruction items can be squeezed to arrange the constant operands in the arrangement space of the instruction items until the space is full, so that the microinstructions can be arranged in one logic item.

[0044] The second storage compression method compresses and merges all fragmented logical items in pairs before storing them in the physical cache items, and stores the merged logical items in the corresponding physical cache items, thereby reducing the waste of instruction storage space in the microinstruction cache caused by fragmented logical items, improving the utilization rate of the microinstruction cache, and allowing more microinstructions to be stored in the microinstruction cache.

[0045] However, the above method only compresses the fragmented logic items, but does not compress other non-fragmented logic items. Therefore, the above method does not compress all logic items as a whole, and the effect of improving the utilization of the microinstruction cache is not obvious, and further, the effect of improving the processor instruction processing speed and reducing the overall power consumption is not obvious.

[0046] At least one embodiment of the present disclosure proposes an instruction operation method, which includes: receiving multiple operation instructions, wherein each of the multiple operation instructions includes an instruction part; in response to at least one object operation instruction among the multiple operation instructions also including a constant operand, compressing the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; storing the multiple operation instructions based on the at least one compressed constant operand.

[0047] In the instruction operation method of the above embodiment of the present disclosure, by compressing the constant operands included in the object operation instructions in multiple operation instructions, each operation instruction to be stored can be compressed as a whole. On the one hand, this reduces the waste of instruction storage space, makes better use of the limited instruction storage space, and improves the performance of the processor front end providing instructions to the processor back end; on the other hand, it improves the instruction processing speed of the processor and reduces the power consumption of the system.

[0048] Various embodiments of the present disclosure will be described below with reference to specific examples.

[0049] Figure 2A A schematic diagram of a scenario in which a processor performs instruction fetching according to at least one embodiment of the present disclosure is shown.

[0050] like Figure 2A As described above, the instruction fetching architecture of the front end of the processor includes a branch predictor (BranchPredictor) 01 , an instruction fetching task queue 02 , a microinstruction queue 03 and a scheduler 04 .

[0051] The branch predictor 01 can perform branch prediction operations on multiple operation instructions. For example, it can perform branch prediction on the jump destination address of the branch instruction (such as if statement, for loop statement, etc.) in the currently executed instruction sequence, generate prediction information, and generate instruction fetch tasks based on the branch prediction information.

[0052] The instruction fetch task queue 02 stores branch prediction information, which is used by the instruction fetch unit to fetch the corresponding operation instruction. For example, the processor front end can select the instruction fetch mode according to the hit situation of the microinstruction obtained after decoding the operation instruction in the microinstruction cache 20. The instruction fetch mode includes the instruction fetch mode and the microinstruction fetch mode. The instruction fetch mode is the default selection.

[0053] For example, in the instruction fetch mode, after the instruction fetch unit obtains the object instruction in the instruction cache 11 according to the instruction fetch task in the instruction fetch task queue 02, the decoding unit 12 decodes the object instruction to obtain one or more microinstructions, which are sent to the microinstruction queue 03 and are also cached in the microinstruction cache 20. If a certain microinstruction is cached in the microinstruction cache 20 and is found to have been cached in the microinstruction cache 20, it is called a hit in the microinstruction cache 20, otherwise it is a miss, that is, the microinstruction has not been cached in the microinstruction cache 20. The "object instruction" here refers to the instruction that is used as the description object among the multiple instructions stored in the instruction cache 11 that have not been decoded by the decoding unit 12.

[0054] For example, within a certain period of time, if all microinstructions obtained by the decoding unit 12 are hit in the microinstruction cache 20, it can be assumed that subsequent microinstructions can also be hit, thereby switching the instruction fetch mode to the microinstruction fetch mode, and the instruction fetch unit directly fetches instructions in the microinstruction cache 20 according to the instruction fetch tasks in the instruction fetch task queue 02. If the instruction fetch unit does not hit the microinstruction in the microinstruction cache 20, the instruction fetch mode is switched back to the instruction fetch mode.

[0055] The microinstruction queue 03 is used to store microinstructions to be allocated to the execution units.

[0056] The scheduler 04 determines on which execution unit the microinstructions in the microinstruction queue 03 are executed. For example, the scheduler 04 distributes the operation instructions to the execution units, such as the integer unit, the floating point unit, etc.

[0057] Figure 2B A flowchart of an instruction operation method provided by at least one embodiment of the present disclosure is shown. The instruction operation method is used, for example, for a processor core of a processor (single-core processor or multi-core processor).

[0058] like Figure 2B As shown, in some embodiments of the present disclosure, the instruction operation method includes steps S30, S31 and S32.

[0059] Step S30: receiving multiple operation instructions.

[0060] Operation instructions include operation codes (Opcode) and operands (Operands). The operation code is used to indicate the type of operation to be performed, and the operand is the data required to execute the operation instruction. For example, the operand can include non-constant operands such as register address (Register Address) or memory address (Memory Address). For another example, the operand can also include constant operands such as immediate number (Immediate) and shift number (Shift Count). Immediate number (Immediate) represents a specific value that can be used directly when the operation instruction is executed. For example, an operation instruction of the type of data transfer, arithmetic operation or logical operation includes an immediate number. The shift number (Shift Count) is used to specify the number of bits of the shift operation in the shift operation instruction.

[0061] For example, the microinstruction cache at the front end of the processor pipeline receives multiple operation instructions, which are microinstructions. The front end of the pipeline includes, for example, an instruction fetch unit, a decoding unit, an instruction cache, a microinstruction cache, an instruction queue, etc. For example, instructions that may be used during the execution of a program are cached in the instruction cache. After the decoding unit obtains the instruction to be operated from the instruction cache according to the instruction fetch address, it performs a decoding operation on it to obtain multiple microinstructions, which are sent to the microinstruction cache. In an embodiment of the present disclosure, each of the multiple operation instructions includes an instruction portion.

[0062] In the present disclosure, the "instruction part" includes an operation code and a non-constant operand. As mentioned above, the operation code is the part of the operation instruction that indicates the type of operation to be performed, which is used to tell the processor what kind of operation needs to be performed, such as addition, subtraction, data transfer, logical operation, etc.

[0063] When the non-constant operand is, for example, a register address or a memory address, when the operation instruction is executed, the processor will perform the operation of the constant operand according to the memory address represented by the non-constant operand.

[0064] For example, in some embodiments of the present disclosure, step S30 in the above instruction operation method also includes step S300.

[0065] Step S300: receiving a plurality of operation instructions from a decoding unit.

[0066] The decoding unit receives instructions from the instruction cache according to the instruction fetch address, analyzes the information such as the opcode and operand in the instruction, and generates multiple corresponding microinstructions. For example, a data transfer instruction can be implemented by two microinstructions: reading the source operand and writing the target location; for another example, a data transfer request instruction can generate a microinstruction for reading the source operand and a microinstruction for writing the target location.

[0067] Step S31: In response to at least one object operation instruction among the multiple operation instructions further including a constant operand, compress the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand.

[0068] Some of the multiple operation instructions may include constant operands, which are operands directly embedded in the operation instructions. Here, "object operation instruction" is used to refer to instructions that are described as objects in the multiple operation instructions.

[0069] In some embodiments of the present disclosure, the constant operand in the above instruction operation method includes an immediate number and / or a shift number.

[0070] For example, an object operation instruction including a constant operand can be compressed by a compression algorithm, thereby obtaining at least one compressed constant operand in the operation instruction. For example, Huffman Coding can be used to make the most commonly used operation instructions use shorter codes, thereby reducing the total length of the operation instructions. For another example, the LZ77 algorithm can be used to identify and replace the operation mode corresponding to the repeated operation code, thereby reducing the redundancy of the operation instruction, as well as other compression algorithms and combinations of multiple compression algorithms. It should be noted that the embodiments of the present disclosure do not limit the specific compression algorithm.

[0071] After compressing the constant operands of at least one object operation instruction among multiple operation instructions, at least one compressed constant operand can be obtained; after compressing the constant operands of each object operation instruction among multiple operation instructions, all compressed constant operands of multiple operation instructions are obtained.

[0072] It should be noted that the object operation instructions to be compressed can be selected according to storage requirements. For example, only a portion of the object operation instructions in multiple operation instructions can be compressed with constant operands, while the other portion of the object operation instructions are not compressed with constant operands or compressed with other compression algorithms.

[0073] Step S32: storing a plurality of operation instructions according to at least one compressed constant operand.

[0074] For example, the instruction storage space storing the operation instruction can be divided into an instruction space and a constant space, the instruction space is used to store the instruction part corresponding to the operation instruction, and the constant space is used to store the constant part corresponding to the operation instruction. For example, multiple operation instructions can be directly stored in the corresponding instruction storage space according to at least one compressed constant operand. For example, the instruction storage space can be a cache, such as a microinstruction cache.

[0075] When storing multiple operation instructions, for example, all compressed constant operands in the multiple operation instructions may be stored; for example, some compressed constant operands and uncompressed constant operands may be stored together.

[0076] For example, in some embodiments of the present disclosure, step S31 in the above instruction operation method also includes step S310.

[0077] Step S310: remove the sign extension bit of the constant operand to compress the constant operand.

[0078] When storing any one of the multiple operation instructions, the instruction part and the constant operand included in the operation instruction can be stored respectively correspondingly. For example, the instruction part is stored in the instruction space, and the constant operand is stored in the constant space.

[0079] The storage of constant operands can be stored according to the granularity of the operation instruction. For example, in the x86 architecture processor, the basic unit (also called granularity) for data storage and processing is 32 bits (Bit), so constant operands (immediate values ​​or shift values) are stored in a 32-bit data format. For example, even if the actual size of some constant operands is less than 32 bits, they will be expanded to 32 bits to maintain a consistent storage format for the operation instruction. For example, if there is an immediate value of 8 bits (1 Byte) in the operation instruction, the immediate value needs to be expanded to 32 bits, occupying 32 bits of storage space.

[0080] For example, the storage of a constant operand can maintain the correct storage of the constant operand through the sign extension bit. For example, the granularity in the constant storage space is 32 bits (Bit), and the constant operand is 8 bits (Bit). For example, the constant operand is the binary number 0b10000001 (-127 in decimal). For example, when it is directly extended to 32 bits without using the sign extension bit, the extended binary number 0b00000000 00000000 00000000 10000001 (129 in decimal) is obtained, resulting in an extension error; for example, when it is extended to 32 bits through the sign extension bit, 0b11111111 11111111 1111111110000001 (-127 in decimal) is obtained, making the extension correct.

[0081] Although storing the operation instructions according to the granularity of the operation instructions can keep the operation instructions in a consistent storage format, the increase of the sign extension bit will cause a certain waste of storage space. Therefore, the sign extension bit of the constant operand can be removed to obtain a compressed constant operand, and then the compressed constant operand can be stored in the constant storage space, so that the constant storage space can be used more effectively.

[0082] For example, when an operation instruction includes an immediate number and / or a displacement number, the immediate number and / or the displacement number after expansion according to the granularity is identified, the number of bits with actual numerical significance is retained, and the sign extension bit is directly removed. For example, the immediate number after expansion according to the granularity in an operation instruction is 0x00000008, which occupies 32 bits. Then, by removing the sign extension bit, the immediate number can be compressed to 0x08, occupying only 8 bits of storage space. For example, the immediate number after expansion according to the granularity in an operation instruction is 0xfffffff8. Then, by removing the sign extension bit, the immediate number is compressed to 0xf8.

[0083] Decoding Microinstruction Fetch Mode In some embodiments of the present disclosure, a plurality of operation instructions in the above instruction operation method are microinstructions, and step S32 includes step S320.

[0084] Step S320: Store the plurality of operation instructions into the microinstruction cache.

[0085] As mentioned above, the operation instructions are microinstructions. Figure 2A As shown, when the instruction fetch mode is the instruction fetch decoding mode, the instruction fetch unit will fetch the object instruction from the instruction cache 11 according to the instruction fetch task stored in the instruction fetch task queue 02, and then decode the object instruction through the decoding unit 12 to obtain one or more microinstructions, and send the one or more microinstructions obtained from the decoding unit 12 to the microinstruction queue 03 for scheduling by the scheduler 04. At the same time, the one or more microinstructions obtained from the decoding unit 12 are also cached in the microinstruction cache 20. The instruction cache 11 is used to store at least one recently used object instruction to reduce the time to obtain instructions from the memory. The decoding unit (Decoder) 12 is used to decode the object instruction taken out from the instruction cache 11 to obtain a microinstruction.

[0086] For example, Figure 2A As shown, in the microinstruction instruction fetch mode, the instruction fetch unit directly obtains one or more microinstructions from the microinstruction cache 20 through the microinstruction cache instruction fetch queue 21 according to the instruction fetch task in the instruction fetch task queue 02, and the one or more microinstructions are transmitted to the microinstruction queue 03 through the microinstruction cache pipeline 22 for storage, so that the scheduler 04 can schedule the microinstructions to the corresponding execution unit for execution.

[0087] For example, in some embodiments of the present disclosure, the microinstruction cache 20 is composed of a hardware module that has been completely designed and laid out.

[0088] For example, the microinstruction cache 20 may include multiple cache lines, each of which may include multiple physical cache entries 200, each of which includes a tag field for identifying the cache entry for indexing. The cache lines are mapped, for example, in a set associative, direct associative, etc. The embodiments of the present disclosure do not limit the specific implementation of the microinstruction cache.

[0089] The time period used to complete one beat of operation in the above processor pipeline is a clock cycle, also called a machine cycle.

[0090] Compared with the decoded instruction fetch mode, the microinstruction fetch mode has at least three advantages:

[0091] First, the bandwidth is higher. The microinstruction fetch mode can send more operation instructions to the microinstruction queue 03 in each machine cycle than the decoding instruction fetch mode. For example, in the same machine cycle, 8 microinstructions can be sent to the microinstruction queue 03 in the microinstruction fetch mode, while only 4 microinstructions can be decoded and issued to the microinstruction queue 03 in the decoding instruction fetch mode.

[0092] Secondly, the latency is lower. The speed from receiving the prediction information to obtaining the microinstructions corresponding to the prediction information in the microinstruction fetch mode is faster than the speed from obtaining the prediction information through the instruction cache and the decoding unit in the decoding instruction fetch mode.

[0093] Thirdly, power consumption is lower. In the microinstruction fetch mode, instructions can be sent directly from the microinstruction cache to the dispatch stage corresponding to the microinstruction queue without going through complex circuits such as the instruction cache and decoding unit in the decoding instruction fetch mode. Therefore, the power consumption of the instruction fetch process in the microinstruction fetch mode is lower.

[0094] Therefore, by storing the microinstructions including the compressed constant operands in the microinstruction cache 20, the microinstruction cache 20 can store more microinstructions, so that the processor front end can process the operation instructions more quickly and efficiently. The microinstruction cache 20 can store more microinstructions and also increase the possibility of the microinstruction cache 20 being hit, thereby enabling the processor to work in the microinstruction fetch mode for more time during the instruction fetch process, which can further improve the performance of the entire processor to a certain extent.

[0095] In some embodiments of the present disclosure, for multiple operation instructions that may be used frequently, after being decoded by the decoding unit 12, the decoded multiple microinstructions can be stored in the microinstruction cache 20 to construct the microinstruction cache 20, thereby further improving the hit rate of the microinstruction cache 20.

[0096] In some embodiments of the present disclosure, the above instruction operation method may further include step S220.

[0097] Step S220: Establishing a logical storage item according to preset constraint rules.

[0098] For example, multiple operation instructions may be stored in the microinstruction cache through a logical storage item according to at least one compressed constant operand.

[0099] Figure 3 A schematic diagram of the structure of a logical storage item and a physical cache item provided by at least one embodiment of the present disclosure is shown.

[0100] like Figure 3 As shown, the logical storage item includes multiple instruction fields and multiple constant storage fields.

[0101] The number of instruction fields and constant storage fields in the logical storage item and the arrangement capacity of each instruction field and each constant storage field are determined according to the preset constraint rules. The arrangement capacity is used to indicate the size of data that can be arranged in each instruction field and each constant storage field. For example, the arrangement capacity can be 32 bits, 64 bits, etc., which is not limited in the present disclosure.

[0102] For example, in some embodiments of the present disclosure, preset constraint rules are used to constrain the maximum number of instruction fields for arranging instruction parts in a logical storage item and the maximum number of constant fields for arranging constant operands.

[0103] For example, when a logical storage item is established according to a preset constraint rule, the preset constraint rule stipulates:

[0104] (a) A logical storage item includes at most 8 instruction fields for arranging 8 instruction parts;

[0105] (b) A logical storage item includes at most four constant storage fields that arrange four constant operands.

[0106] In some embodiments of the present disclosure, the preset constraint rules may further include more constraint rules. For example, the arrangement rules of the instruction part and the constant operands may be agreed upon. For example, when all constant storage fields in a logical storage item are full and there are at least two empty instruction fields, the constant operands may occupy the space of the instruction fields for arrangement until the space of a logical storage item can no longer arrange the operation instructions.

[0107] For example, a logical storage item may be constructed according to a preset constraint rule. For example, a logical storage item 100 including 8 instruction fields Uop and 4 constant storage fields ID may be constructed according to a preset constraint rule.

[0108] In some embodiments of the present disclosure, the logical storage item 100 also includes header data Misc info. For example, the size of the header data Misc info is 16 bits, and the header data Misc info is used to indicate information of the instruction domain and the constant storage domain in the logical storage item 100.

[0109] like Figure 3 As shown, the microinstruction cache 20 includes a plurality of physical cache items 200. Each physical cache item 200 may have a plurality of physical cache slots (Bank) 210 with equal storage capacity. For example, the storage capacity of each physical cache slot is nBits, where n is a positive integer. For example, a physical cache item 200 is composed of 8 physical cache slots 210, and the storage capacity of the physical cache item 200 is nBits*8.

[0110] For example, the microinstruction cache 20 is composed of a plurality of cache modules, for example, the microinstruction cache 20 is composed of two cache modules each having 256 physical cache items. It should be noted that, although the description is given of two cache modules with the same storage capacity being combined into a microinstruction cache, the microinstruction cache may also be composed of a plurality of other cache modules with different storage capacities, and the embodiments of the present disclosure do not limit the number of cache modules and the storage capacity of the cache modules.

[0111] In some embodiments of the present disclosure, preset constraint rules are used to respectively determine the arrangement of multiple operation instructions in logical storage items.

[0112] After the logical storage item is created according to the preset constraint rules, multiple operation instructions stored in the microinstruction cache will need to be stored to determine the arrangement in the logical storage item.

[0113] For example, according to the preset constraint rules, the arrangement of multiple instruction parts and at least one compressed constant operand in the multiple operation instructions is determined respectively.

[0114] For example, in some embodiments of the present disclosure, at least one object operation instruction in the above-mentioned instruction operation method includes multiple object operation instructions; the logical storage item includes multiple instruction domains and multiple constant storage domains, and the instruction parts of the multiple object operation instructions are respectively arranged in the multiple instruction domains, and the compressed constant operands of the multiple object operation instructions are respectively arranged in the multiple constant storage domains.

[0115] For example, when multiple operation instructions are arranged in a logical storage item, if any part of multiple instruction fields or multiple constant storage fields in the logical storage item is full, the overflowing operation instructions are arranged to the next logical storage item.

[0116] In some embodiments of the present disclosure, step S32 in the above instruction operation method also includes step S321.

[0117] Step S321: combine multiple operation instructions into a logical storage item for arrangement.

[0118] refer to Figure 3 , 8 instruction domain Uops and 4 constant storage domain IDs are planned according to the preset constraint rules. When some operation instructions are fully arranged in any part of the 8 instruction domain Uops or 4 constant storage domain IDs in a logical storage item, the remaining multiple operation instructions are transferred to the next logical storage item for arrangement.

[0119] For example, each of the multiple operation instructions needs to be arranged in the same logical storage item. For example, for an operation instruction, its instruction part and constant operand need to be arranged in the same logical storage item. If the current logical storage item only has instruction fields or constant storage fields left, then for the operation instructions that have not been arranged, the next logical storage item will be selected for arrangement based on the principle that the operation instructions are arranged in the same logical storage item.

[0120] In some embodiments of the present disclosure, step S321 in the above instruction operation method also includes step S3210.

[0121] Step S3210: Store the logical storage item in the corresponding physical cache item in the microinstruction cache.

[0122] For example, Figure 3 As shown, when the logical storage item 100 in which the operation instructions are arranged is stored in the physical cache item 200, since the hardware structure of the physical cache item 200 is not exactly the same as the construction form of the logical storage item 100, when the logical storage item 100 is mapped and stored in the physical cache item 200, the operation instructions arranged in the logical cache item 100 can be mapped to each physical cache slot 210 of the physical cache item 200 for storage according to the arrangement capacity size in the logical storage item 100.

[0123] For example, the mapping relationship between the storage in the logical storage item 100 and each physical cache slot 210 in the physical cache item 200 can be determined by dividing the arrangement capacity in the logical storage item 100 by the number of physical cache slots 210 in the physical cache item 200. For example, the logical storage item 100 includes 8 instruction domain Uops with an arrangement capacity of 32 bits and 4 constant storage domain IDs with an arrangement capacity of 32 bits, and the physical cache item 200 includes 8 physical cache slots 210 with a storage capacity of nBits. Then, according to (8*32+4*32) / 8 = 48 (bits), it can be determined that each physical cache slot 210 corresponds to the mapping storage logical physical item with a size of 48 bits, where n is greater than or equal to 48.

[0124] Figure 4 An assembly program corresponding to an operation instruction provided by at least one embodiment of the present disclosure is shown.

[0125] Each assembly program corresponds to at least one machine instruction. For example, the machine instruction can be represented by a binary code or a hexadecimal code. Each machine instruction corresponds to an operation instruction. Each operation instruction is composed of an operation code, a non-constant operand, and a constant operand. According to the execution order of the assembly program, the instruction order of each operation instruction can be determined.

[0126] like Figure 4 In the assembly program shown, the operation code, non-constant operand and constant operand encoding corresponding to each operation instruction are shown in Table 1. The machine instructions shown in Table 1 are represented by hexadecimal codes.

[0127] Table 1

[0128]

[0129] Figure 5 A schematic diagram showing the arrangement of an operation instruction in a logic item.

[0130] like Figure 5 As shown, the operation instructions of the assembly program shown in Table 1 are arranged.

[0131] For example, the instruction part and constant operand of an operation instruction need to be arranged in the same logic item, and when the instruction item or constant item in a logic item is full, it needs to be arranged to the next logic item.

[0132] For example, both logic item A and logic item B include 8 instruction items and 4 constant item IDs. For example, among the 8 operation instructions shown in Table 1, since the constant operands in the operation instructions of instruction sequence 1 to instruction sequence 7 already include 4 constant operands, all constant items of logic item A will be occupied. Therefore, logic item A arranges the operation instructions of instruction sequence 1 to instruction sequence 7, and the operation instruction of instruction sequence 8 needs to be arranged in the next logic item B.

[0133] For example, in logic item A, the instruction parts of the operation instructions of instruction sequence 1 to instruction sequence 7 are respectively arranged in the instruction items of the logic item; and, the constant operands of the operation instructions of instruction sequence 4 to instruction sequence 7 are respectively arranged in the constant items of the logic item (the operation instructions corresponding to instruction sequence 1 to instruction sequence 3 have no constant operands); in logic item B, the operation instructions corresponding to instruction sequence 8 are arranged.

[0134] For example, when arranging operation instructions in logical items, the constant operands of the operation instructions are encoded and arranged according to the actual storage mode in the physical cache items. For example, in the logical items corresponding to the x86-64 architecture, each constant item is usually 32 bits wide. For example, the physical cache items can be stored in Little Endian. Therefore, when the constant operand is an 8-bit immediate value 0x8, which can be encoded as 32 bits, it will be placed in the lowest 8 bits of the 32-bit word, and the remaining bits are filled with sign extension bits.

[0135] For example, instruction portion 5c8 push, instruction portion 5ca push, instruction portion 5cb mov, instruction portion 5ce movl, instruction portion 6d5 movl, instruction portion 6dc sub, and instruction portion 6e0sar are arranged in the instruction item of logic item A. For example, the constant operand is sign-extended and arranged according to the little-endian storage format. For example, the constant operand $0x8 corresponding to the instruction part 5ce movl is sign-extended to 0x00000008 and arranged as 08000000 in the constant item; the constant operand $0xc corresponding to the instruction part 6d5 movl is sign-extended to 0x0000000c and arranged as 0c000000 in the constant item; the constant operand $0x8 corresponding to the instruction part 6dc sub is sign-extended to 0x00000008 and arranged as 08000000 in the constant item; the constant operand $0x3 corresponding to the instruction part 6e0 sar is sign-extended to 0x00000003 and arranged as 03000000 in the constant item. The instruction part 6e3 lea is arranged in the instruction item of the logic item B, and the corresponding constant operand 0x2007be is sign-extended to 0x2007be00, and is arranged as be072000 in the constant item according to the little-endian storage format.

[0136] At this time, there is still an empty instruction item in logic item A, but due to the fact that all constant items in logic item A are already occupied, the operation instruction with instruction sequence 8 needs to be arranged in the next logic item B. Therefore, the 8 operation instructions in arrangement table 1 need to use 2 logic storage items.

[0137] In some embodiments of the present disclosure, step S32 in the above instruction operation method also includes step S322.

[0138] Step S322: Determine the arrangement form of the multiple compressed constant operands in the constant storage domain according to the data size of the compressed constant operands of the multiple object operation instructions and the arrangement capacity of each of the multiple constant storage domains.

[0139] For example, multiple compressed constant operands may be combined into at least one data having a size equal to the arrangement capacity in the constant storage field according to the instruction sequence, so that the multiple compressed constant operands are arranged in one constant storage field.

[0140] It should be noted that, although the instruction part is represented by the operation address and the operation code in the above embodiment, it does not represent a limitation on the arrangement of the content of the instruction part in the instruction field.

[0141] In some embodiments of the present disclosure, in the above instruction operation method, the arrangement of multiple compressed constant operands in the constant storage domain includes: arranging the multiple compressed constant operands in the same object constant storage domain among the multiple constant storage domains.

[0142] Figure 6 A schematic diagram showing the arrangement of an operation instruction in a logical storage item provided by at least one embodiment of the present disclosure is shown.

[0143] like Figure 6 As shown, the operation instructions of the assembly program shown in Table 1 are arranged. For example, the logic storage item 100 includes 8 instruction fields and 4 constant storage fields with an arrangement capacity of 32 bits.

[0144] For example, constant operands can be compressed by removing the sign extension bit of the constant operands. For example, for the operation instructions of instruction sequence 1 to instruction sequence 7, the constant operand 0x00000008 corresponding to the instruction part 5ce movl is compressed to 0x08; the constant operand 0x0000000c corresponding to the instruction part 6d5 movl is compressed to 0x0c; the constant operand $0x8 corresponding to the instruction part 6dc sub is sign-extended to 0x00000008 and compressed to 0x08; the constant operand 0x00000003 corresponding to the instruction part 6e0 sar is compressed to 0x03. The data size of the above multiple compressed constant operands is compressed from the original 32 bits to 8 bits, according to the arrangement capacity of each constant storage domain of 32 bits.

[0145] For example, constant operands in a logical storage item can be arranged according to the Little Endian storage format.

[0146] In some embodiments of the present disclosure, step S32 in the above instruction operation method also includes step S323.

[0147] Step S323: determining the arrangement order of the plurality of compressed constant operands in the object constant storage domain according to the instruction order of the plurality of object operation instructions.

[0148] For example, the compressed constant operands 0x08, 0x0c, 0x08, and 0x03 may be arranged in order from high to low in the object constant storage field according to the instruction sequence, that is, the constant operand 0x08 with a front instruction sequence is arranged in the first 8 high bits in the object constant storage field, and then the constant operands 0x0c, 0x08, and 0x03 are arranged in the corresponding positions in sequence.

[0149] For example, the above four compressed constant operands can be combined into a data of the same size as the capacity arranged in the constant storage domain according to the instruction order, thereby determining the arrangement order of multiple compressed constant operands in the object constant storage domain. For example, the compressed constant operands 0x08, 0x0c, 0x08 and 0x03 are combined into 0x080c0803 according to the instruction order and arranged in a constant storage domain.

[0150] After the operation instructions of instruction sequence 1 to instruction sequence 7 are arranged in the logic storage item 100, there is still 1 instruction field and 3 constant storage fields left in the logic storage item 100. Therefore, the operation instruction of instruction sequence 8 can continue to be arranged in the logic storage item 100. The above method can make the 8 operation instructions that were originally to be arranged in two logic items (logic item A and logic item B) be arranged in one logic storage item, saving the arrangement space of the logic storage item, thereby improving the storage utilization of the microinstruction cache, so that more operation instructions can be stored in the microinstruction cache of the same capacity.

[0151] In some embodiments of the present disclosure, constant operands may be compressed by removing some sign extension bits.

[0152] For example, for the operation instructions from instruction sequence 1 to instruction sequence 7, the constant operand 0x00000008 corresponding to the instruction part 5ce movl is compressed to 0x0008; the constant operand 0x0000000c corresponding to the instruction part 6d5 movl is compressed to 0x000c; the constant operand $0x8 corresponding to the instruction part 6dc sub is sign-extended to 0x00000008 and compressed to 0x0008; the constant operand 0x00000003 corresponding to the instruction part 6e0 sar is compressed to 0x0003.

[0153] For example, the compressed constant operands 0x0008 and 0x000c are combined into 0x0008000c, and the compressed constant operands 0x0008 and 0x0003 are combined into 0x00080003 according to the instruction sequence.

[0154] The data size of the above multiple compressed constant operands is compressed from the original 32 bits to 16 bits. According to the arrangement capacity of each constant storage domain of 32 bits, every two compressed constant operands can be arranged in one constant storage domain. In this way, the original 4 constant operands can occupy 2 constant storage domains instead of 4 constant storage domains.

[0155] After the operation instructions of instruction sequence 1 to instruction sequence 7 are arranged in the logic storage item 100 , there is still 1 instruction field and 2 constant storage fields left in the logic storage item 100 , and the operation instructions of instruction sequence 8 can continue to be arranged in the logic storage item 100 .

[0156] Through the above-mentioned two exemplary compression methods, multiple compressed constant operands can be arranged in the same object constant storage domain in multiple constant storage domains, and the utilization rate of the constant storage domains in the logical storage items is improved; such logical storage items are stored in physical cache items, which also improves the storage utilization rate of the microinstruction cache, so that more operation instructions can be stored in the microinstruction cache of the same capacity.

[0157] Figure 7 A block diagram of an instruction operation device provided by at least one embodiment of the present disclosure is shown.

[0158] like Figure 7 As shown, at least one embodiment of the present disclosure further provides an instruction operation device 800 , including a receiving module 801 , a compression module 802 , and a storage module 803 .

[0159] The receiving module 801 is configured to receive a plurality of operation instructions, wherein each of the plurality of operation instructions includes an instruction part.

[0160] The compression module 802 is configured to, in response to at least one object operation instruction among the multiple operation instructions further including a constant operand, compress the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand.

[0161] The storage module 803 is configured to store a plurality of operation instructions according to at least one compressed constant operand.

[0162] In some embodiments of the present disclosure, the storage module 803 is configured to store the microinstruction cache (see, for example, Figure 2A ) to perform storage operations.

[0163] In some embodiments of the present disclosure, the storage module 803 further includes an arrangement module 804. The arrangement module 804 is configured to combine multiple operation instructions into a logical storage item for arrangement.

[0164] In some embodiments of the present disclosure, the instruction operation device 800 further includes an establishment module 805. The establishment module 805 is configured to establish a logical storage item according to a preset constraint rule, and the preset constraint rule is used to respectively determine the arrangement of multiple operation instructions in the logical storage item.

[0165] In some embodiments of the present disclosure, the arrangement module 804 further includes a cache item storage module 8040. The cache item storage module 8040 is configured to store the logical storage item in the corresponding physical cache item in the microinstruction cache.

[0166] In some embodiments of the present disclosure, the compression module 802 further includes an extension bit removal module 8020. The extension bit removal module 8020 is configured to remove the sign extension bit of the constant operand to compress the constant operand.

[0167] The technical effect of the instruction operation device of the above embodiment of the present disclosure is the same as the technical effect of the above instruction operation method, so it will not be repeated.

[0168] Figure 8A block diagram of another instruction operation device provided by at least one embodiment of the present disclosure is shown.

[0169] like Figure 8 As shown, at least one embodiment of the present disclosure further provides an instruction operation device 600 , including at least one storage unit 610 and at least one processing unit 620 .

[0170] At least one storage unit 610 is configured to store computer executable instructions. At least one processing unit 620 is configured to execute computer executable instructions, wherein the computer executable instructions are executed by at least one processing unit to implement the instruction operation method provided by any embodiment of the present disclosure. The processing unit can be, for example, any processing circuit with processing capabilities, which can be implemented by hardware or firmware, such as a processor (CPU). The storage unit can include, for example, a semiconductor storage unit. The embodiments of the present disclosure do not limit the implementation of the storage unit 610 and the processing unit 620.

[0171] The technical effect of the instruction operation device of the above embodiment of the present disclosure is the same as the technical effect of the above instruction operation method, so it will not be repeated.

[0172] Fig. 9 A block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0173] like Fig. 9 As shown, at least one embodiment of the present disclosure further provides an electronic device 700 , wherein the electronic device 700 includes a decoding unit 701 and a microinstruction cache 702 .

[0174] The microinstruction cache 702 is configured to receive multiple operation instructions from the decoding unit, wherein each of the multiple operation instructions includes an instruction part; in response to at least one object operation instruction among the multiple operation instructions also including a constant operand, compress the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; and store the multiple operation instructions based on the at least one compressed constant operand.

[0175] For example, the electronic device is a processor core, which may be a single-core processor or a multi-core processor. The processor core includes a pipeline for instruction processing, the pipeline includes a front end and a back end, the front end includes a branch prediction unit, an instruction cache, etc. in addition to the above-mentioned decoding unit and microinstruction cache, and the embodiments of the present disclosure do not limit the instruction set (such as X86 instruction set, ARM instruction set, RSIC-V instruction set, etc.) applicable to the processor core and the adopted microarchitecture.

[0176] The technical effect of the electronic device of the above embodiment of the present disclosure is the same as the technical effect of the above instruction operation method, so it will not be repeated.

[0177] At least one embodiment of the present disclosure also provides another electronic device, wherein the electronic device includes the instruction operation device described in at least one of the above embodiments.

[0178] Fig.10 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0179] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.10 The electronic device 1000 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0180] For example, refer to Fig.10 In some examples, the electronic device 1000 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1008 to a random access memory (RAM) 1003. Various programs and data required for the operation of the computer system are also stored in the RAM 1003. The processing device 1001, the ROM 1002, and the RAM 1003 are connected to each other through an Internet 1004. An input / output (I / O) interface 1005 is also connected to the Internet 1004.

[0181] For example, the processing device 1001 may Fig. 9 The example of the electronic device shown includes a microinstruction cache and a microinstruction cache operating device.

[0182] For example, the following components may be connected to the I / O interface 1005: an input device 1006 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1007 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1008 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1009 may allow the electronic device 1000 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1010 is also connected to the I / O interface 1005 as needed. Removable media 1011, such as magnetic disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive 1010 as needed, so that the computer program read therefrom can be installed into the storage device 1008 as needed. Although Fig.10 The electronic device 1000 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0183] For example, the electronic device 1000 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1009 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0184] For example, the electronic device 1000 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0185] At least one embodiment of the present disclosure further provides a non-transitory storage medium that non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a processor, the instruction operation method provided by at least one embodiment of the present disclosure is implemented.

[0186] Fig.11 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. Fig.11 As shown, the non-transitory storage medium 900 can store computer executable instructions 910 non-transitorily. When the computer executable instructions 910 are executed by a computer, the instruction operation method provided by any embodiment of the present disclosure is implemented.

[0187] There are a few points to note about this disclosure:

[0188] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0189] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0190] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A command operation method, comprising: Receiving a plurality of operation instructions, wherein each of the plurality of operation instructions comprises an instruction part; In response to at least one object operation instruction among the plurality of operation instructions further including a constant operand, compressing the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; The plurality of operation instructions are stored according to the at least one compressed constant operand.

2. The instruction operation method according to claim 1, wherein: The plurality of operation instructions are microinstructions, According to the at least one compressed constant operand, storing the plurality of operation instructions comprises: The plurality of operation instructions are stored in a microinstruction cache.

3. The instruction operation method according to claim 2, wherein: According to the at least one compressed constant operand, storing the plurality of operation instructions further comprises: The multiple operation instructions are combined into a logical storage item for arrangement.

4. The instruction operation method according to claim 3, further comprising: The logical storage item is established according to preset constraint rules, wherein the preset constraint rules are used to respectively determine the arrangement of the multiple operation instructions in the logical storage item.

5. The instruction operation method according to claim 3, wherein: The combining the plurality of operation instructions into a logical storage item for arrangement includes: The logical storage item is stored in a corresponding physical cache item in the microinstruction cache.

6. The instruction operation method according to claim 3, wherein: The at least one object operation instruction includes a plurality of object operation instructions; The logic storage item includes a plurality of instruction fields and a plurality of constant storage fields, The multiple instruction fields are respectively arranged with instruction parts of the multiple object operation instructions, and the multiple constant storage fields are respectively arranged with compressed constant operands of the multiple object operation instructions.

7. The instruction operation method according to claim 6, wherein: According to the at least one compressed constant operand, storing the plurality of operation instructions further comprises: According to the data size of the compressed constant operands of the plurality of object operation instructions and according to the arrangement capacity of each of the plurality of constant storage fields, the arrangement form of the plurality of compressed constant operands in the constant storage field is determined.

8. The instruction operation method according to claim 7, wherein: The arrangement of the plurality of compressed constant operands in the constant storage area includes: The plurality of compressed constant operands are arranged in a same object constant storage field in the plurality of constant storage fields.

9. The instruction operation method according to claim 8, wherein: According to the at least one compressed constant operand, storing the plurality of operation instructions further comprises: According to the instruction sequence of the plurality of object operation instructions, an arrangement sequence of the plurality of compressed constant operands in the object constant storage field is determined.

10. The instruction operation method according to any one of claims 1 to 9, wherein: The constant operand includes an immediate value and / or a shift value.

11. The instruction operation method according to any one of claims 1 to 9, wherein: The compressing the constant operand of the at least one object operation instruction comprises: The sign extension bit of the constant operand is removed to compress the constant operand.

12. The instruction operation method according to any one of claims 1 to 9, wherein: The receiving of multiple operation instructions comprises: The plurality of operation instructions are received from a decoding unit.

13. A command operation device, comprising: A receiving module, configured to receive a plurality of operation instructions, wherein each of the plurality of operation instructions includes an instruction part; a compression module configured to, in response to at least one object operation instruction among the plurality of operation instructions further including a constant operand, perform compression processing on the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; The storage module is configured to store the plurality of operation instructions according to the at least one compressed constant operand.

14. A command operation device, comprising: at least one storage unit storing computer executable instructions; as well as at least one processing unit configured to execute said computer executable instructions, Wherein, when the computer executable instructions are executed by the at least one processing unit, the instruction operation method according to any one of claims 1-12 is implemented.

15. An electronic device comprising a decoding unit and a microinstruction cache, wherein: The microinstruction cache is configured as follows: receiving a plurality of operation instructions from the decoding unit, wherein each of the plurality of operation instructions comprises an instruction portion; In response to at least one object operation instruction among the plurality of operation instructions further including a constant operand, compressing the constant operand of the at least one object operation instruction to obtain at least one compressed constant operand; The plurality of operation instructions are stored according to the at least one compressed constant operand.

16. A non-transitory storage medium that non-transitorily stores computer-executable instructions, wherein: When the computer executable instructions are executed by at least one processor, the instruction operation method according to any one of claims 1 to 13 is implemented.

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