Multiplexed calculator circuit and method of performing multiple calculation tasks therefor, electronic chip

Abstract

The application provides a multi-channel calculator circuit, comprising: a processing unit for configuring calculation parameter information and calculation channel information, reading and storing the calculation parameter information and the calculation channel information according to a calculation flag signal, and reading calculation result information according to a corresponding channel completion signal; a parameter unit for generating the calculation parameter information, the calculation channel information and a detection trigger signal according to the configuration information; a detection unit for protecting the calculation parameter information and the calculation channel information according to the detection trigger signal, generating a calculation trigger signal, and generating the calculation flag signal according to the state of the calculation unit; a calculation unit for calculating the calculation parameter information according to the calculation trigger signal, generating the calculation result information and a calculation completion signal; and a storage unit for storing the calculation result information into a corresponding storage channel according to the calculation channel information and the calculation completion signal, and generating the corresponding channel completion signal. The application solves the problems of large chip area or slow processing speed in the prior art.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a multi-channel calculator circuit and a method for performing multiple computing tasks, as well as an electronic chip. Background Technology

[0002] Many chips contain calculation functions such as multiplication, division, and square root. These calculation functions are generally implemented using software or hardware. The disadvantage of using software calculation is that the calculation time is long and the calculation speed is slow, which is not friendly to applications with strict time requirements. The disadvantage of using hardware calculation is that a calculator (multiplication unit, division unit, or square root unit, etc.) can only perform one calculation task. When there are multiple calculation tasks at the same time, multiple independent calculators need to be designed, which will greatly increase the chip area.

[0003] The specific analysis is as follows: When using a single calculator to handle multiple calculation tasks simultaneously, calculation errors may occur in two situations. Let's take a level 2 division calculation task as an example:

[0004] In the first scenario, when the division calculation task (i.e., level 1 division calculation task) in the main function is being calculated, the interrupt function is entered. The division calculation task (i.e., level 2 division calculation task) in the interrupt function is triggered. At this time, the division calculation task in the interrupt function will interrupt and overwrite the division calculation task in the main function, causing the division calculation task in the main function to be calculated incorrectly.

[0005] In the second scenario, when the division task in the main function (i.e., the level 1 division task) has been configured with a dividend or divisor but has not yet started calculation, it enters the interrupt function. The division task in the interrupt function (i.e., the level 2 division task) is triggered. At this time, the dividend and divisor of the division task in the interrupt function will overwrite the dividend and divisor of the division task in the main function, causing the division task in the main function to make a calculation error.

[0006] Therefore, whether it is software computing or hardware computing, in order to ensure the accuracy of the calculation, there are usually several independent calculators required for each level of computing task. For example, a level 1 division calculation task requires one division unit, a level 2 division calculation task requires two division units, a level 3 division calculation task requires three division units, and so on.

[0007] However, for hardware computing, the more calculators in the hardware, the larger the area occupied; for software computing, the more calculators in the software, the longer the calculation time, the slower the calculation speed, and the more CPU resources consumed. Therefore, how to handle multiple computing tasks simultaneously with a single calculator while balancing area usage and calculation speed is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multi-channel calculator circuit and a method for performing multiple calculation tasks, as well as an electronic chip, to solve the problem that existing hardware or software calculation schemes cannot handle multiple calculation tasks simultaneously through a single calculator, resulting in large chip area or slow processing speed.

[0009] To achieve the above and other related objectives, the present invention provides a multi-channel calculator circuit, which includes: a processing unit, a parameter unit, a detection unit, a calculation unit, and a storage unit;

[0010] The processing unit is used to configure calculation parameter information and calculation channel information, read and store the calculation parameter information and calculation channel information from the parameter unit according to the calculation flag signal, and read the calculation result information from the corresponding storage channel of the storage unit according to the corresponding channel completion signal. The calculation flag signal includes a trigger busy flag signal and a calculation busy flag signal.

[0011] The parameter unit is connected to the processing unit and is used to generate the calculation parameter information, the calculation channel information and the detection trigger signal according to the configuration information.

[0012] The detection unit is connected to the parameter unit and is used to protect the calculation parameter information and the calculation channel information according to the detection trigger signal and generate a calculation trigger signal, and to generate the trigger busy flag signal and the calculation busy flag signal according to the state of the calculation unit.

[0013] The calculation unit is connected to the detection unit and is used to calculate the calculation parameter information according to the calculation trigger signal and generate the calculation result information and the calculation completion signal;

[0014] The storage unit is connected to the detection unit and the calculation unit, and is used to store the calculation result information into the corresponding storage channel and generate the corresponding channel completion signal according to the calculation channel information and the calculation completion signal.

[0015] Optionally, the processing unit generates a corresponding parameter configuration signal when configuring each calculation parameter in the calculation parameter information, and generates a corresponding parameter reading signal when reading each calculation parameter in the calculation parameter information; the detection unit includes: a calculation channel module, M calculation parameter modules, a trigger generation module and a flag generation module, where M is an integer greater than or equal to 1;

[0016] The calculation channel module is connected to the parameter unit and is used to protect the calculation channel information according to the detection trigger signal;

[0017] M calculation parameter modules are connected to the parameter unit and are used to protect each calculation parameter in the calculation parameter information according to the detection trigger signal;

[0018] The trigger generation module is connected to the parameter unit and is used to generate the calculation trigger signal based on the detection trigger signal;

[0019] The flag generation module is connected to the processing unit, the trigger generation module, and the calculation unit, and is used to generate the trigger busy flag signal and the calculation busy flag signal. The trigger busy flag signal is triggered by any of the parameter configuration signals, and the trigger busy flag signal is cleared by the calculation trigger signal or any of the parameter read signals. The calculation busy flag signal is triggered by the calculation trigger signal, and the calculation busy flag signal is cleared by the calculation completion signal.

[0020] Optionally, the computing channel module includes: a first multiplexer and a first register, wherein the selection terminal of the first multiplexer is connected to the detection trigger signal, the first input terminal is connected to the output terminal of the first register, the second input terminal is connected to the computing channel information, the output terminal is connected to the input terminal of the first register, and the output terminal of the first register outputs the computing channel information.

[0021] Optionally, the calculation parameter module includes: a second multiplexer and a second register, wherein the selection terminal of the second multiplexer is connected to the detection trigger signal, the first input terminal is connected to the output terminal of the second register, the second input terminal is connected to the corresponding calculation parameters, the output terminal is connected to the input terminal of the second register, and the output terminal of the second register outputs the corresponding calculation parameters.

[0022] Optionally, the trigger generation module includes a D trigger.

[0023] Optionally, the flag generation module includes: a first OR gate, a second OR gate, a first RS flip-flop, and a second RS flip-flop; the input of the first OR gate is connected to each of the parameter configuration signals, and the output is connected to the set terminal of the first RS flip-flop; the reset terminal of the first RS flip-flop is connected to the output of the second OR gate, and the output generates the trigger busy flag signal; the input of the second OR gate is connected to the calculation trigger signal and each of the parameter read signals; the set terminal of the second RS flip-flop is connected to the calculation trigger signal, the reset terminal is connected to the calculation completion signal, and the output generates the calculation busy flag signal.

[0024] Optionally, the storage unit includes: an information conversion module and N storage channels, where N is an integer greater than 1;

[0025] The information conversion module is connected to the detection unit and is used to convert the calculation channel information into a channel selection signal, wherein the channel selection signal is a set of N-bit binary code;

[0026] The N storage channels are connected to the computing unit and the information conversion module, and are used to store the computing result information into the corresponding storage channel and generate the corresponding channel completion signal according to the computing completion signal and the channel selection signal.

[0027] Optionally, the processing unit generates a corresponding channel read signal when reading the calculation result information in the corresponding storage channel; the storage channel includes: an AND gate, a third multiplexer, a third register, and a third RS flip-flop; the first input of the AND gate is connected to the calculation completion signal, the second input is connected to the corresponding bit of the channel selection signal, and the output is connected to the selection terminal of the third multiplexer and the set terminal of the third RS flip-flop; the first input of the third multiplexer is connected to the output of the third register, the second input is connected to the calculation result information, the output is connected to the input of the third register, and the output of the third register outputs the calculation result information; the reset terminal of the third RS flip-flop is connected to the corresponding channel read signal, and the output generates a corresponding channel completion signal.

[0028] The present invention also provides an electronic chip, the electronic chip comprising: a multi-channel calculator circuit as described in any of the above claims.

[0029] The present invention also provides a method for a multi-channel calculator circuit as described in any of the above claims to perform multiple computational tasks, the method comprising:

[0030] Step 1) Execute the previous level calculation task. The processing unit configures the previous level calculation parameter information and the previous level calculation channel information. The parameter unit generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous level calculation parameter information and the previous level calculation channel information. The calculation unit performs calculations on the previous level calculation parameter information.

[0031] When the next level of computation arrives, the processing unit determines whether the busy flag signal is valid. If valid, it reads and stores the previous level computation parameter information and the previous level computation channel information from the parameter unit, configures the next level computation parameter information and the next level computation channel information, generates the next level computation parameter information and the next level computation channel information according to the configuration information, and triggers the detection unit to protect the next level computation parameter information and the next level computation channel information. The computation unit calculates the next level computation parameter information, and then waits for the next level computation task to complete. The processing unit reads the calculation result information of the corresponding stored channel and executes step 2). If invalid, it executes step 3.

[0032] Step 2) The processing unit reconfigures the stored previous-level calculation parameter information and previous-level calculation channel information. The parameter unit generates the previous-level calculation parameter information and previous-level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous-level calculation parameter information and previous-level calculation channel information. The calculation unit calculates the previous-level calculation parameter information, and then waits for the previous-level calculation task to complete. The processing unit reads the calculation result information of the corresponding storage channel.

[0033] Step 3) The processing unit determines whether the computation busy flag signal is valid; if valid, it waits for the previous level computation task to complete and reads the computation result information of the corresponding storage channel before executing step 4); if invalid, it directly executes step 4.

[0034] Step 4) The processing unit configures the next-level calculation parameter information and the next-level calculation channel information. The parameter unit generates the next-level calculation parameter information and the next-level calculation channel information according to the configuration information, and triggers the detection unit to protect the next-level calculation parameter information and the next-level calculation channel information. The calculation unit calculates the next-level calculation parameter information, and then waits for the next-level calculation task to complete. The processing unit reads the calculation result information of the corresponding storage channel.

[0035] As described above, the multi-channel calculator circuit and its method for performing multiple calculation tasks, as well as the electronic chip of the present invention, through the design of processing units, parameter units, detection units, calculation units, and storage units, can perform on-site protection and on-site recovery of calculation parameter information and calculation channel information, enabling multiple calculation tasks to be executed simultaneously with only one calculator; the circuit of the present invention occupies a small area, has a fast calculation speed, consumes few CPU resources, and is simple and convenient to operate, making it suitable for single-level or multi-level calculation tasks. Attached Figure Description

[0036] Figure 1The diagram shown is a schematic representation of the multi-channel calculator circuit of this invention.

[0037] Figure 2 The diagram shown is a schematic representation of the detection unit of this invention.

[0038] Figure 3 The diagram shown is a structural schematic of the storage unit of this invention.

[0039] Figure 4 The diagram shows a method flowchart for the multi-channel calculator circuit of the present invention to perform multiple computational tasks.

[0040] Component designation explanation

[0041] 10-channel calculator circuit

[0042] 100 processing units

[0043] 200 parameter units

[0044] 300 detection units

[0045] 310 Calculation Channel Module

[0046] 320 Calculation Parameter Module

[0047] 330 Trigger Generation Module

[0048] 340 Logo Generation Module

[0049] 400 computing units

[0050] 500 storage units

[0051] 510 Information Conversion Module

[0052] 520 storage channel Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0055] like Figure 1 As shown, this embodiment provides a multi-channel calculator circuit 10, including: a processing unit 100, a parameter unit 200, a detection unit 300, a calculation unit 400, and a storage unit 500.

[0056] The processing unit 100 is used to configure calculation parameter information and calculation channel information, read and store calculation parameter information and calculation channel information from the parameter unit 200 according to the calculation flag signal, and read calculation result information from the corresponding storage channel of the storage unit 400 according to the corresponding channel completion signal; wherein, the calculation flag signal includes the trigger busy flag signal TrigBusy and the calculation busy flag signal CalcBusy. As an example, the processing unit 100 is implemented using a processor.

[0057] In this embodiment, the processing unit 100 can configure computational parameter information and computational channel information for single-level or multi-level computational tasks. When configuring computational parameter information and computational channel information for multi-level computational tasks:

[0058] Since the arrival time of the next level of computing task cannot be determined, the processing unit 100 needs to determine the current stage of the previous level computing task based on the TrigBusy signal and the CalcBusy signal, such as the computing stage, the configuration stage or the configuration stage but not yet started, the computing stage, or the configuration stage.

[0059] If it is determined that the previous level computing task is currently in the computing stage, the processing unit 100 waits for the previous level computing task to finish before configuring the computing parameter information and computing channel information required for the next level computing task.

[0060] If it is determined that the previous level computing task is currently in the configuration stage or has been configured but has not yet started computing, the processing unit 100 reads and stores the computing parameter information and computing channel information required by the previous level computing task from the parameter unit 200 for on-site protection. Then, it configures the computing parameter information and computing channel information required by the next level computing task. After the next level computing task is completed, it reconfigures based on the stored computing parameter information and computing channel information required by the previous level computing task to restore the on-site environment.

[0061] If it is determined that the previous level computing task is currently in the computing completion stage or has not yet started the configuration stage, the processing unit 100 directly configures the computing parameter information and computing channel information required by the next level computing task.

[0062] It is important to note that, regardless of whether it is a single-level or multi-level calculation task, the number of calculation parameters in the calculation parameter information involved in each level of calculation task should be set according to the actual needs. For example, if the calculation task is a square root operation, the number of calculation parameters is 1; if the calculation task is a multiplication operation, division operation, etc., the number of calculation parameters is greater than or equal to 2.

[0063] Taking the example that the number of storage channels in the multi-channel calculator circuit 10 of this embodiment is N (N≥2), each storage channel is sequentially labeled as 1 to N. Regardless of whether it is a single-level computing task or a multi-level computing task, the computing channel information involved in each level of computing task can be any one of 1 to N. However, for multi-level computing tasks, the computing channel information involved in each level of computing task cannot be repeated, and is generally set in an increasing or decreasing order.

[0064] Furthermore, the processing unit 100 generates corresponding parameter configuration signals when configuring each calculation parameter in the calculation parameter information (e.g., generating the first parameter configuration signal Data1Wr when configuring the first calculation parameter CalcData1, generating the second parameter configuration signal Data2Wr when configuring the second calculation parameter CalcData2, etc.), generates corresponding parameter read signals when reading each calculation parameter in the calculation parameter information (e.g., generating the first parameter read signal Data1Rd when reading the first calculation parameter CalcData1, generating the second parameter read signal Data2Rd when reading the second calculation parameter CalcData2, etc.), and generates corresponding channel read signals when reading calculation result information from the corresponding storage channel (e.g., generating the first channel read signal Result1Rd when reading calculation result information Result1 in the first storage channel, generating the second channel read signal Result2Rd when reading calculation result information Result2 in the second storage channel, etc.).

[0065] The parameter unit 200 is connected to the processing unit 100 and is used to generate calculation parameter information, calculation channel information and detection trigger signal DeteTrig according to the configuration information; wherein, the detection trigger signal DeteTrig is generated after the calculation parameter information and calculation channel information.

[0066] The detection unit 300 is connected to the parameter unit 200 and is used to protect the calculation parameter information and calculation channel information according to the detection trigger signal DeteTrig and generate the calculation trigger signal CalcTrig, and generate the trigger busy flag signal TrigBusy and the calculation busy flag signal CalcBusy according to the status of the calculation unit 400.

[0067] Specifically, such as Figure 2As shown, the detection unit 300 includes: a calculation channel module 310, an M calculation parameter module 320, a trigger generation module 330, and a flag generation module 340, where M is an integer greater than or equal to 1.

[0068] The calculation channel module 310 is connected to the parameter unit 200 and is used to protect the calculation channel information according to the detection trigger signal DeteTrig, so as to prevent accidental changes to the calculation channel information in the calculation and thus prevent errors in the storage of calculation results.

[0069] As an example, the calculation channel module 310 includes: a first multiplexer and a first register; wherein, the selection terminal (C terminal) of the first multiplexer is connected to the detection trigger signal DeteTrig, the first input terminal (S1 terminal) is connected to the output terminal (Q terminal) of the first register, the second input terminal (S2 terminal) is connected to the calculation channel information CalcNum, and the output terminal (D terminal) is connected to the input terminal (IN terminal) of the first register; the output terminal (Q terminal) of the first register outputs the calculation channel information CalcNum.

[0070] It should be noted that the enable terminals of the first multiplexer and the first register are not shown in the figure, but the first multiplexer and the first register should also include their respective enable terminals, which are enabled by connecting the corresponding enable signals. This is a well-known technology in the field, so it will not be described in detail.

[0071] In this embodiment, the detection trigger signal DeteTrig is active high; when the detection trigger signal DeteTrig is low, the C terminal of the first multiplexer is connected to "0", and at this time, the S1 terminal of the first multiplexer is connected to the D terminal; when the detection trigger signal DeteTrig is high, the C terminal of the first multiplexer is connected to "1", and at this time, the S2 terminal of the first multiplexer is connected to the D terminal; thus, when the detection trigger signal DeteTrig is active, the calculated channel information CalcNum is stored in the first register for protection.

[0072] M calculation parameter modules 320 are connected to the parameter unit 200 and are used to protect each calculation parameter CalcData1 to CalcDatam in the calculation parameter information according to the detection trigger signal DeteTrig, to prevent accidental changes to the calculation parameters in the calculation, thereby preventing calculation errors. It should be noted that the number M of calculation parameter modules 320 is determined by the number of calculation parameters in the calculation parameter information, and the two are equal; however, the number of calculation parameters in the calculation parameter information should be set according to actual needs, and this embodiment does not impose any restrictions on this.

[0073] As an example, the calculation parameter module 320 includes: a second multiplexer and a second register; the selection terminal (C terminal) of the second multiplexer is connected to the detection trigger signal DeteTrig, the first input terminal (S1 terminal) is connected to the output terminal (Q terminal) of the second register, the second input terminal (S2 terminal) is connected to the corresponding calculation parameters, and the output terminal (D terminal) is connected to the input terminal (IN terminal) of the second register; the output terminal (Q terminal) of the second register outputs the corresponding calculation parameters.

[0074] It should be noted that the enable terminals of the second multiplexer and the second register are not shown in the figure, but the second multiplexer and the second register should also include their respective enable terminals, which are enabled by connecting the corresponding enable signals. This is a well-known technology in the field, so it will not be described in detail.

[0075] In this embodiment, the detection trigger signal DeteTrig is active high; when the detection trigger signal DeteTrig is low, the C terminal of the second multiplexer is connected to "0", and at this time, the S1 terminal of the second multiplexer is connected to the D terminal; when the detection trigger signal DeteTrig is high, the C terminal of the second multiplexer is connected to "1", and at this time, the S2 terminal of the second multiplexer is connected to the D terminal; thus, when the detection trigger signal DeteTrig is active, each calculation parameter CalcData1 to CalcDatam in the calculation parameter information is stored in the second register of the corresponding calculation parameter module 320 for protection.

[0076] The trigger generation module 330 is connected to the parameter unit 200 and is used to generate a calculation trigger signal CalcTrig based on the detection trigger signal DeteTrig.

[0077] As an example, the trigger generation module 330 includes a D flip-flop; wherein the data terminal (D terminal) of the D flip-flop is connected to the detection trigger signal DeteTrig, and the output terminal (Q terminal) generates the calculation trigger signal CalcTrig. It should be noted that the clock terminal of the D flip-flop is not shown in the figure, but the D flip-flop should also include a clock terminal to provide the operating clock; this is well-known in the art and therefore will not be described in detail.

[0078] In this embodiment, the detection trigger signal DeteTrig is active high. When the detection trigger signal DeteTrig is low, the D flip-flop will output a low level when the next clock arrives, which is equivalent to not generating the calculation trigger signal CalcTrig. When the detection trigger signal DeteTrig is high, the D flip-flop will output a high level when the next clock arrives, which is equivalent to generating the calculation trigger signal CalcTrig.

[0079] The flag generation module 340 is connected to the processing unit 100, the trigger generation module 330, and the calculation unit 400, and is used to generate a trigger busy flag signal TrigBusy and a calculation busy flag signal CalcBusy. The trigger busy flag signal TrigBusy is triggered by any parameter configuration signal, and is cleared by the calculation trigger signal CalcTrig or any parameter read signal. The calculation busy flag signal CalcBusy is triggered by the calculation trigger signal CalcTrig, and is cleared by the calculation completion signal CalcEnd.

[0080] As an example, the flag generation module 340 includes: a first OR gate, a second OR gate, a first RS flip-flop, and a second RS flip-flop; the input of the first OR gate is connected to the parameter configuration signals Data1Wr~DatamWr, and the output is connected to the set terminal (S terminal) of the first RS flip-flop; the reset terminal (R terminal) of the first RS flip-flop is connected to the output of the second OR gate, and the output terminal (Q terminal) generates the trigger busy flag signal TrigBusy; the input of the second OR gate is connected to the calculation trigger signal CalcTrig and the parameter read signals Data1Rd~DatamRd; the set terminal (S terminal) of the second RS flip-flop is connected to the calculation trigger signal CalcTrig, the reset terminal (R terminal) is connected to the calculation completion signal CalcEnd, and the output terminal (Q terminal) generates the calculation busy flag signal CalcBusy.

[0081] It should be noted that the clock terminals of the first RS flip-flop and the second RS flip-flop are not shown in the figure, but the first RS flip-flop and the second RS flip-flop should also include their respective clock terminals to provide the working clock. This is well known in the art and therefore will not be described in detail.

[0082] The number of input terminals of the first OR gate and the second OR gate is determined by the number of calculation parameters in the calculation parameter information;

[0083] When the number of calculation parameters M = 1 in the calculation parameter information, the number of input terminals of the first OR gate is (M+1), that is, 2. One input terminal is connected to the parameter configuration signal, and the other input terminal is connected to a low level. The number of input terminals of the second OR gate is (M+1), that is, 2. One input terminal is connected to the calculation trigger signal, and the other input terminal is connected to the parameter reading signal.

[0084] When the number of calculation parameters M≥2 in the calculation parameter information, the number of input terminals of the first OR gate is M, where the M input terminals are connected to the M parameter configuration signals Data1Wr~DatamWr; the number of input terminals of the second OR gate is (M+1), where one input terminal is connected to the calculation trigger signal CalcTrig, and the remaining M input terminals are connected to the M parameter read signals Data1Rd~DatamRd.

[0085] In this embodiment, all parameter configuration signals Data1Wr~DatamWr and all parameter read signals Data1Rd~DatamRd are active high. When any one of the parameter configuration signals Data1Wr~DatamWr is "1", the first OR gate outputs "1", setting the output of the first RS flip-flop to 1, that is, the busy flag signal TrigBusy is "1", and the busy flag signal is triggered. When the calculation trigger signal CalcTrig is "1" or any one of the parameter read signals Data1Rd~DatamRd is "1", the second OR gate outputs "1", clearing the output of the first RS flip-flop to zero, that is, the busy flag signal TrigBusy is "0", and the busy flag signal is cleared.

[0086] When the TrigBusy flag signal is "1", it indicates that the processing unit 100 has started configuring the calculation parameter information, but the calculation unit 400 has not yet started the calculation. If a next-level calculation task arrives at this time, the processing unit 100 needs to read and store the calculation parameter information and calculation channel information required by the previous-level calculation task (preserve the scene) before configuring the calculation parameter information and calculation channel information required by the next-level calculation task. After the next-level calculation task is completed, the stored calculation parameter information and calculation channel information required by the previous-level calculation task are reconfigured (restore the scene) to avoid calculation errors caused by the configuration being overwritten in the previous-level calculation task.

[0087] When the calculation trigger signal CalcTrig is "1", the output of the second RS flip-flop is set to 1, that is, the calculation busy flag signal CalcBusy is "1" and the calculation busy flag signal CalcBusy is triggered; when the calculation completion signal CalcEnd is "1", the output of the second RS flip-flop is cleared to zero, that is, the calculation busy flag signal CalcBusy is "0" and the calculation busy flag signal CalcBusy is cleared to zero.

[0088] The busy calculation flag signal CalcBusy being "1" indicates that the calculation unit 400 is performing calculations. If a next-level calculation task arrives at this time, the processing unit 100 needs to wait for the previous-level calculation task to complete before configuring the calculation parameter information and calculation channel information required by the next-level calculation task. Otherwise, the previous-level calculation task will result in a calculation error due to the configuration being overwritten.

[0089] The calculation unit 400 is connected to the detection unit 300 and is used to calculate the calculation parameter information according to the calculation trigger signal CalcTrig and generate the calculation result information and the calculation completion signal CalcEnd.

[0090] The calculation unit 400 can be a functional unit that performs multiplication, division, addition, subtraction, square root, or compound operations on each calculation parameter in the calculation parameter information. The specific operation performed has no substantial impact on this embodiment.

[0091] In this embodiment, the calculation unit 400 is triggered by the calculation trigger signal CalcTrig to perform specific operations on each calculation parameter in the calculation parameter information to generate calculation result information, and generates a calculation completion signal CalcEnd after the calculation is completed.

[0092] The storage unit 500 is connected to the detection unit 300 and the calculation unit 400, and is used to store the calculation result information into the corresponding storage channel and generate the corresponding channel completion signal according to the calculation channel information CalcNum and the calculation completion signal CalcEnd.

[0093] Specifically, such as Figure 3 As shown, the storage unit 500 includes: an information conversion module 510 and N storage channels 520, where N is an integer greater than 1.

[0094] The information conversion module 510 is connected to the detection unit 300 and is used to convert the calculation channel information CalcNum into a channel selection signal. The channel selection signal is a set of N-bit binary codes, such as Sele1 to Selen. During the conversion, the corresponding bits of the binary code are set to 1 according to the calculation channel information, and the remaining bits are set to 0.

[0095] N storage channels 520 are connected to the calculation unit 400 and the information conversion module 510, and are used to store the calculation result information into the corresponding storage channel and generate the corresponding channel completion signal according to the calculation completion signal CalcEnd and the channel selection signal.

[0096] As an example, storage channel 520 includes: an AND gate, a third multiplexer, a third register, and a third RS flip-flop; the first input of the AND gate is connected to the calculation completion signal CalcEnd, the second input is connected to the corresponding bit of the channel selection signal, and the output is connected to the selection terminal (C terminal) of the third multiplexer and the set terminal (S terminal) of the third RS flip-flop; the first input terminal (S1 terminal) of the third multiplexer is connected to the output terminal (Q terminal) of the third register, the second input terminal (S2 terminal) is connected to the calculation result information, the output terminal (D terminal) is connected to the input terminal (IN terminal) of the third register, and the output terminal (Q terminal) of the third register outputs the calculation result information; the reset terminal (R terminal) of the third RS flip-flop is connected to the corresponding channel read signal, and the output terminal (Q terminal) generates the corresponding channel completion signal.

[0097] It should be noted that the enable terminals of the third multiplexer and the third memory, as well as the clock terminal of the third RS flip-flop, are not shown in the figure. However, the third multiplexer and the third memory should also include their respective enable terminals, which are enabled by connecting the corresponding enable signals. The third RS flip-flop should also include a clock terminal to provide the working clock. This is well-known technology in the field and therefore will not be described in detail.

[0098] In this embodiment, when the storage unit 500 receives the calculation completion signal CalcEnd (which is active high) from the calculation unit 400, if the calculation channel information CalcNum = 1, then the channel selection signals Sele1 to Selen are 1000... At this time, the AND gate in the first storage channel 520 outputs "1", and the AND gates in the other storage channels 520 output "0". Thus, the C terminal of the third multiplexer in the first storage channel 520 is connected to "1", the S2 terminal is connected to the D terminal, the calculation result information is stored in the third register in the first storage channel 520 and then output. At the same time, the output of the third RS flip-flop in the first storage channel 520 is set to 1, that is, the first channel completion signal OK1 is generated. At this time, the processing unit 100 reads the calculation result information Result1 from the third register of the first storage channel according to the first channel completion signal OK1 and generates the first channel read signal Result1Rd. The first channel read signal Result1Rd can clear the output of the third RS flip-flop in the first storage channel 520. The working principle of other storage channels is the same, and will not be described in detail here. Establishing a channel mode to store the computation results of each level of computation tasks separately, such as storing the computation results of each level of computation tasks in different storage channels, can avoid the problems of the computation results of multiple computation tasks being overwritten and stored in a disorderly manner.

[0099] Correspondingly, such as Figure 4As shown, this embodiment also provides a method for the multi-channel calculator circuit 10 described above to perform multiple computational tasks, the method comprising the following steps:

[0100] Step 1) Execute the previous level calculation task. The processing unit 100 configures the previous level calculation parameter information and the previous level calculation channel information. The parameter unit 200 generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit 300 to protect the previous level calculation parameter information and the previous level calculation channel information. The calculation unit 400 calculates the previous level calculation parameter information.

[0101] When the next level of calculation task arrives, the processing unit 100 determines whether the TrigBusy signal is valid. If valid, it indicates that the circuit is in the configuration start stage or has been configured but has not yet started calculation. The processing unit 100 then reads and stores the previous level calculation parameter information and the previous level calculation channel information from the parameter unit 200 for field protection, configures the next level calculation parameter information and the next level calculation channel information, generates the next level calculation parameter information and the next level calculation channel information according to the configuration information, and triggers the detection unit 300 to protect the next level calculation parameter information and the next level calculation channel information. The calculation unit 400 calculates the next level calculation parameter information. After that, it waits for the next level of calculation task to be completed. The processing unit 100 reads the calculation result information of the corresponding stored channel and then executes step 2). If invalid, it indicates that the circuit is in the configuration start stage, the calculation stage, or the calculation completion stage. Then, it executes step 3).

[0102] Step 2) Processing unit 100 reconfigures the stored previous-level calculation parameter information and previous-level calculation channel information to perform on-site recovery. Parameter unit 200 generates previous-level calculation parameter information and previous-level calculation channel information according to the configuration information, and triggers detection unit 300 to protect the previous-level calculation parameter information and previous-level calculation channel information. Calculation unit 400 calculates the previous-level calculation parameter information. After that, it waits for the previous-level calculation task to complete, and then processing unit 100 reads the calculation result information of the corresponding storage channel.

[0103] Step 3) The processing unit 100 determines whether the calculation busy flag signal CalcBusy is valid; if valid, it means that the circuit is in the calculation stage, and the processing unit 100 waits for the previous level calculation task to complete and reads the calculation result information of the corresponding storage channel before executing step 4); if invalid, it means that the circuit is in the stage of not yet starting configuration or the stage of calculation completion, and then directly executes step 4).

[0104] Step 4) Processing unit 100 configures the next-level calculation parameter information and the next-level calculation channel information. Parameter unit 200 generates the next-level calculation parameter information and the next-level calculation channel information according to the configuration information, and triggers detection unit 300 to protect the next-level calculation parameter information and the next-level calculation channel information. Calculation unit 400 calculates the next-level calculation parameter information. After that, it waits for the next-level calculation task to complete, and then processing unit 100 reads the calculation result information of the corresponding storage channel.

[0105] In the above steps, after generating the calculation parameter information and calculation channel information of any level, the parameter unit 200 also generates a detection trigger signal DeteTrig. The detection unit 300 protects the calculation parameter information and calculation channel information of the current level according to the detection trigger signal DeteTrig and generates a calculation trigger signal CalcTrig. The calculation unit 400 calculates the calculation parameter information of the current level according to the calculation trigger signal CalcTrig and generates calculation result information and calculation completion signal. The storage unit 500 stores the calculation result information into the corresponding storage channel according to the calculation channel information and calculation completion signal and generates the corresponding channel completion signal. The processing unit 100 then reads the calculation result information from the corresponding storage channel according to the corresponding channel completion signal.

[0106] The following examples illustrate the specific process of the multi-channel calculator circuit 10 performing multiple calculation tasks. Here, we only take a three-level division calculation task (involving three storage channels and two calculation parameters for each level of division calculation task) as an example, and do not limit the number of levels, storage channels, and calculation parameters of the multiple calculation tasks.

[0107] First example:

[0108] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs the division operation on CalcData11 and CalcData21.

[0109] When the second-level division calculation task arrives, the processing unit 100 determines that the Trigger Busy flag signal TrigBusy is "0". If the processing unit 100 determines that the Calculation Busy flag signal CalcBusy is "1", the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel before executing the second step. Otherwise, the second step is executed directly.

[0110] Step 2: The processing unit 100 configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2). The parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2. The calculation unit 400 performs a division operation on CalcData12 and CalcData22.

[0111] When the third-level division calculation task arrives, the processing unit 100 determines that the Trigger Busy flag signal TrigBusy is "0". If the Trigger Busy flag signal CalcBusy is "1", the processing unit 100 will continue to determine whether the Calculation Busy flag signal CalcBusy is "1". If it is "1", the processing unit 100 will wait for the second channel completion signal OK2 to be "1" and read the calculation result information Result2 of the second storage channel before executing the third step. Otherwise, the third step will be executed directly.

[0112] Step 3: Processing unit 100 configures third-level calculation parameter information (such as CalcData13 and CalcData23) and third-level calculation channel information (such as CalcNum=3). Parameter unit 200 generates CalcData13, CalcData23, and CalcNum=3 according to the configuration information and triggers detection unit 300 to protect CalcData13, CalcData23, and CalcNum=3. Calculation unit 400 performs division operation on CalcData13 and CalcData23. After that, processing unit 100 waits for the third channel completion signal OK3 to be "1" and reads the calculation result information Result3 of the third storage channel.

[0113] Second example:

[0114] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs the division operation on CalcData11 and CalcData21.

[0115] When the second-level division calculation task arrives, the processing unit 100 determines that the Trigger Busy flag signal TrigBusy is "0". If the processing unit 100 determines that the Calculation Busy flag signal CalcBusy is "1", the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel before executing the second step. Otherwise, the second step is executed directly.

[0116] Step 2: The processing unit 100 configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2). The parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2. The calculation unit 400 performs a division operation on CalcData12 and CalcData22.

[0117] When the third-level division calculation task arrives, processing unit 100 determines that the TrigBusy flag signal is "1". Then, processing unit 100 reads and stores CalcData12, CalcData22, and CalcNum=2 from parameter unit 200 for on-site protection. It configures the third-level calculation parameter information (such as CalcData13 and CalcData23) and the third-level calculation channel information (such as CalcNum=3). Parameter unit 200 generates CalcData13, CalcData23, and CalcNum=3 according to the configuration information and triggers detection unit 300 to protect CalcData13, CalcData23, and CalcNum=3. Calculation unit 400 performs division on CalcData13 and CalcData23. Afterwards, processing unit 100 waits for the third channel completion signal OK3 to be "1". 1” and read the calculation result information Result3 from the third storage channel; finally, the processing unit 100 reconfigures the relevant information of the second-level division calculation task (such as the second-level calculation parameter information and the second-level calculation channel information) according to the stored CalcData12, CalcData22, CalcNum=2 to perform on-site restoration. The parameter unit 200 generates CalcData12, CalcData22, CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, CalcNum=2. The calculation unit 400 performs division operation on CalcData12 and CalcData22, that is, executes the second-level division calculation task. After that, the processing unit 100 waits for the second channel completion signal OK2 to be “1” and reads the calculation result information Result2 from the second storage channel.

[0118] Third example:

[0119] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs the division operation on CalcData11 and CalcData21.

[0120] When the second-level division calculation task arrives, the processing unit 100 determines that the TrigBusy flag signal is "1". Then, the processing unit 100 reads and stores CalcData11, CalcData21, and CalcNum=1 from the parameter unit 200 for on-site protection, configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2), the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, and the calculation unit 400 performs division operation on CalcData12 and CalcData22.

[0121] When the third-level division calculation task arrives, the processing unit 100 determines that the Trigger Busy flag signal TrigBusy is "0". If the Trigger Busy flag signal CalcBusy is "1", the processing unit 100 will continue to determine whether the Calculation Busy flag signal CalcBusy is "1". If it is "1", the processing unit 100 will wait for the second channel completion signal OK2 to be "1" and read the calculation result information Result2 of the second storage channel before executing the second step. Otherwise, the second step will be executed directly.

[0122] Step 2: Processing unit 100 configures third-level calculation parameter information (such as CalcData13 and CalcData23) and third-level calculation channel information (such as CalcNum=3). Parameter unit 200 generates CalcData13, CalcData23, and CalcNum=3 according to the configuration information and triggers detection unit 300 to protect CalcData13, CalcData23, and CalcNum=3. Calculation unit 400 performs a division operation on CalcData13 and CalcData23. Afterwards, processing unit 100 waits for the third channel completion signal OK3 to be "1" and reads the calculation result information Result3 from the third storage channel. Finally, processing unit 100 calculates the result based on the stored Calc... Data11, CalcData21, and CalcNum=1 are reconfigured with relevant information for the first-level division calculation task (such as first-level calculation parameter information and first-level calculation channel information) for on-site restoration. The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs division operation on CalcData11 and CalcData21, that is, executes the first-level division calculation task. After that, the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel.

[0123] Fourth example:

[0124] Step 1: Execute the first-level division calculation task. The processing unit 100 configures the first-level calculation parameter information (such as CalcData11 and CalcData21) and the first-level calculation channel information (such as CalcNum=1). The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs the division operation on CalcData11 and CalcData21.

[0125] When the second-level division calculation task arrives, the processing unit 100 determines that the TrigBusy flag signal is "1". Then, the processing unit 100 reads and stores CalcData11, CalcData21, and CalcNum=1 from the parameter unit 200 for on-site protection, configures the second-level calculation parameter information (such as CalcData12 and CalcData22) and the second-level calculation channel information (such as CalcNum=2), the parameter unit 200 generates CalcData12, CalcData22, and CalcNum=2 according to the configuration information and triggers the detection unit 300 to protect CalcData12, CalcData22, and CalcNum=2, and the calculation unit 400 performs division operation on CalcData12 and CalcData22.

[0126] When the third-level division calculation task arrives, the processing unit 100 determines that the TrigBusy flag signal is "1". Then, the processing unit 100 reads and stores CalcData12, CalcData22, and CalcNum=2 from the parameter unit 200 for field protection, configures the third-level calculation parameter information (such as CalcData13 and CalcData23) and the third-level calculation channel information (such as CalcNum=3), and the parameter unit 200 generates CalcData13, CalcData23, and CalcNum=3 according to the configuration information and triggers the detection unit 300 to check CalcData13, CalcData23, and CalcNum=3. lcData23 and CalcNum=3 are protected. Calculation unit 400 performs a division operation on CalcData13 and CalcData23. Afterwards, processing unit 100 waits for the third channel completion signal OK3 to be "1" and reads the calculation result information Result3 from the third storage channel. Then, processing unit 100 reconfigures the relevant information of the second-level division calculation task (such as second-level calculation parameter information and second-level calculation channel information) according to the stored CalcData12, CalcData22, and CalcNum=2 to perform on-site restoration. Parameter unit 200 generates CalcData based on the configuration information. 12. CalcData12, CalcData22, CalcNum = 2 and trigger the detection unit 300 to protect CalcData12, CalcData22, CalcNum = 2. The calculation unit 400 performs a division operation on CalcData12 and CalcData22, that is, executes the second-level division calculation task. After that, the processing unit 100 waits for the second channel completion signal OK2 to be "1" and reads the calculation result information Result2 of the second storage channel. Finally, the processing unit 100 reconfigures the first-level division calculation task according to the stored CalcData11, CalcData21, CalcNum = 1. The relevant information of the task (such as the first-level calculation parameter information and the first-level calculation channel information) is used for on-site recovery. The parameter unit 200 generates CalcData11, CalcData21, and CalcNum=1 according to the configuration information and triggers the detection unit 300 to protect CalcData11, CalcData21, and CalcNum=1. The calculation unit 400 performs a division operation on CalcData11 and CalcData21, that is, executes the first-level division calculation task. After that, the processing unit 100 waits for the first channel completion signal OK1 to be "1" and reads the calculation result information Result1 of the first storage channel.

[0127] Accordingly, this embodiment also provides an electronic chip, including: the multi-channel calculator circuit 10 described above; of course, the electronic chip may also include other functional circuits, which has no substantial impact on this embodiment. It should be noted that the electronic chip can be any kind of chip with computing function, and this embodiment does not limit it.

[0128] In summary, the multi-channel calculator circuit and its method for performing multiple computational tasks, along with the electronic chip of this invention, through the design of processing units, parameter units, detection units, calculation units, and storage units, can perform on-site protection and on-site recovery of computational parameter information and computational channel information, enabling the simultaneous execution of multiple computational tasks using only one calculator. This invention features a small circuit footprint, high computational speed, low CPU resource consumption, and simple and convenient operation, making it suitable for single-level or multi-level computational tasks. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A multi-channel calculator circuit, characterized in that, The multi-channel calculator circuit includes: a processing unit, a parameter unit, a detection unit, a calculation unit, and a storage unit; The processing unit is used to configure calculation parameter information and calculation channel information, read and store the calculation parameter information and calculation channel information from the parameter unit according to the calculation flag signal, and read the calculation result information from the corresponding storage channel of the storage unit according to the corresponding channel completion signal. The calculation flag signal includes a trigger busy flag signal and a calculation busy flag signal. The parameter unit is connected to the processing unit and is used to generate the calculation parameter information, the calculation channel information and the detection trigger signal according to the configuration information. The detection unit is connected to the parameter unit and is used to protect the calculation parameter information and the calculation channel information according to the detection trigger signal and generate a calculation trigger signal, and to generate the trigger busy flag signal and the calculation busy flag signal according to the state of the calculation unit. The calculation unit is connected to the detection unit and is used to calculate the calculation parameter information according to the calculation trigger signal and generate the calculation result information and the calculation completion signal; The storage unit is connected to the detection unit and the calculation unit, and is used to store the calculation result information into the corresponding storage channel and generate the corresponding channel completion signal according to the calculation channel information and the calculation completion signal.

2. The multi-channel calculator circuit according to claim 1, characterized in that, The processing unit generates a corresponding parameter configuration signal when configuring each calculation parameter in the calculation parameter information, and generates a corresponding parameter reading signal when reading each calculation parameter in the calculation parameter information; the detection unit includes: a calculation channel module, M calculation parameter modules, a trigger generation module and a flag generation module, where M is an integer greater than or equal to 1; The calculation channel module is connected to the parameter unit and is used to protect the calculation channel information according to the detection trigger signal; M calculation parameter modules are connected to the parameter unit and are used to protect each calculation parameter in the calculation parameter information according to the detection trigger signal; The trigger generation module is connected to the parameter unit and is used to generate the calculation trigger signal based on the detection trigger signal; The flag generation module is connected to the processing unit, the trigger generation module, and the calculation unit, and is used to generate the trigger busy flag signal and the calculation busy flag signal. The trigger busy flag signal is triggered by any of the parameter configuration signals, and the trigger busy flag signal is cleared by the calculation trigger signal or any of the parameter read signals. The calculation busy flag signal is triggered by the calculation trigger signal, and the calculation busy flag signal is cleared by the calculation completion signal.

3. The multi-channel calculator circuit according to claim 2, characterized in that, The computing channel module includes: a first multiplexer and a first register. The selection terminal of the first multiplexer is connected to the detection trigger signal, the first input terminal is connected to the output terminal of the first register, the second input terminal is connected to the computing channel information, the output terminal is connected to the input terminal of the first register, and the output terminal of the first register outputs the computing channel information.

4. The multi-channel calculator circuit according to claim 2 or 3, characterized in that, The calculation parameter module includes: a second multiplexer and a second register. The selection terminal of the second multiplexer is connected to the detection trigger signal, the first input terminal is connected to the output terminal of the second register, the second input terminal is connected to the corresponding calculation parameters, the output terminal is connected to the input terminal of the second register, and the output terminal of the second register outputs the corresponding calculation parameters.

5. The multi-channel calculator circuit according to claim 2, characterized in that, The trigger generation module includes a D trigger.

6. The multi-channel calculator circuit according to claim 2, characterized in that, The flag generation module includes: a first OR gate, a second OR gate, a first RS flip-flop, and a second RS flip-flop; the input of the first OR gate is connected to each of the parameter configuration signals, and the output is connected to the set terminal of the first RS flip-flop; the reset terminal of the first RS flip-flop is connected to the output of the second OR gate, and the output generates the trigger busy flag signal; the input of the second OR gate is connected to the calculation trigger signal and each of the parameter read signals; the set terminal of the second RS flip-flop is connected to the calculation trigger signal, the reset terminal is connected to the calculation completion signal, and the output generates the calculation busy flag signal.

7. The multi-channel calculator circuit according to claim 1, characterized in that, The storage unit includes: an information conversion module and N storage channels, where N is an integer greater than 1; The information conversion module is connected to the detection unit and is used to convert the calculation channel information into a channel selection signal, wherein the channel selection signal is a set of N-bit binary code; The N storage channels are connected to the computing unit and the information conversion module, and are used to store the computing result information into the corresponding storage channel and generate the corresponding channel completion signal according to the computing completion signal and the channel selection signal.

8. The multi-channel calculator circuit according to claim 7, characterized in that, The processing unit generates a corresponding channel read signal when reading the calculation result information in the corresponding storage channel. The storage channel includes an AND gate, a third multiplexer, a third register, and a third RS flip-flop. The first input of the AND gate is connected to the calculation completion signal, the second input is connected to the corresponding bit of the channel selection signal, and the output is connected to the selection terminal of the third multiplexer and the set terminal of the third RS flip-flop. The first input of the third multiplexer is connected to the output of the third register, the second input is connected to the calculation result information, and the output is connected to the input of the third register. The output of the third register outputs the calculation result information. The reset terminal of the third RS flip-flop is connected to the corresponding channel read signal, and the output generates a corresponding channel completion signal.

9. An electronic chip, characterized in that, The electronic chip includes: a multi-channel calculator circuit as described in any one of claims 1-8.

10. A method for a multi-channel calculator circuit to perform multiple computational tasks as described in any one of claims 1-8, characterized in that, The method includes: Step 1) Execute the previous level calculation task. The processing unit configures the previous level calculation parameter information and the previous level calculation channel information. The parameter unit generates the previous level calculation parameter information and the previous level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous level calculation parameter information and the previous level calculation channel information. The calculation unit performs calculations on the previous level calculation parameter information. When the next level of computation arrives, the processing unit determines whether the busy flag signal is valid. If valid, it reads and stores the previous level computation parameter information and the previous level computation channel information from the parameter unit, configures the next level computation parameter information and the next level computation channel information, generates the next level computation parameter information and the next level computation channel information according to the configuration information, and triggers the detection unit to protect the next level computation parameter information and the next level computation channel information. The computation unit calculates the next level computation parameter information, and then waits for the next level computation task to complete. The processing unit reads the calculation result information of the corresponding stored channel and executes step 2). If invalid, it executes step 3. Step 2) The processing unit reconfigures the stored previous-level calculation parameter information and previous-level calculation channel information. The parameter unit generates the previous-level calculation parameter information and previous-level calculation channel information according to the configuration information, and triggers the detection unit to protect the previous-level calculation parameter information and previous-level calculation channel information. The calculation unit calculates the previous-level calculation parameter information, and then waits for the previous-level calculation task to complete. The processing unit reads the calculation result information of the corresponding storage channel. Step 3) The processing unit determines whether the computation busy flag signal is valid; if valid, it waits for the previous level computation task to complete and reads the computation result information of the corresponding storage channel before executing step 4); if invalid, it directly executes step 4. Step 4) The processing unit configures the next-level calculation parameter information and the next-level calculation channel information. The parameter unit generates the next-level calculation parameter information and the next-level calculation channel information according to the configuration information, and triggers the detection unit to protect the next-level calculation parameter information and the next-level calculation channel information. The calculation unit calculates the next-level calculation parameter information, and then waits for the next-level calculation task to complete. The processing unit reads the calculation result information of the corresponding storage channel.

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