Method and device for generating wafer graph and equipment for testing wafer

Abstract

The invention provides a method and device for generating a wafer graph and equipment for testing a wafer, and the method comprises the steps: determining any one of a plurality of test groups divided on the wafer as a preset test group, and determining a first coordinate of a calibration position on the preset test group and a second coordinate of a calibration position of a test structure in the preset test group; determining a first position relationship between a preset test group and the wafer, and arranging the test groups on the wafer according to the sizes of the test groups and the first position relationship; according to the second coordinates and the first coordinates, determining a second position relationship between the test structures and the test groups where the test structures are located, and according to the second position relationship, arranging the test structures in each test group; and arranging the chips in each test group according to the first coordinates, the sizes of the chips and the sizes of the test groups to generate a first wafer graph. The method is not influenced by the number of chips in the test group, and the efficiency of generating the wafer graph is greatly improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method and device for generating a wafer map and equipment for testing a wafer. Background Art

[0002] Wafer Map is an important tool in the wafer testing process. It can display the specific location information of the test structure and chip on the wafer. Based on this location information, bad chips can be tracked and traced back. Since the test structure and chip are of different sizes and their distribution positions on the wafer are also different, when generating a wafer map, engineers need to traverse each test structure and chip position on the wafer one by one, and this process needs to be completed manually. However, when there are a large number of chips, the efficiency of generating a wafer map is extremely low. Summary of the invention

[0003] The present application provides a method and apparatus for generating a wafer map and equipment for testing wafers, so as to solve the existing problem of extremely low efficiency in generating a wafer map including chip location information when the number of chips is large.

[0004] Based on the above problems, in a first aspect, an embodiment of the present disclosure provides a method for generating a wafer map, comprising: Providing a wafer, the wafer comprising a plurality of test groups, wherein each of the test groups comprises a test structure and a chip arranged in the same manner; Determine any one of the multiple test groups divided on the wafer as a preset test group, determine a first coordinate of a calibrated position on the preset test group and a second coordinate of a calibrated position of a test structure in the preset test group; The test groups are positioned within the field of view of the observation device, and the sizes of the test groups are determined according to the positions of the first matching marks located at the same position within each test group; The chip is placed within the field of view of the observation device, and the size of the chip is determined according to the position of the second matching mark located at the same position in each chip; The edge of the wafer is located within the field of view of the observation device, and the third coordinate of the center point of the wafer is determined according to the position coordinates of at least three points on the arc of the edge of the wafer; Determine a first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to a size of the test group and the first positional relationship; determining a second positional relationship between the test structure and the test group to which it belongs according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; According to the first coordinates, the size of the chip and the size of the test group, the chips in each test group are arranged to generate a first wafer map.

[0005] In combination with the first aspect, in a possible implementation manner, placing the test group within the field of view of the observation device and determining the size of the test group according to the position of the first matching mark located at the same position in each test group includes: The test groups are placed within the field of view of the observation device, and any mechanism located at the same position in each test group is determined as a first matching identifier; Determine the lateral size of the test group according to the distance between two preset positions of the first matching marks that are adjacent in the lateral direction; wherein the lateral size of the test group includes: the sum of the length of the horizontal side of the test group and the width of the slicing blocks between the test groups; The longitudinal dimension of the test group is determined according to the distance between two longitudinally adjacent preset positions of the first matching marks; wherein the longitudinal dimension of the test group includes: the sum of the length of the vertical side of the test group and the width of the slicing blocks between the test groups.

[0006] In combination with the first aspect, in a possible implementation manner, placing the chip within the field of view of the observation device and determining the size of the chip according to the position of the second matching mark located at the same position in each chip includes: The chip is placed within the field of view of the observation device, and any mechanism located at the same position in each chip is determined as a second matching mark; Determine the lateral size of the chip according to the distance between two preset positions of the second matching marks that are adjacent in the lateral direction; wherein the lateral size of the chip includes: the sum of the length of the horizontal side of the chip and the width of the dicing blocks between the chips; The longitudinal dimension of the chip is determined according to the distance between two longitudinally adjacent preset positions of the second matching marks; wherein the longitudinal dimension of the chip includes: the sum of the length of the vertical side of the chip and the width of the dicing blocks between the chips.

[0007] In combination with the first aspect, in a possible implementation manner, making the edge of the wafer within the field of view of the observation device, and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the edge of the wafer, includes: Make the edge of the wafer located within the field of view of the observation device, determine the fourth coordinate of the observation object located at the center of the field of view of the observation device; determine the first coordinate deviation values ​​between the fourth coordinate and the positions of multiple arbitrary points on the arc of the edge of the wafer; determine the fifth coordinate of the position of each arbitrary point according to the fourth coordinate and the multiple first coordinate deviation values; or, Make the multiple arcs of the edge of the wafer be located in the field of view of the observation device in sequence, and determine the fourth coordinate of the observation object located at the center of the field of view of the observation device in sequence; determine the first coordinate deviation value between the fourth coordinate and the position of any point on the multiple arcs in the field of view of the observation device respectively; determine the fifth coordinate of the position of each arbitrary point according to the multiple fourth coordinates and the corresponding first coordinate deviation values; The center point of the wafer is fitted based on the fifth coordinates corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

[0008] In combination with the first aspect, in a possible implementation manner, arranging the chips in each test group according to the first coordinates, the size of the chip, and the size of the test group to generate a first wafer map includes: Preliminarily arranging the chips in the test group according to the sixth coordinate of the preset position of the second matching mark of any chip, the size of the chip and the size of the test group; Determine an intersection area formed by the diced blocks between the test groups and their adjacent test structures as a first area; Based on the first coordinate, the horizontal width and the vertical width of the first area, the sixth coordinate and the size of the chip, the chip position correction method is determined, and the chip positions preliminarily arranged in each test group are corrected to generate a first wafer map.

[0009] In combination with the first aspect, in a possible implementation manner, the method further includes: The first area is located within the field of view of an observation device, and a horizontal width and a vertical width of the first area are determined, including: The first area is located within the field of view of the observation device, and four straight lines are input so that the four straight lines coincide with four sides of the first area respectively; The horizontal width and the vertical width of the first area are determined according to the distances between the four straight lines which are parallel to each other.

[0010] In combination with the first aspect, in a possible implementation, the method further includes: placing the pads of the chip within the field of view of the observation device, determining the position coordinates of the pads in the chip, and generating a second wafer map including the position coordinates of the pads in the chip based on the first wafer map, including: The pad of the chip is located within the field of view of the observation device, and the seventh coordinate of the observation object located at the center of the field of view of the observation device is determined; Determine a second coordinate deviation value between the seventh coordinate and the pad position of the chip; Determine an eighth coordinate of the pad of the chip by subtracting the seventh coordinate from the second coordinate deviation value; According to the eighth coordinate and the arrangement of the chips in the first wafer map, a third positional relationship between the chip pads and the chip is determined, and according to the third positional relationship, a second wafer map including the position coordinates of the chip pads is generated.

[0011] In combination with the first aspect, in a possible implementation, after determining the first matching mark, the method further includes: determining a first angle of rotation of the wafer according to an angle between a straight line connecting at least two preset positions of the first matching marks in the same row or column and a horizontal line; rotating the wafer according to the first angle so that the test group is adjusted to a horizontal state within the field of view of the observation device; or, After determining the second matching mark, it also includes: determining the second angle of rotation of the wafer based on the angle between the straight line connecting at least two preset positions of the second matching marks in the same row or column and the horizontal line; rotating the wafer according to the second angle so that the chip is adjusted to a horizontal state within the field of view of the observation device.

[0012] In a second aspect, a device for generating a wafer map is provided, comprising: A calibration module is used to provide a wafer, which includes multiple test groups on the wafer, wherein each of the test groups includes a test structure and a chip arranged in the same manner; determine any one of the multiple test groups divided on the wafer as a preset test group, determine the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure in the preset test group; make the test group within the field of view of an observation device, and determine the size of the test group according to the position of a first matching mark located at the same position in each test group; make the chip within the field of view of the observation device, and determine the size of the chip according to the position of a second matching mark located at the same position in each chip; make the edge of the wafer within the field of view of the observation device, and determine the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the edge of the wafer; A wafer map generation module is used to determine a first position relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to the size of the test group and the first position relationship; determine a second position relationship between a test structure and the test group to which it belongs according to the second coordinate and the first coordinate, and arrange the test structure in each test group according to the second position relationship; arrange the chips in each test group according to the first coordinate, the size of the chip and the size of the test group to generate a first wafer map.

[0013] In a third aspect, a device for testing wafers is provided, comprising the apparatus for generating a wafer image as described in the second aspect.

[0014] The beneficial effects of the embodiments of the present disclosure include: A method and apparatus for generating a wafer map and a device for testing a wafer provided by an embodiment of the present disclosure include: providing a wafer, wherein the wafer includes multiple test groups, wherein each test group includes test structures and chips arranged in the same manner; determining any one of the multiple test groups divided on the wafer as a preset test group, determining a first coordinate of a calibrated position on the preset test group and a second coordinate of a calibrated position of the test structure in the preset test group; placing the test group within a field of view of an observation device, and determining a size of the test group according to the position of a first matching mark located at the same position in each test group; placing the chip within the field of view of the observation device, and determining a size of the test group according to the position of a second matching mark located at the same position in each chip The position of the wafer is identified, and the size of the chip is determined; the edge of the wafer is located within the field of view of the observation device, and the third coordinate of the center point of the wafer is determined according to the position coordinates of at least three points on the arc of the wafer edge; according to the third coordinate and the first coordinate, the first position relationship between the preset test group and the wafer is determined, and each test group is arranged on the wafer according to the size of the test group and the first position relationship; according to the second coordinate and the first coordinate, the second position relationship between the test structure and the test group is determined, and the test structure in each test group is arranged according to the second position relationship; according to the first coordinate, the size of the chip and the size of the test group, the chips in each test group are arranged to generate a first wafer map. The method for generating a wafer map provided by the embodiment of the present disclosure generates a wafer map including test structure and chip position information by arranging the test group on the wafer, further arranging the test structure and the chip in the test group, and compared with the prior art, it is not affected by the number of chips in the test group, and the efficiency of generating a wafer map is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A flowchart of a method for generating a wafer map provided by an embodiment of the present disclosure; Figure 2 One of the schematic diagrams of a wafer map provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of a wafer testing device provided in an embodiment of the present disclosure; Figure 4 A second schematic diagram of a wafer diagram provided for an embodiment of the present disclosure; Figure 5 A third schematic diagram of a wafer diagram provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of observing a wafer edge arc provided by an embodiment of the present disclosure; Figure 7 A schematic diagram of observing a pad in a chip provided by an embodiment of the present disclosure; Figure 8 A schematic diagram of the structure of an apparatus for generating a wafer map provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The embodiments of the present disclosure provide a method and apparatus for generating a wafer map and a device for testing a wafer. The preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure and are not used to limit the present disclosure. In addition, the embodiments in the present application and the features in the embodiments can be combined with each other if there is no conflict.

[0017] The present disclosure provides a method for generating a wafer map. Figure 1 As shown, the following steps are included: S101, providing a wafer, wherein the wafer includes multiple test groups, wherein each test group includes test structures and chips arranged in the same manner; S102, determining any one of the multiple test groups divided on the wafer as a preset test group, determining a first coordinate of a calibration position on the preset test group and a second coordinate of a calibration position of a test structure in the preset test group; S103, placing the test group within the field of view of the observation device, and determining the size of the test group according to the position of the first matching mark located at the same position in each test group; S104, placing the chip within the field of view of the observation device, and determining the size of the chip according to the position of the second matching mark located at the same position in each chip; S105, making the edge of the wafer be within the field of view of the observation device, and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge; S106, determining a first positional relationship between a preset test group and the wafer according to the third coordinate and the first coordinate, and arranging each test group on the wafer according to the size of the test group and the first positional relationship; S107, determining a second positional relationship between the test structure and the test group to which it belongs according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; S108 , arranging the chips in each test group according to the first coordinates, the size of the chips, and the size of the test group, and generating a first wafer map.

[0018] In the present disclosure, Figure 2As shown, wafer 201, as a basic material for semiconductor chip manufacturing, can provide a stable carrier for the construction of various semiconductor devices and circuits. Chip 202 is located on wafer 201, and can integrate a large number of electronic components such as transistors, resistors, capacitors, etc., and realize specific functions through specific circuit design and manufacturing processes. Slicing blocks for dividing chips are reserved between chips 202. For some wafers 201, test structures 203 are also included. These test structures 203 can be connected to chips 202 to perform performance tests on chips 202, such as BB structures (Bonding Box), including pads (Pad) and test circuits for electrical testing, which can be used to test chip performance. These structures allow chips to be tested at the wafer level to verify whether their electrical characteristics and functions meet the expected standards. However, due to the different sizes of the test structure 203 and the chip 202, when generating a wafer map, engineers need to traverse each test structure 203 and chip 202 position on the wafer 201 one by one. When the number of chips 202 is large, a large amount of labor costs will be generated, and the efficiency of generating a wafer map is extremely low.

[0019] In the present disclosure, Figure 3 As shown, the example is to generate a wafer image by moving the wafer 201. The method concept provided for generating a wafer image by moving the observation device 301 is consistent with that for generating a wafer image by moving the wafer 201. The wafer 201 is placed on the carrier 302. The carrier 302 includes a precise moving device. A spatial rectangular coordinate system is established with the preset position of the carrier 302 as the origin, so that the wafer 201 can be moved to the position of the specified coordinates within a certain spatial range. The observation device 301 is used to observe the wafer 201, and the coordinates of the observed object on the wafer 201 when it coincides with the center position of the field of view of the observation device 301 are used as the specified coordinates to which the wafer 201 is moved. In one possible embodiment, the preset position of the carrier 302 coincides with the center position of the field of view of the observation device 301. As Figure 2As shown, a plurality of test groups 204 are divided on the wafer 201, and each test group 204 includes a test structure 203 and a chip 202 arranged in the same manner. Slicing blocks for dividing chips are reserved between the test groups 204. The positions of the preset test groups can be calibrated using these slicing blocks. For example, in the intersection area formed by the slicing blocks between the test groups 204 and the test structures 203 adjacent to the slicing blocks, the position of the center point A of the area is determined as the calibrated position of the preset test group, and the coordinates of point A are determined as the first coordinates (X1, Y1, Z1), which may refer to the position coordinates when the wafer 201 is moved so that point A coincides with the center of the field of view of the observation device 301. The calibrated position coordinates of the test structure 203 in the preset test group 204 are determined as the second coordinates (X2, Y2, Z2), which may refer to the position coordinates when the wafer 201 is moved so that the calibrated position of the test structure 203 coincides with the center of the field of view of the observation device 301. In a possible implementation, the position of the pad in the test structure is determined as the second coordinate. The test group 204 is placed within the field of view of the observation device 301, and the same position in each test group 204 is determined to be the position of the first matching mark. The size of the test group can be determined based on the position of the first matching mark. Similarly, the chip 202 is placed within the field of view of the observation device 301, and the same position in each chip 202 is determined to be the position of the second matching mark. The size of the chip can be determined based on the position of the second matching mark. The edge of the wafer 201 is placed within the field of view of the observation device 301, and the position coordinates of at least three points on the arc of the edge of the wafer 201 are determined. Based on the principle that three non-collinear points can uniquely determine a circle, the coordinates of the center point of the wafer 201 are determined as the third coordinates (X3, Y3, Z3).

[0020] Further, with the third coordinate as the center of the circle and the first coordinate as the reference position of the test group 204, the test group 204 is arranged on the wafer 201 in combination with the size of the test group 204, and the position coordinates of each test group 204 on the wafer 201 can be determined. According to the second coordinate of the calibration position of the test structure 203 in the preset test group 204, the position coordinates of the test structure 203 in each test group 204 can be determined, and the test structure 203 is arranged in the test group 204. According to the first coordinate, the size of the chip 202 and the size of the test group 204, the chip 202 is arranged in the test group 204, and the position coordinates of the chip 202 in each test group 204 can be determined. Thus, a first wafer map including the position coordinates of the test structure 203 and the chip 202 is generated.

[0021] In the embodiment of the present application, by determining the calibrated position coordinates of the preset test group 204 and the test structure 203 therein, the size of the test group 204, the size of the chip 202 and the coordinates of the center of the wafer 201, the test group 204 is arranged on the wafer 201, and the test structure 203 and the chip 202 are further arranged in each test group 204, and a wafer map including the position information of the test structure 203 and the chip 202 is generated. Therefore, the wafer map is not affected by the number of chips 202 in the test group 204, and the efficiency of generating the wafer map is greatly improved.

[0022] In another embodiment of the present disclosure, in the above step S103, the test group is located within the field of view of the observation device, and the size of the test group is determined according to the position of the first matching mark located at the same position in each test group, including the following steps: Step 1: Place the test group within the field of view of the observation device, and determine any mechanism located at the same position in each test group as the first matching identifier; Step 2: Determine the horizontal size of the test group according to the distance between two preset positions of the first matching marks that are adjacent in the horizontal direction; wherein the horizontal size of the test group includes: the sum of the length of the horizontal side of the test group and the width of the block divided between the test groups; Step 3: Determine the longitudinal size of the test group according to the distance between two longitudinally adjacent preset positions of the first matching markers; wherein the longitudinal size of the test group includes: the sum of the length of the vertical side of the test group and the width of the block between the test groups.

[0023] In the embodiment of the present disclosure, by using precise image matching and feature recognition algorithms, the first matching mark with high recognition and uniqueness in the test group 204 can be accurately determined, and then the size of the test group 204 can be determined according to the distance between adjacent first matching marks. For the above step 1, any mechanism is selected in the test group 204 as the first matching mark, and the first matching mark has the characteristics of high recognition and uniqueness. The same position of each test group 204 includes the first matching mark. For the above step 2, illustratively, as Figure 4 As shown, the preset positions of two first matching marks adjacent in the horizontal direction are located at point B and point C respectively, and the distance BC between point B and point C is equal to the horizontal dimension of the test group 204, wherein the horizontal dimension of the test group 204 includes: the sum of the length of the horizontal side of the test group 204 and the width of the block between the test groups 204. For the above step 3, exemplarily, as Figure 4As shown, the preset positions of two first matching marks adjacent in the longitudinal direction are located at points C and D respectively, and the distance CD between points C and D is equal to the longitudinal dimension of the test group 204, wherein the longitudinal dimension of the test group 204 includes: the sum of the length of the vertical side of the test group 204 and the width of the dicing block between the test groups 204. Determining the size of the test group 204 is conducive to the subsequent arrangement of the test group 204 on the wafer 201 and the determination of the specific position coordinates of each test group 204 on the wafer 201.

[0024] In another embodiment of the present disclosure, in the above step S104, the chip is placed within the field of view of the observation device, and the size of the chip is determined according to the position of the second matching mark located at the same position in each chip, including the following steps: Step 1: Place the chip within the field of view of the observation device, and determine any mechanism located at the same position in each chip as the second matching mark; Step 2: Determine the lateral size of the chip according to the distance between two preset positions of the second matching marks that are adjacent in the lateral direction; wherein the lateral size of the chip includes: the sum of the length of the horizontal side of the chip and the width of the dicing blocks between the chips; Step 3: Determine the longitudinal dimension of the chip according to the distance between two preset positions of the second matching marks adjacent to each other in the longitudinal direction; wherein the longitudinal dimension of the chip includes: the sum of the length of the vertical side of the chip and the width of the dicing blocks between the chips.

[0025] In the embodiment of the present disclosure, accurate image matching and feature recognition algorithms are used to accurately determine the second matching mark with high recognition and uniqueness in the chip 202, and then determine the size of the chip 202 according to the distance between adjacent second matching marks. For the above step 1, any mechanism is selected in the chip 202 as the second matching mark, and the second matching mark has the characteristics of high recognition and uniqueness. The same position of each chip 202 includes the second matching mark. For the above step 2, illustratively, as Figure 5 As shown, the preset positions of the two second matching marks adjacent in the horizontal direction are located at points E and F respectively, and the distance EF between points E and F is equal to the horizontal dimension of the chip 202, wherein the horizontal dimension of the chip 202 includes: the sum of the length of the horizontal side of the chip 202 and the width of the dicing block between the chips 202. For the above step 3, exemplarily, as Figure 4As shown, the preset positions of the two second matching marks adjacent in the longitudinal direction are located at points F and G respectively, and the distance FG between points F and G is equal to the longitudinal dimension of the chip 202, wherein the longitudinal dimension of the chip 202 includes: the sum of the length of the vertical side of the chip 202 and the width of the dicing block between the chips 202. Determining the size of the chip 202 is conducive to the subsequent arrangement of the chips 202 in the test group 204 and the determination of the specific position coordinates of the chips 202 in each test group 204. The wafer map can show the specific position and size of the chip 202, which is convenient for the implementation of the steps of testing, cutting and packaging the wafer.

[0026] In another embodiment of the present disclosure, in the above step S105, the edge of the wafer is located within the field of view of the observation device, and the third coordinate of the center point of the wafer is determined according to the position coordinates of at least three points on the arc of the edge of the wafer, including the following steps: Step 1: Make the edge of the wafer within the field of view of the observation device, determine the fourth coordinate of the observation object located at the center of the field of view of the observation device; determine the first coordinate deviation values ​​between the fourth coordinate and the positions of multiple arbitrary points on the arc of the wafer edge; determine the fifth coordinate of the position of each arbitrary point according to the fourth coordinate and the multiple first coordinate deviation values; or, Step 2, making multiple arcs of the edge of the wafer located in the field of view of the observation device in sequence, and determining the fourth coordinate of the observation object located at the center of the field of view of the observation device in sequence; within the field of view of the observation device, respectively determining the first coordinate deviation value between the fourth coordinate and the position of any point on the multiple arcs; and respectively determining the fifth coordinate of the position of each arbitrary point according to the multiple fourth coordinates and the corresponding first coordinate deviation values; Step 3: Fit the center point of the wafer based on the fifth coordinates corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

[0027] In the disclosed embodiment, accurate positioning of the center point of the wafer 201 is a key step in generating a wafer map. Based on the principle that three non-collinear points can uniquely determine a circle, the edge arc of the wafer 201 can be fitted with the aid of machine vision technology, thereby achieving accurate positioning of the center point of the wafer 201. Figure 6As shown, in order to determine the position coordinates of at least three non-collinear points on the arc, for the above step 1, the edge of the wafer 201 is located within the field of view of the observation device 301, and the observation object at the center of the field of view is point H, whose coordinates are the fourth coordinates (X4, Y4, Z4). The arc of the edge of the wafer 201 within the field of view is regarded as a curve on a two-dimensional plane, and multiple points are selected at different positions of the curve, for example, a point is selected at the starting position, the middle position, and a point near the end of the arc, and the coordinate deviation values ​​of these points from the fourth coordinate are determined respectively, that is, the first coordinate deviation (△X1, △Y1). Then, according to the difference between the fourth coordinate and the multiple first coordinate deviation values, the fifth coordinate (X5, Y5, Z5) = (X4-△X1, Y4-△Y1, Z4) of the position of any point can be determined. For the above step 2, multiple arcs on the edge of the wafer 201 are sequentially located within the field of view of the observation device 301, and the position coordinates of the point located at the center of the field of view of the observation device 301 are sequentially determined, that is, the fourth coordinates (X4, Y4, Z4), and the deviation values ​​between the positions of any point on the multiple arcs and the corresponding fourth coordinates, that is, the first coordinate deviation values ​​(△X1, △Y1), are respectively determined. Then, according to the difference between the multiple fourth coordinates and the multiple first coordinate deviation values ​​corresponding to them, the fifth coordinates (X5, Y5, Z5) = (X4-△X1, Y4-△Y1, Z4) of the position of each arbitrary point can be determined. For the above step 3, based on the fifth coordinates of the above at least three points, the center of the wafer 201 is fitted. Fitting the center of the circle can refer to the process of determining the center position of a circle according to a set of data points by mathematical methods. There are many methods for fitting the center of the circle, such as the least squares method, the geometric method, the iterative method, etc., and finally the position coordinates of the center point of the wafer 201, that is, the third coordinates (X3, Y3, Z3) are determined. By determining the position coordinates of the center point of the wafer 201 , the specific position of the entire wafer 201 in the space coordinate system can be accurately determined, so as to facilitate subsequent operations on the semiconductor devices on the wafer 201 .

[0028] In another embodiment of the present disclosure, in the above step S108, arranging the chips in each test group according to the first coordinate, the size of the chip and the size of the test group to generate a first wafer map includes the following steps: Step 1: preliminarily arrange the chips in the test group according to the sixth coordinate of the preset position of the second matching mark of any chip, the size of the chip and the size of the test group; Step 2: determine the intersection area formed by the diced blocks between the test groups and their adjacent test structures as the first area; Step 3: Determine the chip position correction method based on the first coordinate, the horizontal width and vertical width of the first area, the sixth coordinate and the chip size, and correct the chip positions preliminarily arranged in each test group to generate a first wafer map.

[0029] In the embodiment of the present disclosure, based on the position of the test group 204 determined on the wafer 201 and the position of the test structure 203 determined in the test group 204, the position of the chip 202 is further determined in the test group 204, and a first wafer map including the position information of the chip 202 is generated. Figure 2 As shown, the test group 204 includes a test structure 203 and a chip 202. The test groups 204 include dicing blocks, and the intersection area of ​​the area formed by the dicing blocks and the test structure is the first area. Any preset position point A is determined in the first area. For example, point A can be located at the center of the intersection area, and the position coordinates of point A are the first coordinates (X1, Y1, Z1). With A as the calibration position of the preset test group 204, the test groups 204 are arranged on the wafer 201 according to the coordinates of the center point of the wafer 201 and the size of the test group 204, and the position coordinates of each test group 204 can be determined. For each test group 204, the arrangement of the test structure 203 and the chip 202 therein is the same. According to the second coordinates (X2, Y2, Z2) of the calibration position of the test structure 203 in the preset test group 204, the relative position of the test structure 203 and the test group 204 can be determined. By arranging the test structure 203 in the test group 204, the position of the test structure 203 in each test group 204 can be determined. Further, the position of the chip 202 is determined in the test group 204, and a wafer map including the position information of the chip 202 is generated. For the above step 1, the preset position of the second matching mark in the chip 202 is point E, and the coordinates of point E are the sixth coordinates (X6, Y6, Z6). The coordinates are used as the preset position of the chip 202. For example, point E can be used as the position coordinates of the vertex of the upper left corner of the chip 202. According to the size of the chip 202 that has been determined and the size of the test group 204, the chip 202 is preliminarily arranged in the test group 204. Since the size of the test structure 203 is much smaller than the size of the chip 202, the position of the chip 202 and the test structure 203 can be avoided from overlapping or covering. In a possible implementation, the result of the preliminary arrangement of the chip 202 is determined as the generated wafer map. Since the sixth coordinate is used as the vertex of the upper left corner of the chip 202, the position of the chip 202 has a certain position deviation from the actual position. In order to correct the position deviation, for the above step 3, the position correction method of the chip is determined based on the first coordinate, the horizontal width and vertical width of the first area, the sixth coordinate and the size of the chip. For example, the point corresponding to the first coordinate is located at the center point A of the first area. According to the first coordinate (X1, Y1, Z1) of point A and the horizontal width h1 and vertical width h2 of the first area, the position coordinate of the vertex at the lower right corner of the first area can be determined. , the coordinate deviation between the sixth coordinate of the preset position of the second matching mark and the coordinate of this point is The obtained coordinate deviation value is modulo the size of the chip 202 to determine the compensation value. For example, if the size of the chip 202 is (X, Y), the compensation value is , the compensation value is compensated to the position coordinates of the chips 202 preliminarily arranged above, the positions of the chips 202 preliminarily arranged in each test group 204 are corrected, and a first wafer map including a one-to-one correspondence with the actual chip 202 position coordinates is generated.

[0030] In another embodiment of the present disclosure, it also includes: The first area is located within the field of view of the observation device, and the lateral width and longitudinal width of the first area are determined, including: Step 1: Make the first area within the field of view of the observation device, and input four straight lines so that the four straight lines coincide with the four sides of the first area respectively; Step 2: Determine the horizontal width and vertical width of the first area according to the distances between four pairs of parallel straight lines.

[0031] In the embodiment of the present disclosure, the horizontal width and the vertical width of the first area are determined by fitting the distances between the straight lines where the four sides of the first area are located. Figure 2 As shown, for the above step 1, the first area is located within the field of view of the observation device 301, four straight lines are input, and the positions of the straight lines are moved so that the straight lines coincide with the four sides of the first area respectively. For the above step 2, the distances between the two parallel straight lines are fitted respectively, so as to determine the horizontal width and the vertical width of the first area. Through the fitting method, the horizontal width and the vertical width of the first area can be determined more accurately.

[0032] In another embodiment of the present disclosure, the method further includes: positioning the pads of the chip within the field of view of the observation device, determining the position coordinates of the pads in the chip, and generating a second wafer map including the position coordinates of the pads in the chip based on the first wafer map, including: Step 1: Make the pad of the chip within the field of view of the observation device, and determine the seventh coordinate of the observation object located at the center of the field of view of the observation device; Step 2, determining a second coordinate deviation value between the seventh coordinate and the pad position of the chip; Step 3, determining the eighth coordinate of the pad of the chip according to the difference between the seventh coordinate and the second coordinate deviation value; Step 4: Determine a third positional relationship between the chip pads and the chip based on the eighth coordinates and the arrangement of the chips in the first wafer image, and generate a second wafer image including the position coordinates of the chip pads based on the third positional relationship.

[0033] In the embodiment of the present disclosure, the pad in the chip 202 may be a channel that allows the transmission of electronic signals and current, and is used to connect the chip 202 to an external circuit board or other electronic components. By determining the position of the pad in a chip 202, the position of the pad in each chip 202 can be determined based on the first wafer map. For example, Figure 7 As shown, for the above step 1, the pad of chip 202 is located within the field of view of the observation device 301, the pad is located at point J, and the coordinates of point I corresponding to the center of the field of view of the observation device 301 are the seventh coordinates (X7, Y7, Z7). For the above step 2, the coordinate deviation value between point I and point J can be determined as the second coordinate deviation value (△X2, △Y2) by machine vision fitting. For the above step 3, the pad position coordinates are the eighth coordinates, and the eighth coordinates can be expressed as (X8, Y8, Z8) = (X7-△X2, Y7-△Y2, Z7). For the above step 4, after determining the position coordinates of the pad, according to the position coordinates of the chip 202 arrangement in the first wafer map, the chip 202 to which the pad belongs and the positional relationship of the pad relative to the chip 202 can be determined, thereby determining the position of the pad in each chip 202, and then generating a second wafer map including the position coordinates of the pad in the chip 202. Determining the position of the pad is helpful in using the pad as a test interface during the wafer 201 test phase, and connecting to a tester via a probe to perform electrical performance tests on each chip 202 .

[0034] In another embodiment of the present disclosure, after determining the first matching mark, the method further includes: determining a first angle of wafer rotation according to an angle between a straight line connecting at least two preset positions of first matching marks in the same row or column and a horizontal line; rotating the wafer according to the first angle so that the test group is adjusted to a horizontal state within the field of view of the observation device; or, The second angle of wafer rotation is determined based on the angle between the straight line connecting at least two second matching marker preset positions in the same row or column and the horizontal line; the wafer is rotated according to the second angle so that the chip is adjusted to a horizontal state within the field of view of the observation device.

[0035] In the embodiment of the present disclosure, after the first matching mark is determined, the angle of the wafer 201 can be adjusted by performing linear fitting on the preset positions of at least two first matching marks on the same row or column to achieve precise alignment of the wafer 201. For example, Figure 4As shown, point B and point C are preset positions of the first matching mark on the same row, and point C and point D are preset positions of the first matching mark on the same column. By fitting a straight line along the preset positions in at least two first matching mark images in the same row or column, the fitting straight line may refer to finding a straight line through a set of data points so that the straight line is as close to these data points as possible. The method of fitting a straight line may include the least square method, the matrix method, etc. According to the angle between the fitting straight line and the horizontal line, the first angle of rotation of the wafer 201 is determined. The wafer 201 is rotated according to the first angle, and the rotation angle of the wafer 201 is gradually adjusted until the desired preset alignment accuracy is reached, so that the test group 204 on the wafer 201 is aligned to a horizontal state within the field of view of the observation device 301. By identifying and matching the first matching mark with high recognition in the test group 204, the test group 204 can be more accurately aligned to a horizontal state.

[0036] After the second matching mark is determined, the angle of the wafer 201 can be adjusted by performing linear fitting on the preset positions of at least two second matching marks on the same row or column to achieve precise alignment of the wafer 201. For example, Figure 5 As shown, point E and point F are preset positions of the second matching mark on the same row, and point F and point G are preset positions of the second matching mark on the same column. By fitting a straight line along the preset positions in at least two second matching mark images in the same row or column, the fitting straight line may refer to finding a straight line through a set of data points so that the straight line is as close to these data points as possible. The method of fitting a straight line may include the least squares method, the matrix method, etc. According to the angle between the fitting straight line and the horizontal line, the second angle of rotation of the wafer 201 is determined. The wafer 201 is rotated according to the second angle, and the rotation angle of the wafer 201 is gradually adjusted until the desired preset alignment accuracy is reached, so that the chip 202 on the wafer 201 is aligned to a horizontal state within the field of view of the observation device 301. By identifying and matching the second matching mark with high recognition in the chip 202, the chip 202 can be aligned to a horizontal state more accurately.

[0037] Based on the same inventive concept, the embodiments of the present disclosure also provide a device for generating a wafer image and a device for testing a wafer. Since the principles of the problems solved by these devices and equipment are similar to those of the aforementioned method for generating a wafer image, the implementation of the device and equipment can refer to the implementation of the aforementioned method, and the repeated parts will not be repeated.

[0038] The present disclosure provides a device for generating a wafer map, such as Figure 8 As shown, including: The calibration module 801 is used to provide a wafer, which includes multiple test groups on the wafer, wherein each of the test groups includes a test structure and a chip arranged in the same manner; determine any one of the multiple test groups divided on the wafer as a preset test group, determine the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure in the preset test group; make the test group within the field of view of the observation device, and determine the size of the test group according to the position of the first matching mark located at the same position in each test group; make the chip within the field of view of the observation device, and determine the size of the chip according to the position of the second matching mark located at the same position in each chip; make the edge of the wafer within the field of view of the observation device, and determine the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the edge of the wafer; The wafer map generation module 802 is used to determine the first position relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to the size of the test group and the first position relationship; determine the second position relationship between the test structure and the test group to which it belongs according to the second coordinate and the first coordinate, and arrange the test structure in each test group according to the second position relationship; arrange the chips in each test group according to the first coordinate, the size of the chip and the size of the test group to generate a first wafer map.

[0039] In another embodiment of the present disclosure, the calibration module 801 is used to locate the test group within the field of view of the observation device, and determine any mechanism located at the same position in each test group as a first matching identifier; Determine the lateral size of the test group according to the distance between two preset positions of the first matching marks that are adjacent in the lateral direction; wherein the lateral size of the test group includes: the sum of the length of the horizontal side of the test group and the width of the slicing blocks between the test groups; The longitudinal dimension of the test group is determined according to the distance between two longitudinally adjacent preset positions of the first matching marks; wherein the longitudinal dimension of the test group includes: the sum of the length of the vertical side of the test group and the width of the slicing blocks between the test groups.

[0040] In another embodiment of the present disclosure, the calibration module 801 is used to make the chip be located within the field of view of the observation device, and determine any mechanism located at the same position in each chip as a second matching mark; Determine the lateral size of the chip according to the distance between two preset positions of the second matching marks that are adjacent in the lateral direction; wherein the lateral size of the chip includes: the sum of the length of the horizontal side of the chip and the width of the dicing blocks between the chips; The longitudinal dimension of the chip is determined according to the distance between two longitudinally adjacent preset positions of the second matching marks; wherein the longitudinal dimension of the chip includes: the sum of the length of the vertical side of the chip and the width of the dicing blocks between the chips.

[0041] In another embodiment of the present disclosure, the calibration module 801 is used to make the edge of the wafer within the field of view of the observation device, determine the fourth coordinate of the observation object located at the center of the field of view of the observation device; determine the first coordinate deviation values ​​between the fourth coordinate and the positions of multiple arbitrary points on the arc of the edge of the wafer; determine the fifth coordinate of the position of each arbitrary point according to the fourth coordinate and the multiple first coordinate deviation values; or, Make the multiple arcs of the edge of the wafer be located in the field of view of the observation device in sequence, and determine the fourth coordinate of the observation object located at the center of the field of view of the observation device in sequence; determine the first coordinate deviation value between the fourth coordinate and the position of any point on the multiple arcs in the field of view of the observation device respectively; determine the fifth coordinate of the position of each arbitrary point according to the multiple fourth coordinates and the corresponding first coordinate deviation values; The center point of the wafer is fitted based on the fifth coordinates corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

[0042] In another embodiment of the present disclosure, the wafer map generation module 802 is used to preliminarily arrange the chips in the test group according to the sixth coordinate of the preset position of the second matching mark of any chip, the size of the chip and the size of the test group; Determine an intersection area formed by the diced blocks between the test groups and their adjacent test structures as a first area; Based on the first coordinate, the horizontal width and the vertical width of the first area, the sixth coordinate and the size of the chip, the chip position correction method is determined, and the chip positions preliminarily arranged in each test group are corrected to generate a first wafer map.

[0043] In another embodiment of the present disclosure, the wafer map generation module 802 is further used to: The first area is located within the field of view of an observation device, and a horizontal width and a vertical width of the first area are determined, including: The first area is located within the field of view of the observation device, and four straight lines are input so that the four straight lines coincide with four sides of the first area respectively; The horizontal width and the vertical width of the first area are determined according to the distances between the four straight lines which are parallel to each other.

[0044] In another embodiment of the present disclosure, the wafer map generation module 802 is further used to: locate the pads of the chip within the field of view of the observation device, determine the position coordinates of the pads in the chip, and generate a second wafer map including the position coordinates of the pads in the chip based on the first wafer map, including: The pad of the chip is located within the field of view of the observation device, and the seventh coordinate of the observation object located at the center of the field of view of the observation device is determined; Determine a second coordinate deviation value between the seventh coordinate and the pad position of the chip; Determine an eighth coordinate of the pad of the chip by subtracting the seventh coordinate from the second coordinate deviation value; According to the eighth coordinate and the arrangement of the chips in the first wafer map, a third positional relationship between the chip pads and the chip is determined, and according to the third positional relationship, a second wafer map including the position coordinates of the chip pads is generated.

[0045] In another embodiment of the present disclosure, after determining the first matching mark, the calibration module 801 is further used to: determine the first angle of rotation of the wafer according to the angle between the straight line connecting at least two preset positions of the first matching marks in the same row or column and the horizontal line; rotate the wafer according to the first angle so that the test group is adjusted to a horizontal state within the field of view of the observation device; or, After determining the second matching mark, the calibration module 801 is further used to: determine the second angle of rotation of the wafer based on the angle between the straight line connecting at least two preset positions of the second matching marks in the same row or column and the horizontal line; rotate the wafer according to the second angle so that the chip is adjusted to a horizontal state within the field of view of the observation device.

[0046] An embodiment of the present disclosure provides a device for testing a wafer, including: a device for generating a wafer image as described in any of the above embodiments.

[0047] Through the description of the above implementation methods, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware, or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0048] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present disclosure.

[0049] Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description of the embodiment, or can be changed accordingly and located in one or more devices different from the present embodiment. The modules in the above embodiment can be combined into one module, or can be further divided into multiple sub-modules.

[0050] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0051] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A method for generating a wafer map, characterized in that: include: Providing a wafer, the wafer comprising a plurality of test groups, wherein each of the test groups comprises a test structure and a chip arranged in the same manner; Determine any one of the multiple test groups divided on the wafer as a preset test group, determine a first coordinate of a calibrated position on the preset test group and a second coordinate of a calibrated position of a test structure in the preset test group; The test groups are positioned within the field of view of the observation device, and the sizes of the test groups are determined according to the positions of the first matching marks located at the same position within each test group; The chip is placed within the field of view of the observation device, and the size of the chip is determined according to the position of the second matching mark located at the same position in each chip; The edge of the wafer is located within the field of view of the observation device, and the third coordinate of the center point of the wafer is determined according to the position coordinates of at least three points on the arc of the edge of the wafer; Determine a first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to a size of the test group and the first positional relationship; determining a second positional relationship between the test structure and the test group to which it belongs according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; According to the first coordinates, the size of the chip and the size of the test group, the chips in each test group are arranged to generate a first wafer map.

2. The method according to claim 1, characterized in that The step of placing the test group within the field of view of the observation device and determining the size of the test group according to the position of the first matching mark located at the same position in each test group includes: The test groups are placed within the field of view of the observation device, and any mechanism located at the same position in each test group is determined as a first matching identifier; Determine the lateral size of the test group according to the distance between two preset positions of the first matching marks that are adjacent in the lateral direction; wherein the lateral size of the test group includes: the sum of the length of the horizontal side of the test group and the width of the slicing blocks between the test groups; The longitudinal dimension of the test group is determined according to the distance between two longitudinally adjacent preset positions of the first matching marks; wherein the longitudinal dimension of the test group includes: the sum of the length of the vertical side of the test group and the width of the slicing blocks between the test groups.

3. The method according to claim 1, characterized in that The step of placing the chip within the field of view of the observation device and determining the size of the chip according to the position of the second matching mark located at the same position in each chip includes: The chip is placed within the field of view of the observation device, and any mechanism located at the same position in each chip is determined as a second matching mark; Determine the lateral size of the chip according to the distance between two preset positions of the second matching marks that are adjacent in the lateral direction; wherein the lateral size of the chip includes: the sum of the length of the horizontal side of the chip and the width of the dicing blocks between the chips; The longitudinal dimension of the chip is determined according to the distance between two longitudinally adjacent preset positions of the second matching marks; wherein the longitudinal dimension of the chip includes: the sum of the length of the vertical side of the chip and the width of the dicing blocks between the chips.

4. The method according to claim 1, characterized in that The step of making the edge of the wafer be located within the field of view of the observation device and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the edge of the wafer includes: Make the edge of the wafer located within the field of view of the observation device, determine the fourth coordinate of the observation object located at the center of the field of view of the observation device; determine the first coordinate deviation values ​​between the fourth coordinate and the positions of multiple arbitrary points on the arc of the edge of the wafer; determine the fifth coordinate of the position of each arbitrary point according to the fourth coordinate and the multiple first coordinate deviation values; or, Make the multiple arcs of the edge of the wafer be located in the field of view of the observation device in sequence, and determine the fourth coordinate of the observation object located at the center of the field of view of the observation device in sequence; determine the first coordinate deviation value between the fourth coordinate and the position of any point on the multiple arcs in the field of view of the observation device respectively; determine the fifth coordinate of the position of each arbitrary point according to the multiple fourth coordinates and the corresponding first coordinate deviation values; The center point of the wafer is fitted based on the fifth coordinates corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

5. The method according to claim 1, characterized in that The step of arranging the chips in each test group according to the first coordinates, the size of the chips, and the size of the test group to generate a first wafer map includes: Preliminarily arranging the chips in the test group according to the sixth coordinate of the preset position of the second matching mark of any chip, the size of the chip and the size of the test group; Determine an intersection area formed by the diced blocks between the test groups and their adjacent test structures as a first area; Based on the first coordinate, the horizontal width and the vertical width of the first area, the sixth coordinate and the size of the chip, the chip position correction method is determined, and the chip positions preliminarily arranged in each test group are corrected to generate a first wafer map.

6. The method according to claim 5, characterized in that Also includes: The first area is located within the field of view of an observation device, and a horizontal width and a vertical width of the first area are determined, including: The first area is located within the field of view of the observation device, and four straight lines are input so that the four straight lines coincide with four sides of the first area respectively; The horizontal width and the vertical width of the first area are determined according to the distances between the four straight lines which are parallel to each other.

7. The method according to claim 1, characterized in that Also includes: The method comprises: placing the pads of the chip within the field of view of the observation device, determining the position coordinates of the pads in the chip, and generating a second wafer map including the position coordinates of the pads in the chip based on the first wafer map, including: The pad of the chip is located within the field of view of the observation device, and the seventh coordinate of the observation object located at the center of the field of view of the observation device is determined; Determine a second coordinate deviation value between the seventh coordinate and the pad position of the chip; Determine an eighth coordinate of the pad of the chip by subtracting the seventh coordinate from the second coordinate deviation value; According to the eighth coordinate and the arrangement of the chips in the first wafer map, a third positional relationship between the chip pads and the chip is determined, and according to the third positional relationship, a second wafer map including the position coordinates of the chip pads is generated.

8. The method according to claim 1, characterized in that After determining the first matching mark, the method further includes: determining a first angle of rotation of the wafer according to an angle between a straight line connecting at least two preset positions of the first matching marks in the same row or column and a horizontal line; rotating the wafer according to the first angle so that the test group is adjusted to a horizontal state within the field of view of the observation device; or After determining the second matching mark, it also includes: determining the second angle of rotation of the wafer based on the angle between the straight line connecting at least two preset positions of the second matching marks in the same row or column and the horizontal line; rotating the wafer according to the second angle so that the chip is adjusted to a horizontal state within the field of view of the observation device.

9. A device for generating a wafer map, characterized in that: include: A calibration module is used to provide a wafer, which includes multiple test groups on the wafer, wherein each of the test groups includes a test structure and a chip arranged in the same manner; determine any one of the multiple test groups divided on the wafer as a preset test group, determine the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure in the preset test group; make the test group within the field of view of an observation device, and determine the size of the test group according to the position of a first matching mark located at the same position in each test group; make the chip within the field of view of the observation device, and determine the size of the chip according to the position of a second matching mark located at the same position in each chip; make the edge of the wafer within the field of view of the observation device, and determine the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the edge of the wafer; A wafer map generation module is used to determine a first position relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to the size of the test group and the first position relationship; determine a second position relationship between a test structure and the test group to which it belongs according to the second coordinate and the first coordinate, and arrange the test structure in each test group according to the second position relationship; arrange the chips in each test group according to the first coordinate, the size of the chip and the size of the test group to generate a first wafer map.

10. A device for testing wafers, characterized in that: Includes the device for generating a wafer map as described in claim 9.

Images