Data processing system with tagged and untagged address pointers and method for accessing locations in data processing system

Abstract

A data processing system includes a processor and a memory. The processor is configured to execute instructions to access a location pointed by an address pointer. The memory is coupled to the processor and configured to have a plurality of memory portions. A first address pointer for accessing a first portion of the memory includes a type bit field, a flag bit field, and a first address bit field. A second address pointer for accessing a second portion of the memory is configured to have only the type bit field and a second address bit field and not the flag bit field. The type bit field is set to a first value for a tagged pointer and a second value for an untagged pointer. In another embodiment, a method for accessing a location in the data processing system is provided.

Description

Technical Field

[0001] The present disclosure relates generally to data processing, and more particularly, to a data processing system having tagged and untagged address pointers and a method for accessing the data processing system. Background Art

[0002] A tagged address pointer includes a tag bit with metadata that reveals information about the data to which the address pointer points. Tagged address pointers are used for various purposes. Recently, tagged address pointers have been used to implement or improve memory security. For example, tagged address pointers can be used to detect out-of-bounds read accesses to memory and write accesses that result in overflows. For this purpose, the tag value, i.e., the metadata, should be large enough. A typical requirement is that at least one byte of data is used for the tag. Having an extra bit for the tag is not a problem in systems with 64-bit address pointers because these systems typically do not require 2 64 bytes of address space. If the maximum virtual memory size is limited to 2 L , then the upper 64-L bits are available for tagging. This works well for 64-bit processor cores, but not so well for 32-bit processor cores, where the address space in pointers is more densely populated. Some cost-effective microcontrollers include 32-bit processors, and often do not have virtual memory support. This limits the possibilities for memory tagging, or limits the size of tags that can be used for, e.g., memory security. Summary of the invention

[0003] According to an embodiment, a data processing system is provided, comprising: a processor configured to execute instructions to access a location pointed to by an address pointer; and a memory coupled to the processor, the memory being configured to have a plurality of memory portions, wherein a first address pointer is configured to include a tag, the first address pointer is used to access a first portion of the memory, and wherein a second address pointer is configured to have no tag, the second address pointer is used to access a second portion of the memory, wherein the first address pointer is configured to have a type bit field, a tag bit field, and a first address bit field, wherein the second address pointer is configured to have only the type bit field and the second address bit field without the tag bit field, and wherein the type bit field is set to a first value for a tagged pointer and a second value for an untagged pointer. The tag can be used to detect a security problem of the memory. The first portion of the memory can be a random access memory, and the second portion of the memory is used to start one or more of a read-only memory, a peripheral, and a field programmable gate array. The type bit field can include a single bit. The type bit field can include multiple bits. The type bit field may include two type bits for providing three tagged address pointer types, each of the three address pointer types addressing a specific address range in the data processing system. The type bit field may include the most significant bit of the first address pointer. The processor may also be configured to reconfigure the tagged address pointer to remove the type bit field, the tag bit field, and reformat the first address bit field according to predefined criteria.

[0004] In another embodiment, a method is provided, comprising: executing instructions by a processor to access a location in a data processing system pointed to by an address pointer; checking whether the address pointer is a tagged address pointer or an untagged address pointer, wherein the tagged address pointer has a type bit field, a tag bit field, and a first address bit field, wherein the untagged address pointer has the type bit field and a second address bit field without the tag bit field, and wherein the type bit field is set to a first value for the tagged address pointer and a second value for the untagged address pointer; using a tag in the tag bit field of the tagged address pointer according to a specified purpose in a data processing system including the processor; and accessing the location using the address in the address bit field of the tagged address pointer. The method may also include reconfiguring the tagged address pointer to remove the type bit field and the tag bit field before using the tagged address pointer for a load or store operation to a memory location. The type bit field may include a single bit. The type bit field may include a plurality of bits. The type bit field may include two type bits for providing three tagged address pointer types, each of the three address pointer types addressing a specific address range. The tag may be used to detect a memory security issue.

[0005] In yet another embodiment, a computer program is provided that includes instructions stored in a non-transitory medium, the instructions when executed performing operations including: executing instructions by a processor to access a location in a data processing system pointed to by an address pointer; checking whether the address pointer is a tagged address pointer or an untagged address pointer, wherein the tagged address pointer has a type bit field, a tag bit field, and a first address bit field, wherein the untagged address pointer has the type bit field and a second address bit field without the tag bit field, and wherein the type bit field is set to a first value for the tagged address pointer and a second value for the untagged address pointer; using a tag in the tag bit field of the tagged address pointer according to a specified purpose in a data processing system including the processor; and accessing the location using the address in the address bit field of the tagged address pointer. The computer program may also include reconfiguring the tagged address pointer to remove the type bit field and the tag bit field from the tagged address pointer before using the tagged address pointer for a load or store operation to a memory location. The type bit field may include a single bit. The type bit field may include multiple bits. The type bit field may include two type bits for providing three tagged address pointer types, each of which addresses a specific address range. The tags may be used to detect memory security issues. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals indicate like elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0007] Figure 1 A block diagram of a data processing system according to an embodiment is shown.

[0008] Figure 2 An untagged address pointer and a tagged address pointer are shown according to an embodiment.

[0009] Figure 3 Shown for Figure 1 An example memory map of a memory of a data processing system.

[0010] Figure 4 A tagged address pointer is shown with the type bit remapped for memory access operations.

[0011] Figure 5 An example of a tagged address pointer with more than one type bit is shown according to an embodiment.

[0012] Figure 6A method for accessing a memory using an address pointer having a type bit field according to an embodiment is shown. DETAILED DESCRIPTION

[0013] In general, a data processing system is provided that uses a combination of tagged and untagged address pointers. Tagged address pointers are used to access selected locations in the memory space of the data processing system, while untagged address pointers are used to access other locations in the memory space. Tagged address pointers are typically used for memory security, i.e., detecting out-of-bounds memory accesses and use-after-free accesses, but other uses are possible. Detecting memory security issues may only be necessary to protect data in random access memory (RAM). Data in read-only memory (ROM), code in ROM, code in RAM, and peripheral devices generally do not require memory security protection. Therefore, the data processing system provides for the use of tagged and untagged address pointers. In one embodiment, the pointer type bit is a type bit field that indicates whether the remaining bits in the address pointer represent a tagged address pointer that includes a tag bit field and a memory address, or whether the address pointer is an untagged address pointer that includes only a memory address without a tag.

[0014] The use of a type bit to distinguish tagged pointers from untagged pointers allows tagged pointers to be selectively used for portions of memory space that require tagging. This is applicable to processors where having enough bits for tagging in an address pointer may be a challenge, such as 32-bit processors. Using a 32-bit system as an example, if a memory region that needs to be tagged for memory security requires an N-bit address, 31-N bits are available for tagging bits. In many cases, 31-N bits will be sufficient for tagging. For example, a microcontroller with 512KB of RAM gives N=19, which means that 32-19=13 bits are available for tagging, plus the type bit, which is a suitable number of bits for memory security purposes.

[0015] Figure 1A block diagram of a data processing system 10 according to an embodiment is shown. The data processing system 10 may be implemented using one or more integrated circuits. The data processing system 10 includes a processor core 12, an address decoder 19, and a memory mapping area 20. Other embodiments may have additional hardware modules. The processor core 12 may be, for example, part of a microprocessor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a similar device. The processor core 12 may be a RISC-V processor or any other type of processor architecture. The processor core 12 may be one of a plurality of processor cores. The processor core 12 executes instructions of a computer program stored in a portion of a memory 20. The processor core 12 includes a load storage unit 13, a pointer type checker circuit 14, a tagged pointer reconfiguration circuit 15, a tag application 16, an address reformatting circuit 17, and a multiplexer 18.

[0016] In response to receiving load and store instructions, the load store unit 13 controls access to the memory 20. Depending on which portion of the memory 20 is being accessed, either a tagged address pointer or an untagged address pointer may be used to access the memory 20. The pointer type checker circuit 14 is responsible for checking the type bit of the address pointer to determine whether the address pointer is tagged or untagged. The untagged address pointer labeled "untagged pointer" is provided to the input of the multiplexer 18. The tagged address pointer labeled "tagged pointer" is first reconfigured by the tagged pointer reconfiguration circuit 15 to separate the tag portion of the address pointer from the address portion. Figure 2 . The tag in the address pointer marked as "tag" may include metadata that can be used in the tag application 16, which metadata may relate to, for example, memory security. The address portion of the tagged address pointer marked as "address" is provided to the address reformatting circuit 17 to be reformatted into a form expected by the memory 20. The multiplexer 18 is coupled to provide the untagged pointer (untagged pointer) or the reformatted address (address) from the address reformatting circuit 17 to the address decoder 19 depending on the control signal from the pointer type checker 14. The address decoder 19 is coupled to provide the address to the memory 20. The memory 20 represents all the memory of the data processing system 10 and includes a random access memory (RAM) 21, a read-only memory (ROM) 22, and a memory-mapped peripheral 23. In response to receiving the address from the address decoder 19, the read or write data marked as "R / W data" can be read from the location in the memory 20, or the read or write data can be written to the location in the memory 20.

[0017] Figure 2An untagged address pointer 31 and a tagged pointer 32 according to an embodiment are shown. For illustrative purposes, a 32-bit address pointer is shown. Other embodiments may include more or fewer bits. The type bit determines which of the tagged pointer or the untagged pointer is selected. In the untagged address pointer 31, the type bit in the bit field 33 is a logical zero to indicate that the address pointer 31 is untagged and only includes the address bit field 34 in addition to the type bit field 33. The type bit field 35 is a logical one to indicate that the address pointer 32 is a tagged address pointer. In other embodiments, the type bit logic may be inverted. In the example 32-bit processor, the type bit fields 33 and 35 occupy the most significant bits (MSBs) of the address pointers 31 and 32, respectively. In the address pointer 32, the tag bit field 36 includes a tag T and the address bit field 37 includes an address that occupies 31-T bits on the right hand side (least significant bit) of the address pointer 32. In one embodiment, pointer operations require that the address occupy the LSB bit. Other embodiments may be different. It is not absolutely necessary to make the pointer type bit as the MSB.

[0018] Figure 3 Show Figure 1 40 of memory 20. For example, memory map 40 is from the CORE-V-MCU system of the RISC-V core of the CORE-V family of the OpenHW Group, which is an open source 32-bit design. When an address used by a load or store operation causes the processor to access memory or a peripheral, the address must be mapped back to the address expected by the surrounding system. For untagged pointers, typically no or minimal remapping is required. The type bit is replaced with either zero or one. For tagged pointers, both the type field and the tag field are replaced with appropriate values, according to predefined criteria for the processor architecture, so that the value will address the correct location in the address space.

[0019] In one embodiment, memory tags are selectively applied. Tagged address pointers are typically used for memory security, i.e., detecting out-of-bounds memory accesses and use-after-free accesses. Therefore, only data in RAM may need to be protected. Code and data in ROM, code in RAM, and peripheral domains typically do not require memory security protection. For example, memory tags may be used for RAM memory of memory map 40, which corresponds to Figure 3 The total memory size of the RAM memory alone is 512KB, corresponding to 2 19In the memory map 40, the first 3 bits of the address are always 0, and the next bit is always 1. Therefore, in this case, the MSB bit can be used as a type bit to indicate whether the address pointer is tagged or untagged. Bits 30 down to 19 can be used as tags. The remaining 19 bits below the tag (bits 18 to 0) are used to access 2 19 Bytes of RAM memory address range. Figure 3 , it would not be possible to implement a tagged memory address pointer for all of the memory space shown in , since there would not be enough extra bits available for tagging. Selectively tagging only the portions of memory that need tagging and using type bits as shown can improve memory security in relatively small systems where tagging would otherwise be unavailable.

[0020] Figure 4 An example tagged address pointer 51 is shown with the type bit and tag remapped for memory access operations. When the tagged address pointer causes the processor core 12 to access the RAM 21, the Figure 1 The address reformatting circuit 17 in the memory remaps the tagged access pointer by removing the type and tag bits and replacing them with a properly formatted address determined by predefined criteria so that the RAM 21 is accessible. Figure 3 In the example memory map 40 of FIG. 4 , the replacement address value 52 corresponds to a tagged address in which the 13 most significant bits are replaced with the twelve bits corresponding to 0x1c0 (see FIG. 4 ). Figure 3 ) followed by a single zero bit. The 19 least significant bits are passed directly from the tagged address to the resulting reformatted address replacing the address value 52.

[0021] Figure 5An example address pointer for a 32-bit processor with more than one type bit according to an embodiment is shown. As shown, more than one bit can be used to indicate the type of tagged and untagged address pointers. In the case of two type bits, one memory area can be defined in the case of tagging, and three different areas can be defined in the case of tagging. Each of these areas will have a different replacement address value. For example, using two type bits, three tagged pointer types can be provided, wherein each type of addressing can have a specific address range of different sizes, and therefore the tag size (T1, T2, and T3) can also be different. In Figure 5, address pointer 61 is untagged, which is indicated by the value of 00 in the type bit field and the remaining bits including two type bits of the address bit field. Address pointer 62 is tagged and includes two type bits with a value of 01 of the tag bit field indicating T1 bits, so that the address bit field may include 30-T1 bits. Address pointer 63 is tagged and includes two type bits with a value of 10 of the tag bit field indicating T2 bits, so that the address bit field may include 30-T2 bits. The address pointer 64 is tagged and includes two type bits with a value of 11 for a tag bit field indicating T3 bits, so that the address bit field may include 30-T3 bits.

[0022] Figure 6 A method 80 for accessing memory using an address pointer with a type bit field according to an embodiment is shown. The method 80 starts at box 81. At box 81, a load or store instruction is executed by a processor to access a location pointed to by an address pointer. At box 82, the address pointer type bit field is checked to determine whether the address pointer is tagged or untagged. At decision box 83, if it is determined that the address pointer is untagged, a "no" path is taken to box 87, where the address of the address pointer is passed to the surrounding system of which the processor is a part to access memory or peripherals. However, if it is determined at decision box 83 that the type bit indicates that the pointer is tagged, a "yes" path will be taken to box 84. At box 84, the tagged address pointer is reconfigured to separate the tag and the address. At box 85, the tag is used for specific purposes, such as certain memory security issues, such as detecting out-of-bounds memory access and use-after-free access. At box 86, the address portion is reformatted according to a limited system address without a tag. At box 87, the reformatted address is then passed to the system to access the memory or peripherals.

[0023] Using type bits to distinguish tagged from untagged pointers in the manner described allows tagged pointers to be selectively used for portions of memory space that require tagging for systems with a limited number of address pointer bits.

[0024] Various embodiments or portions of embodiments may be implemented in hardware or as instructions on a non-transitory machine-readable storage medium, which includes any mechanism for storing information in a form readable by a machine, such as a personal computer, laptop, file server, smart phone, or other computing device. Non-transitory machine-readable storage media may include volatile and non-volatile memory, such as read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory, etc. Non-transitory machine-readable storage media do not include transitory signals.

[0025] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to a specific embodiment be construed as a key, essential, or requisite feature or element of any or all claims.

[0026] Furthermore, as used herein, the terms "a" and "an" are defined as one or more than one. In addition, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing the claim element so introduced to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "an". The same applies to the use of definite articles.

[0027] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A data processing system, characterized in that: include: a processor configured to execute instructions to access a location pointed to by an address pointer; as well as a memory coupled to the processor, the memory being configured to have a plurality of memory portions, wherein a first address pointer is configured to include a tag, the first address pointer being used to access a first portion of the memory, and wherein a second address pointer is configured to have no tag, the second address pointer being used to access a second portion of the memory, wherein the first address pointer is configured to have a type bit field, a tag bit field and a first address bit field, wherein the second address pointer is configured to have only the type bit field and the second address bit field without the tag bit field, and wherein the type bit field is set to a first value for a tagged pointer and a second value for an untagged pointer.

2. The data processing system according to claim 1, characterized in that: The first portion of the memory is a random access memory, and the second portion of the memory is used to boot one or more of a read only memory, a peripheral, and a field programmable gate array.

3. The data processing system according to claim 1, characterized in that: The type bit field includes two type bits for providing three tagged address pointer types, each of the three address pointer types addressing a specific address range in the data processing system.

4. The data processing system according to claim 1, characterized in that: The processor is also configured to reconfigure the tagged address pointer to remove the type bit field, the tag bit field, and to reformat the first address bit field according to predefined criteria.

5. A method, characterized in that include: executing instructions by a processor to access a location in a data processing system pointed to by an address pointer; checking whether the address pointer is a tagged address pointer or an untagged address pointer, wherein the tagged address pointer has a type bit field, a tag bit field, and a first address bit field, wherein the untagged address pointer has the type bit field and the second address bit field but not the tag bit field, and wherein the type bit field is set to a first value for the tagged address pointer and to a second value for the untagged address pointer; using the tag in the tag bit field of the tag address pointer according to a specified purpose in a data processing system including the processor; as well as The location is accessed using the address in the address bit field of the tag address pointer.

6. The method according to claim 5, characterized in that Also included is reconfiguring the tagged address pointer to remove the type bit field and the tag bit field before using the tagged address pointer for a load or store operation to a memory location.

7. The method according to claim 5, characterized in that The type bit field includes two type bits for providing three tagged address pointer types, each of which addresses a specific address range.

8. A computer program comprising instructions stored in a non-transitory medium, characterized in that When executed, the instructions perform operations including: executing instructions by a processor to access a location in a data processing system pointed to by an address pointer; checking whether the address pointer is a tagged address pointer or an untagged address pointer, wherein the tagged address pointer has a type bit field, a tag bit field, and a first address bit field, wherein the untagged address pointer has the type bit field and the second address bit field but not the tag bit field, and wherein the type bit field is set to a first value for the tagged address pointer and to a second value for the untagged address pointer; using the tag in the tag bit field of the tag address pointer according to a specified purpose in a data processing system including the processor; as well as The location is accessed using the address in the address bit field of the tag address pointer.

9. The computer program according to claim 8, characterized in that Also included is reconfiguring the tagged address pointer to remove the type bit field and the tag bit field from the tagged address pointer before using the tagged address pointer for a load or store operation to a memory location.

10. The computer program according to claim 8, characterized in that The type bit field includes two type bits for providing three tagged address pointer types, each of which addresses a specific address range.

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