Floating internal context memory

Abstract

A floating internal context memory is disclosed. In an embodiment, a processing device comprises: a memory to: store a plurality of memory pages having corresponding physical memory addresses in the memory; storing an active multi-level page table (MPT) that maps a virtual memory address to a physical memory address for a corresponding allocated memory page of a plurality of memory pages stored in the memory; and storing a floating MPT, the floating MPT mapping, at least in part, a virtual memory address to a physical memory address for a corresponding backup memory page stored in the memory, the floating MPT and the active MPT using a common mapping scheme; and a processor to receive a request to add virtual address-to-physical address mappings to the active MPT for more of the plurality of memory pages, and in response to receiving the request, abut at least a portion of the floating MPT with the active MPT, the active MPT is caused to provide virtual address-to-physical address mappings for at least some of the spare memory pages.

Description

Technical Field

[0001] The present invention relates to computer systems and, in particular, but not exclusively, to memory mapping. Background Art

[0002] Virtual memory may be used (e.g., by an operating system) to allow a process to work with contiguous segments of memory, while the physical memory corresponding to the virtual memory of a process is typically scattered across different areas of physical memory, or may have been moved to other storage, such as non-volatile memory. Virtual addresses are used by programs executed by accessing processes, while physical addresses are used by the hardware (or more specifically, by the random access memory subsystem). When a process requests access to data in memory, the hardware finds the physical memory address that maps to the requested virtual address provided by the process.

[0003] The mapping between virtual memory addresses and physical memory addresses may be provided by a page table, where each mapping is also referred to as a page table entry (PTE).

[0004] Multilevel Paging is a paging scheme consisting of two or more levels of page tables in a hierarchical manner. It is also called hierarchical paging. Level 1 page table entries are pointers to level 2 page tables, level 2 page table entries are pointers to level 3 page tables, and so on. The entries of the last level page table store the actual frame information of the physical memory address being sought. The level 1 page table includes a single page table, and the address of the page table is stored in the page table base register (PTBR). Summary of the invention

[0005] According to an embodiment of the present disclosure, a processing device is provided, comprising: a memory, the memory being used to: store a plurality of memory pages, the plurality of memory pages having corresponding physical memory addresses in the memory; store an active multi-level page table (MPT), the active multi-level page table mapping virtual memory addresses to physical memory addresses for corresponding allocated memory pages in the plurality of memory pages stored in the memory; and store a floating MPT, the floating MPT at least partially mapping virtual memory addresses to physical memory addresses for corresponding spare memory pages in the plurality of memory pages stored in the memory, the floating MPT and the active MPT using a common mapping scheme; and a processor, the processor being used to: receive a request to add virtual address to physical address mappings for more memory pages in the plurality of memory pages to the active MPT; and in response to receiving the request, contiguously connect at least a portion of the floating MPT to the active MPT so that the active MPT provides the virtual address to physical address mappings for at least some of the spare memory pages.

[0006] Further in accordance with an embodiment of the present disclosure, the processor is configured to generate the floating MPT and store the floating MPT in the memory.

[0007] Further according to an embodiment of the present disclosure, the processor is used to add at least one page table entry (PTE) present in the floating MPT to a given page of the active MPT so as to add the virtual address to physical address mapping for the at least some of the spare memory pages to the active MPT.

[0008] In addition, according to an embodiment of the present disclosure, the at least one PTE provides the physical memory address of at least one page in the floating MPT, and the providing includes the PTE providing the physical memory addresses of: the at least some memory pages in the spare memory pages; or pages in a lower level of the floating MPT.

[0009] Furthermore, according to an embodiment of the present disclosure, the processor is configured to remove the at least one PTE from the floating MPT.

[0010] Further in accordance with an embodiment of the present disclosure, the processor is configured to close a gap in the floating MPT created by removing the at least one PTE from the floating MPT.

[0011] Still further in accordance with an embodiment of the present disclosure, the processor is configured to traverse the active MPT including at least a portion of a contiguous portion of the floating MPT to convert a given virtual memory address to a given physical memory address of a given memory page of the spare memory pages.

[0012] Furthermore, according to an embodiment of the present disclosure, the given virtual memory address includes multiple parts, and the processor traverses the active MPT based on applying the multiple parts of the given virtual memory address to corresponding levels of the active MPT to find the given physical memory address of the given backup memory page.

[0013] In addition, according to an embodiment of the present disclosure, the processor is used to follow the physical memory address in the page table entry (PTE) in the corresponding level of the active MPT to find the given physical memory address of the given backup memory page, and the index to the PTE in the corresponding level of the active MPT is indicated by the multiple parts of the given virtual memory address.

[0014] Further in accordance with an embodiment of the present disclosure, the active MPT and the floating MPT are tree data structures.

[0015] Furthermore, according to an embodiment of the present disclosure, the number of at least some of the mapped spare memory pages is equal to 2 to the power of n, where n is an integer; and the virtual memory addresses of at least some of the memory pages mapped in the active MPT are aligned so that the n least significant bits of each of the virtual memory addresses are equal to 0.

[0016] Furthermore, according to an embodiment of the present disclosure, the processor is configured to add mappings of the at least some of the spare memory pages to the active MPT according to a minimum memory size.

[0017] In addition, according to an embodiment of the present disclosure, the processor is used to remove at least one page table entry (PTE) present in the active MPT to a given page of the floating MPT so as to remove the virtual address to physical address mapping for the unused memory page from the active MPT to the floating MPTT.

[0018] According to another embodiment of the present disclosure, a method is also provided, comprising: storing a plurality of memory pages, the plurality of memory pages having corresponding physical memory addresses in a memory; storing an active multi-level page table (MPT), the active multi-level page table (MPT) mapping virtual memory addresses to physical memory addresses of corresponding allocated memory pages in the plurality of memory pages stored in the memory; and storing a floating MPT, the floating MPT at least partially mapping virtual memory addresses to physical memory addresses of corresponding spare memory pages in the plurality of memory pages stored in the memory, the floating MPT and the active MPT using a common mapping scheme; and receiving a request to add virtual address to physical address mappings for more memory pages in the plurality of memory pages to the active MPT; and in response to receiving the request, contiguously placing at least a portion of the floating MPT with the active MPT so that the active MPT provides the virtual address to physical address mappings for at least some of the spare memory pages.

[0019] In further accordance with an embodiment of the present disclosure, the method includes generating a floating MPT.

[0020] Further according to an embodiment of the present disclosure, the method includes: adding at least one page table entry (PTE) present in the floating MPT to a given page of the active MPT so as to add the virtual address to physical address mapping for at least some of the spare memory pages to the active MPT.

[0021] In addition, according to an embodiment of the present disclosure, the at least one PTE provides the physical memory address of at least one page of the floating MPT, and the providing includes the PTE providing the physical memory addresses of: the at least some memory pages in the spare memory pages; or pages in a lower level of the floating MPT.

[0022] Furthermore, according to an embodiment of the present disclosure, the method includes: removing the at least one PTE from the floating MPT.

[0023] Further in accordance with an embodiment of the present disclosure, the method includes closing a gap in the floating MPT created by removing the at least one PTE from the floating MPT.

[0024] Still further in accordance with an embodiment of the present disclosure, the method includes traversing the active MPT including at least a portion of a contiguous portion of the floating MPT to convert a given virtual memory address to a given physical memory address of a given memory page of the spare memory pages.

[0025] Furthermore, according to an embodiment of the present disclosure, the given virtual memory address includes multiple parts, and the traversal includes traversing the active MPT based on applying the multiple parts of the given virtual memory address to corresponding levels of the active MPT to find the given physical memory address of the given backup memory page.

[0026] In addition, according to an embodiment of the present disclosure, the method includes: following the physical memory address in the page table entry (PTE) in the corresponding level of the active MPT to find the given physical memory address of the given backup memory page, wherein the index to the PTE in the corresponding level of the active MPT is indicated by the multiple parts of the given virtual memory address.

[0027] Further in accordance with an embodiment of the present disclosure, the active MPT and the floating MPT are tree data structures.

[0028] Furthermore, according to an embodiment of the present disclosure, the number of at least some of the mapped spare memory pages is equal to 2 to the power of n, where n is an integer; and the virtual memory addresses of at least some of the memory pages mapped in the active MPT are aligned so that the n least significant bits of each of the virtual memory addresses are equal to 0.

[0029] Furthermore, according to an embodiment of the present disclosure, the method: adds mappings of the at least some of the spare memory pages to the active MPT according to a minimum memory size.

[0030] Furthermore, according to an embodiment of the present disclosure, the method includes removing at least one page table entry (PTE) present in the active MPT to a given page of the floating MPT so as to remove virtual address to physical address mappings for unused memory pages from the active MPT to the floating MPT. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present invention will be understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a block diagram illustration of a device constructed and operative in accordance with an embodiment of the present invention;

[0033] Figure 2 is used for Figure 1 A schematic representation of an active multi-level page table in a device of;

[0034] Figure 3 yes Figure 2 A schematic diagram of a portion of an active multi-level page table;

[0035] Figures 4 to 5 yes Figure 2 A schematic representation of an active multi-level page table showing how virtual memory addresses are mapped to physical memory addresses;

[0036] Figure 6 is used for Figure 1 A schematic representation of a floating multi-level page table in a device of;

[0037] Figure 7 is a schematic representation of an active multi-level page table and a floating multi-level page table, illustrating making at least a portion of the floating multi-level page table contiguous with the active multi-level page table; and

[0038] Figure 8 Yes Figure 1 A flow chart of the steps in a method of using a device. DETAILED DESCRIPTION

[0039] Overview

[0040] As previously described, page tables, and in particular multi-level page tables, are used to provide mappings between virtual memory addresses and physical memory addresses for processes. Because scalable amounts of memory may be required, a certain amount of physical memory is allocated to a process and mapped using a multi-level page table (MPT). When more memory is needed, the process may request one or more memory pages selected by a page provider (e.g., by an operating system) from a backup memory page and mapped in the MPT for the process.

[0041] Due to the MPT structure, adding a memory page may require adding one or more entries to the MPT. For example, if the MPT has seven levels, then in some cases, adding a virtual address to physical address mapping for one memory page to the MPT may only require adding one entry to the MPT (e.g., in the seventh (lowest) level of the MPT). In some cases, six new pages and seven new entries may need to be added to the MPT in order to add a virtual address to physical address mapping for one memory page to the MPT.

[0042] One solution to provide spare pages is to use a linked list to store spare memory pages that are not currently associated with a virtual address, but are available to page providers on demand for adding mappings of new pages to the MPT. However, using a linked list results in the following problems. If a process requires a large resource, such as 512MB, the page provider will need to allocate 128K pages in memory (512MB divided by 4KB, assuming that each memory page is 4KB) to provide the requested 512MB. The page provider will need to iterate the linked list 128K times and add the mapping of the page to the MPT. Assuming that each last-hop MPT page (i.e., the lowest level in the MPT) includes 512 page table entries (PTEs) that reference 512 physical memory pages, adding a 128K memory page will require adding 256 last-hop pages and pages in the higher levels of the MPT to reference the new last-hop page. Assuming that it takes 4 microseconds to find an item in the linked list and add the mapping of the memory page to the MPT, it takes 512 milliseconds to iterate the linked list. That is, about half a second, which is too long for most processes.

[0043] Therefore, an embodiment of the present invention provides a device that stores two MPTs: an active MPT that maps virtual memory addresses to physical memory addresses for memory pages allocated to a process; and a floating MPT that at least partially maps virtual memory addresses to physical memory addresses for corresponding spare memory pages. The active MPT and the floating MPT use a common mapping scheme. In response to receiving a request to add virtual address to physical address mappings for more memory pages to the active MPT, a page provider of the device contiguously connects at least a portion of the floating MPT to the active MPT so that the active MPT also provides virtual address to physical address mappings for at least some of the spare memory pages. In this way, a linked list can be avoided. The floating MPT can be stored in some unused areas of the active MPT or in a different area of ​​the memory.

[0044] The process can be any suitable process, for example, a software process running on a CPU, or a hardware process such as a packet processing in a network interface controller or switch. The functionality of the page provider can be implemented by any one or more of the following: firmware, an operating system, and / or any suitable processing circuit, and the selection can depend on the operating environment. For example, if the process is a software process, the page provider can be implemented using an operating system, and if the process is a hardware process, the page provider can be implemented using firmware or processing circuits of a hardware processor. In some embodiments, the process and the page provider are executed in the same processing unit. In other embodiments, the process and the page provider are executed in different processing units.

[0045] In some embodiments, adding mappings for multiple spare memory pages to the active MPT may involve copying one PTE from the floating MPT to the active MPT. The copied PTE provides links from the active MPT to all pages in the floating MPT below the copied PTE, which in turn provides the physical memory address of the spare memory page. For example, if the copied PTE is from level 5 of the floating MPT, and the PTE references pages in levels 6 and 7 of the floating MPT, which in turn provide physical addresses for spare memory pages, then a single PTE copied from level 5 of the floating MPT to level 5 of the active MPT allows the active MPT to provide virtual address to physical address mappings for spare memory pages via the pre-existing structure of the floating MPT, which is now contiguous with the active MPT.

[0046] For example, the 256 last hop MPT pages may be referenced in a penultimate hop MPT page of the floating MPT (e.g., in the first half or the second half of the penultimate page). Thus, only 256 PTEs are copied from the floating MPT to the 256 PTEs of the same level of the active MPT to provide references to the 256 last hop MPT pages of the floating MPT and provide a virtual address to physical address mapping to a 128K memory page or 512MB.

[0047] Similarly, virtual address to physical address mapping for 256K memory pages or 1 GB may be provided by copying a single PTE in the stages above the second-to-last stage in the floating MPT to the stages above the second-to-last stage in the active MPT.

[0048] The PTEs copied from the floating MPT to the active MPT are then removed from the floating MPT, and the entries in the floating MPT may be rearranged, referred to herein as closing the gap, as described in the disclosed embodiments.

[0049] Embodiments of the present invention improve the way a computer or other processing device works by: providing better computer performance; providing higher processing speeds; providing less waiting time; and reducing power consumption.

[0050] System Description

[0051] Reference now Figure 1 , Figure 1 is a block diagram of a device 10 constructed and operative in accordance with an embodiment of the present invention. The device may be implemented as any suitable processing device, for example, a network interface controller device.

[0052] The device 10 includes a processor 12 and a memory 14. The memory 14 is configured to store a plurality of memory pages 16 having corresponding physical memory addresses in the memory 14. The memory 14 is configured to store an active multi-level page table (MPT) 18 that maps virtual memory addresses to physical memory addresses for corresponding allocated memory pages in the plurality of memory pages 16 stored in the memory 14. The memory 14 is configured to store a floating MPT 20 that at least partially maps virtual memory addresses to physical memory addresses for corresponding spare memory pages in the plurality of memory pages 16 stored in the memory 14. The floating MPT 20 and the active MPT 18 typically use a common mapping scheme. The memory 14 is configured to store other data used by the processor 12. The active MPT 18 and the floating MPT 20 may be tree data structures.

[0053] Reference now Figure 2 , Figure 2 is used for Figure 1 Schematic diagram of an active MPT 18 in device 10. Figure 2 The active MPT 18 is shown to have a plurality of stages 22. Figure 2 In the example of FIG. 1 , the active MPT 18 includes seven levels 22 (levels 1 to 7, or levels 22-1 to 22-7). The active MPT 18 may include two or more levels 22. The active MPT 18 includes a plurality of pages 24 (including page 24-1 in a first level 22-1 of the active MPT 18, page 24-2 in a second level 22-2 of the active MPT 18, and so on, up to page 24-7 in a seventh level 22-7 of the active MPT 18). The active MPT 18 includes a base table page address register 26 that includes a physical memory address of the page 24-1 in the first level 22-1 of the active MPT 18. The page 24-1 in the first level 22-1 of the active MPT 18 includes a page table entry (PTE) that includes a physical memory address of the page 24-2 in the second level 22-2 of the active MPT 18. Similarly, page 24-2 in the second level 22-2 of the active MPT 18 includes a PTE that includes the physical memory address of page 24-3 in the third level 22-3 of the active MPT 18, etc. Page 24-7 in the seventh level 22-7 of the active MPT 18 includes a PTE that includes the physical memory address of the memory page 16 allocated to the process associated with the active MPT 18.

[0054] The process associated with active MPT 18 may be any suitable process, such as a software program running on a CPU (which may be part of processor 12 or a separate processor), or a hardware process such as packet processing running in packet processing hardware (not shown) in a network interface controller or switch.

[0055] The processor 12 is configured to implement the functionality of a page provider to generate a mapping to a memory page, and may be implemented using any one or more of the following: firmware, an operating system, and / or any suitable processing circuitry, and the selection may depend on the operating environment. For example, if the process is a software process, the page provider may be implemented using an operating system, and if the process is a hardware process, the page provider may be implemented using firmware or processing circuitry of a hardware processor. In some embodiments, the process and the page provider are executed in the same processing unit (e.g., in the processor 12). In other embodiments, the process and the page provider are executed in different processing units.

[0056] See now Figure 3 , Figure 3 yes Figure 2 Schematic diagram of a portion of an active multi-level page table 18. Figure 3 2. A page 24 in a first level 22-1 and a second level 22-2 of an active MPT 18 is shown. The page 24-1 in the first level 22-1 of the active MPT 18 includes a plurality of page table entries (PTEs) 28. Each PTE 28 includes a physical memory address of a corresponding page 24-2 in the second level 22-2 of the active MPT 18. Each page 24-2 in the second level 22-2 of the active MPT 18 also includes a plurality of PTEs 28, wherein each PTE 28 includes a third level 22-3 ( Figure 2 ), and so on. In this manner, each PTE 28 for each page 24 provides a physical memory address to a corresponding page 24 in the next lower level 22 of the active MPT 18. The PTE 28 for a page 24 in the last level (e.g., level 22-7) of the active MPT 18 includes a physical memory address for memory page 16 ( Figure 2 )'s physical memory address.

[0057] See now Figures 4 to 5 , Figures 4 to 5 yes Figure 2 Schematic representation of an active multi-level page table 18 showing how virtual memory addresses 30 are mapped to physical memory addresses 32. Figure 4 The virtual memory address 30 is shown to include a plurality of portions 34. The base table page address register 26 gives the physical memory address of a page 24-1 in the first level 22-1 of the active MPT 18.

[0058] Then, from the memory 14 ( Figure 1 ) Search page 24-1 and search as follows. Figure 5 As shown, the first portion 34-1 of the virtual memory address 30 ( Figure 4 ) provides an index 36-1 (e.g., 63:57) of a PTE in page 24-1, which includes a physical memory address 38-1 of one of pages 24-2 in the second level 22-2 of the active MPT 18, such as Figure 5 As shown in more detail in .

[0059] Page 24-2 is then retrieved from memory and searched as follows: The second portion 34-2 of the virtual memory address 30 provides an index 36-2 (eg, 56:48) of a PTE in page 24-2, which includes a physical memory address 38-2 of one of pages 24-3 in the third level 22-3 of the active MPT 18, and so on.

[0060] The above operation is repeated for each portion 34 of the virtual memory address 30 of each level 22 in the active MPT 18 until one of the pages 24-7 is found in the last level (level 22-7). The seventh portion 34-7 of the virtual memory address 30 provides an index 36-7 (e.g., 11:0) of a PTE in page 24-7 that includes the physical memory address 32 of one of the memory pages 16. In the manner described above, the virtual memory address 30 is mapped to the physical memory address 32 of one of the memory pages 16.

[0061] Reference now Figure 6 , Figure 6 is used for Figure 1 1 is a schematic representation of a floating MPT 20 in a device 10 of FIG. The floating MPT 20 has substantially the same structure as the active MPT 18. The floating MPT 20 includes a plurality of levels 40. A first level 40-1 of the floating MPT 20 includes a page 42-1 having a PTE 46 including a physical memory address 44 of a page 42-2 in a next lower level 40-2 of the floating MPT 20. The lower level 40 of the floating MPT 20 includes a plurality of pages 42 having physical memory addresses 44 referenced by PTEs 46 included in the pages 42 in a level higher than the level 40.

[0062] Figure 64 shows a portion 50 of the floating MPT 20. The PTE 46-5 in the page 42-5 in the fifth level 40-5 of the floating MPT 20 includes the physical memory address 44-5 of the page 42-6 in the sixth level 40-6 of the floating MPT 20. The page 42-6 includes the PTE 46-6 (only some are labeled for simplicity), which includes the physical memory address 44-6 of the page 42-7 in the seventh level 40-7 (only some are labeled for simplicity). The page 42-7 includes the PTE 46-7 (only one is labeled for simplicity), which includes the physical memory address 44-6 of the page 42-7 stored in the memory 14 ( Figure 1 ) in the physical memory addresses 44-7 of the spare memory pages 52 (only some are marked for simplicity).

[0063] Reference now Figure 7 , Figure 7 is a schematic representation of an active MPT 18 and a floating MPT 20, illustrating contiguousness of at least a portion of the floating MPT 20 with the active MPT 18. The floating MPT 20 or a portion thereof may be contiguous with the active MPT 18 to provide additional virtual memory address to physical memory address mappings to spare memory pages 52 in the active MPT 18. Contiguousness of (a portion of) the floating MPT 20 with the active MPT 18 may be performed by copying one or more PTEs 46 from the floating MPT 20 (e.g., level 40-6 or higher, such as level 40-5) to one of the pages 24 in the same level 22 in the active MPT 18.

[0064] For example, the 256 last-hop (level 40-7) pages 42-7 are referenced in one of the second-to-last-hop (level 40-6) pages 42-6 of the floating MPT 20 (e.g., in the first half or the second half of the second-to-last page 42-6). Therefore, only the 256 PTEs 46-6 are copied from the floating MPT 20 to the 256 PTEs in the page 24 of the same level 22-6 of the active MPT 18 to provide references to the 256 last-hop MPT pages 42-7 of the floating MPT 20 in the active MPT 18, and thereby provide a virtual address to physical address mapping to the 128K spare memory page 52 (or 512MB) in the active MPT 18.

[0065] Similarly, a virtual address to physical address mapping may be provided for 256K spare memory pages 52 (or 1 GB) by copying a single PTE 465 in a level 40-5 higher than the penultimate level 40-6 in the floating MPT 20 to a PTE 28-5 of a page 24-5 in a level 22-5 higher than the penultimate level 22-6 in the active MPT 18. Thus, a virtual address to physical address mapping is provided for 256K spare memory pages 52 (or 1 GB) in the active MPT 18.

[0066] The number of mapped spare memory pages 52 is usually equal to 2 n , where n is an integer and the virtual memory addresses of the spare memory pages 52 mapped in the active MPT 18 are aligned such that the n least significant bits of each virtual memory address are equal to zero.

[0067] Reference now Figure 8 , Figure 8 Yes Figure 1 Flowchart 80 of steps in a method of using the device 10. Also refer to Figure 1 The processor 12 is configured to generate the floating MPT 20 (block 82) and store the floating MPT 20 in the memory 14 (block 84). In some embodiments, the floating MPT 20 has the same number of levels as the active MPT 18. In other embodiments, the floating MPT 20 has a different number of levels than the active MPT 18. The processor 12 is configured to receive a request to add virtual address to physical address mappings for more memory pages in the plurality of memory pages 16 to the active MPT 18 (block 86).

[0068] In response to receiving the request, the processor 12 is configured to contiguously move at least a portion of the floating MPT 20 to the active MPT 18 such that the active MPT 18 is a spare memory page 52 ( Figure 6 ) provides virtual address to physical address mapping (block 88). The processor 12 is configured to add mappings of at least some of the memory pages of the spare memory pages 52 to the active MPT 18 according to the minimum memory size. The minimum memory size is, for example, 512MB or 1GB.

[0069] The processor 12 is configured to store at least one PTE 46 (e.g., Figure 7 PTE 46-5) is added to a given page of the active MPT 18 (e.g., Figure 7 24-5 of the floating MPT 20) to add virtual address to physical address mappings for at least some of the spare memory pages 52 to the active MPT 18 (block 90). The added PTEs provide pages 42 of the floating MPT 20 (e.g., Figure 7 42-6 or 42-7), which includes PTE 46 providing the physical memory addresses of: at least some memory pages of spare memory page 52; or at a lower level 40 of floating MPT 20 (e.g., Figure 7 The processor 12 is configured to remove the PTEs added to the active MPT 18 from the floating MPT 20 and close the gap in the floating MPT 20 created by removing the PTEs from the floating MPT 20 (block 92).

[0070] The processor 12 is configured to traverse the active MPT 18 (now including the contiguous floating MPT 20 (the contiguous portion thereof)) to translate a given virtual memory address into a given physical memory address of a given memory page in the spare memory page 52 (block 94). The given virtual memory address includes a portion (e.g., Figure 4 2. The processor 12 is configured to traverse the active MPT 18 to find a given physical memory address of a given spare memory page 52 based on applying the portion 34 of the given virtual memory address to the corresponding level 22 of the active MPT 18 (block 96). For example, portion 34-1 is applied in page 24-1, portion 34-2 is applied in page 24 of level 22-2, and so on, as described above with reference to FIG. Figure 4 and Figure 5 The processor 12 is configured to follow the physical memory address 38 in the page table entry (PTE) 28 in the corresponding level 22 of the active MPT 18 to find the given physical memory address of the given spare memory page 52 (block 98). The index 36 of the PTE 28 in the corresponding level 22 of the active MPT 18 is indicated by the portion 34 of the given virtual memory address.

[0071] The mapping of the unused memory page may be removed from the active MPT 18 by the processor 12 being configured to remove at least one PTE present in the active MPT 18 to a given page of the floating MPT 20 so as to remove the virtual address to physical address mapping of the unused memory page from the active MPT 18 to the floating MPT 20. Removing the mapping of the unused page from the active MPT 18 is similar to the above-described method with reference to FIG. Figure 8 The described manner of adding a mapping of spare memory pages from the floating MPT 20 to the active MPT 18 is performed.

[0072] In practice, some or all of the functions of processor 12 may be combined in a single physical component, or may alternatively be implemented using multiple physical components. These physical components may include hardwired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of processor 12 may be performed by a programmable processor under the control of suitable software. For example, the software may be downloaded to the device in electronic form over a network. Alternatively, or in addition, the software may be stored in a tangible, non-volatile computer-readable storage medium, such as an optical, magnetic, or electronic memory.

[0073] For the sake of clarity, various features of the invention described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, various features of the invention described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0074] The above embodiments are cited by way of example, and the present invention is not limited by what has been specifically shown and described above. On the contrary, the scope of the present invention includes the combination and sub-combination of the various features described above, as well as changes and modifications thereof that occur to those skilled in the art upon reading the above description and are not disclosed in the prior art.

Claims

1. A processing device comprising: A memory, the memory being used for: storing a plurality of memory pages, the plurality of memory pages having corresponding physical memory addresses in the memory; storing an active multi-level page table MPT, the active multi-level page table mapping virtual memory addresses to physical memory addresses for corresponding allocated memory pages of the plurality of memory pages stored in the memory; as well as storing a floating MPT that at least in part maps virtual memory addresses to physical memory addresses for corresponding spare memory pages of the plurality of memory pages stored in the memory, the floating MPT and the active MPT using a common mapping scheme; as well as A processor, the processor being configured to: receiving a request to add virtual address to physical address mappings for more memory pages of the plurality of memory pages to the active MPT; as well as In response to receiving the request, at least a portion of the floating MPT is contiguous with the active MPT such that the active MPT provides the virtual address to physical address mapping for at least some of the spare memory pages.

2. The apparatus of claim 1, wherein the processor is configured to generate the floating MPT and store the floating MPT in the memory.

3. The apparatus of claim 1 , wherein the processor is configured to add at least one page table entry (PTE) present in the floating MPT to a given page of the active MPT so as to add the virtual address to physical address mapping for the at least some of the spare memory pages to the active MPT.

4. The apparatus of claim 3 , wherein the at least one PTE provides a physical memory address of at least one page in the floating MPT, the providing comprising the PTE providing physical memory addresses of: the at least some of the spare memory pages; or pages in a lower level of the floating MPT.

5. The apparatus of claim 3, wherein the processor is to remove the at least one PTE from the floating MPT.

6. The apparatus of claim 5, wherein the processor is to close a gap in the floating MPT created by removing the at least one PTE from the floating MPT.

7. The apparatus of claim 1, wherein the processor is to traverse the active MPT including at least a portion of a contiguous portion of the floating MPT to convert a given virtual memory address to a given physical memory address of a given memory page of the spare memory pages.

8. The apparatus of claim 7, wherein: The given virtual memory address comprises a plurality of parts; and The processor traverses the active MPT based on applying the portions of the given virtual memory address to corresponding stages of the active MPT to find the given physical memory address of a given spare memory page.

9. The apparatus of claim 8, wherein: The processor is configured to follow a physical memory address in a page table entry PTE in a corresponding level of the active MPT to find the given physical memory address of the given spare memory page; An index to the PTE in a corresponding level of the active MPT is indicated by the multiple portions of the given virtual memory address.

10. The apparatus of claim 1, wherein the active MPT and the floating MPT are tree data structures.

11. The apparatus of claim 1, wherein: The number of the at least some of the mapped spare memory pages is equal to 2 to the power of n, where n is an integer; And the virtual memory addresses of the at least some memory pages mapped in the active MPT are aligned such that n least significant bits of each of the virtual memory addresses are equal to zero.

12. The apparatus of claim 1, wherein the processor is to add mappings of the at least some of the spare memory pages to the active MPT according to a minimum memory size.

13. The apparatus of claim 1, wherein the processor is to remove at least one page table entry (PTE) present in the active MPT to a given page of the floating MPT so as to remove virtual address to physical address mappings for unused memory pages from the active MPT to the floating MPT.

14. A method comprising: storing a plurality of memory pages, the plurality of memory pages having corresponding physical memory addresses in the memory; storing an active multi-level page table MPT, the active multi-level page table MPT mapping virtual memory addresses to physical memory addresses for corresponding allocated memory pages of the plurality of memory pages stored in the memory; as well as storing a floating MPT that at least in part maps virtual memory addresses to physical memory addresses for corresponding spare memory pages of the plurality of memory pages stored in the memory, the floating MPT and the active MPT using a common mapping scheme; as well as receiving a request to add virtual address to physical address mappings for more memory pages of the plurality of memory pages to the active MPT; as well as In response to receiving the request, at least a portion of the floating MPT is contiguous with the active MPT such that the active MPT provides the virtual address to physical address mapping for at least some of the spare memory pages.

15. The method according to claim 14, further comprising: The floating MPT is generated.

16. The method according to claim 14, further comprising: At least one page table entry (PTE) present in the floating MPT is added to a given page of the active MPT so as to add the virtual address to physical address mappings for the at least some of the spare memory pages to the active MPT.

17. The method of claim 16, wherein the at least one PTE provides a physical memory address of at least one page of the floating MPT, the providing comprising the PTE providing physical memory addresses of: the at least some of the spare memory pages; or pages in a lower level of the floating MPT.

18. The method according to claim 16, further comprising: The at least one PTE is removed from the floating MPT.

19. The method according to claim 18, further comprising: A gap in the floating MPT created by removing the at least one PTE from the floating MPT is closed.

20. The method of claim 14, further comprising: The active MPT including at least a portion of a contiguous portion of the floating MPT is traversed to translate a given virtual memory address into a given physical memory address of a given memory page of the spare memory pages.

21. The method of claim 20, wherein: The given virtual memory address comprises a plurality of parts; and The traversing includes traversing the active MPT based on applying the portions of the given virtual memory address to corresponding stages of the active MPT to find the given physical memory address of a given spare memory page.

22. The method according to claim 21, further comprising: A physical memory address in a page table entry PTE in a corresponding level of the active MPT is followed to find the given physical memory address of the given spare memory page, wherein an index to the PTE in the corresponding level of the active MPT is indicated by the multiple portions of the given virtual memory address.

23. The method of claim 14, wherein the active MPT and the floating MPT are tree data structures.

24. A method according to claim 14, wherein the number of at least some of the mapped spare memory pages is equal to 2 to the power of n, where n is an integer; and the virtual memory addresses of at least some of the memory pages mapped in the active MPT are aligned so that the n least significant bits of each of the virtual memory addresses are equal to 0.

25. The method of claim 14, further comprising: Mappings of the at least some of the spare memory pages are added to the active MPT according to a minimum memory size.

26. The method of claim 14, further comprising: At least one page table entry (PTE) present in the active MPT is removed to a given page of the floating MPT so as to remove virtual address to physical address mappings for unused memory pages from the active MPT to the floating MPT.

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