System communication techniques via PCIe (High Speed Serial Computer Extension Bus) linking

Abstract

Examples relate to apparatuses, devices, methods, and computer programs for root complexes (RCs) and / or endpoints (EPs) for PCIe (High Speed Serial Computer Extension Bus) systems, to PCIe systems, and to gateway devices including PCIe systems. In one embodiment, a device configured for an RC of a PCIe system includes a memory and one or more processors configured to generate a PCIe VDM (Vendor Definition Message) message for an EP of the PCIe system.

Description

[0001] Divisional application

[0002] This application is a divisional application of the prior Chinese application with application number 202080040256.9. The name of the invention of the prior Chinese application is "System communication technology linked via PCIe (high-speed serial computer expansion bus)" and the application date is March 27, 2020. Technical Field

[0003] The present disclosure relates to improvements in PCIe (Peripheral Component Interconnect express) messaging, and more particularly to the use of VDM (Vendor Defined Message) messaging to facilitate bidirectional messaging between subsystems of a WAN (Wide Area Network). Background Art

[0004] PCIe is a communication standard used to provide communication between devices of a computer system, such as between devices of a personal computer system, or between devices of an embedded system (such as a gateway device). For example, in a gateway device, PCIe can be used to provide communication between a network processing SoC (System on Chip) and a WAN (Wide Area Network) technology front-end SoC. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Some examples of apparatus and / or methods will be described below by way of example only and with reference to the accompanying drawings, in which:

[0006] Figure 1a to Figure 1c A block diagram showing an example of devices configured for a root complex (RC) of a PCIe (PCIe Express) system;

[0007] Figure 1d A flowchart showing an example of a method for RC of a PCIe system;

[0008] Figure 1e A block diagram showing an example of a gateway device;

[0009] Figure 2a to Figure 2c A block diagram showing an example of a device configured for an endpoint (EP) of a PCIe system;

[0010] Figure 2d A flowchart showing an example of a method for an EP of a PCIe system;

[0011] Figure 3A schematic diagram is shown showing hardware blocks and related signaling for enhanced VDM (Vendor Defined Message) messaging;

[0012] Figure 4a A schematic diagram showing an example of a header for a VDM message; and

[0013] Figure 4b A table showing events and messages that may be communicated via enhanced VDM messaging. DETAILED DESCRIPTION

[0014] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are shown. In the drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity purposes.

[0015] Therefore, although other examples can have various modifications and alternative forms, some specific examples thereof are shown in the figures and will be described in detail later. However, this detailed description does not limit other examples to the described specific forms. Other examples may encompass all modifications, equivalents, and alternative forms that fall within the scope of the present disclosure. Throughout the description of the drawings, the same or similar numbers refer to similar or similar elements; when compared to each other, these elements may be implemented equivalently or in modified form while providing the same or similar functions.

[0016] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the elements may be directly connected or may be coupled via one or more intervening elements. If two elements A and B are combined using "or", then, if not otherwise explicitly or implicitly defined, such wording should be understood to disclose all possible combinations, i.e., only A, only B, and A and B. Alternative wording for the same combination is "at least one of A and B" or "A and / or B". Such wording applies mutatis mutandis to combinations of more than two elements.

[0017] For the purpose of describing a specific example, the terms used herein are not intended to be restrictive for other examples. Whenever a singular form such as "one", "a kind of" and "the" is used, and only a single element is not explicitly or implicitly defined as mandatory, other examples may also use plural elements to implement the same function. Similarly, when the function is subsequently described as being implemented using multiple elements, other examples may implement the same function using a single element or processing entity. It should also be understood that the terms "include", "comprise", "contain", and / or "have" specify the presence of the features, whole pieces, steps, operations, processes, actions, elements and / or parts when used, but do not exclude the presence or addition of one or more other features, whole pieces, steps, operations, processes, actions, elements, parts and / or any groups thereof.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) are used herein according to their common meaning in the art to which examples belong.

[0019] AnyWAN system architecture is becoming more and more popular and accepted in the telecommunications industry for the latest generation of home gateway solutions. The two subsystems of this architecture are networking processing SoC (system-on-chip) and WAN (wide area network) technology front-end SoC. Industry-standard protocols (such as PCIe links) can be used to interconnect two SoC subsystems. In many cases, data path performance and efficiency are well solved via this standard link. However, challenges may be faced regarding non-data system communications, because standard links do not include a two-way communication mechanism via messages or signaling, and two SoC subsystems run simultaneously without any appliances to notify each other of key system events. In addition, as discussed in more detail below, the examples and techniques discussed herein can be used in other systems and devices that employ the PCIe system architecture.

[0020] Various examples discussed herein may create and / or employ a bidirectional communication mechanism of in-band messaging to address various system communication targets, such as reporting of a local system about to reset, power outage, highly unstable WAN speeds and / or lost link, etc. In various examples, due to the timely communication of subsystem status between subsystems, sideband signals via standard connections (such as PCIe (PCIe Express)) may be omitted and system robustness may be greatly improved.

[0021] In existing systems, all standard-based PCIe messaging is in-band; however, the standard-defined in-band messaging protocol is limited in the directions in which various messaging can be sent, such as: (1) Interrupt message: only from EP (endpoint) to RC (root complex); (2) Error report message: only from EP to RC; (3) VDM (vendor defined message): only from EP to RC (wherein the format and content of the payload are undefined in existing systems). Each of these three messages (and others) is one-way messaging and has a limited scope of application.

[0022] Various examples discussed herein may employ in-band VDM with an extended range of applications, which may define content formats to address bidirectional communications. For EP to RC, the examples discussed herein may employ message formats created for VDM, and VDM usage may be extended. In addition, for RC to EP, the examples discussed herein may employ message formats created for VDM, and one (or more) applications on the VDM mechanism may be added.

[0023] In the PCIe base specification, Vendor Defined Messages (VDMs) are optional features that can be used for system communication via a PCIe link. However, the message format, usage, and generation mechanism are not defined in the PCIe specification.

[0024] Various examples discussed herein may employ VDMs that extend the prior art by defining a system communication message format and enabling bidirectional messaging over a PCIe link to efficiently transmit system event information.

[0025] With the extended VDM definition employed by various instances, there is a defined in-band message format that can be used (e.g., sent or received, depending on the subsystem / instance) to notify other subsystems of the PCIe link in a timely manner, so each subsystem (e.g., EP or RC) can handle events such as system reset, power failure, link loss, etc. in a managed manner. In contrast, in existing systems that do not employ the techniques discussed herein, neither subsystem is aware of such system events, or must employ sideband signaling to communicate (however, in a socket and add-in card system configuration, such sideband signaling is not possible).

[0026] Figure 1a to Figure 1c A block diagram of an example of a device 10 configured for a root complex (RC) 100 of a PCIe (PCIe Express) system 1000 is shown. Figure 1a to Figure 1c Also shown is a block diagram of an example of an apparatus 10 configured for use with the RC 100 of the PCIe system 1000. The components of the apparatus 10 are defined as component implements, which correspond to the respective structural components of the device 10. Figure 1a to Figure 1c Also shown is an RC 100 including a corresponding device 10. The device 10 includes a memory 12 (i.e., memory means) and one or more processors 14 (i.e., processing means). Optionally, the device 10 also includes an interface 16 (i.e., communication means), for example, an interface for communicating with the RC and / or for communicating with the EP via the RC. The one or more processors are connected to the memory 12 and / or the interface 16. Figure 1a to Figure 1cA PCIe system including an RC 100 (having a device 10) and an EP 100 is also shown. For example, the PCIe system may be a PCIe system of a gateway device, such as a modem or a router, for example, an xDSL (x Digital Subscriber Line, where x represents different DSL standards or implementations) modem or router, an xPON (x Passive Optical Network, where x represents different PON standards or implementations), a cable modem or router, a DOCSIS (Data Over Cable Service Interface Specification, a cable communication standard) modem or router, etc. The example also provides a gateway device including an RC (having a device 10) and one or more EPs (for example, having a device 20, such as a combination thereof). Figure 2a to Figure 2c The gateway device may also include a network processor and / or a video processor, which may be linked to the EP via the RC and the PCIe system, thereby providing a communication path.

[0027] Various examples of the present disclosure relate to a root complex (RC) of a PCIe system, and to one or more endpoints (EP) connected to the RC. Generally speaking, the root complex of a PCIe system connects a processor and a memory subsystem of a computer system (e.g., an embedded computer system such as a gateway) to one or more PCIe endpoints (e.g., via one or more PCIe switches). In addition, PCIe endpoints may be connected to each other via the root complex. In the PCIe specification (e.g., PCIe specification 3.0 and later specifications), the concept of vendor-defined messages is introduced, which may be used by endpoints in other systems only to transmit messages to the root complex. However, the PCIe VDM messages defined by PCIe 3.0 and later specifications do not support the reverse direction. By extending the message format to support message delivery from the RC to one or more EPs of the PCIe system, the examples of the present disclosure extend the versatility of the PCIe VDM messages.

[0028] Figure 1a An example of a device configured for RC of the PCIe system 1000 is shown. Figure 1a The one or more processors 14 of the device 10 are configured to generate a PCIe VDM message for the EP endpoint 200 of the PCIe system. The one or more processors may be configured to transmit the generated PCIe VDM message to the EP, for example, via the RC and / or the PCIe system.

[0029] Previously (as defined in, for example, the PCIe 3.0 standard), VDMs were (only) generated by EPs for communication from EPs to RCs. However, in examples, VDMs may also be generated by RCs, for example, to convey information about the state of the RC, or to trigger an interrupt at the corresponding EP. For example, a PCIe VDM message may maintain the header format defined by the PCIe specification ( Figure 4a ), and the fourth byte group (bytes 12 to 15) is used for the message content exchanged between the RC and the EP (see Figure 4a to Figure 4b ). For example, some bit fields of the vendor-defined portion of the header may be used only by the RC or the EP, and / or some bit fields of the vendor-defined portion of the header may be used only by both the RC and the EP.

[0030] For example, a PCIe VDM message may include an interrupt trigger of an EP of a PCIe system. Generally speaking, an interrupt trigger is information that causes the receiver of an interrupt to trigger an interrupt, that is, a context switch of the processor of the receiver to a context for handling interrupts. For example, an interrupt is generally used to notify the receiver of the arrival of a message, so as to cause the receiver to receive or read the message from a buffer. For example, Figure 4b As shown, in bits [31:28] of the fourth byte group, the RC to EP interrupt encoding may be included in the PCIe VDM message. For example, the EP's interrupt trigger may be suitable for notifying the EP (e.g., the EP's system-on-chip (SoC)) of the arrival of the message. In some examples, one or more processors may be configured to generate an interrupt trigger for the EP, for example, based on the state of the RC.

[0031] Alternatively or additionally, the PCIe VDM message may be used to notify the EP of an error present at the RC. For example, when an error exists at the RC, the EP may suspend the transmission of data to the RC until the error is resolved (e.g., by a reset of the RC). Thus, the PCIe VDM message may include information about the error at the RC. For example, Figure 4b As shown, in bits [27:24] of the fourth byte group, the RC to EP error encoding may be included in the PCIe VDM message. For example, the error at the RC may optionally include a power-off alarm indication, i.e., the last message transmitted by the RC before the RC was shut down or reset. Such a "power-off alarm" indication may indicate a serious error at the RC that can only be repaired by resetting the RC. Thus, the PCIe VDM message may include an indication of a serious error at the RC of the PCIe system.

[0032] In some instances, a PCIe VDM message may include information about a reset state at the RC. For example, the reset state at the RC may generally reflect a reset state of the RC or one or more components of the PCIe system. For example, the reset state may indicate whether (for example) a buffer manager, a central queue manager, a packet processor, and / or a host of a PCIe system or a root complex is in a reset state (or not in a reset state). For example, a PCIe VDM message may include a notification that the RC of the PCIe system is being reset. For example, each of the different components named above may be represented by an information bit about the reset state, wherein 1 (or 0) indicates that the corresponding component is in a reset state, and wherein 0 (or 1) indicates that the corresponding component is not in a reset state. Thus, if Figure 4b As shown, in bit [7:0] of the fourth byte group, a reset communication may be included, which may include the RC side reset state at bit [7:4]: BM (Buffer Manage, Buffer Manager) / CQM (Central Queue Manage, Central Queue Manager) / PP (Packet Processor, Packet Processor) / Host in reset. In various embodiments, one or more processors may be configured to determine the reset state at the RC, for example by processing the reset state of one or more components.

[0033] Another type of status information that may be of interest (e.g., in a gateway device) may be the status of one or more networking subsystems and, therefore, data paths that are connected to the PCIe system. Thus, a PCIe VDM message may include information about the status of at least one data path. For example, at least one data path may involve at least one networking technology that is supported by a gateway device that includes a PCIe system, such as at least one network technology accessible via the PCIe system. For example, Figure 4b As further shown, in bits [15:12] of the fourth byte group, RC-side status encoding may be included, which may relate to the status of a data path known to the RC. For example, information about the status of at least one data path may include information about at least one of the following items: a LAN (local area network) data path of the gateway device, a WiFi (wireless fidelity) / WLAN (wireless local area network) data path of the gateway device, a voice port of the gateway device, and a video port of the gateway device. Similarly, each data path of the gateway device may use one bit to represent information about the status of at least one data path.

[0034] Another type of status information that may be of interest (e.g., in a gateway device) may be buffer status, such as the buffer status of a TX (Transmitter) buffer and / or a RX (Receive) buffer of a RC (or a corresponding EP). For example, a PCIe VDM message may include information about buffer status, such as the buffer status of a RX and / or TX buffer of a RC, and / or the buffer status of a RX and / or TX buffer of a gateway device (e.g., a processor, such as a network processor or a video processor of the gateway device). For example, if Figure 4b As further shown, in bits [23:16] of the fourth byte group, the PCIe VDM message may include a buffer status, which may include, for example, a Tx buffer status level at bit 16, a Tx buffer exceeded threshold at bit 17, an Rx buffer status level at bit 18, an Rx buffer exceeded threshold at bit 19, and a descriptor of the buffer status at bits [23:20]. For example, information about the buffer status may indicate whether the TX and / or RX buffers of the RC or gateway device are above an upper buffer threshold (i.e., too full), or below a lower buffer threshold (i.e., too empty). The EP may adjust its data transmission accordingly, for example, to avoid over-utilizing or under-utilizing the buffers of the RC or gateway device.

[0035] In some instances, the RC may be capable of not only generating VDM messages, but also forwarding messages received from the EP. Thus, one or more processors may be configured to process (e.g., receive and process) a PCIe VDM message from another EP of the PCIe system (e.g., not the EP for which the PCIe VDM message generated by the RC is intended), or a PCIe VDM message from the EP for which the DM message generated by the RC is intended. One or more processors may be configured to forward (e.g., hand over) a PCIe VDM message received from another EP to the EP (or another EP). Thus, the PCIe VDM message received from another EP may include an identifier of the EP (or another EP) as a target identifier, and the one or more processors may be configured to forward or hand over the PCIe VDM message to the EP or another EP based on the target identifier. If the PCIe VDM message is intended for the RC (as a target), the PCIe VDM message may include an identifier of the RC as a target identifier.

[0036] The interface 16 may correspond to one or more inputs and / or outputs for receiving and / or transmitting information, which may be a digital (bit) value within a module, between modules, or between modules of different entities according to a specified code. For example, the interface 16 may include an interface circuit configured to receive and / or transmit information. In an example, one or more processors 14 may be implemented using one or more processing units, one or more processing devices, any apparatus for processing (such as a processor, a computer, or a programmable hardware component operating with corresponding adaptation software). In other words, the described functions of one or more processors 14 may also be implemented in software, which is then executed on one or more programmable hardware components. Such hardware components may include a general-purpose processor, a digital signal processor (DSP), a microcontroller, etc. For example, the memory 12 may include a machine-readable and writable memory, such as a volatile memory (such as a random access memory (RAM) or a volatile memory register), or a non-volatile memory (such as a flash memory).

[0037] More details and aspects of the device, EP, RC, PCIe system and / or gateway device will be combined with the concepts or one or more examples described above or below (for example, Figure 1a , Figure 1c to Figure 4b ) are mentioned. The device, EP, RC, PCIe system and / or gateway device may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0038] Figure 1b Another example of a device configured for RC of PCIe system 1000 is shown. Figure 1b The one or more processors 14 of the device 10 are configured to process the PCIe VDM message of the EP 200 of the PCIe system. Figure 1a As described above, the RC (or one or more processors of the device 10 of the RC) may be configured to receive a PCIe VDM message from an EP and forward it to another EP. Figure 1b In the example shown, one or more processors may also be configured to process the received EP for use at the RC. For example, some status information that may be communicated from the RC to the EP may also be communicated from the EP to the RC. For example, the PCIe VDM message may include at least one of a data path state at the EP, a reset state at the EP, and a buffer state at the EP. For example, the data path state at the EP, the reset state at the EP, and the buffer state at the EP may be implemented similarly to the data path state at the RC or gateway device, the reset state at the RC or gateway device, and the buffer state at the RC or gateway device.

[0039] For example, the data path state at the EP may indicate the state of the data path provided by the EP. For example, if the PCIe system is a PCIe system of a gateway device, the EP may be an EP for providing a data path to the gateway device. For example, the EP may be one of an EP for providing WiFi / WLAN functions, an EP for providing LAN functions, and an EP for providing WAN functions. Therefore, the data path state at the EP may indicate the state of the data path provided by the EP, such as a link state (indicating whether a link (on the data path) is available), a link table state (indicating whether a link is stable), and / or a link speed encoding (indicating a link speed provided by a link).

[0040] As previously noted, the data path state of the EP may indicate the state of the data path provided by the EP. For example, one of the data paths provided by the EP may be a WAN data path. Thus, the data path state of the EP may include information about the WAN data path, such as a link speed of the WAN data path. In some instances, when the WAN data path has a low link speed (e.g., a link speed below a threshold), the RC may adjust its behavior. For example, a PCIe VDM message may include an indication that the WAN link (provided by the EP) is slower than a threshold rate. In this case, the RC may adjust the data throughput for the EP to avoid over-utilization of the WAN link provided by the EP. For example, one or more processors may also be configured to reduce the data path throughput of the EP based on an indication that the WAN link is slower than a threshold rate. For example, the threshold rate may be dynamic and may be updated by the corresponding EP. For example, the threshold may be a percentage of the average data rate of the WAN link, for example, 80% of the average data rate of the WAN link.

[0041] To further save energy at the RC, one or more processors may be configured to reduce the virtual functions of the SoC of the RC. In other words, the one or more processors may also be configured to reduce the virtual functions based on an indication that the WAN link is slower than a threshold rate. In a PCIe system, there are two types of functions: a physical function, which has full access to the PCIe system and its configuration; and a virtual function, which is typically based on an underlying physical function and typically has (only) the ability to transmit data via the PCIe system or receive data via the PCIe system. By reducing the virtual function, its data throughput can be capped (e.g., according to the rate supported by the WAN link).

[0042] The reset state at the EP may indicate the reset state of one or more components of the EP. For example, the reset state at the EP may indicate the reset state of one or more of the following components of the EP: a DMA (Direct Memory Access) component, a Media Access Control (MAC) (Digital Front End, DFE) component of a digital front end, an Analog Front End (AFE) component, and a Line Driver (LD) component.

[0043] The buffer status at the EP may indicate the status of the RX buffer and / or TX buffer of the EP. For example, the buffer status at the EP may indicate whether the RX buffer and / or TX buffer of the EP is underutilized or overutilized (or in between). As previously described in conjunction with the buffer status at the RC and Figure 4b As shown, in bits [23:16] of the fourth byte group, the PCIe VDM message may include a buffer status, which may include, for example, a Tx buffer status level at bit 16, a Tx buffer exceed threshold at bit 17, an Rx buffer status level at bit 18, an Rx buffer exceed threshold at bit 19, and a descriptor of the buffer status at bits [23:20].

[0044] More details and aspects of the device, EP, RC, PCIe system and / or gateway device will be combined with the concepts or one or more examples described above or below (for example, Figure 1a , Figure 1c to Figure 4b ) are mentioned. The device, EP, RC, PCIe system and / or gateway device may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0045] Figure 1c Another example of an apparatus for configuring RC 100 for use in PCIe system 1000 is shown. For example, the processing circuit may be configured to Figure 1a and Figure 1b In other words, Figure 1c The equipment can be combined Figure 1a and Figure 1b Functions of the device shown.

[0046] More details and aspects of the device, EP, RC, PCIe system and / or gateway device will be combined with the concepts or one or more examples described above or below (for example, Figure 1a to Figure 1b , Figure 1d to Figure 4b) are mentioned. The device, EP, RC, PCIe system and / or gateway device may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0047] Figure 1d FIG. 1 is a flow chart showing an example method of the RC 100 of the PCIe system 1000. Figure 1d In, various features of the method are shown, which may correspond to Figure 1a to Figure 1c Therefore, according to the characteristics of the device instance Figure 1a to Figure 1c A subset of features implemented by a device of a PCIe system, a subset of features shown below may be part of the method. The method may include generating 110 a PCIe VDM message for an EP 200 of a PCIe system. The method may include processing 120 a PCIe VDM message from an EP 200 of a PCIe system, such as from the same EP or another EP. For example, if a VDM is received from another EP, the VDM may be received via an interconnect structure and another RC, the other RC being associated with another EP. The method may include forwarding 125 a PCIe VDM message received from another EP to the EP. The method may include reducing 130 a data path throughput of the EP based on an indication that a WAN link is slower than a threshold rate. The method may include scaling back 140 a virtual function based on an indication that a WAN link is slower than a threshold rate.

[0048] More details and aspects of the method will be combined with the concepts or one or more examples described above or below (e.g., Figure 1a to Figure 1c , Figure 1e to Figure 4b ) is mentioned. The method may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0049] Figure 1eA block diagram of an example of a gateway device 1100 is shown, including a PCIe system (having three RCs 100, RC0, RC1, and RC2 (each including a device 10), which are connected via an interconnection structure; and one or more EPs 200 (e.g., having a device 20)). For example, the gateway device may be a modem or a router, such as an xDSL (x Digital Subscriber Line, where x represents different DSL standards or implementations) modem or router, xPON (x Passive Optical Network, where x represents different PON standards or implementations), a cable modem or router, a DOCSIS (Data Over Cable Service Interface Specification, a cable communication standard) modem or router, etc. The gateway device may also include a network processor 1200, a video processor 1300, and / or a memory 1400, which may be linked to the EPs via the interconnection structure and the RCs of the PCIe system 1000, thereby providing a communication path (in Figure 1e in the example: WiFi, LAN and WAN, but other combinations are also possible).

[0050] More details and aspects of the gateway device will be combined with the concepts or one or more examples described above or below (for example, Figure 1a to Figure 1d , Figures 2a to 4b The gateway device may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0051] Figure 2a to Figure 2c A block diagram of an example of a device 20 configured for (ie, suitable for, or configured to provide functionality to) an endpoint EP 200 of a PCIe system 1000 is shown. Figure 2a to Figure 2c An EP 200 including a corresponding device 20 is also shown. Figure 1a to Figure 1c Also shown is a block diagram of an instance of an apparatus 20 configured for an EP 200 of a PCIe system 1000. The components of the apparatus 20 are defined as component devices, which correspond to the corresponding structural components of the device 20. The device 20 includes a memory 22 (i.e., a memory device) and one or more processors 24 (i.e., a processing device). Optionally, the device 10 also includes an interface 12 (i.e., a communication device), for example, an interface for communicating with the EP and / or for communicating with the RC via the EP. One or more processors are connected to the memory 22 and / or the interface 26. The functions provided by the instance of the device may be different. Figure 2a to Figure 2c Also shown is a PCIe system including RC 100 and EP 200 (with device 20).

[0052] Combination Figure 1a to Figure 1d The examples shown primarily involve RC and its interaction with one or more EPs, while Figure 2a to Figure 2dThe example shown involves an EP and involves an apparatus that provides PCIe VDM message processing functionality to the EP. A gateway device may include one or more of such EPs with corresponding apparatus 20.

[0053] Figure 2a An example of a device configured for the endpoint EP 200 of the PCIe system 1000 is shown. Figure 2a The one or more processors of the device are configured to process PCIe VDM messages from the RC root complex 100 of the PCIe system. For example, the PCIe VDM message may be similar to the one combined with Figure 1a to Figure 1c The PCIe VDM message generated by the device 10 described above is implemented by the PCIe VDM message. In other words, the PCIe VDM message processed by the EP / device 20 may be generated by the RC. Alternatively, the PCIe VDM message processed by the EP / device 20 may be generated by another EP and forwarded by one or more RCs arranged between the EPs. In other words, the PCIe VDM message may be a PCIe VDM message from another EP forwarded by the RC.

[0054] For example, if combined Figure 1a As shown, a PCIe VDM message may include an interrupt trigger of an EP of a PCIe system. Generally speaking, an interrupt trigger is information that causes the receiver of the interrupt to trigger an interrupt, that is, the context of the receiver's processor switches to a context for manipulating the interrupt. For example, an interrupt is typically used to notify the receiver of the arrival of a message to cause the receiver to receive or read the message from a buffer. However, other interrupts may also be used, such as an interrupt that notifies the EP to retrieve an updated version of a configuration or to change the energy-saving settings of the corresponding EP. One or more processors may also be configured to manipulate related interrupts based on the interrupt trigger. For example, one or more processors may be configured to manipulate the interrupt itself, or to provide the interrupt to the processor / SoC of the EP.

[0055] In various examples, the PCIe VDM message may include information about the reset state at the RC. For example, the PCIe VDM message may include a notification that the RC is being reset. In this case, the EP may take steps to mitigate the reset of the RC. For example, the one or more processors may also be configured to clear pending packets in an internal FIFO (first-in-first-out buffer) of the EP of the PCIe system in response to the notification that the RC is being reset because communication via the PCIe system may be temporarily unavailable. After the reset state at the RC indicates that the RC is being reset, communication with the RC may be reinitiated.

[0056] Resetting the RC typically takes precedence over errors at the RC, e.g., errors that can be mitigated (only) by resetting the RC. For example, a PCIe VDM message may include information about errors at the RC. This information about errors at the RC may be used to prepare the EP for an upcoming reset of the EC. For example, a PCIe VDM message may include an indication of a severe error at the RC of the PCIe system (i.e., a "power-off alarm" for the RC). In this case, the EP has two options: the PCIe subsystem of the EP (which may be implemented by device 20) may be reset, or the entire EP may be reset. Therefore, one or more processors may also be configured to make a determination whether to perform a (EP) full system reset or a PCIe module reset (e.g., a PCIe module of the EP) based at least in part on the indication of a severe error. For example, depending on the type of error indicated by the information about the error at the RC, a full system reset or a PCIe module reset may be performed.

[0057] In various examples, the PCIe VDM message includes information about the state of a data path, such as a data path provided by another (or incidentally, the same) EP of the PCIe system. The PCIe VDM message may also include information about the state of a buffer at the RC or at a gateway device (e.g., a network processor of the gateway device).

[0058] The interface 26 may correspond to one or more inputs and / or outputs for receiving and / or transmitting information, which may be a digital (bit) value within a module, between modules, or between modules of different entities according to a specified code. For example, the interface 26 may include an interface circuit configured to receive and / or transmit information. In an example, one or more processors 24 may be implemented using one or more processing units, one or more processing devices, any apparatus for processing (such as a processor, a computer, or a programmable hardware component operating with corresponding adaptation software). In other words, the described functions of one or more processors 24 may also be implemented in software, which is then executed on one or more programmable hardware components. Such hardware components may include a general-purpose processor, a digital signal processor (DSP), a microcontroller, etc. For example, the memory 22 may include a machine-readable and writable memory, such as a volatile memory (such as a random access memory (RAM) or a volatile memory register) or a non-volatile memory (such as a flash memory).

[0059] More details and aspects of the device, EP, PCIe system and / or gateway device will be combined with the concepts or one or more examples described above or below (for example, Figures 1a to 1e , Figures 2b to 4b ) is mentioned. The method may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0060] Figure 2b Another example of a device configured for the endpoint EP 200 of the PCIe system 1000 is shown. Figure 2a The one or more processors of the device are configured to generate a PCIe VDM message for the RC root complex of the PCIe system. For example, the PCIe VDM message generated by the one or more processors may be a PCIe VDM message generated by the one or more processors. Figure 1a to Figure 1c PCIe VDM messages processed by one or more processors of device 10.

[0061] For example, the PCIe VDM message includes at least one of the data path state at the EP, the reset state at the EP, and the buffer state at the EP. Therefore, the one or more processors may be configured to determine at least one of the data path state at the EP (i.e., its), the reset state at the EP (i.e., its), and the buffer state at the EP (i.e., its). For example, the one or more processors may obtain information about at least one of the data path state at the EP (i.e., its), the reset state at the EP (i.e., its), and the buffer state at the EP (i.e., its) from the processor / SoC of the EP, and may determine at least one of the data path state at the EP (i.e., its), the reset state at the EP (i.e., its), and the buffer state at the EP (i.e., its) based on the information obtained from the processor or SoC of the EP.

[0062] In some examples, the EP may be configured to provide a WAN data path for the gateway device. The PCIe VDM message may include an indication that the WAN link is slower than a threshold rate (or whether it is). Therefore, the one or more processors may be configured to determine whether the WAN link is slower than a threshold rate (or whether it is), and configured to include corresponding information in the PCIe VDM message. For example, the one or more processors may also be configured to set the threshold rate, for example, as a percentage of the average data rate of the WAN link, such as 60% or 80% of the average data rate of the WAN link.

[0063] More details and aspects of the device, EP, PCIe system and / or gateway device will be combined with the concepts or one or more examples described above or below (for example, Figures 1a to 2a , Figure 2c to Figure 4b ) is mentioned. The method may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0064] Figure 2c Another example of a device configured for use in the endpoint EP 200 of the PCIe system 1000 is shown. For example, the processing circuit may be configured to Figure 2a and Figure 2b In other words, Figure 2cThe equipment can be combined Figure 2a and Figure 2b Functions of the device shown.

[0065] More details and aspects of the device, EP, PCIe system and / or gateway device will be combined with the concepts or one or more examples described above or below (for example, Figures 1a to 2b , Figure 2d to Figure 4b ) is mentioned. The method may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0066] Figure 2d FIG. 1 is a block diagram showing an example of a method for endpoint EP 200 of PCIe system 1000. Figure 2d In the figure, various features of the method are shown, which may correspond to Figure 2a to Figure 2c Therefore, according to the characteristics of the device instance Figure 2a to Figure 2c The method may include processing 210 a PCIe VDM message for an RC 100 of a PCIe system. The method may include manipulating 220 a related interrupt based on an interrupt trigger. The method may include clearing 230 pending packets in an internal FIFO of an EP of the PCIe system in response to a notification that the RC is being reset. The method may include making a determination 240 whether to perform a full system reset or perform a PCIe module reset based at least in part on an indication of a severe error. The method may include generating 250 a PCIe VDM message for an RC of the PCIe system.

[0067] More details and aspects of the method will be combined with the concepts or one or more examples described above or below (e.g., Figures 1a to 2c , Figures 3 to 4b ) is mentioned. The method may include one or more additional optional features corresponding to one or more aspects of the concepts or one or more examples described above or below.

[0068] refer to Figure 3 , Figure 3 In accordance with various aspects discussed herein is a schematic diagram illustrating hardware blocks and related signaling for enhanced VDM messaging. Figure 3 Root complex and endpoint hardware interactions regarding enhanced VDM signaling may be illustrated according to various examples.

[0069] exist Figure 3, the unshaded boxes (boxes 330, 340, 350, 360, 370, parts of boxes 365 and 380) and most of the paths with less dense dashed line style (direction EP to RC) indicate the signaling path used by the existing system with PCIe interconnect: one (or more) EP devices 350 send a message or message encoding interrupt to RC 340, RC receives the notification and retrieves the message or manipulates the interrupt. Some parts of the paths with less dense dashed line style indicate extensions or modifications of the present message transmission path based on aspects of various examples discussed herein.

[0070] exist Figure 3 In the figure, the boxes with hatching (boxes 310, 320, 335, parts of boxes 365 and 380) and the paths with denser dashed line patterns (direction RC to EP) indicate the added functionality adopted by the various examples discussed herein. These aspects can be added in various examples to achieve symmetric communication by allowing the RC to send messages and interrupts to the EP side. These added functions may include, but are not limited to, RC-SoC event / status feed 310, which can be used to generate VDM messages 335, which can be sent from RC to EP via RC application logic 330, RC 340, EP 350, and sent to EP-SoC ICU (Interrupt Control Uni) 370 via EP application logic 360. Furthermore, the functionality related to VDM messaging may be extended at the EP side to facilitate VDM messaging 365 based on EP-SoC event / status feed 380 sent from EP to RC via EP application logic 360, EP 350, RC 340, and RC application logic 330 to RC-SoC ICU 320. For example, the apparatus 10 of FIGS. 1a to 1c may implement one or more of blocks 310, 320, 330, and 335. Figure 2a to Figure 2c Device 20 may implement one or more of blocks 360 , 365 , 370 , and 380 .

[0071] refer to Figure 4a and Figure 4b , Figure 4a and Figure 4b Example message formats and system event definitions are shown that may be used for bidirectional messaging via enhanced VDM messaging in a PCIe system in accordance with various aspects discussed herein. Figure 4a A schematic diagram showing an example of a header of a VDM message, as specified by the PCIe 3.0 specification. Figure 4aA possible example header of a VDM message is shown, which may be employed by various examples discussed herein. In various examples, additional or alternative information may be communicated via the VDM message header. For example, the header may be implemented similarly to the VDM message header used by PCIe Standard 3.0 (and later versions). Each row of the header includes four bytes, where the first row below the bit counter starts at byte 0, the second row starts at byte 4, the third row starts at byte 8, and the fourth row starts at byte 12 (a total of 16 bytes). Bytes 0 to 4 include fields that are present in (all) Translation Layer Packet (TLP) headers. Byte 0 includes Fmt[2:0] (the format of the TLP) and Type[4:0] (the type of the TLP). Byte 1 includes a reserved bit at bit 7, TC[2:0] (traffic class at bits [6:4]), a reserved bit at bit 3, Attr[2] (attribute bit at bit 2), a reserved bit at bit 1, and a TH bit at bit 0 (indicating the presence of a TLP processing hint). Byte 2 includes a TD bit at bit 7 (indicating the presence of a TLP summary), an EP bit at bit 6 (indicating the location of the TLP), Attr[l:0] (attribute at bits [5:4]), and an AT[1:0] field at bits [3:2]. In addition, from bit 2 of byte 2 to bit 0 of byte 3, a length field [9:0] is included, which indicates the length of the data payload. The requester ID of bytes 4 and 5 is implementation specific. Byte 6 includes a tag for the message and byte 7 includes a vendor defined message code. If the PCIe ID (identifier) ​​routing approach is used, then bytes 8 and 9 form a 16-bit field for the target ID, otherwise these bytes are reserved. Bytes 10 and 11 form a 16-bit field that defines the vendor ID of the vendor of the message, as specified by defined. Figure 4b A typical table of events and messages may be inserted in the fourth row (bytes 12 to 15), for example (marked "for vendor definition").

[0072] Figure 4b According to various examples discussed herein, a table of events and messages that may be communicated via enhanced VDM messaging is shown. In various examples, this may include (but is not necessarily limited to) one or more of the following, as well as example bits that may be used to communicate these states, messages, etc. (which may also vary in some examples):

[0073] [31:24]RC→EP, which may include:

[0074] [31:28] RC to EP interrupt code, and

[0075] [27:24] RC to EP error coding (optionally including power failure alarm indication);

[0076] [23:16] Buffer status, which may include:

[0077] 16Tx buffer status level,

[0078] 17Tx buffer exceeds threshold,

[0079] 18Rx buffer status level,

[0080] 19Rx buffer exceeds threshold, and

[0081] [23:20] Buffer status descriptor;

[0082] [15:8] Data path status, which may include:

[0083] [15:12] RC side status encoding, for example, LAN (Local Area Network) / WiFi (Wireless Fidelity) / Voice / Video port status, and

[0084] [11:8] EP side status encoding: link, link stability, link speed encoding; and

[0085] [7:0] Reset communication, which may include:

[0086] [7:4] RC side reset status: reset BM (buffer manager) / CQM (central queue manager) / PP (packet processor) / host, and

[0087] [3:0] EP side reset status: DMA (direct memory access) / MAC (DFE) (media access control of digital front end) / AFE (analog front end) / LD (line driver).

[0088] Possible example applications and use cases of the examples discussed herein may include, but are not limited to: (1) SoC subsystem software reset synchronization: the RC SoC is resetting and the EP SoC is notified so that the EP SoC can clear pending packets in the internal FIFO; (2) WAN link status: the EP SoC notifies the RC SoC that the WAN link is very slow (e.g., slower than a threshold link rate), the RC SoC can reduce the data path throughput feed, which can help avoid buffer overflows, and the RC SoC side can reduce VFs (virtual functions) to save system energy; (3) one (or more) RC SoC interrupts to the EP SoC processor: the RC SoC can send a message to trigger an interrupt, which is then handled by the EP SoC processor; (4) RC SoC critical error: the RC SoC can report a critical error to the EP SoC, and the EP SoC can decide whether to perform a full subsystem reset or just a PCIe module reset.

[0089] The examples discussed herein have several advantages over existing techniques. For example, sideband signaling used in some existing systems is not a solution for socket and card configurations. In addition, sideband signaling limits the system events to be communicated, such as one signal that can indicate an event. In addition, sideband signaling uses additional pins, resulting in higher implementation costs.

[0090] The techniques employed by the various examples discussed herein are flexible and extensible because the message formats can be adapted to individual system objectives, including new system objectives. In addition, sideband signaling can be omitted.

[0091] These techniques and examples may be implemented without requiring changes to the PCIe specification, and thus, the examples discussed herein may be employed in conjunction with any PCIe system that may be used as currently employed (unlike sideband signaling, which requires additional pins). Furthermore, unlike prior art techniques (e.g., employing sideband signaling), the techniques discussed herein and employed by various examples have negligible system overhead, since the VDM may utilize writes and interrupts over PCIe to signal message arrival.

[0092] The techniques discussed in this article and adopted in various examples provide simple and effective enhancements that can be used in conjunction with various PCIe system architectures to enhance / strengthen the system communication mechanism between two (or more) subsystems interconnected according to any of a variety of architectures, such as: (1) network processor + AnyWAN (xDSL (x Digital Subscriber Line Network, where x represents different DSL standards or implementations), xPON (x Passive Optical Network, where x represents different PON standards or implementations), DOCSIS (Data Over Cable Service Interface Specification, a cable communication standard) on PCIe; (2) network processor + WiFi on PCIe; (3) network processor + video processor on PCIe; and so on.

[0093] Examples herein may include subject matter such as methods, apparatus for performing actions or blocks of the method, and at least one machine-readable medium comprising executable instructions that, when executed by a machine (e.g., a processor with memory, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc.), cause the machine to perform actions of a method or apparatus or system according to one or more of the examples described for concurrent communication utilizing multiple communication technologies.

[0094] The aspects and features mentioned and described with one or more of the previously detailed examples and figures may also be combined with one or more of the other examples to replace similar features of the other examples or to introduce the features additionally to the other examples.

[0095] Example 1 relates to a device (10) configured as a root complex (RC) (100) of a PCIe (PCIe Express) system (1000), including a memory (12). The device (10) includes one or more processors (14) configured to generate a PCIe VDM (Vendor Defined Message) message for an EP (Endpoint) (200) of the PCIe system.

[0096] In Example 2, the subject matter of Example 1 or any of the examples described herein may also include that the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0097] In Example 3, the subject matter of Examples 1-2 or any of the examples described herein may also include that the PCIe VDM message includes information about an error at the RC.

[0098] In Example 4, the subject matter of Example 3 or any of the examples described herein may also include that the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0099] In Example 5, the subject matter of any of Examples 1-4 or any of the examples described herein may also include that the PCIe VDM message includes information about a reset state at the RC.

[0100] In Example 6, the subject matter of Example 5 or any of the examples described herein may also include that the PCIe VDM message includes a notification that an RC of the PCIe system is being reset.

[0101] In Example 7, the subject matter of any of Examples 1-6 or any of the examples described herein may also include that the PCIe VDM message includes information about a status of at least one data path.

[0102] In Example 8, the subject matter of any of Examples 1-7 or any of the examples described herein may also include that the PCIe VDM message includes information about a buffer status.

[0103] In Example 9, the subject matter of any one of Examples 1 to 8 or any of the examples described herein may also include one or more processors configured to process a PCIe VDM message from another EP of the PCIe system, and configured to forward the PCIe VDM message received from the other EP to the EP.

[0104] Example 10 relates to a device (20) configured as an endpoint (EP) (200) of a PCIe (PCIe) system (1000), comprising a memory (22). The device (20) comprises one or more processors (24) configured to process PCIe (PCIe) VDM (Vendor Defined Message) messages from an RC (Root Complex) (100) of the PCIe system.

[0105] In Example 11, the subject matter of Example 10 or any of the examples described herein may also include that the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0106] In Example 12, the subject matter of Example 11 or any of the examples described herein may also include that the one or more processors are further configured to manipulate a related interrupt based on the interrupt trigger.

[0107] In Example 13, the subject matter of any of Examples 10-12 or any of the examples described herein may also include that the PCIe VDM message includes information about a reset state at the RC.

[0108] In Example 14, the subject matter of Example 13 or any of the examples described herein may also include that the PCIe VDM message includes a notification that the RC is resetting.

[0109] In Example 15, the subject matter of Example 14 or any of the examples described herein may also include that one or more processors are also configured to clear pending data packets in an internal FIFO (first in first out) of the EP of the PCIe system in response to a notification that the RC is being reset.

[0110] In Example 16, the subject matter of any of Examples 10-15 or any of the examples described herein may also include that the PCIe VDM message includes information about an error at the RC.

[0111] In Example 17, the subject matter of any of Examples 10-16 or any of the examples described herein may also include that the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0112] In Example 18, the subject matter of Example 17 or any of the examples described herein may also include that the one or more processors are further configured to make a determination whether to perform a full system reset or to perform a PCIe module reset based at least in part on the indication of the severe error.

[0113] In Example 19, the subject matter of any of Examples 10-18 or any of the examples described herein may also include that the PCIe VDM message includes information about a status of a data path.

[0114] In Example 20, the subject matter of any of Examples 10-19 or any of the examples described herein may also include that the PCIe VDM message includes information about a buffer status.

[0115] In Example 21, the subject matter of any of Examples 10-20 or any of the examples described herein may also include that the PCIe VDM message is a PCIe VDM message from another EP forwarded by the RC.

[0116] Example 22 relates to a device (20) configured as an endpoint (EP) (200) of a PCIe (PCIe Express) system (1000), comprising a memory (22). The device (20) comprises one or more processors (24) configured to generate a PCIe VDM (Vendor Defined Message) message of an RC (Root Complex) of the PCIe system.

[0117] In Example 23, the subject matter of Example 22 or any of the examples described herein may also include that the PCIe VDM message includes at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

[0118] In Example 24, the subject matter of any of Examples 22-23 or any of the examples described herein may also include that the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0119] Example 25 relates to a device (10) configured as a root complex (RC) (100) for a PCIe (PCIe Express) system (1000), including a memory (12). The device (10) includes one or more processors (14) configured to process PCIe VDM (Vendor Defined Message) messages of an EP (Endpoint) (200) of the PCIe system.

[0120] In Example 26, the subject matter of Example 25 or any of the examples described herein may also include that the PCIe VDM message includes at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

[0121] In Example 27, the subject matter of any of Examples 25-26 or any of the examples described herein may also include that the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0122] In Example 28, the subject matter of Example 27 or any of the examples described herein may also include that the one or more processors are further configured to reduce the data path throughput of the EP based on an indication that the WAN link is slower than a threshold rate.

[0123] In Example 29, the subject matter of any of Examples 27-28 or any of the examples described herein may also include that the one or more processors are further configured to scale back the virtual function based on an indication that the WAN link is slower than a threshold rate.

[0124] Example 30 relates to an apparatus comprising an apparatus for performing any of the described operations of any of Examples 1 to 29.

[0125] Example 31 relates to a machine-readable medium storing instructions executed by a processor to perform any of the described operations of any of Examples 1 to 29.

[0126] Example 32 relates to an apparatus comprising a memory interface. The apparatus comprises a processing circuit configured to perform any of the described operations of any of Examples 1-29.

[0127] Example 33 relates to a device (10) configured for a root complex (RC) (100) of a PCIe (PCIe Express) system (1000), comprising a memory device (12). The device (10) comprises a processing device (14) configured to generate a PCIe VDM (Vendor Defined Message) message for an EP (Endpoint) (200) of the PCIe system.

[0128] In Example 34, the subject matter of Example 33 or any of the examples described herein may also include that the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0129] In Example 35, the subject matter of any of Examples 33-34 or any of the examples described herein may also include that the PCIe VDM message includes information about an error at the RC.

[0130] In Example 36, the subject matter of Example 35 or any of the examples described herein may also include that the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0131] In Example 37, the subject matter of any of Examples 33-36 or any of the examples described herein may also include that the PCIe VDM message includes information about a reset state at the RC.

[0132] In Example 38, the subject matter of Example 37 or any of the examples described herein may also include that the PCIe VDM message includes a notification that an RC of the PCIe system is being reset.

[0133] In Example 39, the subject matter of any of Examples 33 to 38 or any of the examples described herein may also include that the PCIe VDM message includes information about a status of at least one data path.

[0134] In Example 40, the subject matter of any of Examples 33 to 39 or any of the examples described herein may also include that the PCIe VDM message includes information about a buffer status.

[0135] In Example 41, the subject matter of any one of Examples 33 to 40 or any one of the examples described herein also includes that the processing tool is configured to process a PCIe VDM message from another EP of the PCIe system, and is configured to forward the PCIe VDM message received from the other EP to the EP.

[0136] Example 42 relates to a device (20) configured as an endpoint (EP) (1000) of a PCIe (PCIe) system (1000), comprising a memory device (22). The device (20) comprises a processing device (24) configured to process a PCIe (PCIe) VDM (Vendor Defined Message) message from an RC (Root Complex) (100) of the PCIe system.

[0137] In Example 43, the subject matter of Example 42 or any of the examples described herein may also include that the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0138] In Example 44, the subject matter of Example 43 or any of the examples described herein may also include that the treatment tool is further configured to manipulate a related interrupt based on the interrupt trigger.

[0139] In Example 45, the subject matter of any of Examples 42-44 or any of the examples described herein may also include that the PCIe VDM message includes information about a reset state at the RC.

[0140] In Example 46, the subject matter of Example 45 or any of the examples described herein may also include that the PCIe VDM message includes a notification that the RC is resetting.

[0141] In Example 47, the subject matter of Example 46 or any of the examples described herein may also include that the processing device is also configured to clear pending data packets in an internal FIFO (first in first out) of the EP of the PCIe system in response to the notification that the RC is being reset.

[0142] In Example 48, the subject matter of any of Examples 42-47 or any of the examples described herein may also include that the PCIe VDM message includes information about an error at the RC.

[0143] In Example 49, the subject matter of any of Examples 42-48 or any of the examples described herein may also include that the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0144] In Example 50, the subject matter of Example 49 or any of the examples described herein may also include that the processing tool is further configured to make a determination whether to perform a full system reset or perform a PCIe module reset based at least in part on the indication of the serious error.

[0145] In Example 51, the subject matter of any of Examples 42 to 50 or any of the examples described herein may also include that the PCIe VDM message includes information about a status of a data path.

[0146] In Example 52, the subject matter of any of Examples 42-51 or any of the examples described herein may also include that the PCIe VDM message includes information about a buffer status.

[0147] In Example 53, the subject matter of any of Examples 42 to 52 or any of the examples described herein may also include that the PCIe VDM message is a PCIe VDM message from another EP forwarded by the RC.

[0148] Example 54 relates to a device (20) configured for an endpoint (EP) (200) of a PCIe (PCIe Express) system (1000), comprising a memory device (22). The device (20) comprises a processing device (24) configured to generate a PCIe VDM (Vendor Defined Message) message of an RC (Root Complex) of the PCIe system.

[0149] In Example 55, the subject matter of Example 54 or any of the examples described herein may also include that the PCIe VDM message includes at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

[0150] In Example 56, the subject matter of any of Examples 54-55 or any of the examples described herein may also include that the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0151] Example 57 relates to a device (10) configured for a root complex (RC) (100) of a PCIe (PCIe Express) system (1000), comprising a memory device (12). The device (10) comprises a processing device (14) configured to process a PCIe VDM (Vendor Defined Message) message of an EP (Endpoint) (200) of the PCIe system.

[0152] In Example 58, the subject matter of Example 57 or any of the examples described herein may also include that the PCIe VDM message includes at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

[0153] In Example 59, the subject matter of any of Examples 57-58 or any of the examples described herein may also include that the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0154] In Example 60, the subject matter of Example 59 or any of the examples described herein also includes the processing device being further configured to reduce the data path throughput of the EP based on an indication that the WAN link is slower than a threshold rate.

[0155] In Example 61, the subject matter of any of Examples 59-60 or any of the examples described herein may also include the processing appliance being further configured to scale back the virtual function based on an indication that the WAN link is slower than a threshold rate.

[0156] Example 62 relates to a device comprising an apparatus for performing any of the operations described in any of Examples 33 to 61.

[0157] Example 63 relates to a machine-readable medium storing instructions executed by a processor to perform any of the described operations of any of Examples 33 to 61.

[0158] Example 64 relates to an apparatus comprising a memory interface. The apparatus comprises a processing tool configured to perform any of the operations described in any of Examples 33 to 61.

[0159] Example 65 relates to a method for a root complex (RC) (100) of a PCIe (PCIe express) system (1000), the method comprising generating (110) a PCIe VDM (Vendor Defined Message) message for an EP (Endpoint) (200) of the PCIe system.

[0160] In Example 66, the subject matter of Example 65 or any of the examples described herein may also include that the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0161] In Example 67, the subject matter of any of Examples 65-66 or any of the examples described herein may also include that the PCIe VDM message includes information about an error at the RC.

[0162] In Example 68, the subject matter of Example 67 or any of the examples described herein may also include the PCIe VDM message including an indication of a severe error at a RC of the PCIe system.

[0163] In Example 69, the subject matter of any of Examples 65-68 or any of the examples described herein may also include that the PCIe VDM message includes information about a reset state at the RC.

[0164] In Example 70, the subject matter of Example 69 or any of the examples described herein may also include that the PCIe VDM message includes a notification that an RC of the PCIe system is being reset.

[0165] In Example 71, the subject matter of any of Examples 65-70 or any of the examples described herein may also include that the PCIe VDM message includes information about a status of at least one data path.

[0166] In Example 72, the subject matter of any of Examples 65-71 or any of the examples described herein may also include that the PCIe VDM message includes information about a buffer status.

[0167] In Example 73, the subject matter of any of Examples 65 to 72 or any of the examples described herein may also include that the method includes processing (120) a PCIe VDM message from another EP of the PCIe system, and forwarding (125) the PCIe VDM message received from the other EP to the EP.

[0168] Example 74 relates to a method for an endpoint (EP) (200) of a PCIe (PCIe express) system (1000), comprising processing (210) a PCIe (PCIe express) VDM (Vendor Defined Message) message from an RC (Root Complex) (100) of the PCIe system.

[0169] In Example 75, the subject matter of Example 74 or any of the examples described herein may also include that the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0170] In Example 76, the subject matter of Example 75 or any of the examples described herein may also include that the method further includes manipulating (220) a related interrupt based on the interrupt trigger.

[0171] In Example 77, the subject matter of any of Examples 74-76 or any of the examples described herein may also include that the PCIe VDM message includes information about a reset state at the RC.

[0172] In Example 78, the subject matter of Example 77 or any of the examples described herein may also include that the PCIe VDM message includes a notification that the RC is resetting.

[0173] In Example 79, the subject matter of Example 78 or any of the examples described herein may also include that the method further includes clearing (230) pending data packets in an internal FIFO (first in first out) of the EP of the PCIe system in response to the notification that the RC is being reset.

[0174] In Example 80, the subject matter of any of Examples 74-79 or any of the examples described herein may also include that the PCIe VDM message includes information about an error at the RC.

[0175] In Example 81, the subject matter of any of Examples 74-80 or any of the examples described herein may also include that the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0176] In Example 82, the subject matter of Example 81 or any of the examples described herein may also include that the method further includes making a determination whether to perform a full system reset or perform a PCIe module reset based at least in part on the indication of the severe error (240).

[0177] In Example 83, the subject matter of any of Examples 74-82 or any of the examples described herein may also include that the PCIe VDM message includes information about a status of a data path.

[0178] In Example 84, the subject matter of any of Examples 74 to 83 or any of the examples described herein may also include that the PCIe VDM message includes information about a buffer status.

[0179] In Example 85, the subject matter of any of Examples 74 to 84 or any of the examples described herein may also include that the PCIe VDM message is a PCIe VDM message from another EP forwarded by the RC.

[0180] Example 86 relates to a method (20) for an endpoint (EP) (200) of a PCIe (PCIe express) system (1000), comprising generating (250) a PCIe VDM (Vendor Defined Message) message of an RC (Root Complex) of the PCIe system.

[0181] In Example 87, the subject matter of Example 86 or any of the examples described herein may also include that the PCIe VDM message includes at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

[0182] In Example 88, the subject matter of any of Examples 86-87 or any of the examples described herein may also include that the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0183] Example 89 relates to a method (10) for a root complex (RC) (100) of a PCIe (PCIe express) system (1000), comprising processing (120) a PCIe VDM (Vendor Defined Message) message from an EP (Endpoint) (200) of the PCIe system.

[0184] In Example 90, the subject matter of Example 89 or any of the examples described herein may also include that the PCIe VDM message includes at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

[0185] In Example 91, the subject matter of any of Examples 89-90 or any of the examples described herein may also include that the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0186] In Example 92, the subject matter of Example 91 or any of the examples described herein may also include that the method further includes reducing (130) the data path throughput of the EP based on an indication that the WAN link is slower than a threshold rate.

[0187] In Example 93, the subject matter of any of Examples 91-92 or any of the examples described herein may also include that the method further includes scaling down (140) the virtual function based on an indication that the WAN link is slower than a threshold rate.

[0188] Example 94 relates to an apparatus or device comprising an apparatus for performing any of the operations described in any of Examples 65 to 93.

[0189] Example 95 relates to a machine-readable medium storing instructions executed by a processor to perform any of the methods of any of Examples 65 to 93.

[0190] Example 96 relates to a device comprising a memory interface. The device comprises a processing circuit configured to perform any of the methods of any of Examples 65 to 93.

[0191] Example 97 relates to a system comprising the device (10) according to one of Examples 1 to 9 or 25 to 29 and the device (20) according to one of Examples 10 to 24.

[0192] Example 98 relates to a system comprising the device (10) according to one of Examples 33 to 41 or 57 to 61 and the device (20) according to one of Examples 42 to 56.

[0193] Example 99 relates to a system comprising two devices according to one of Examples 30, 32, 62, 64, 94 or 96.

[0194] In Example 100, the subject matter of one of Examples 97-99 or any one of the examples described herein may also include that the system is a gateway device.

[0195] Example 101 relates to a machine-readable storage medium including program code, which, when executed, causes the machine to perform at least one of the methods of one of Examples 65 to 93.

[0196] Example 102 relates to a computer program having a program code for performing at least one of the methods of one of Examples 65 to 93, when the computer program is executed on a computer, a processor, or a programmable hardware component.

[0197] Example 103 relates to a machine-readable storage device including machine-readable instructions, which, when executed, implement a method or realize an apparatus as shown in any example and claimed in any pending claims.

[0198] Example A1 is a device applied to a root complex (RC) of a PCIe (PCIe express) system, comprising: a memory; and one or more processors configured to generate a PCIe VDM (vendor defined message) message of an EP (endpoint) of the PCIe system.

[0199] Example A2 includes the subject matter of any variation of any one (or more) of Examples A1, wherein the PCIe VDM message includes a notification that an RC of the PCIe system is being reset.

[0200] Example A3 includes the subject matter of any variation of any one (or more) of Examples A1, wherein the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0201] Example A4 includes the subject matter of any variation of any one (or more) of Examples A1, wherein the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0202] Example A5 is a device configured for use at an endpoint (EP) of a PCIe (PCIe) system, comprising: a memory; and one or more processors configured to process PCIe (PCIe) VDM (Vendor Defined Message) messages of an RC (Root Complex) of the PCIe system.

[0203] Example A6 includes the subject matter of any variation of any one (or more) of Example A5, wherein the PCIe VDM message includes a notification that the RC is resetting.

[0204] Example A7 includes the subject matter of any variation of any one (or more) of Examples A6, wherein the one or more processors are further configured to clear pending data packets in an internal FIFO (first in first out) of an EP of the PCIe system.

[0205] Example A8 includes the subject matter of any variation of any one (or more) of Example A5, wherein the PCIe VDM message includes an interrupt trigger of an EP of the PCIe system.

[0206] Example A9 includes the subject matter of any variation of any one (or more) of Examples A8, wherein the one or more processors are further configured to manipulate a related interrupt based on the interrupt trigger.

[0207] Example A10 includes the subject matter of any variation of any one (or more) of Examples A5, wherein the PCIe VDM message includes an indication of a severe error at a RC of the PCIe system.

[0208] Example A11 includes the subject matter of any variation of any one (or more) of Examples A10, wherein the one or more processors are further configured to make a determination whether to perform a full system reset or perform a PCIe module reset based at least in part on the indication of the serious error.

[0209] Example A12 is a device configured for use at an endpoint (EP) of a PCIe (PCIe express) system, comprising: a memory; and one or more processors configured to generate a PCIe VDM (vendor defined message) message for an RC (root complex) of the PCIe system.

[0210] Example A13 includes the subject matter of any variation of any of one (or more) examples A12, wherein the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0211] Example A14 is a device configured for use at a root complex (RC) of a PCIe (PCIe express) system, comprising: a memory; and one or more processors configured to process PCIe VDM (vendor defined message) messages of an EP (endpoint) of the PCIe system.

[0212] Example A15 includes the subject matter of any variation of any one (or more) of examples A14, wherein the PCIe VDM message includes an indication that the WAN link is slower than a threshold rate.

[0213] Example A16 includes the subject matter of any variation of any of one (or more) examples A15, wherein the one or more processors are further configured to reduce the data path throughput feed.

[0214] Example A17 includes the subject matter of any variation of any of one (or more) examples A15, wherein the one or more processors are further configured to reduce the VF.

[0215] Example A18 includes an apparatus comprising means for performing any of the described operations of Examples A1-A17.

[0216] Example A19 includes a machine-readable medium storing instructions executed by a processor to perform any of the described operations of Examples A1-A17.

[0217] Example A20 includes an apparatus comprising: a memory interface; and a processing circuit configured to perform any of the described operations of Examples A1-A17.

[0218] The above description of the illustrated examples of the disclosed subject matter (including those described in the Abstract and / or Appendix) is not intended to be exhaustive, or to limit the disclosed examples to the precise forms disclosed. Although one or more specific examples are described herein for illustrative purposes, various modifications are possible, which are considered to be within the scope of such one or more examples, as those skilled in the relevant art may recognize. In the context of the present disclosure, at least some of the examples may be construed as embodiments of the present disclosure.

[0219] In this regard, while the disclosed subject matter has been described in conjunction with various examples and corresponding drawings, it should be understood that other similar examples may be used, where applicable, and modifications and additions may be made to the described examples for performing the same, similar, or alternative functions of the disclosed subject matter without departing from the subject matter. Therefore, the disclosed subject matter should not be limited to any single example described herein, but rather should be interpreted in breadth and scope in accordance with the appended claims below.

[0220] In particular, with respect to the various functions performed by the components or structures (assemblies, devices, circuits, systems, etc.) described above, unless otherwise indicated, the terms used to describe such components (including references to "apparatus") are intended to correspond to any component or structure that performs the designated functions of the described components (e.g., functionally equivalent), even if structurally not equivalent to the disclosed structures that perform the functions of the exemplary embodiments shown herein. In addition, while particular features may have been described with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments, as may be desirable or advantageous for any given or particular application.

[0221] Examples may also be (or relate to) a computer program with a program code, which, when executed on a computer or processor, is used to perform one or more of the above methods. The steps, operations or processes of the various methods described above may be performed by a programmed computer or processor. Examples may also include program storage devices (such as digital data storage media, which are machine, processor or computer readable, and have encoded machine executable, processor executable or computer executable programs of instructions). These instructions perform (or cause to perform) some or all of the actions of the methods described above. Program storage devices may include (or may be) for example digital memories, magnetic storage media (such as disks and tapes), hard drives, or optically readable digital data storage media. Other examples may also include computers, processors or control units (which are programmed to perform the actions of the methods described above) or (field) programmable logic arrays ((F) PLAs) or (field) programmable gate arrays ((F) PGAs) (which are programmed to perform the actions of the methods described above).

[0222] The description and drawings illustrate only the principles of the present disclosure. In addition, all examples described herein are clearly intended to be used for illustrative purposes only in principle to assist the reader in understanding the principles of the present disclosure and the concepts proposed by one (or more) inventors to advance the art. All statements describing the principles, aspects and examples of the present disclosure and specific examples thereof are intended to include their equivalents.

[0223] A functional block represented as a "means for..." performing a specific function may refer to a circuit configured to perform the specific function. Thus, a "means for something" may be implemented as a "means configured or suitable for something," such as a device or circuit configured or suitable for the corresponding task.

[0224] The functions of the various elements shown in the drawings (including any functional blocks marked as "apparatus", "apparatus for providing a signal", "apparatus for generating a signal", etc.) can be implemented in the form of dedicated hardware, such as "signal provider", "signal processing unit", "processor", "controller", etc., as well as hardware capable of executing software in conjunction with appropriate software. When provided by a processor, these functions can be provided by a single dedicated processor, a single shared processor, or multiple independent processors (some or all of which can be shared). However, the term "processor" or "controller" is not limited to hardware that is exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read-only memories (ROMs), random access memories (RAMs), and non-volatile storage devices for storing software. Other hardware (conventional and / or customized) may also be included.

[0225] For example, a block diagram may show a high-level circuit diagram implementing the principles of the present disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, etc. may represent various processes, operations, or steps; for example, they may be generally represented in a computer-readable medium and executed by a computer or processor, whether or not such a computer or processor is explicitly shown. The methods disclosed in the specification or claims may be implemented by a device having apparatus for performing the corresponding actions of these methods.

[0226] It should be understood that the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims cannot be interpreted in a specific order unless otherwise explicitly or implicitly stated, for example, for technical reasons. Therefore, the disclosure of multiple actions or functions will not be limited to a specific order unless such actions or functions are non-interchangeable for technical reasons. In addition, in some instances, a single action, function, process, operation or step may include or be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-operations, respectively. Such sub-actions may be included in the disclosure of the single action and as part thereof, unless explicitly excluded.

[0227] In addition, the following claims are hereby incorporated into the Detailed Description, where each claim can stand on its own as a separate example. Although each claim can stand on its own as a separate example, it should be noted that although a dependent claim may refer to a specific combination with one or more other claims in the claims, other examples may also include a combination of a dependent claim with the subject matter of each other dependent or independent claim. Unless a specific combination is indicated as unintended, such a combination is explicitly proposed in this category. In addition, such a combination is also intended to include claim features of any other independent claim, even if the claim is not directly dependent on the independent claim.

Claims

1. A device (10) configured for a root complex RC (100) of a high-speed serial computer expansion bus PCIe system (1000), comprising: Memory (12); and One or more processors (14) configured to: A PCIe vendor defined message VDM message is generated for an endpoint EP (200) of the PCIe system.

2. The apparatus of claim 1, wherein the PCIe VDM message comprises an interrupt trigger of an EP of the PCIe system. 3 . The apparatus of claim 1 , wherein the PCIe VDM message includes information about an error at the RC. 4 . The apparatus of claim 3 , wherein the PCIe VDM message includes an indication of a severe error at an RC of the PCIe system. 5 . The apparatus of claim 1 , wherein the PCIe VDM message includes information about a reset state at the RC.

6. The apparatus of claim 5, wherein the PCIe VDM message includes a notification that an RC of the PCIe system is being reset. 7 . The device of claim 1 , wherein the PCIe VDM message includes information on a status of at least one data path. 8 . The apparatus of claim 1 , wherein the PCIe VDM message includes information about a buffer status.

9. The apparatus of claim 1, wherein the one or more processors are configured to process a PCIe VDM message from another EP of the PCIe system and forward the PCIe VDM message received from the another EP to the EP.

10. A device (20) configured for an endpoint EP (200) of a high-speed serial computer expansion bus PCIe system (1000), comprising: Memory (22); and One or more processors (24) configured to: Processing a high-speed serial computer expansion bus PCIe vendor defined message VDM message from the root complex RC (100) of the PCIe system.

11. The apparatus of claim 10, wherein the PCIe VDM message comprises an interrupt trigger of an EP of the PCIe system. 12 . The apparatus of claim 10 , wherein the PCIe VDM message includes information about a reset state at the RC.

13. The apparatus of claim 10, wherein the PCIe VDM message includes information about an error at the RC.

14. The apparatus of claim 10, wherein the PCIe VDM message includes information about a status of a data path.

15. The apparatus of claim 10, wherein the PCIe VDM message includes information about a buffer status. 16 . The apparatus of claim 10 , wherein the PCIe VDM message is a PCIe VDM message from another EP forwarded through the RC.

17. A device (20) configured for an endpoint EP (200) of a high-speed serial computer expansion bus PCIe system (1000), comprising: Memory (22); and One or more processors (24) configured to: A PCIe vendor defined message VDM message for a root complex RC of the PCIe system is generated. 18 . The apparatus of claim 17 , wherein the PCIe VDM message comprises at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

19. A device (10) configured for a root complex RC (100) of a high-speed serial computer expansion bus PCIe system (1000), comprising: Memory (12); and One or more processors (14) configured to: Processing a PCIe vendor defined message VDM message of an endpoint EP (200) of the PCIe system.

20. The apparatus of claim 19, wherein the PCIe VDM message comprises at least one of a data path status at the EP, a reset status at the EP, and a buffer status at the EP.

21. A method for a root complex RC (100) of a high-speed serial computer expansion bus PCIe system (1000), comprising: A PCIe vendor defined message VDM message is generated (110) for an endpoint EP (200) of the PCIe system.

22. A method for an endpoint EP (200) of a high-speed serial computer expansion bus PCIe system (1000), comprising: Processing (210) a PCIe vendor defined message VDM message from a root complex RC (100) of the PCIe system.

23. A method (20) for an endpoint EP (200) of a high-speed serial computer expansion bus PCIe system (1000), comprising: A PCIe vendor defined message VDM message for a root complex RC of the PCIe system is generated (250).

24. A method (10) for a root complex RC (100) of a high-speed serial computer expansion bus PCIe system (1000), comprising: A PCIe vendor defined message VDM message from an endpoint EP (200) of the PCIe system is processed (120).

25. A computer program having a program code for carrying out at least one method according to one of claims 21 to 24, when the computer program is executed on a computer, a processor or a programmable hardware component.

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