A heterogeneous acceleration system, method, apparatus, computing device, and storage medium

Abstract

The application relates to the technical field of computers and discloses a heterogeneous acceleration system, method, device, computing equipment and storage medium, which comprises a host end, a plurality of heterogeneous acceleration clusters and a storage device used for storing target data, the host end is used for sending an acceleration calculation request to the heterogeneous acceleration clusters; any target heterogeneous acceleration device in the heterogeneous acceleration clusters reads target data directly from the storage device in a preset direct transmission mode and carries out corresponding calculation processing on the target data to obtain an acceleration calculation result and write the acceleration calculation result into a target cache device in response to the acceleration calculation request under the condition that the acceleration calculation request is received; and the host end directly accesses the target cache device to obtain the acceleration calculation result. The transmission path of the target data is shortened, the time consumption of the target data in the transmission process is reduced, the data transmission time delay of the target heterogeneous acceleration device is reduced, and the performance of the computing equipment is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a heterogeneous acceleration system, method, device, computing device and storage medium. BACKGROUND

[0002] In today's era of rapid development of information technology, the data processing tasks carried by servers and other computing devices are increasingly heavy, and the amount of data in the database is growing in a massive manner. In the face of frequent data reading needs, the drawbacks of the traditional method of reading data only by the host are evident. Therefore, introducing a heterogeneous acceleration device to assist the server in reading database data has become a necessary choice to improve system data throughput and response speed.

[0003] In related technologies, data in the disk is first transmitted to the file cache of the host, then to the internal cache of the process, and finally to the heterogeneous acceleration device. The heterogeneous acceleration device performs corresponding acceleration tasks based on the obtained data, and finally feeds back the acceleration task execution results to the host.

[0004] Overall, the entire data transmission path is long, and the data in the disk needs to be forwarded multiple times before entering the heterogeneous acceleration device, resulting in a large data transmission process delay. Even if the heterogeneous acceleration device has powerful data processing capabilities, the overall delay is still very prominent, and the acceleration advantage is difficult to fully demonstrate, which seriously restricts the performance of the computing device in high-performance data processing scenarios. SUMMARY

[0005] The present application provides a heterogeneous acceleration system, method, device, computing device and storage medium to solve the defects of large data transmission process delay of the heterogeneous acceleration device in related technologies.

[0006] The first aspect of the present application provides a heterogeneous acceleration system, comprising: a host, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, wherein the heterogeneous acceleration cluster comprises a plurality of heterogeneous acceleration devices;

[0007] The host is configured to send an acceleration computing request to the heterogeneous acceleration cluster;

[0008] Any target heterogeneous acceleration device in the heterogeneous acceleration cluster is configured to, in the case of receiving the acceleration computing request, respond to the acceleration computing request, read target data directly from the storage device using a preset direct transmission mode, and perform corresponding computing processing on the target data to obtain an acceleration computing result, and write the acceleration computing result to a target cache device;

[0009] The host is configured to directly access the target cache device to obtain the acceleration computing result.

[0010] In an alternative embodiment, the target heterogeneous acceleration device comprises:

[0011] a target protocol control module configured to receive the acceleration computation request sent by the host; wherein the target cache device comprises a device memory of the target heterogeneous acceleration device, and the host directly accesses the device memory through the target protocol control module, so as to keep cache consistency between the host and the target heterogeneous acceleration device;

[0012] the target protocol control module is connected to a target protocol switch, so that the target heterogeneous acceleration device communicates with the host and the storage device through the target protocol switch.

[0013] In an alternative embodiment, the host is configured to:

[0014] obtain a raw data request input by a user;

[0015] in response to the raw data request, allocate a virtual address of the target data on the target heterogeneous acceleration device;

[0016] determine configuration parameters of the acceleration computation request according to the virtual address and the raw data request;

[0017] generate the acceleration computation request according to the configuration parameters of the acceleration computation request, and send the acceleration computation request to the target heterogeneous acceleration device.

[0018] In an alternative embodiment, the host is configured to:

[0019] convert the virtual address into a physical address in a device memory of the heterogeneous acceleration card;

[0020] determine a bus address according to the physical address, and take the bus address as a destination address;

[0021] determine file index information of a to-be-accessed file and a logical offset value of the target data in the to-be-accessed file according to the raw data request;

[0022] determine a source address and a data length of the target data in the storage device according to the file index information of the to-be-accessed file and the logical offset value of the target data in the to-be-accessed file;

[0023] generate a direct storage device access descriptor according to the destination address, the source address and the data length;

[0024] generate the acceleration computation request based on the direct storage device access descriptor, so that the target heterogeneous acceleration device responds to the acceleration computation request based on a direct storage device access engine.

[0025] In an optional implementation, the target cache device includes a device memory of a target heterogeneous acceleration device, and the target heterogeneous acceleration device is configured to:

[0026] In response to the acceleration calculation request, an access start command is sent to the storage device, so that the storage device, in response to the access start command, moves the target data to a peer access space in the device memory according to the destination address in a preset direct transmission mode;

[0027] When the acceleration calculation result is obtained, the acceleration calculation result is written into the peer access space;

[0028] The peer access space in the device memory is exposed on a peer communication bus of the target heterogeneous acceleration device, and the peer access space supports direct access of the host end and the storage device.

[0029] In an optional implementation, the host end is configured to:

[0030] Receive an interrupt signal fed back by the target heterogeneous acceleration device when the acceleration calculation result is obtained, and perform direct access to the peer access space of the target heterogeneous acceleration device in response to the interrupt signal to obtain the acceleration calculation result.

[0031] In an optional implementation, the storage device is configured to:

[0032] The target data read by the target heterogeneous acceleration device is regarded as original data meeting a current query condition, and the original data is transmitted to a file cache system of the host end.

[0033] The acceleration calculation result includes current query condition information.

[0034] In an optional implementation, the heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate in a full connection mode, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate through a target protocol switch.

[0035] In an optional implementation, the host end is configured to:

[0036] Obtain a global heterogeneous acceleration state table; the global heterogeneous acceleration configuration table includes global location information, acceleration unit function, current use, instruction type, current task execution information, and current resource occupation information of each acceleration unit, and each heterogeneous acceleration device includes a plurality of acceleration units.

[0037] screening, according to the acceleration computing requirement characterized by the acceleration computing request, a target heterogeneous acceleration device from the candidate heterogeneous acceleration devices in the global heterogeneous acceleration state table, so as to send the acceleration computing request to the target heterogeneous acceleration device.

[0038] screening, according to the global heterogeneous acceleration state table, a target heterogeneous acceleration device from the candidate heterogeneous acceleration devices, so as to send the acceleration computing request to the target heterogeneous acceleration device.

[0039] In an optional implementation, the host end is configured to:

[0040] analyze a task execution feature of the acceleration computing request to obtain task execution feature information of the acceleration computing request;

[0041] in a case where the task execution feature information indicates that a task execution mode of the acceleration computing request is a sequential mode, screening a plurality of target acceleration units from the candidate heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster;

[0042] screening, according to the global heterogeneous acceleration state table, a target heterogeneous acceleration device from the candidate heterogeneous acceleration devices in the global heterogeneous acceleration state table, so as to send the acceleration computing request to the target heterogeneous acceleration device.

[0043] In an optional implementation, the host end is configured to:

[0044] in a case where the task execution feature information indicates that a task execution mode of the acceleration computing request is an out-of-order mode, screening a plurality of target acceleration units from the candidate heterogeneous acceleration devices, which satisfy a preset screening condition in terms of remaining computing resources;

[0045] screening, according to the global heterogeneous acceleration state table, a target heterogeneous acceleration device from the candidate heterogeneous acceleration devices in the global heterogeneous acceleration state table, so as to send the acceleration computing request to the target heterogeneous acceleration device.

[0046] In an optional implementation, the host end is further configured to:

[0047] generating a target token for the target heterogeneous acceleration device; wherein the target token comprises a valid bit, a physical address start address, a data length, a read-write permission bit, a heterogeneous acceleration device unique identifier, an acceleration unit unique identifier, and a target priority;

[0048] sending, according to the heterogeneous acceleration device unique identifier, the target token to the corresponding target heterogeneous acceleration device, so that the target heterogeneous acceleration device performs a to-be-executed heterogeneous acceleration task based on the target token to perform corresponding computing processing on the target data, and obtains an acceleration computing result.

[0049] In an optional implementation, the target heterogeneous acceleration device is configured to:

[0050] receiving the target token sent by the host end;

[0051] In a case where the valid bit of the target token represents that the target token is currently valid, determining, according to the unique identifier of the acceleration unit in the target token, a target acceleration unit to be executed with the heterogeneous acceleration task and a task type of the heterogeneous acceleration task to be executed;

[0052] Determining, according to the physical address start address, the data length and the read-write permission bit in the target token, a permission range of the target acceleration unit; wherein the permission range comprises a target read-write range of the target cache device;

[0053] Determining, according to the target priority in the target token, an execution priority of the target acceleration unit.

[0054] In an optional implementation, the host end is configured to:

[0055] Obtaining a waiting cycle number of each candidate acceleration unit in the candidate heterogeneous acceleration device;

[0056] Determining, according to the waiting cycle number of the candidate acceleration unit, a time priority of the candidate acceleration unit; and obtaining a task priority of the heterogeneous acceleration task to be executed corresponding to the candidate acceleration unit;

[0057] Determining, according to the time priority and the task priority of the candidate acceleration unit, a target priority.

[0058] In an optional implementation, a target communication interface is arranged between the host end and each of the heterogeneous acceleration devices, and the acceleration calculation request comprises a database query statement; the target communication interface is configured to:

[0059] Performing semantic analysis on the database query statement to obtain a semantic analysis result;

[0060] Extracting, according to the semantic analysis result, a target action instruction from the database query statement;

[0061] Converting, according to the target action instruction, the database query statement into a heterogeneous acceleration device universal statement, and inputting the heterogeneous acceleration device universal statement into the target heterogeneous acceleration device;

[0062] The target action instruction at least comprises a data query instruction, a data insertion instruction, a data update instruction and a data deletion instruction.

[0063] The second aspect of the application provides a heterogeneous acceleration method, which is applied to a host end and comprises:

[0064] sending an acceleration computation request to any target heterogeneous acceleration device in a heterogeneous acceleration cluster, to read target data directly from a storage device based on the heterogeneous acceleration device in a preset direct transmission mode, the storage device being configured to store target data, and to perform corresponding computation processing on the target data to obtain an acceleration computation result, and to write the acceleration computation result into a target cache device;

[0065] when it is determined that the heterogeneous acceleration device has written the acceleration computation result into the target cache device, directly accessing the target cache device to obtain the acceleration computation result.

[0066] The third aspect of the present application provides a heterogeneous acceleration method, applied to a target heterogeneous acceleration device, and the method comprises the following steps:

[0067] receiving an acceleration computation request sent by a host end;

[0068] in response to the acceleration computation request, reading target data directly from a storage device in a preset direct transmission mode, the storage device being configured to store target data;

[0069] performing corresponding computation processing on the target data to obtain an acceleration computation result, and writing the acceleration computation result into a target cache device;

[0070] sending an interrupt request to the host end to instruct the host end to directly access the target cache device, so that the host end obtains the acceleration computation result.

[0071] The fourth aspect of the present application provides a heterogeneous acceleration device, applied to a host end, and the device comprises:

[0072] a request acceleration module, configured to send an acceleration computation request to any target heterogeneous acceleration device in a heterogeneous acceleration cluster, to read target data directly from a storage device based on the heterogeneous acceleration device in a preset direct transmission mode, the storage device being configured to store target data, and to perform corresponding computation processing on the target data to obtain an acceleration computation result, and to write the acceleration computation result into a target cache device;

[0073] a reading module, configured to, when it is determined that the heterogeneous acceleration device has written the acceleration computation result into the target cache device, directly access the target cache device to obtain the acceleration computation result.

[0074] The fifth aspect of the present application provides a heterogeneous acceleration device, applied to a target heterogeneous acceleration device, and the device comprises:

[0075] a receiving module, configured to receive an acceleration computation request sent by a host end;

[0076] a data reading module, configured to read target data from a storage device directly in a preset direct transmission mode in response to the acceleration calculation request, wherein the storage device is configured to store the target data;

[0077] an acceleration calculation module, configured to perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and write the acceleration calculation result into a target cache device;

[0078] a sending module, configured to send an interrupt request to the host end to instruct the host end to perform direct access on the target cache device, so that the host end obtains the acceleration calculation result.

[0079] The sixth aspect of the present application provides a computing device, comprising the heterogeneous acceleration system as described in the first aspect and various possible designs of the first aspect.

[0080] The seventh aspect of the present application provides a non-volatile computer readable storage medium, wherein the non-volatile computer readable storage medium stores computer execution instructions, and when a processor executes the computer execution instructions, the method as described in the second aspect and various possible designs of the second aspect or the method as described in the third aspect and various possible designs of the third aspect is implemented.

[0081] The eighth aspect of the present application provides a computer program product, comprising computer instructions for causing a computer to execute the method as described in the second aspect and various possible designs of the second aspect or the method as described in the third aspect and various possible designs of the third aspect.

[0082] The technical solution of the present application has the following advantages:

[0083] This application provides a heterogeneous acceleration system, method, apparatus, computing device, and storage medium. The system includes: a host terminal, several heterogeneous acceleration clusters, and a storage device for storing target data. Each heterogeneous acceleration cluster includes multiple heterogeneous acceleration devices. The host terminal sends accelerated computing requests to the heterogeneous acceleration clusters. Upon receiving an accelerated computing request, any target heterogeneous acceleration device in the cluster, in response to the request, directly reads the target data from the storage device using a preset direct transmission mode, performs corresponding computational processing on the target data, obtains the accelerated computing result, and writes the accelerated computing result to a target cache device. The host terminal directly accesses the target cache device to obtain the accelerated computing result. The system provided by the above solution allows the target heterogeneous acceleration devices to directly obtain target data from the storage device through direct data transmission, significantly shortening the transmission path of the target data and reducing the time consumption during transmission. This reduces the data transmission latency of the target heterogeneous acceleration devices, laying the foundation for improving the performance of computing devices. Attached Figure Description

[0084] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0085] Figure 1 A flowchart illustrating a heterogeneous acceleration method for traditional database query operations;

[0086] Figure 2 This is a schematic diagram of the interaction process of the heterogeneous acceleration system provided in the embodiments of this application;

[0087] Figure 3 This is a schematic diagram of the structure of a heterogeneous acceleration system provided in an embodiment of this application;

[0088] Figure 4 This is a schematic diagram of the heterogeneous acceleration device provided in the embodiments of this application;

[0089] Figure 5 This is a schematic diagram of another heterogeneous acceleration system provided in an embodiment of this application;

[0090] Figure 6 A schematic diagram of the structure of the target token provided in the embodiments of this application;

[0091] Figure 7 A flowchart illustrating a heterogeneous acceleration method provided in an embodiment of this application;

[0092] Figure 8Another flowchart of a heterogeneous acceleration method provided by an embodiment of the present application is shown in FIG. 6.

[0093] Figure 9 A structural diagram of a heterogeneous acceleration device provided by an embodiment of the present application is shown in FIG. 4.

[0094] Figure 10 Another structural diagram of a heterogeneous acceleration device provided by an embodiment of the present application is shown in FIG. 5.

[0095] Figure 11 A structural diagram of a computing device provided by an embodiment of the present application is shown in FIG. 6.

[0096] The specific embodiments of the present application have been shown in the above-described drawings, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present disclosure concept in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0097] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative work under the premise, belong to the scope of protection of the present application.

[0098] In addition, the terms "first", "second", and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. In the description of the following embodiments, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0099] In the related art, with the continuous development of technologies such as mobile Internet, artificial intelligence, big data analysis, and scientific computing, the amount of data grows exponentially, and the demand for data processing and analysis also increases. Under this background, the traditional database system that only takes the central processing unit (CPU) as the core operation component faces great challenges. Its ability to process massive data, ensure data real-time, and cope with diversified workloads is quite insufficient.

[0100] Database heterogeneous acceleration, which leverages heterogeneous acceleration devices such as Field Programmable Gate Arrays (FPGAs), Graphics Processing Units (GPUs), and dedicated processors to improve operating speed, has emerged. It fully utilizes different types of hardware resources, such as CPUs, GPUs, FPGAs, and dedicated processors, while combining software and hardware optimization techniques to improve the performance and efficiency of database systems. On one hand, it achieves parallel processing and pipelined dedicated hardware acceleration; on the other hand, software heterogeneous acceleration, through database engine customization, query optimization techniques, and data compression algorithms, can significantly improve the computation speed and storage efficiency of databases. It is worth noting that in existing heterogeneous computing architectures, when page data is transferred from the host CPU to the hardware acceleration device via Direct Memory Access (DMA), it is first transferred from the disk to the host-side file cache, then read into the process's internal cache, and finally transferred to the FPGA. This long transfer path and numerous copying operations result in low efficiency due to multiple data transfers.

[0101] Among them, such as Figure 1 The diagram illustrates the process of a traditional heterogeneous acceleration method for database query operations. The process is as follows: The host initiates a DMA transfer to read the target file page from the disk into the file system cache. The host then requests a pin page (physical memory page) in the database application and copies data from the file system cache to the database pin page. The host then transfers the database pin page content to the heterogeneous acceleration device via DMA, enabling the device to access the database page. Once the heterogeneous acceleration device receives the database page, it initiates parallel computing to filter the page, finding rows that match the filter conditions (the matching results). It then extracts the target retrieval fields from these matching rows, performs projection calculations to extract the decomposition results from the matching results, assembling the target retrieval fields into the query results. After obtaining the query results, it sends them to the host's memory, allowing the host to receive the query results. This process involves multiple transfers, resulting in significant transmission latency, high CPU load, and substantial host-side memory consumption.

[0102] To solve the above problems, the embodiment of the present application provides a heterogeneous acceleration system, method, device, computing device and storage medium. The system comprises a host, a plurality of heterogeneous acceleration clusters and a storage device for storing target data. The heterogeneous acceleration cluster comprises a plurality of heterogeneous acceleration devices. The host is configured to send an acceleration calculation request to the heterogeneous acceleration cluster. Any target heterogeneous acceleration device in the heterogeneous acceleration cluster is configured to, in response to the acceleration calculation request, directly read the target data from the storage device using a preset direct transmission mode, perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and write the acceleration calculation result to a target cache device, when receiving the acceleration calculation request. The host is configured to directly access the target cache device to obtain the acceleration calculation result. The system provided by the above scheme can directly obtain the target data from the storage device by the target heterogeneous acceleration device through the data direct transmission mode, greatly shortens the transmission path of the target data, reduces the time consumption of the target data in the transmission process, and thus reduces the data transmission delay of the target heterogeneous acceleration device, thereby laying a foundation for improving the performance of the computing device.

[0103] The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0104] The embodiment of the present application provides a heterogeneous acceleration system for reducing the data transmission delay of target data to a heterogeneous acceleration device in the case of accelerating the host computing task based on the heterogeneous acceleration device.

[0105] As shown in Figure 2 the interaction flow diagram of the heterogeneous acceleration system provided by the embodiment of the present application. The system comprises a host, a plurality of heterogeneous acceleration clusters and a storage device for storing target data. The heterogeneous acceleration cluster comprises a plurality of heterogeneous acceleration devices.

[0106] The host is configured to send an acceleration calculation request to the heterogeneous acceleration cluster. Any target heterogeneous acceleration device in the heterogeneous acceleration cluster is configured to, in response to the acceleration calculation request, directly read the target data from the storage device using a preset direct transmission mode, perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and write the acceleration calculation result to a target cache device, when receiving the acceleration calculation request. The host is configured to directly access the target cache device to obtain the acceleration calculation result.

[0107] The target cache device comprises the device memory of the target heterogeneous acceleration device, the storage device and the system memory of the host.

[0108] It should be noted that the host end includes a CPU and the like, and the host end serves as the control center of the system and is responsible for sending an acceleration calculation request to the heterogeneous acceleration cluster. In the initial stage of the data processing process, the host end receives a calculation task instruction of a user or an upper application, converts the calculation task instruction into an acceleration calculation request, and accurately sends the acceleration calculation request to the heterogeneous acceleration cluster. In addition, the host end also has the ability to directly access the memory of the heterogeneous acceleration device, and after the target heterogeneous acceleration device completes the calculation, the host end can directly obtain the acceleration calculation result stored in the memory of the device in order to perform subsequent data processing, analysis or directly output to the corresponding user.

[0109] It should be further noted that the heterogeneous acceleration cluster is composed of a plurality of heterogeneous acceleration devices, and the types of the heterogeneous acceleration devices are various, such as GPUs, FPGAs and the like, each of which is good at different types of calculation tasks. When a target heterogeneous acceleration device in the heterogeneous acceleration cluster receives the acceleration calculation request sent by the host end, the target heterogeneous acceleration device responds quickly. The preset direct transmission mode is adopted to bypass the intermediate links such as the host memory that may be passed in the traditional data transmission, and the target data is directly read from the storage device. This direct transmission mode greatly reduces the data transmission path and reduces the delay and overhead of the data in the transmission process. After the target data is read, the target heterogeneous acceleration device uses its own computing resources to perform corresponding calculation processing on the data according to the task requirements, such as complex mathematical operations and the like. After the calculation is completed, the acceleration calculation result is written into the device memory of the target heterogeneous acceleration device, and the host end is waited to read.

[0110] On the basis of the above embodiment, as Figure 3 A structure diagram of a heterogeneous acceleration system provided by the embodiment of the present application is provided, and as a kind of implementable mode, in an embodiment, target heterogeneous acceleration device includes:

[0111] Target protocol control module is used to receive the acceleration calculation request sent by the host end;Wherein, the host end directly accesses the device memory (DRAM) by target protocol control module, to make the host end and target heterogeneous acceleration device keep cache consistent.

[0112] Wherein, target protocol control module (CXL control module) is connected with target protocol switch, to make target heterogeneous acceleration device communicate with host end and storage device by target protocol switch. The device memory of target heterogeneous acceleration device is dynamic random access memory (Dynamic Random Access Memory, for short: DRAM).

[0113] It should be noted that the target protocol adopted in the embodiments of the present application is an open high-speed interconnection standard (Compute Express Link, CXL) protocol. In the related art, the host end CPU and the heterogeneous acceleration device are mainly connected through a traditional PCIe bus. In this case, the memory of the heterogeneous acceleration device and the CPU addressing space are not uniformly addressed, which leads to the fact that the CPU cannot directly access the memory of the acceleration device at byte granularity. At the same time, the PCIe bus does not have cache coherence characteristics, and when the heterogeneous acceleration device modifies the memory device, the CPU host end cannot perceive the modification of the data. When data transmission is performed between the host end and the acceleration card, it is necessary to first flush the respective cache caches into the memory, and then start the DMA transmission, and such a transmission process has a large delay. The cache coherence bus such as CXL, OpenCAPI, Cache Coherent Interconnect eXtension (CCIX) can solve the above problems. The memory (device memory) on the acceleration card side and the memory on the host side are uniformly addressed, and the cache coherence is maintained by hardware, so that the CPU can access the memory of the acceleration card as if it is accessing the local memory.

[0114] On the basis of the above-mentioned embodiments, as a kind of implementable mode, in an embodiment, the host end is used to obtain the original data request of user input;In response to the original data request, the virtual address of target data on target heterogeneous acceleration device is allocated;According to the virtual address and the original data request, the configuration parameter of acceleration calculation request is determined;According to the configuration parameter of acceleration calculation request, the acceleration calculation request is generated, and the acceleration calculation request is sent to target heterogeneous acceleration device.

[0115] Wherein, the original data request of user input includes data query request and the like, and the virtual address is obtained by application layer through memory map (memory map, mmap) function to obtain a block of cache space.

[0116] Specifically, first, the user initiates a request for reading a file "filename" through an application layer; a host obtains file meta information according to the file name in a kernel file system layer, the file meta information at least including file index information of a to-be-accessed file in a storage device; initiates a DMA operation and saves the file meta information (Inode) to a host memory; calculates an offset of a file data block in a disk (storage device) through the file meta information (inode) and an access address carried by an original data request; further fills a DMA descriptor, obtains configuration parameters of an accelerated computing request, and generates a corresponding accelerated computing request, so as to configure a source address on the disk and a destination address on a memory device in an FPGA (target heterogeneous acceleration device) to enable the target heterogeneous acceleration device to start a disk controller to initiate a corresponding CXL P2P-DMA operation and start data transfer to cache target data to a device memory of the target heterogeneous acceleration device.

[0117] Among them, P2P represents a peer-to-peer network (Peer-to-Peer), that is, an end-to-end transmission method of a database file, and the data page (target data) of the target file can be directly transmitted to the memory device of the heterogeneous acceleration device through end-to-end transmission.

[0118] Specifically, in an embodiment, the host can convert a virtual address into a physical address in a device memory of a heterogeneous acceleration card; determine a bus address according to the physical address, and take the bus address as a destination address; determine file index information of a to-be-accessed file and a logical offset value of target data in the to-be-accessed file according to an original data request; determine a source address of the target data in a storage device and a data length according to the file index information of the to-be-accessed file and the logical offset value of the target data in the to-be-accessed file; generate a direct storage device access descriptor according to the destination address, the source address and the data length; and generate an accelerated computing request based on the direct storage device access descriptor, so that the target heterogeneous acceleration device responds to the accelerated computing request based on a direct storage device access engine.

[0119] It should be noted that the heterogeneous acceleration system provided by the embodiments of the present application adopts an x86 PCIe architecture. In the architecture, when a CPU executes a program instruction, a virtual address of a memory read / write access is first issued, and then the virtual address is converted into a physical address by a memory management unit (MMU). The MMU maintains a mapping table of the virtual address and the physical address. The host sends the virtual address to the MMU, and the MMU looks up and returns the corresponding physical address according to the internal mapping table. The physical address determines the actual storage location of the target data in the memory of the heterogeneous acceleration card device. If the data accessed by the physical address is in the Cache (cache memory), the data is directly read from the Cache; if not, the physical address is converted into a bus address through a Host Bridge (host bridge) in the Root Complex (root complex), the Host Bridge serving as a bridge between the CPU and the system bus and being responsible for converting the physical address into a bus address format. In the PCIe bus environment, the Host Bridge converts the physical address into a bus address conforming to the PCIe bus transmission requirements according to the PCIe bus protocol specification, and the bus address is used for subsequent addressing of data transmission on the system bus to access the device memory space based on the bus address.

[0120] Specifically, after obtaining the bus address, the bus address is taken as a destination address. The host parses the original data request to extract the related information of the to-be-accessed file, and determines the file index information of the to-be-accessed file and the logical offset value of the target data in the to-be-accessed file. For a file access request in a file system, the file index information includes an inode number (index number) of the to-be-accessed file, and various attributes and storage location information of the file can be obtained in the file system metadata through the index number. The logical offset value represents the relative position of the target data in the file. The host looks up the corresponding file metadata in the file system according to the file index information of the to-be-accessed file. Through the file metadata, the source address of the target data on the storage device is determined in combination with the logical offset value of the target data. Specifically, the distribution of the data blocks in the to-be-accessed file on the storage device can be determined according to the file index information, and the start address of the data block where the target data is located is calculated as the source address in combination with the logical offset value. Meanwhile, the length of the target data to be read or operated is determined according to the requirement of the data amount in the original data request.

[0121] Specifically, after collecting the destination address (i.e. bus address), source address (address of the target data in the storage device), data length and other information, the host generates a direct storage device access descriptor (DMA descriptor) according to the format requirements of the direct storage device access protocol. The host integrates the direct storage device access descriptor with other related control information to generate an acceleration computing request. The related control information can include the type and priority of the computing task. The generated acceleration computing request is sent to the target heterogeneous acceleration device. After receiving the request, the target heterogeneous acceleration device parses the direct storage device access descriptor therein and reads the target data directly from the storage device through the direct storage device access engine according to the information in the descriptor, and then performs corresponding computing processing.

[0122] For example, taking a file to be accessed with a file name of "1.txt" as an example, the software execution method for reading the "1.txt" file from the disk SSD to the FPGA_DDR (device) is as follows:

[0123] (1) The application layer obtains a virtual address (VA) of a buffer (cache area) through the mmap function.

[0124] (2) The application layer initiates a read operation read (file, buffer, count) based on the above virtual address (VA).

[0125] (3) The vfs_read (buffer, file_inode, offset, count) interface function is called in the kernel layer, and the four important parameters of the virtual address VA of the buffer, the file index file_inode, the offset value of the file to be read offset, and the number of bytes to be read count are passed in, wherein the number of bytes to be read is also referred to as the data length. There are two main functions in the file system, which are to complete the allocation of physical cache for the virtual address and to find the offset address of the target data in the disk in the file system.

[0126] (4) Based on the buffer (VA) parameter, a system call is made, which further calls the FPGA memory registration method to map the user-allocated virtual memory to the physical address of the FPGA memory, then calls get_user_page to obtain a page, continues to call page_to_phys() to obtain the physical address PA value, and finally the dma_map_single() function obtains the bus address BA value, which is filled into the destination address of the DMA descriptor.

[0127] (5) Based on the file parameter, the file index inode is obtained at the file system layer, and then the inode information is saved to the system memory of the host, ext4_get_block is called, the physical block corresponding to the logical offset is obtained, and finally blk_offset is obtained by combining offset, blk_offset is taken as the source address of the DMA descriptor; Count is taken as the length of the DMA descriptor. At this point, the several key parameters required by the function have been obtained.

[0128] (6) Finally, the P2P-DMA transmission is initiated by the DMA engine, and the data transmission is completed.

[0129] Among them, the P2P-DMA driver is loaded first after the heterogeneous acceleration device is powered on, so that the user state can identify this memory and further operate this memory space. When the application program encounters FPGA_DDR memory access when executing related code, it will call the related interface function to realize the direct access of the memory device.

[0130] Among them, the conversion process from virtual address to bus address can be realized by registering and adding the heterogeneous acceleration device memory region node on the host side. The specific implementation process is as follows:

[0131] (1) MMU performs VA->PA mapping to realize access to the heterogeneous acceleration device. When the storage device applies for memory, the virtual address of the page in the kernel state needs to be obtained, so the mapping between the physical address and the virtual address of the device memory needs to be constructed in the driver. This operation is realized by filling the kernel MMU page table. The mapping is a fixed linear mapping. The kernel-related address conversion application programming interface (API) function such as virt_to_phy can directly perform linear address conversion to realize the mapping between the virtual address and the physical address.

[0132] (2) OS layer (operating system layer) needs struct page, which is used to manage heterogeneous acceleration device memory in Linux operating system, memory subsystem, which describes the physical memory in the system through struct page, and applies and releases the required memory page through functions such as get_free_pages and kfree_pages. After the system startup is completed, the struct page array for managing FPGA physical memory has not been created in the memory subsystem, and a page array is applied through the devm_memremap_pages function. The page array is added to the device_zone of the memory subsystem, and the struct page array of the FPGA physical memory page is created in the driver program as a device zone (DEVICE_ZONE) and added to the kernel zone. At the same time, the mapping between the physical address and the virtual address of the kernel device zone memory page is created to support the memory universal address conversion function. When the disk device performs P2P transmission, only the device zone flag needs to be added when allocating the destination address memory page, so as to realize the allocation of the FPGA physical memory space from the physical page, thereby realizing the direct memory access of the disk to the device memory of the heterogeneous acceleration device on the software.

[0133] (3) The mmap mapping to the address space of the user state process is divided into two modes of user state and kernel state. When the process is in the user state, it can only access the memory region of the user space, and when it is in the kernel state, it is accessed through the kernel state page table. Although the kernel state can allocate the device memory page table for access after adding the page array of the memory device to the device_zone in the kernel zone and performing the mapping between the physical address and the virtual address, the user state still cannot access the device memory. Therefore, in the Linux operating system, the memory subsystem uses the mmap memory mapping technology to realize the mapping of the kernel state memory to the user state, so that the user process can also access the memory of the FPGA device.

[0134] Correspondingly, in an embodiment, the target heterogeneous acceleration device sends an access start command to the storage device in response to the acceleration calculation request, so that the storage device moves the target data to the peer access space in the device memory according to the destination address in response to the access start command by using the preset direct transmission mode; and writes the acceleration calculation result into the peer access space when the acceleration calculation result is obtained.

[0135] The access start command includes a DMA start command, the peer access space in the device memory is exposed on the peer communication bus of the target heterogeneous acceleration device, and the peer access space supports the direct access of the host end and the storage device.

[0136] Specifically, in order to realize CXL P2P DMA, the target heterogeneous acceleration device exposes a part of the local memory segment on the base address register space (Base Address Register, BAR) for implementation of the hardware implementation part. The CXL device (target heterogeneous acceleration device) exposes its control registers and internal memory blocks on the bus through the BAR, so as to be accessed by other CXL devices (storage devices and host ends). The BAR saves the bus address area (peer access space) in which the device registers and memories can be accessed. By exposing the internal memory through the BAR, the device can select to expose its internal memory through the BAR, so that the CPU or other CXL devices can directly access this part of the memory. How to expose this relatively large memory space (peer access space) in the FPGA logic is described in detail below.

[0137] The implementation of the FPGA logic is to use a DMA basic function core, which has the following three functions:

[0138] (1) Data to AXI Lite Master Interface: a control interface based on the AXI-Lite bus, through which the registers of the internal IP core of the acceleration card can be read and written;

[0139] (2) Data to DMA Interface: through the DMA mode, the data movement between the host memory and the FPGA memory is completed, and this function is used under the DMA architecture (non-P2P);

[0140] (3) Data to DMA Bypass Interface: supporting data transmission bypassing the DMA Engine (Host DMA Bypass), that is, the function used in the embodiments of the present application, through which the FPGA side DDR (device memory) is connected. The DMA is initiated by the disk on the peer side, and the FPGA has the function of PCIe protocol conversion. In order to enable the host end to access the DDR space on the FPGA acceleration card, the data after passing through the IP core is converted into an AXI-MM protocol interface, which is directly connected to the memory controller IP (Mig) of the AXI-S interface. The host can access the FPGA side DDR to read the acceleration calculation result.

[0141] Among them, as Figure 4As shown, the structural diagram of the heterogeneous acceleration device provided by the embodiment of the application, the CXL control module is the target protocol control module, which is an important interface module of the whole system and is connected with other components through specific lines. It is responsible for receiving instructions and data requests from the host and transmitting relevant information of the host end to the internal module. At the same time, it can also feed back the results or state information processed in the FPGA to the host end, which is the key hub for communication and interaction between the whole system and the external host, ensuring accurate transmission and interaction of data and instructions between the host and the FPGA system. The heterogeneous acceleration device completes the protocol analysis, response and related control operations in the CXL control module. At the same time, the module is also connected with the CXL control module in each FPGA in the FPGA cluster, and ensures the cache consistency between the FPGA and the CPU through the CXL protocol.

[0142] DMA (Direct Memory Access) is used to realize the direct transmission of data between different storage areas without frequent intervention of the CPU, greatly improving the efficiency of data transmission. Data can be directly transmitted from the host memory to the FPGA device memory, or quickly moved between different memory areas in the FPGA. The DMA Bypass (DMA bypass) and other identifiers in the figure indicate that it may support multiple data transmission modes to adapt to different application scenarios and data transmission requirements. In some cases with high real-time requirements, a specific DMA mode can be used to optimize the data transmission path and reduce latency.

[0143] The bus crossbar module connects multiple modules in the system, such as DMA, memory controller, control management module and acceleration computing module, etc. According to the requirements of the system and the current task state, it dynamically switches the bus connection between each module, ensures that data can be transmitted to the corresponding module at the correct time through the correct path, avoids data transmission conflicts, and improves the overall performance and resource utilization of the system. By reasonably configuring the bus connection, it can optimize the flow of data in the system. When the acceleration computing module needs to read a large amount of data from the memory, the bus crossbar can quickly establish a direct data channel from the memory controller to the acceleration computing module, reducing the intermediate links of data transmission and improving the data transmission speed.

[0144] The control management module is responsible for the global control and coordination of the entire FPGA system. It receives instructions from the host end and state information from various modules within the system, and formulates the system's operation strategy and task scheduling scheme based on these information. When the host end sends an acceleration calculation request, the control management module allocates resources reasonably and schedules various modules to work cooperatively according to the current resource usage of the system, such as the free space of the memory, the load of the acceleration calculation module, etc., to ensure that the task can be executed efficiently and orderly. Real-time monitoring of the working state of each module in the system, including whether the module is running normally, whether there are errors or abnormal conditions, etc. Once a problem is found, take appropriate measures to handle it, such as restarting the faulty module, adjusting task allocation, etc., to ensure the stability and reliability of the system. The function acceleration module includes multiple acceleration units, which are used to execute acceleration calculation tasks and significantly improve the calculation speed and efficiency by quickly processing the input data.

[0145] The memory controller is responsible for managing the memory of the FPGA device, including memory allocation, recycling, and address mapping operations, etc. When the system needs to use memory to store data or programs, the memory controller allocates the corresponding memory space according to the request and records the usage of the memory for subsequent management and recycling. At the same time, it is also responsible for converting virtual addresses to physical addresses to ensure that data can be accurately stored and read to the correct location in memory. Control the read and write operations of data in memory, work with the bus crossbar and other modules to ensure that data can be quickly and accurately written to memory or read from memory. For example, when the acceleration calculation module needs to read data in memory for calculation, the memory controller will read the corresponding data from memory according to the scheduling of the bus crossbar and transmit it to the acceleration calculation module; when the calculation result needs to be stored in memory, the memory controller will write the result to the specified memory location.

[0146] The FPGA device memory is a storage area inside the FPGA, used to store various data required during system operation, including input data (target data), intermediate calculation results, and final output results (accelerated calculation results), etc. For example, in a data processing task, the data transmitted by the host end is first stored in the FPGA device memory for reading and processing by the acceleration calculation module. The intermediate results generated by the acceleration calculation module during the calculation process are also temporarily stored in the memory until the calculation is completed, and the final results are also stored in the memory, waiting for the host end to read or further process. In some cases, the FPGA device memory can also serve as a cache to cache some frequently used data or calculation results, reducing the number of accesses to external storage devices (such as solid state drives (SSD)), and improving the overall performance of the system. For example, for some repeatedly used intermediate calculation results, storing them in the FPGA device memory can avoid repeated calculations and speed up the processing speed of subsequent tasks.

[0147] Specifically, after passing through the CXL control module, the valid data (target data) is transmitted through the DMA module supporting the internal Advanced eXtensible Interface (AXI) bus for direct memory access (DMA). Since the AXI bus has a master-slave mode, M in the figure represents the master mode interface, and S represents the slave mode interface. The memory, acceleration calculation module, and control management module are connected to each other through a bus crossbar switch.

[0148] Correspondingly, in an embodiment, the host end receives an interrupt signal fed back by the target heterogeneous acceleration device when obtaining the accelerated calculation result, and in response to the interrupt signal, directly accesses the opposite end access space of the target heterogeneous acceleration device to obtain the accelerated calculation result.

[0149] Specifically, this embodiment sets up a CXL Bar space (peer access space) in the device memory for P2P transmission. Starting from address 0, this 8GB memory space is accessible to either the host or the SSD, without address translation required on the FPGA. When constructing the DMA descriptor, the host simply maps the FPGA-DDR address to the corresponding address space. Upon receiving the DMA start command, the SSD uses its DMA engine to move the data to the FPGA-DDR. Other acceleration IP cores within the FPGA can read the data to be computed (target data) from the same address space and complete the acceleration. After the computation is complete, an interrupt is sent to the host, i.e., an interrupt signal is fed back to the host. The host responds to the interrupt signal by notifying the FPGA to initiate a DMA operation, directly moving the computed result to the host memory, or notifying the SSD's DMA engine to move the target data and the accelerated computation result back to the SSD for storage. Thus, through the above hardware and software design, end-to-end DMA transmission of files from the SSD to the FPGA_DDR is achieved.

[0150] Based on the above embodiments, such as Figure 5 This is a schematic diagram of another heterogeneous acceleration system provided in an embodiment of this application. As an implementable approach, in one embodiment, a storage device is used to take the target data read by the target heterogeneous acceleration device as the original data that meets the current query conditions, and transmit the original data to the file caching system on the host side.

[0151] The accelerated calculation results include information about the current query conditions. For example... Figure 5 The heterogeneous acceleration system shown adopts an architecture combining CPUs and FPGA heterogeneous device clusters. Multiple FPGA clusters are connected to storage devices and the CPU host via switching chips supporting the CXL heterogeneous cache coherency protocol. Within each FPGA cluster, components are interconnected in a fully connected manner, and the number of FPGAs can be flexibly configured according to actual needs. Figure 5 Let's take a cluster of four FPGAs (heterogeneous acceleration cluster) as an example. In terms of data transmission, a P2P (memory-to-heterogeneous acceleration device) direct transmission mode is used, where the application controls the direct transmission of data from the storage device to the FPGA cluster.

[0152] Specifically, in one embodiment, heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate with each other using a fully connected method, while heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate with each other through a target protocol switch.

[0153] Specifically, the CPU host end runs a database software, which is responsible for receiving user query requests and data operation instructions, processing and analyzing data, and returning the results to the user or other application programs. The database software interacts with the database enhanced file system layer through the host interface to transfer data and instructions. The database enhanced file system layer performs read and write operations on files through the Portable Operating System Interface (POSIX) file system interface. The database enhanced file system layer includes a file cache system for storing raw data provided by storage devices such as disks, a device data cache and a computing unit management responsible for managing the data cache of devices (such as FPGA acceleration cards) and coordinating the work of computing units (computing modules in FPGA), ensuring efficient transmission and processing of data between devices and the host. The database enhanced file system layer links the original file system layer, which includes a file system interface and a metadata management module. The file system interface provides a bottom-level file system operation interface, responsible for interacting with actual storage devices to implement basic operations such as file storage, reading, and writing. The metadata management module is responsible for managing file metadata, such as file name, size, creation time, modification time, access permissions, and other information, ensuring that the file system can accurately locate and manage files. The host end connects to storage devices and heterogeneous acceleration clusters through the CXL exchange chip (target protocol switch) through the file system interface, realizing data storage and reading.

[0154] Among them, the CXL exchange chip (CXL switch) as the data exchange hub in the system, connect the host end, storage devices and multiple FPGA acceleration cards (heterogeneous acceleration cards), realize the high-speed transmission and exchange of data between them. CXL is a high-speed interconnection technology that can provide high-bandwidth, low-latency data transmission channels to meet the requirements of heterogeneous acceleration systems for data transmission performance. Connects with the host's original file system, storage devices and multiple FPGA acceleration cards respectively, forms a data transmission network, ensures efficient data communication between components.

[0155] Specifically, after obtaining the accelerated computing result and the original data, the host end can analyze the original data based on the current query condition information in the accelerated computing result, such as verifying the accuracy of the accelerated result.

[0156] On the basis of the above embodiments, as an implementable manner, in an embodiment, the host end is configured to obtain a global heterogeneous acceleration state table; the global heterogeneous acceleration state table includes global position information, acceleration unit function, current use, instruction type, current task execution information, and current resource occupation information of each acceleration unit; each heterogeneous acceleration device includes a plurality of acceleration units; according to acceleration computing demand represented by an acceleration computing request, the global heterogeneous acceleration state table is screened to select a candidate heterogeneous acceleration device whose acceleration unit function matches the acceleration computing demand; according to the global heterogeneous acceleration state table, the candidate heterogeneous acceleration device is screened to select a target heterogeneous acceleration device, so as to send the acceleration computing request to the target heterogeneous acceleration device.

[0157] In the global heterogeneous acceleration state table 1, the global position information of each acceleration unit is represented by coordinates, the acceleration unit function is represented by a function type, the current use is represented by a use type, the instruction type is represented by an instruction type, the current task execution information is represented by a task ID and an execution order number, and the current resource occupation information is represented by a resource allocation type.

[0158] Table 1

[0159]

[0160] In the global heterogeneous acceleration state table 1, the global position information of each acceleration unit is represented by coordinates, the acceleration unit function is represented by a function type, the current use is represented by a use type, the instruction type is represented by an instruction type, the current task execution information is represented by a task ID and an execution order number, and the current resource occupation information is represented by a resource allocation type.

[0161] Specifically, for each candidate heterogeneous acceleration device, the host end calculates a comprehensive load index according to the current use, the current task execution information, and the current resource occupation information. This index can be a weighted average value, which comprehensively considers the busy degree of the device, the resource remaining amount, and the like. For example, the busy degree of the device can be determined according to the number of tasks being processed and the complexity of the tasks, and the resource remaining amount can be weighted according to the memory idle space, the calculation resource idle proportion, and the like. Thus, the comprehensive load index of each candidate acceleration unit in the candidate heterogeneous acceleration device is obtained, and finally, the target acceleration unit is selected from the candidate acceleration units according to a preset load balancing strategy, and the candidate heterogeneous acceleration device including the target acceleration unit is selected as the target heterogeneous acceleration device. Thus, the system can more intelligently allocate the computing task, fully utilize the resources of the heterogeneous acceleration device, improve the overall performance and efficiency of the system, and ensure the timely processing of the task and the stable operation of the system.

[0162] Specifically, in an embodiment, the host can analyze the task execution feature of the acceleration computing request to obtain task execution feature information of the acceleration computing request; in a case where the task execution feature information indicates that the task execution mode of the acceleration computing request is a sequential mode, a plurality of target acceleration units are selected from the candidate heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster; and the candidate heterogeneous acceleration device including the target acceleration units is taken as the target heterogeneous acceleration device.

[0163] It should be noted that, in the heterogeneous acceleration system provided by the embodiments of the present application, the heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate in a full connection manner, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate through a target protocol switch. In a case where the task execution mode of the acceleration computing request is a sequential mode, since in the sequential mode, the acceleration units executed later need to take the intermediate results obtained by the acceleration units executed before as input, in order to reduce the delay of intermediate result transmission between the acceleration units, the embodiments of the present application select a plurality of target acceleration units from the candidate heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster, so as to avoid the cross-cluster communication in the task execution process, and further improve the heterogeneous acceleration efficiency.

[0164] Correspondingly, in an embodiment, in a case where the task execution feature information indicates that the task execution mode of the acceleration computing request is a disorder mode, a plurality of target acceleration units whose remaining computing resources satisfy a preset screening condition are selected from the candidate heterogeneous acceleration devices; and the candidate heterogeneous acceleration device including the target acceleration units is taken as the target heterogeneous acceleration device.

[0165] It should be noted that, in a case where the task execution mode of the acceleration computing request is a disorder mode, since the target acceleration units independently run without interaction in the execution process of the disorder mode, a plurality of target acceleration units whose remaining computing resources satisfy a preset screening condition can be selected from the candidate heterogeneous acceleration devices, and then the candidate heterogeneous acceleration device including the target acceleration units is taken as the target heterogeneous acceleration device.

[0166] Specifically, in actual application, a plurality of acceleration units with the most remaining computing resources can be taken as the plurality of target acceleration units whose remaining computing resources satisfy the preset screening condition.

[0167] Specifically, in an embodiment, the host end is also configured to generate a target token for the target heterogeneous acceleration device; the target token includes a valid bit, a physical address start address, a data length, a read-write permission bit, a unique identifier of the heterogeneous acceleration device, a unique identifier of the acceleration unit, and a target priority; the target token is sent to the corresponding target heterogeneous acceleration device according to the unique identifier of the heterogeneous acceleration device, so that the target heterogeneous acceleration device executes the to-be-executed heterogeneous acceleration task based on the target token to perform corresponding calculation processing on the target data and obtain an acceleration calculation result.

[0168] It should be noted that the heterogeneous acceleration system provided by the embodiments of the present application is in a multi-card environment in a heterogeneous acceleration cluster, and the target token (Token) is a mechanism for coordinating and controlling resource access and task execution order between multiple FPGA cards. It is similar to a kind of permission identifier, only FPGA card (target heterogeneous acceleration device) that obtains the target token can execute a specific operation or access shared resources, thereby avoiding conflicts and unordered competition between multiple cards. The shared resources include device memory.

[0169] As shown in FIG. 1, the target token includes a valid bit (1 bit), a physical address start address (64 bits), a data length (16 bits), a read-write permission bit (1 bit), a unique identifier of the heterogeneous acceleration device (8 bits), a unique identifier of the acceleration unit (16 bits), and a target priority (8 bits). The unique identifier of the heterogeneous acceleration device is the FPGA number, and the unique identifier of the acceleration unit is the acceleration unit ID. Figure 6 Correspondingly, in an embodiment, the target heterogeneous acceleration device is configured to receive the target token sent by the host end; in the case that the valid bit of the target token represents that the token is currently valid, the target acceleration unit of the to-be-executed heterogeneous acceleration task and the task type of the to-be-executed heterogeneous acceleration task are determined according to the unique identifier of the acceleration unit in the target token; the permission range of the target acceleration unit is determined according to the physical address start address, the data length, and the read-write permission bit in the target token; the permission range includes the target read-write range of the device memory; and the execution priority of the target acceleration unit is determined according to the target priority in the target token.

[0170]

[0171] ​Specifically, when an FPGA card obtains a target token, it first checks the permission range corresponding to the token. The token specifies the storage area that the card can access and the type of task that is allowed to be executed (such as a full table scan module, a sorting module, a regular expression module, a hash join module, etc.). According to the permissions granted by the target token, the FPGA card loads the corresponding target data from the local memory (device memory) (if the task data is not ready, it needs to wait for the data transmission to be completed), processes the target data according to the predetermined task logic. During processing, the validity of the token is continuously monitored, because the control management module on the card will decide to reclaim the token in advance and redistribute it according to the global situation. Once the task is executed, the FPGA card will perform the corresponding subsequent operation according to the system requirements, store the execution result to the specified location, and then return the target token to the control management module.

[0172] In the field of database acceleration, when multiple FPGA cards are used to process large-scale data, the token execution mode can reasonably allocate the access permissions of each card to the acceleration unit and input data, ensure that each card calculates in the correct order and with the correct permissions, avoid data conflicts and repeated calculations, and also avoid performance degradation or system crashes caused by resource competition. The FPGA multi-card token execution mode provides effective resource coordination and task execution guarantee for multi-card FPGA systems in various application scenarios, thereby improving the performance and stability of the system.

[0173] Correspondingly, in an embodiment, the host is configured to obtain the waiting period number of each candidate acceleration unit in the candidate heterogeneous acceleration device; determine the time priority of the candidate acceleration unit according to the waiting period number of the candidate acceleration unit; obtain the task priority of the to-be-executed heterogeneous acceleration task corresponding to the candidate acceleration unit; and determine the target priority according to the time priority and the task priority of the candidate acceleration unit.

[0174] Specifically, the determination rule of the target priority includes a time interval round-robin allocation strategy and a task priority allocation strategy. The time level is represented by 8 bits, and the waiting period is accumulated by 1 (the upper four bits represent the waiting level 0-15). The weight is set to 25%. The task priority is set to 0-15 levels, and the larger the number, the higher the priority. The weight is set to 75%. The task priority is set according to the execution demand of the user for the to-be-executed task, which is not limited in the embodiment of the present application. Finally, the target priority is determined according to the time priority and the task priority of the candidate acceleration unit. After calculation, the target token is given to the heterogeneous acceleration device to which the candidate acceleration unit with the highest score belongs. Global coordination and management are realized through the token mode, which can be accurately controlled according to the predetermined strategy.

[0175] The token method proposed by the embodiments of the present application can coordinate different tasks performed by each card according to specific task processes and priorities. The FPGA group in the cluster can configure core acceleration function IPs (acceleration units) such as data filtering, full table scanning, regular expression, sorting, and hash connection according to requirements. Meanwhile, the management module of the calculation unit in the FPGA is also covered. The system can adapt to new system scale by adjusting the token generation and distribution mechanism, increase or decrease the number of FPGA cards, and maintain stable operation of the system.

[0176] On the basis of the above-mentioned embodiments, as an implementable manner, in an embodiment, a target communication interface is arranged between the host and each heterogeneous acceleration device, the acceleration calculation request includes a database query statement, the target communication interface is configured to perform semantic analysis on the database query statement to obtain a semantic analysis result; target action instructions are extracted from the database query statement according to the semantic analysis result; and the database query statement is converted into a heterogeneous acceleration device universal statement according to the target action instructions, so as to input the heterogeneous acceleration device universal statement into the target heterogeneous acceleration device.

[0177] The target action instructions at least include data query instructions, data insertion instructions, data update instructions, and data deletion instructions.

[0178] It should be noted that the database query statement is usually generated by a user or an application program, and is used to obtain and operate data from a database. The database query statement has different syntax structures and expression methods, and direct sending of the database query statement to the heterogeneous acceleration device may not be correctly understood and executed.

[0179] Specifically, the target communication interface uses relevant semantic analysis techniques and algorithms to analyze the database query statement to analyze keywords, operators, table names, field names and other elements in the statement, determine the database operation type, data range, conditions and other information involved in the statement, and obtain a semantic analysis result, and then accurately extract corresponding target action instructions from the database query statement according to the semantic analysis result.

[0180] Specifically, the heterogeneous acceleration device generally has its own specific instruction set and data processing method, which may not be compatible with the database query statement sent by the host. Therefore, the database query statement is converted into a heterogeneous acceleration device universal statement so that the heterogeneous acceleration device can understand and execute it. The statement conversion involves syntax structure adjustment, data format conversion, operator mapping, etc. For example, some functions or operators in the database query statement can be converted into equivalent forms that can be recognized and executed by the heterogeneous acceleration device, while ensuring that the converted statement can accurately realize the function and intention of the original statement.

[0181] Specifically, the target communication interface is located between the host software and the FPGA hardware, responsible for defining clear interaction rules and data formats. It receives operation requests from the host database application on the one hand, and sends converted FPGA understandable instructions (heterogeneous acceleration device general statement) to the FPGA hardware on the other hand, and receives FPGA processed results and original data feedback to the host software.

[0182] Among them, the instruction conversion module is one of the core parts of the target communication interface, responsible for parsing various query statements (such as SQL statements) and operation instructions (such as insert, delete, update, etc.) from the host database, and converting them into specific format instructions (FPGA instruction parsing module corresponding processing in FPGA) that FPGA can understand according to the predefined mapping rules. The embodiment of the present application adopts a self-defined binary format for data encapsulation. For database query statements, it is split and encoded according to specific fields. The keywords (SELECT, FROM, WHERE, etc.), table names, column names, condition values, etc. in the SQL statement are represented by 8-bit binary code respectively, and combined into a complete query instruction according to a certain order and sent to FPGA. For the return result, FPGA also encapsulates it according to the specified format, adds row identification and result status identification, etc. information, so that the host software can accurately parse it. Among them, the current query condition information includes row identification and result status identification, and the result status identification represents whether this query hits.

[0183] Specifically as follows: define instructions for data query (SELECT), data insertion (INSERT), data update (UPDATE), and data deletion (DELETE) operations. The operation code uses 2 bits, SELECT format "00", INSERT format "01", UPDATE format "10", and DELETE format "11".

[0184] Data query instruction, its format includes operation code "00" (representing query operation), table identification (16-bit representation, 8-bit representation corresponding to the database table to be queried, 8-bit representation corresponding to the connected database table), column identification (8-bit number representation, corresponding column number), condition judgment and screening keyword (WHERE corresponds to "00" indicating, specifying screening condition; GROUP BY corresponds to "01" indicating, used for grouping query; ORDER BY corresponds to "10" indicating, used for sorting query result; HAVING corresponds to "11" indicating, after grouping operation, used for further screening grouped result), condition expression value (used for specifying query condition) and additional field identification (COUNT corresponds to "0000" indicating, SUM corresponds to "0001" indicating, AVG corresponds to "0010" indicating, MIN corresponds to "0011" indicating, MAX corresponds to "0100" indicating) and the like. After FPGA receives such instruction, specific query task to be executed can be clearly known.

[0185] Data insertion instruction: its format includes operation code "01" (representing insertion operation), table identification (8-bit representation, 8-bit representation corresponding to the database table to be queried), column identification (8-bit number representation, corresponding column number), column value (64-bit representation, corresponding numerical value).

[0186] Data update instruction: its format includes operation code "10" (representing update operation), table identification (8-bit representation, 8-bit representation corresponding to the database table to be queried), column identification (8-bit number representation, corresponding column number), column value (64-bit representation, corresponding numerical value), condition judgment and screening keyword (WHERE corresponds to "00" indicating, specifying screening condition), condition expression value (used for specifying query condition).

[0187] Data deletion instruction: its format includes operation code "11" (representing deletion operation), table identification (8-bit representation, 8-bit representation corresponding to the database table to be queried), condition judgment and screening keyword (WHERE corresponds to "00" indicating, specifying screening condition): condition expression value (used for specifying query condition).

[0188] Further, after the target heterogeneous acceleration device completes the acceleration calculation, the calculation result is fed back to the host end by the FPGA in the FPGA cluster connected with the host. The calculation result contains the location information of the data meeting the query condition, such as the page number, the row number, and the like. In the host end, the original data page where the row data meeting the query condition is located is transmitted from the storage device to the host end through a traditional transmission path, to be used as a data cache. The converted FPGA-understandable instruction is sent to the FPGA hardware through the self-defined callback module, and after the acceleration is completed, the calculation result is fed back to the callback module for processing, so as to realize the customized control over the interaction process between the database and the FPGA.

[0189] For the heterogeneous acceleration system provided by the embodiments of the present application, the communication between the storage device, the host end and the heterogeneous acceleration device adopts the CXL protocol, and a new data transmission mode is constructed based on the unified memory addressing and direct access characteristics of the CXL technology. In this mode, byte granularity data access with cache consistency can be ensured. Traditional data transmission usually involves multiple levels of cache, copying and complex bus transmission protocol conversion, which is not only cumbersome, but also easy to cause data delay and inconsistency. The CXL technology directly breaks through this barrier and establishes a direct channel between the data source and the target storage through the peer-to-peer end-to-end transmission mode.

[0190] From the perspective of database file transmission, the data needs to be transferred in the file system cache, the application layer page and the like for multiple times, and then transmitted to the heterogeneous acceleration device through DMA and the like. This process involves many links, and each link may introduce delay and consume a large amount of system resources. The peer-to-peer end-to-end transmission realized by the CXL technology can directly transmit the database file from the storage source to the acceleration card memory and the host memory, skipping unnecessary transfer links.

[0191] In terms of byte granularity data access with cache consistency, the CXL enables the CPU to operate on the host memory and the acceleration card memory as if in a unified memory space. This means that the interaction of data between different devices does not need to perform complex data format conversion and synchronization operation, greatly improving the data processing efficiency. At the same time, the advantage of greatly reducing the access path directly leads to the reduction of delay. Data does not need to be transmitted in a roundabout way between multiple levels of cache and devices, but flows directly along the optimized end-to-end path, thereby meeting the needs of modern database systems for efficient data processing and low delay response. This method opens up a new path for data transmission under the heterogeneous computing architecture, and is expected to play an important role in the fields of database management and big data processing, and improve the performance and reliability of the overall system.

[0192] The system provided by the embodiments of the present application supports more hardware acceleration modules of computing-intensive operations. Due to the limitation of FPGA resources, the microarchitecture in a fixed mode is used in the related art, which causes low performance and resource utilization in different application scenarios of a database. In the field of heterogeneous computing, the resource pooling technology provides a new idea for improving performance. This configurable architecture can adapt to diversified application requirements. When facing different data processing scenarios, the efficient use of resources can be realized by flexibly adjusting the configuration of the acceleration function in the FPGA.

[0193] The embodiments of the present application provide a system supporting multi-FPGA database acceleration, which aims to significantly improve the performance of a database by using multiple field programmable gate arrays (FPGAs). Specifically, the FPGAs are processed in clusters, and a token pipelining mode is used in the cluster to realize the pooling of acceleration modules. In the data processing flow, the clustered FPGAs work cooperatively. For example, in the data filtering link, the FPGA reasonably configured can quickly screen out data meeting the conditions, reducing unnecessary data transmission and processing. The token pipelining mode ensures the ordered processing of data in the cluster and improves the processing efficiency.

[0194] Through the pooling of the acceleration modules, each FPGA can be flexibly optimized and configured according to different database application scenarios, so as to improve the overall performance. In different scenarios, such as in a transaction database with high demand for data encryption and decryption, sorting and aggregation operations are also frequent when processing order data. The configurable FPGA acceleration architecture can reasonably allocate FPGA resources according to these scenario characteristics, a part of which is used for encryption and decryption, and another part is used for sorting and aggregation operations, so as to improve the performance of the entire database system in this scenario and meet the business requirements.

[0195] The heterogeneous acceleration system provided by the embodiment of the application comprises a host end, a plurality of heterogeneous acceleration clusters and a storage device for storing target data, the heterogeneous acceleration cluster comprises a plurality of heterogeneous acceleration devices; the host end is configured to send an acceleration calculation request to the heterogeneous acceleration cluster; any target heterogeneous acceleration device in the heterogeneous acceleration cluster is configured to, in response to the acceleration calculation request, directly read the target data from the storage device by using a preset direct transmission mode, perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and write the acceleration calculation result into a target cache device, when the acceleration calculation request is received; and the host end is configured to directly access the target cache device to obtain the acceleration calculation result. The system provided by the above scheme can directly obtain the target data from the storage device by using the data direct transmission mode, so that the database file page can be directly transmitted from the disk to the FPGA without being forwarded by the CPU, the transmission path of the target data is greatly shortened, the time consumption of the target data in the transmission process is reduced, and the data transmission delay of the target heterogeneous acceleration device is reduced, thereby laying a foundation for improving the performance of the computing device. Moreover, the CXL Switch is connected with the host and the storage device, and the consistency and scalability of the data on the heterogeneous device are ensured. Inside the FPGA cluster, the components are interconnected in a full connection mode, the intra-cluster communication delay is reduced, and the number of FPGAs in the cluster can be flexibly configured according to actual needs. Moreover, the control mode adopts a token method, different tasks are executed by the cards according to a specific task flow and priority, the FPGA group in the cluster can be configured with different core acceleration IPs according to needs, clear interaction rules and data formats are defined, operation requests from the host database application are received, converted into FPGA understandable instructions and sent to the FPGA hardware, the calculation results processed by the FPGA are fed back to the host system, and the original data page (original data) where the qualified row data is located is directly transmitted back to the host end by the storage device to be used as data cache.

[0196] The embodiment of the application provides a heterogeneous acceleration method, which is used for reducing the data transmission delay of target data to a heterogeneous acceleration device in the case of accelerating a host end computing task based on the heterogeneous acceleration device.

[0197] As shown in Figure 7 , a flowchart of a heterogeneous acceleration method provided by the embodiment of the application is shown, the method comprises the following steps:

[0198] Step 701: Send an accelerated computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster, so as to directly read the target data from the storage device based on the heterogeneous acceleration device and adopt a preset direct transmission mode. The storage device is used to store the target data and perform corresponding calculation processing on the target data to obtain the accelerated computing result, and write the accelerated computing result to the target cache device.

[0199] Step 702: When it is determined that the heterogeneous acceleration device has written the accelerated computing results to the target cache device, the target cache device is directly accessed to obtain the accelerated computing results.

[0200] Regarding the heterogeneous acceleration method in this embodiment, the specific implementation of each step has been described in detail in the embodiments related to the heterogeneous acceleration system, and will not be elaborated here.

[0201] The heterogeneous acceleration method provided in this application is applied to the host side of the heterogeneous acceleration system provided in the above embodiments. Its implementation method and principle are the same, and will not be described again.

[0202] This application provides a heterogeneous acceleration method to reduce data transmission latency from target data to the heterogeneous acceleration device while accelerating host-side computing tasks based on the heterogeneous acceleration device. The execution subject of this application is the target heterogeneous acceleration device in the heterogeneous acceleration system provided in the above embodiments.

[0203] like Figure 8 The diagram shown is a flowchart of another heterogeneous acceleration method provided in this application embodiment. The method includes:

[0204] Step 801: Receive the accelerated computing request sent by the host.

[0205] Step 802: In response to the accelerated computing request, the target data is read directly from the storage device using a preset direct transfer mode; wherein the storage device is used to store the target data.

[0206] Step 803: Perform corresponding calculations on the target data to obtain accelerated calculation results, and write the accelerated calculation results to the target cache device.

[0207] Step 804: Send an interrupt request to the host to instruct the host to directly access the target cache device, so that the host can obtain accelerated calculation results.

[0208] Regarding the heterogeneous acceleration method in this embodiment, the specific implementation of each step has been described in detail in the embodiments related to the heterogeneous acceleration system, and will not be elaborated here.

[0209] The heterogeneous acceleration method provided in this application is applied to the target heterogeneous acceleration device in the heterogeneous acceleration system provided in the above embodiments. Its implementation method and principle are the same, and will not be described again.

[0210] This application provides a heterogeneous acceleration device for executing the heterogeneous acceleration method provided in the above embodiments.

[0211] like Figure 9 The diagram shown is a structural schematic of a heterogeneous acceleration device provided in an embodiment of this application. The heterogeneous acceleration device 90 includes: a request acceleration module 901 and a read module 902.

[0212] The request acceleration module is used to send an acceleration computing request to any target heterogeneous acceleration device in the heterogeneous acceleration cluster. Based on the heterogeneous acceleration device, it uses a preset direct transmission mode to directly read target data from the storage device. The storage device is used to store the target data and perform corresponding calculations on the target data to obtain the acceleration computing result, which is then written to the target cache device. The read module is used to directly access the target cache device to obtain the acceleration computing result when it is determined that the heterogeneous acceleration device has written the acceleration computing result to the target cache device.

[0213] Regarding the heterogeneous acceleration device in this embodiment, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0214] The heterogeneous acceleration device provided in this application embodiment is used to execute the heterogeneous acceleration method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0215] This application provides a heterogeneous acceleration device for executing the heterogeneous acceleration method provided in the above embodiments.

[0216] like Figure 10 The diagram shown is a structural schematic of another heterogeneous acceleration device provided in an embodiment of this application. The heterogeneous acceleration device 100 includes: a receiving module 1001, a data reading module 1002, an accelerated computing module 1003, and a transmitting module 1004.

[0217] The system includes a receiving module for receiving accelerated computing requests from the host; a data reading module for responding to the accelerated computing requests by directly reading target data from a storage device using a preset direct transmission mode; the storage device for storing the target data; an accelerated computing module for performing corresponding calculations on the target data to obtain accelerated computing results and writing the results to the target cache device; and a sending module for sending an interrupt request to the host to instruct the host to directly access the target cache device so that the host can obtain the accelerated computing results.

[0218] As to the specific way in which each module performs operations in the heterogeneous acceleration device in this embodiment, detailed descriptions have been made in the embodiments related to the method, and thus will not be elaborated here.

[0219] The heterogeneous acceleration device provided by the embodiments of the present application is used to perform the heterogeneous acceleration method provided by the above embodiments, and has the same implementation manner and principle, and thus will not be elaborated here.

[0220] The embodiments of the present application provide a computing device for deploying the heterogeneous acceleration system provided by the above embodiments.

[0221] As shown in FIG. 1, it is a structural schematic diagram of the computing device provided by the embodiments of the present application. The computing device comprises the heterogeneous acceleration system provided by the above embodiments. Figure 11

[0222] Among them, the computing device can be a server or the like.

[0223] The electronic device provided by the embodiments of the present application is used to deploy the heterogeneous acceleration system provided by the above embodiments, and has the same implementation manner and principle, and thus will not be elaborated here.

[0224] The embodiments of the present application provide a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores computer execution instructions. When the processor executes the computer execution instructions, the heterogeneous acceleration method provided by any one of the above embodiments is realized.

[0225] The storage medium containing computer executable instructions provided by the embodiments of the present application can be used to store the computer execution instructions of the heterogeneous acceleration method provided in the above embodiments, and has the same implementation manner and principle, and thus will not be elaborated here.

[0226] The embodiments of the present application provide a computer program product comprising computer instructions, and the computer instructions are used to make a computer execute the heterogeneous acceleration method provided in the above embodiments.

[0227] The computer program product provided by the embodiments of the present application can be used to execute the computer instructions of the heterogeneous acceleration method provided in the above embodiments, and has the same implementation manner and principle, and thus will not be elaborated here.

[0228] ​In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented by other manners. For example, the apparatus embodiments described above are merely illustrative, for example, the division of units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or components shown or discussed can be indirect coupling or communication connection through some interfaces, apparatuses or units, and can be electrical, mechanical or other forms.

[0229] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0230] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0231] The integrated unit realized in the form of software functional unit can be stored in a computer readable storage medium. The software functional unit stored in a storage medium includes a plurality of instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor execute part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0232] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be invoked or provided. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file and the like, and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0233] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional modules is exemplified, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can refer to the corresponding process in the foregoing method embodiments, which will not be described here.

[0234] The above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A heterogeneous acceleration system, comprising: include: The system includes a host, several heterogeneous acceleration clusters, and a storage device for storing target data, wherein the heterogeneous acceleration clusters include multiple heterogeneous acceleration devices. The host is used to send accelerated computing requests to the heterogeneous acceleration cluster; Upon receiving the accelerated computing request, any target heterogeneous acceleration device in the heterogeneous acceleration cluster, in response to the accelerated computing request, directly reads target data from the storage device using a preset direct transmission mode, performs corresponding calculations on the target data to obtain the accelerated computing result, and writes the accelerated computing result into the target cache device; heterogeneous acceleration devices within the same heterogeneous acceleration cluster communicate using a fully connected method, while heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate through a target protocol switch; The host is used to directly access the target cache device to obtain the accelerated computing results; wherein, the target cache device includes the device memory and storage device of the target heterogeneous acceleration device and the system memory of the host, the device memory and the system memory are uniformly addressed, and cache consistency is maintained based on hardware, so that the host accessing the device memory is equivalent to accessing the system memory; The host terminal is also used for: Generate a target token for the target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address start address, a data length, a read / write permission bit, a unique identifier for the heterogeneous acceleration device, a unique identifier for the acceleration unit, and a target priority; Based on the unique identifier of the heterogeneous acceleration device, the target token is sent to the corresponding target heterogeneous acceleration device, so that the target heterogeneous acceleration device executes the heterogeneous acceleration task to be executed based on the target token, and performs corresponding calculations on the target data to obtain accelerated calculation results. Among them, executing heterogeneous acceleration tasks includes performing specific operations or accessing shared resources, including device memory.

2. The system of claim 1, wherein, The target heterogeneous acceleration device includes: The target protocol control module is used to receive the accelerated computing request sent by the host; wherein, the target cache device includes the device memory of the target heterogeneous acceleration device, and the host directly accesses the device memory through the target protocol control module to keep the cache consistent between the host and the target heterogeneous acceleration device; The target protocol control module is connected to the target protocol switch so that the target heterogeneous acceleration device can communicate with the host and storage devices through the target protocol switch.

3. The system of claim 1, wherein, The host terminal is used for: Request the raw data input by the user; In response to the original data request, allocate a virtual address for the target data on the target heterogeneous acceleration device; Based on the virtual address and the original data request, determine the configuration parameters for the accelerated computing request; Based on the configuration parameters of the accelerated computing request, an accelerated computing request is generated and sent to the target heterogeneous acceleration device.

4. The system of claim 3, wherein, The host terminal is used for: Translate the virtual address into a physical address in the device memory of the heterogeneous accelerator card; determine a bus address according to the physical address, and take the bus address as a destination address; determine file index information of a file to be accessed and a logical offset value of target data in the file to be accessed according to the original data request; determine a source address and a data length of the target data in the storage device according to the file index information of the file to be accessed and the logical offset value of the target data in the file to be accessed; generate a direct storage device access descriptor according to the destination address, the source address and the data length; generate an acceleration calculation request based on the direct storage device access descriptor, so that the target heterogeneous acceleration device responds to the acceleration calculation request based on a direct storage device access engine.

5. The system of claim 4, wherein, The target cache device includes a device memory of a target heterogeneous acceleration device, and the target heterogeneous acceleration device is configured to: send an access start command to the storage device in response to the acceleration calculation request, so that the storage device responds to the access start command, adopts a preset direct transmission mode, and moves the target data to a peer access space in the device memory according to the destination address; write the acceleration calculation result into the peer access space when the acceleration calculation result is obtained; The peer access space in the device memory is exposed on a peer communication bus of the target heterogeneous acceleration device, and the peer access space supports direct access of the host end and the storage device.

6. The system of claim 5, wherein, The host end is configured to: receive an interrupt signal fed back by the target heterogeneous acceleration device when the acceleration calculation result is obtained, and perform direct access on the peer access space of the target heterogeneous acceleration device in response to the interrupt signal, so as to obtain the acceleration calculation result.

7. The system of claim 1, wherein, The storage device is configured to: take the target data read by the target heterogeneous acceleration device as original data conforming to a current query condition, and transmit the original data to a file cache system of the host end. The acceleration calculation result includes current query condition information.

8. The system of claim 1, wherein, The host end is configured to: obtain a global heterogeneous acceleration state table; the global heterogeneous acceleration state table includes global position information, acceleration unit function, current use, instruction type, current task execution information and current resource occupation information of each acceleration unit, and each heterogeneous acceleration device includes a plurality of acceleration units; screen a selected heterogeneous acceleration device in which the acceleration unit function matches the acceleration calculation demand from the global heterogeneous acceleration state table according to the acceleration calculation demand represented by the acceleration calculation request; screen a target heterogeneous acceleration device from the selected heterogeneous acceleration device according to the global heterogeneous acceleration state table, so as to send the acceleration calculation request to the target heterogeneous acceleration device.

9. The system of claim 8, wherein, The host end is configured to: analyze task execution characteristics of the acceleration calculation request to obtain task execution characteristic information of the acceleration calculation request; screen a plurality of target acceleration units from selected heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster in a case where a task execution mode of the acceleration calculation request is represented by the task execution characteristic information. The target cache device includes a device memory of a target heterogeneous acceleration device, and the target heterogeneous acceleration device is configured to: send an access start command to the storage device in response to the acceleration calculation request, so that the storage device responds to the access start command, adopts a preset direct transmission mode, and moves the target data to a peer access space in the device memory according to the destination address; write the acceleration calculation result into the peer access space when the acceleration calculation result is obtained; The peer access space in the device memory is exposed on a peer communication bus of the target heterogeneous acceleration device, and the peer access space supports direct access of the host end and the storage device. The host end is configured to: receive an interrupt signal fed back by the target heterogeneous acceleration device when the acceleration calculation result is obtained, and perform direct access on the peer access space of the target heterogeneous acceleration device in response to the interrupt signal, so as to obtain the acceleration calculation result. The storage device is configured to: take the target data read by the target heterogeneous acceleration device as original data conforming to a current query condition, and transmit the original data to a file cache system of the host end. The acceleration calculation result includes current query condition information. The host end is configured to: obtain a global heterogeneous acceleration state table; the global heterogeneous acceleration state table includes global position information, acceleration unit function, current use, instruction type, current task execution information and current resource occupation information of each acceleration unit, and each heterogeneous acceleration device includes a plurality of acceleration units; screen a selected heterogeneous acceleration device in which the acceleration unit function matches the acceleration calculation demand from the global heterogeneous acceleration state table according to the acceleration calculation demand represented by the acceleration calculation request; screen a target heterogeneous acceleration device from the selected heterogeneous acceleration device according to the global heterogeneous acceleration state table, so as to send the acceleration calculation request to the target heterogeneous acceleration device. The host end is configured to: analyze task execution characteristics of the acceleration calculation request to obtain task execution characteristic information of the acceleration calculation request; in a case where a task execution mode of the acceleration calculation request is represented by the task execution characteristic information, screen a plurality of target acceleration units from selected heterogeneous acceleration devices belonging to the same heterogeneous acceleration cluster. The target heterogeneous acceleration device is selected as the target heterogeneous acceleration device from the candidate heterogeneous acceleration device including the target acceleration unit.

10. The system of claim 9, wherein, The host end is configured to: In a case where the task execution feature information represents that the task execution mode of the acceleration calculation request is an out-of-order mode, the target acceleration unit is selected from the candidate heterogeneous acceleration device in which the remaining computing resources meet the preset screening condition. The target heterogeneous acceleration device is selected as the target heterogeneous acceleration device from the candidate heterogeneous acceleration device including the target acceleration unit.

11. The system of claim 1, wherein, The target heterogeneous acceleration device is configured to: receive the target token sent by the host end; in a case where the valid bit of the target token represents that the token is currently valid, determine the target acceleration unit of the heterogeneous acceleration task to be executed and the task type of the heterogeneous acceleration task to be executed according to the acceleration unit unique identifier in the target token; determine the authority range of the target acceleration unit according to the physical address start address, the data length and the read-write permission bit in the target token; the authority range includes a target read-write range of the target cache device; determine the execution priority of the target acceleration unit according to the target priority in the target token.

12. The system of claim 8, wherein, The host end is configured to: obtain the number of waiting cycles of each candidate acceleration unit in the candidate heterogeneous acceleration device; determine the time priority of the candidate acceleration unit according to the number of waiting cycles of the candidate acceleration unit; obtain the task priority of the heterogeneous acceleration task to be executed corresponding to the candidate acceleration unit; determine the target priority according to the time priority and the task priority of the candidate acceleration unit.

13. The system of claim 1, wherein, The target communication interface is provided between the host end and each of the heterogeneous acceleration devices, the acceleration calculation request includes a database query statement, and the target communication interface is configured to: perform semantic analysis on the database query statement to obtain a semantic analysis result; extract a target action instruction from the database query statement according to the semantic analysis result; convert the database query statement into a heterogeneous acceleration device universal statement according to the target action instruction, and input the heterogeneous acceleration device universal statement into the target heterogeneous acceleration device. The target action instruction at least includes a data query instruction, a data insertion instruction, a data update instruction and a data deletion instruction.

14. A heterogeneous acceleration method, comprising: The method is applied to a host end, and the method includes: sending an acceleration calculation request to any target heterogeneous acceleration device in a heterogeneous acceleration cluster, so as to directly read target data from a storage device in a preset direct transmission mode based on the heterogeneous acceleration device, the storage device is configured to store target data and perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and the acceleration calculation result is written into a target cache device; the heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate in a full connection mode, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate through a target protocol switch. When it is determined that the heterogeneous acceleration device has written the acceleration calculation result into a target cache device, directly accessing the target cache device to obtain the acceleration calculation result; wherein the target cache device includes a device memory of a target heterogeneous acceleration device, a storage device, and a system memory of a host end, the device memory and the system memory implement unified addressing, and cache consistency is maintained based on hardware, so that the host end accessing the device memory is equivalent to accessing the system memory; The method further includes: generating a target token for the target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address start address, a data length, a read-write permission bit, a heterogeneous acceleration device unique identifier, an acceleration unit unique identifier, and a target priority; sending the target token to a corresponding target heterogeneous acceleration device according to the heterogeneous acceleration device unique identifier, so that the target heterogeneous acceleration device executes a to-be-executed heterogeneous acceleration task based on the target token to perform corresponding calculation processing on the target data to obtain an acceleration calculation result; wherein executing the to-be-executed heterogeneous acceleration task includes executing a specific operation or accessing a shared resource, and the shared resource includes a device memory.

15. A heterogeneous acceleration method, comprising: The method is applied to a target heterogeneous acceleration device, and the method includes: receiving an acceleration calculation request sent by a host end; in response to the acceleration calculation request, directly reading target data from a storage device in a preset direct transmission mode; wherein the storage device is used to store target data; performing corresponding calculation processing on the target data to obtain an acceleration calculation result, and writing the acceleration calculation result into a target cache device; the target cache device includes a device memory of a target heterogeneous acceleration device, a storage device, and a system memory of a host end, the device memory and the system memory implement unified addressing, and cache consistency is maintained based on hardware, so that the host end accessing the device memory is equivalent to accessing the system memory; sending an interrupt request to the host end to instruct the host end to directly access the target cache device, so that the host end obtains the acceleration calculation result; The method further includes: receiving a target token sent by a host end to execute a to-be-executed heterogeneous acceleration task based on the target token to perform corresponding calculation processing on the target data to obtain an acceleration calculation result; wherein the host end generates a target token for the target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address start address, a data length, a read-write permission bit, a heterogeneous acceleration device unique identifier, an acceleration unit unique identifier, and a target priority; and the target token is sent to a corresponding target heterogeneous acceleration device according to the heterogeneous acceleration device unique identifier; wherein executing the to-be-executed heterogeneous acceleration task includes executing a specific operation or accessing a shared resource, and the shared resource includes a device memory.

16. A heterogeneous acceleration device, comprising: The device is applied to a host end, and the device includes: The request acceleration module is configured to send an acceleration calculation request to any target heterogeneous acceleration device in a heterogeneous acceleration cluster, to read target data directly from a storage device based on the heterogeneous acceleration device in a preset direct transmission mode, to perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and to write the acceleration calculation result into a target cache device; the heterogeneous acceleration devices in the same heterogeneous acceleration cluster communicate in a full connection mode, and the heterogeneous acceleration devices in different heterogeneous acceleration clusters communicate through a target protocol switch; The reading module is configured to directly access the target cache device to obtain the acceleration calculation result when it is determined that the heterogeneous acceleration device has written the acceleration calculation result into the target cache device; wherein the target cache device includes a device memory of the target heterogeneous acceleration device, the storage device, and a system memory of the host end, the device memory and the system memory are implemented in unified addressing, and cache consistency is maintained based on hardware, so that the host end accessing the device memory is equivalent to accessing the system memory; The request acceleration module is further configured to: generate a target token for the target heterogeneous acceleration device; wherein the target token includes a valid bit, a physical address start address, a data length, a read-write permission bit, a heterogeneous acceleration device unique identifier, an acceleration unit unique identifier, and a target priority; send the target token to the corresponding target heterogeneous acceleration device according to the heterogeneous acceleration device unique identifier, so that the target heterogeneous acceleration device performs a to-be-executed heterogeneous acceleration task based on the target token to perform corresponding calculation processing on the target data to obtain an acceleration calculation result; wherein performing the to-be-executed heterogeneous acceleration task includes performing a specific operation or accessing a shared resource, and the shared resource includes a device memory.

17. A heterogeneous acceleration device, comprising: The device is applied to a target heterogeneous acceleration device, and the device includes: a receiving module configured to receive an acceleration calculation request sent by a host end; a data reading module configured to directly read target data from a storage device in a preset direct transmission mode in response to the acceleration calculation request; wherein the storage device is configured to store target data; an acceleration calculation module configured to perform corresponding calculation processing on the target data to obtain an acceleration calculation result, and to write the acceleration calculation result into a target cache device; the target cache device includes a device memory of the target heterogeneous acceleration device, the storage device, and a system memory of the host end, the device memory and the system memory are implemented in unified addressing, and cache consistency is maintained based on hardware, so that the host end accessing the device memory is equivalent to accessing the system memory; a sending module configured to send an interrupt request to the host end to instruct the host end to directly access the target cache device, so that the host end obtains the acceleration calculation result; The acceleration calculation module is further configured to: receive a target token sent by the host end, to perform a to-be-executed heterogeneous acceleration task based on the target token to perform corresponding calculation processing on the target data to obtain an acceleration calculation result; The host end generates a target token for the target heterogeneous acceleration device; the target token includes a valid bit, a physical address start address, a data length, a read-write permission bit, a heterogeneous acceleration device unique identifier, an acceleration unit unique identifier, and a target priority; and the target token is sent to the corresponding target heterogeneous acceleration device according to the heterogeneous acceleration device unique identifier. The executing the to-be-executed heterogeneous acceleration task includes executing a specific operation or accessing a shared resource, and the shared resource includes a device memory.

18. A computing device, comprising: The application relates to a heterogeneous acceleration system. The non-volatile computer readable storage medium stores computer execution instructions, and when the processor executes the computer execution instructions, the method in claims 14 or 15 is realized.

19. A non-transitory computer readable storage medium, comprising: The computer instructions are used for making the computer execute the method in claims 14 or 15.

20. A computer program product, characterised in that, ​

Images