A coarse-grained reconfigurable chip mapping method and device based on pre-scheduling

Abstract

The present invention relates to the field of chip compilation mapping technology, and in particular to a method and device for coarse-grained reconfigurable chip mapping based on pre-scheduling. The method comprises: compiling an intermediate representation through a compiler front end according to an input program; constructing a data flow graph structure according to the intermediate representation; pre-scheduling according to the data flow graph and reconfigurable chip structure information to obtain a time period for the operation; searching the mapping results according to the pre-allocated time period to determine the final mapping scheme; and generating configuration information for execution on the coarse-grained reconfigurable chip. The present invention can effectively reduce the complexity of the mapping algorithm, improve the execution performance of tasks on the coarse-grained reconfigurable chip, fully consider the heterogeneous resources on the coarse-grained reconfigurable chip during the mapping process, and is suitable for multi-node and complex-structured data flow graph mapping in complex tasks, significantly improving the mapping efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip compilation technology, and in particular to a coarse-grained reconfigurable chip mapping method and device based on pre-scheduling. Background Art

[0002] With the recent development of technologies such as artificial intelligence, large language models, big data, and cloud computing, the hardware requirements for various computing tasks have become increasingly stringent. This has led to the need for hardware processors with larger scale, higher performance, and greater energy efficiency. Reconfigurable processors, such as coarse-grained reconfigurable architectures (CGRAs), offer high energy efficiency while maintaining sufficient configuration flexibility. They combine the high flexibility of general-purpose processors with the high performance of application-specific integrated circuits (ASICs).

[0003] To leverage CGRA's advantages in performance, energy efficiency, and flexibility, a key task is solving the loop mapping problem during compilation. Loops account for a significant portion of the time in compute- and storage-intensive applications, making them suitable for acceleration using spatially parallel architectures like CGRA. The CGRA compiler typically spends a significant amount of time solving loop mapping problems. When the loop body is large and the generated data flow graph has many nodes and edges, solving complex problems like loop mapping incurs significant time overhead. Therefore, accelerating compilation and solving loop mapping problems is extremely important.

[0004] However, with the growth of data flow graph scale and complexity, existing loop mapping acceleration methods are mainly based on traditional search methods and integer linear programming methods to directly solve complex mapping problems, which requires a large time cost and easily leads to the inability to obtain loop mapping results or low execution performance of the program on coarse-grained reconfigurable chips. Summary of the Invention

[0005] To address the technical issues in the prior art where, as the scale and complexity of data flow graphs increase, existing loop mapping acceleration methods primarily rely on traditional search methods and integer linear programming methods to directly solve complex mapping problems, which consumes a significant amount of time and easily leads to the inability to obtain loop mapping results or low program execution performance on coarse-grained reconfigurable chips, the present invention provides a coarse-grained reconfigurable chip mapping method and apparatus based on pre-scheduling. The technical solution is as follows:

[0006] On the one hand, a method for coarse-grained reconfigurable chip mapping based on pre-scheduling is provided, characterized in that the method includes:

[0007] S1. Input a preset input program into the compiler front end, and output an intermediate representation of the source code in the preset input program;

[0008] S2. Build a data flow graph structure based on the intermediate representation;

[0009] S3. Obtaining coarse-grained reconfigurable chip structure information; pre-scheduling each operation in the data flow graph according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation;

[0010] S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period, and a mapping solution is obtained using a heuristic search method;

[0011] S5. Based on the mapping solution, generate configuration information executed on the coarse-grained reconfigurable chip, and complete the coarse-grained reconfigurable chip mapping based on pre-scheduling.

[0012] Optionally, in S1, inputting the preset input program into the compiler front end and outputting an intermediate representation of the source code in the preset input program includes:

[0013] S11. Obtain a preset input program; the preset input program is a high-level language code written in C, C++, or Python, and annotates loops that need to be accelerated on the coarse-grained reconfigurable chip;

[0014] S12, inputting the preset input program into the compiler front end, and outputting an intermediate representation of the source code in the preset input program;

[0015] The intermediate representation is the LLVM (The LLVM Compiler Infrastructure) intermediate representation in the .ll format. The preset input program is input to the compiler front end and the intermediate representation is output.

[0016] Optionally, in S2, a data flow graph structure is constructed based on the intermediate representation, including:

[0017] Based on the intermediate representation, the operations of the program and the dependencies between the operations are constructed into a data flow graph structure; wherein the data flow graph structure includes: nodes in the data flow graph and edges in the data flow graph.

[0018] Optionally, nodes in the data flow graph include: corresponding operations in the LLVM intermediate representation, including addition, multiplication, reading, writing, bitwise operations, and other operations, complex tasks or simple tasks;

[0019] The edges in the data flow graph represent the dependency information between computing operations.

[0020] Optionally, the coarse-grained reconfigurable chip structure information includes:

[0021] Processing unit information, including the number of processing units in the chip and how they are connected to each other;

[0022] Memory cell information, including the number of memory cells in the chip and the cache hierarchy;

[0023] and operation computing information, including whether the operation is supported by the processing unit, the number of execution cycles of the operation on the processing unit, whether the operation supports parallel computing, and the input and output information of the operation.

[0024] Optionally, in S3, each operation in the data flow graph is pre-scheduled according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation, including:

[0025] S31, establishing a group of inequalities related to time and resource constraints of mapping a data flow graph on a coarse-grained reconfigurable chip;

[0026] S32. Solve the inequality group based on the integer linear programming method to obtain the operation scheduling plan under the minimum cycle start interval and obtain the pre-allocated time period of the operation.

[0027] Optionally, a group of inequalities related to time and resource constraints of mapping a data flow graph on a coarse-grained reconfigurable chip is established, including:

[0028] The inequality of the time constraint describes the dependency between operations and is defined as:

[0029] TE Y ≤ TS X

[0030] Where X and Y represent two dependent operations, T represents the time period, E represents the end time of the operation, and S represents the start time of the operation.

[0031] Resource constraint inequalities describe the constraints on the use of computing and storage resources by operations. The inequalities for computing resource constraints are defined as:

[0032]

[0033] Inequality defining storage resource constraints: U T ≤ M i

[0034] Among them, M i Indicates the number of available storage resources of type i, U T is the number of operations using storage resource i during time period T.

[0035] Optionally, in S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period, and a mapping solution is obtained using a heuristic search method, including:

[0036] S41. Based on the pre-allocated time period, generate a data flow graph that needs to be mapped and a coarse-grained reconfigurable chip structure graph expanded in the time domain, and model the subgraph isomorphism problem;

[0037] S42. Solve the subgraph isomorphism problem between the data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain based on the heuristic search method;

[0038] S43, determining whether there is a legal solution to the subgraph isomorphism problem: If there is a legal solution to the subgraph isomorphism problem, determining that the current loop start interval is legal; otherwise, increasing the loop start interval, and repeating steps S42 to S43 until a legal solution to the subgraph isomorphism problem is found;

[0039] S44: Based on the legal solutions to the subgraph isomorphism problem, a mapping scheme of the data flow graph on the coarse-grained reconfigurable chip is generated.

[0040] Optionally, in S5, the configuration information includes: execution information of the operation on the processing unit, operation execution timing information, memory access information, register access information and data transmission information.

[0041] On the other hand, a coarse-grained reconfigurable chip mapping device based on pre-scheduling is provided, which is applied to a coarse-grained reconfigurable chip mapping method based on pre-scheduling, and the device includes:

[0042] The data preprocessing module is used to input the preset input program into the compiler front end and output the intermediate representation;

[0043] Data flow graph construction module, used to build data flow graph structure based on intermediate representation;

[0044] A pre-scheduling module is used to obtain the coarse-grained reconfigurable chip structure information; map the data flow graph structure on the coarse-grained reconfigurable chip; pre-scheduling is performed based on the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation;

[0045] A mapping scheme confirmation module is used to search the mapping results according to a pre-assigned time period and confirm the mapping scheme;

[0046] The coarse-grained reconfigurable chip mapping module is used to generate configuration information executed on the coarse-grained reconfigurable chip based on a mapping scheme, and complete the coarse-grained reconfigurable chip mapping based on pre-scheduling.

[0047] On the other hand, a coarse-grained reconfigurable chip mapping device based on pre-scheduling is provided, and the coarse-grained reconfigurable chip mapping device based on pre-scheduling includes: a processor; a memory, wherein computer-readable instructions are stored on the memory, and when the computer-readable instructions are executed by the processor, any one of the above-mentioned coarse-grained reconfigurable chip mapping methods based on pre-scheduling is implemented.

[0048] On the other hand, a computer-readable storage medium is provided, wherein the storage medium stores at least one instruction, and the at least one instruction is loaded and executed by a processor to implement any one of the above-mentioned coarse-grained reconfigurable chip mapping methods based on pre-scheduling.

[0049] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0050] In an embodiment of the present invention, by pre-analyzing and scheduling complex data flow graphs, the search space of the mapping problem is effectively narrowed, and the mapping solution speed of the loop on the coarse-grained reconfigurable chip is significantly improved; by modeling the data flow graph and the coarse-grained reconfigurable chip structure information, it can be flexibly optimized in the scheduling and mapping stages, significantly improving the execution performance of the loop on the coarse-grained reconfigurable chip, effectively improving the utilization of chip resources, and reducing energy consumption; through the mapping method based on subgraph isomorphism search, high-quality mapping solutions can be efficiently generated, significantly accelerating the compilation speed, effectively improving the system performance, and enhancing the flexibility and scalability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 A schematic flow chart of a coarse-grained reconfigurable chip mapping method based on a pre-scheduling method provided in an embodiment of the present invention;

[0053] Figure 2 A schematic diagram of the data flow diagram structure provided by an embodiment of the present invention;

[0054] Figure 3 A schematic diagram of the results of the pre-scheduling method provided by an embodiment of the present invention;

[0055] Figure 4 A schematic diagram of a coarse-grained reconfigurable chip structure deployed in the time domain provided by an embodiment of the present invention;

[0056] Figure 5 An example diagram of solving the subgraph isomorphism problem based on pattern graph matching search provided by an embodiment of the present invention;

[0057] Figure 6 A schematic diagram of a mapping scheme for a data flow graph on a coarse-grained reconfigurable chip provided by an embodiment of the present invention;

[0058] Figure 7 A block diagram of a coarse-grained reconfigurable chip mapping device based on pre-scheduling provided by an embodiment of the present invention;

[0059] Figure 8 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0061] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as an "exemplary" in the present invention should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner. Furthermore, in the embodiments of the present invention, "and / or" can mean both or either of the two.

[0062] In the embodiments of the present invention, sometimes a subscript such as W1 may be written as a non-subscript such as W1. When the difference is not emphasized, the meanings to be expressed are the same.

[0063] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0064] The embodiment of the present invention provides a method for coarse-grained reconfigurable chip mapping based on pre-scheduling, which can be implemented by a coarse-grained reconfigurable chip mapping device based on pre-scheduling, which can be a terminal or a server. Figure 1 The flowchart of the coarse-grained reconfigurable chip mapping method based on pre-scheduling is shown in FIG. Figure 1 As shown, the present invention proposes a coarse-grained reconfigurable chip mapping method based on pre-scheduling, and the processing flow of the method may include the following steps:

[0065] S1. Input a preset input program into the compiler front end, and output an intermediate representation of the source code in the preset input program;

[0066] In one feasible implementation, in S1, inputting a preset input program into a compiler front end and outputting an intermediate representation of the source code in the preset input program includes:

[0067] S11. Obtain a preset input program; the preset input program is a high-level language code written in C, C++, or Python, and annotates loops that need to be accelerated on the coarse-grained reconfigurable chip;

[0068] S12, inputting the preset input program into the compiler front end, and outputting an intermediate representation of the source code in the preset input program;

[0069] Among them, the intermediate representation is the LLVM intermediate representation in .ll format. The preset input program is input to the compiler front end and the intermediate representation is output.

[0070] In one feasible implementation, the present invention generates an intermediate representation (IR) from the input program through a compiler. This provides comprehensive and accurate information about the program to be mapped to the subsequent coarse-grained reconfigurable chip mapping process, serving as a key input for generating the subsequent mapping solution. This IR reflects all of the program's operations and the dependencies between them, ensuring that the chip mapping fully considers these dependencies, generates a correct mapping solution, and ensures that the program will run correctly on the coarse-grained reconfigurable chip.

[0071] In a feasible implementation, the intermediate representation is an intermediate form of the source code during the compilation process, between the source language and the target language.

[0072] In a feasible implementation, the loop that needs to be accelerated on the coarse-grained reconfigurable chip is marked by annotation as follows: marking in the code by adding annotations. The accelerated loop refers to the loop executed on the coarse-grained reconfigurable chip. For example, for C / C++, the marking method is to add a line of code before the for loop: / / pragma CGRA. In a feasible implementation, the LLVM in the present invention was originally named after Low Level Virtual Machine, and LLVM is the full name of the LLVM project. LLVM is not a virtual machine, but a collection of compilation frameworks and tool chains.

[0073] S2. Build a data flow graph structure based on the intermediate representation;

[0074] In a feasible implementation, in S2, a data flow graph structure is constructed based on the intermediate representation, including:

[0075] Based on the intermediate representation, the program operations and the dependencies between the operations are constructed into a data flow graph structure (Graph); wherein the data flow graph structure includes: nodes in the data flow graph and edges in the data flow graph.

[0076] In one feasible implementation, the nodes in the data flow graph include: corresponding operations in the LLVM intermediate representation, including addition, multiplication, reading, writing, bitwise operations, and other operations, complex tasks or simple tasks;

[0077] The edges in the data flow graph represent the dependency information between computing operations.

[0078] In a feasible implementation, the coarse-grained reconfigurable chip structure information includes:

[0079] Processing unit information, including the number of processing units in the chip and how they are connected to each other;

[0080] Memory cell information, including the number of memory cells in the chip and the cache hierarchy;

[0081] and operation computing information, including whether the operation is supported by the processing unit, the number of execution cycles of the operation on the processing unit, whether the operation supports parallel computing, and the input and output information of the operation.

[0082] In a feasible implementation, Figure 2 As shown in Figure 2, in a data flow graph, nodes represent operations and edges represent dependencies. For example, two memory read (LOAD) operations are performed first, and then the addition operation (ADD) performed depends on the results of the two memory read operations.

[0083] In a feasible implementation, by constructing a data flow graph, the complex loop mapping problem can be abstracted into a subgraph isomorphism matching problem of the graph, which can effectively reduce the difficulty of solving the mapping problem and make it possible to accurately represent the dependency of operations and the execution order of the program during mapping, thereby improving the speed and quality of solving the mapping problem.

[0084] S3. Obtain the coarse-grained reconfigurable chip structure information; pre-schedule each operation in the data flow graph according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation.

[0085] In a feasible implementation, the coarse-grained reconfigurable chip structure information specifically includes processing unit information, including the number of processing units in the chip and the connection method between them; storage unit information, including the number of storage units in the chip and the cache hierarchy; and operation calculation information, including whether the operation is supported by the processing unit, the number of execution cycles of the operation on the processing unit, whether the operation supports parallel computing, and the input and output information of the operation.

[0086] In a feasible implementation, in S3, each operation in the data flow graph is pre-scheduled based on the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation, including:

[0087] S31, establishing a group of inequalities related to time and resource constraints of mapping a data flow graph on a coarse-grained reconfigurable chip;

[0088] S32. Solve the inequality group based on the integer linear programming method to obtain the operation scheduling plan under the minimum cycle start interval and obtain the pre-allocated time period of the operation.

[0089] In a feasible implementation, the operation refers to an operation in a program, such as an addition operation (ADD), a multiplication operation (MUL), a memory read operation (LOAD), a memory write operation (WRITE), etc.

[0090] In a feasible implementation, a set of inequalities related to time and resource constraints for mapping a data flow graph on a coarse-grained reconfigurable chip is established, including:

[0091] The time constraint inequality describes the dependency between operations. That is, for two operations in a loop iteration, if there is a dependency between the two operations, then the operation X that depends on the result of the other operation must be executed after the corresponding operation Y is completed. That is, the start time of X should not be earlier than the end time of Y. Define TS X is the start time of operation X, TE X is the end time of operation X. If there is an edge from the node corresponding to operation Y to the node corresponding to operation X in the data flow graph, the inequality defining the time constraint is:

[0092] TE Y ≤ TS X

[0093] Where X and Y represent two dependent operations, T represents the time period, E represents the end time of the operation, and S represents the start time of the operation.

[0094] The resource constraint inequality describes the constraints on the use of computing and storage resources by an operation. That is, in the same time period, the computing and storage resources used by an operation should not exceed the total computing and storage resources on the chip. Define the number of processing units on the chip as N, the point set in the data flow graph as V, and TS X is the start time of operation X, TE X is the end time of operation X, then for any time period T, the inequality defining the computing resource constraint is:

[0095]

[0096] Inequality defining storage resource constraints: U T ≤ M i

[0097] Among them, M i Indicates the number of available storage resources of type i, U T is the number of operations using storage resource i during time period T.

[0098] In a feasible implementation, the method for solving the integer linear programming is to use an integer linear programming solver, such as Gurobi.

[0099] In one feasible implementation, the operation scheduling scheme generated by the pre-scheduling method includes the original data flow graph, the minimum loop start interval, the type of processing unit that executes each operation, and the time period for each operation on the data flow graph to start execution in one loop.

[0100] The minimum loop start interval is the minimum number of time cycles between two adjacent iterations of the loop under the constraints of computing resources and operation timing, so that the loop can be repeatedly run with this start interval on the coarse-grained reconfigurable chip.

[0101] In a feasible implementation, Figure 3 As shown in FIG, a schematic diagram of the results of the pre-scheduling method provided by an embodiment of the present invention is shown. The horizontal axis indicates which processing unit performs the operation, and the vertical axis indicates the time period for the operation to be executed in each loop iteration. Figure 3 ,For the data flow graph corresponding to the loop given in the figure, when the storage resources are unlimited and there are 2 processing units, the minimum loop start interval is 4 cycles.

[0102] By establishing a set of inequalities related to the time and resource constraints of data flow graph mapping on a coarse-grained reconfigurable chip and solving this set of inequalities based on the integer linear programming method, an operation scheduling scheme with the minimum loop start interval can be obtained, thereby narrowing the search space when solving the loop mapping problem on the coarse-grained reconfigurable chip, and converting the original problem into two independent sub-problems for solution, effectively reducing the complexity of solving the mapping problem. The allocation of operation time periods and the allocation of specific operation units can be solved in two stages respectively, improving the efficiency and success rate of compilation mapping, thereby improving the efficiency of task execution on the coarse-grained reconfigurable chip.

[0103] S4. Search the mapping results according to the pre-assigned time period and confirm the mapping solution;

[0104] In a feasible implementation, in S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period, and a mapping solution is obtained using a heuristic search method, including:

[0105] S41. Based on the pre-allocated time period, a data flow graph that needs to be mapped and a coarse-grained reconfigurable chip structure graph expanded in the time domain are generated to model the subgraph isomorphism problem.

[0106] The coarse-grained reconfigurable chip structure graph, expanded in the time domain, includes information about processing units and the data they transmit. The subgraph isomorphism problem is the isomorphism between the scheduled data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain. Specifically, the subgraph isomorphism problem is to determine whether the scheduled data flow graph is a subgraph of the coarse-grained reconfigurable chip structure graph expanded in the time domain.

[0107] In a feasible implementation, Figure 4 , which shows a schematic diagram of a coarse-grained reconfigurable chip structure in the time domain provided by an embodiment of the present invention.

[0108] Figure 4 In the figure, nodes PE1 and PE2 describe two processing units on a coarse-grained reconfigurable chip. The vertical axis represents the time period. The edge describes that after each time period, the processing unit can pass the data to another processing unit in the next time period or keep the data in the current processing unit for subsequent calculation.

[0109] It should be noted that by expanding the coarse-grained reconfigurable chip structure in the time domain and solving the corresponding subgraph isomorphism problem, it is helpful to fully analyze and utilize the available resources on the coarse-grained reconfigurable chip, ensuring that the program can utilize the effective resources on the chip as much as possible in each time cycle, thereby improving the execution performance of the program on the coarse-grained reconfigurable chip.

[0110] In a feasible implementation, in S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period, and a mapping solution is obtained using a heuristic search method, further comprising:

[0111] S42. Based on the heuristic search method, solve the subgraph isomorphism problem between the data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain.

[0112] In one feasible implementation, the subgraph isomorphism problem refers to whether the scheduled data flow graph is a subgraph of the coarse-grained reconfigurable chip structure graph expanded in the time domain. A heuristic search method involves starting from an empty set and gradually adding node pairs consisting of nodes in the data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain to the matched subgraph until a complete match is achieved. During each match, if for a node X in the data flow graph, a node Y can be found in the coarse-grained reconfigurable chip structure graph expanded in the time domain, and neither X nor Y is in the matched subgraph, and the edges of X in the matched subgraph are the same as or a subset of the edges of Y in the matched subgraph, then the node pair consisting of X and Y can be added to the matched subgraph. If no such node pair (X, Y) exists, the node pair added in the last step is deleted and the search is backtracked. If the final matched subgraph is equal to the data flow graph, a valid mapping solution has been found; otherwise, no valid mapping solution exists for the current startup interval.

[0113] Specifically, during the search, a pattern graph is constructed based on the node's neighborhood information and out-degree and in-degree information, and search and pruning based on pattern graph matching are performed. This pruning helps eliminate search subtrees that are unlikely to match between the data flow graph and the coarse-grained reconfigurable chip structure diagram during the search, thereby narrowing the search space, avoiding incorrect or inefficient search path selection, and accelerating the process of obtaining a feasible solution.

[0114] like Figure 5 As shown, an example diagram of solving the subgraph isomorphism problem based on pattern graph matching search provided by an embodiment of the present invention is shown.

[0115] like Figure 5 The pattern graph describes the neighborhood information and out-degree and in-degree information of the node. Each time when trying to add a node pair, the pattern graph is matched for the node pair to be added. If the match is successful, the node pair can be added to the matched maximum common subgraph.

[0116] It should be noted that by solving the subgraph isomorphism problem based on a heuristic pattern graph matching search method, the mapping problem of the data flow graph on the coarse-grained reconfigurable chip can be solved with higher efficiency. It can take into account the dependencies between operations in the program and the data transmission mode and storage hierarchy of the processing units in the coarse-grained reconfigurable chip, thereby improving the resource utilization of the coarse-grained reconfigurable chip, accelerating the compilation speed, and improving the quality of the compilation results.

[0117] In a feasible implementation, in S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to a pre-allocated time period, and a mapping solution is obtained using a heuristic search method, further comprising:

[0118] S43, determining whether there is a legal solution to the subgraph isomorphism problem: If there is a legal solution to the subgraph isomorphism problem, determining that the current loop start interval is legal; otherwise, increasing the loop start interval, and repeating steps S42 to S43 until a legal solution to the subgraph isomorphism problem is found;

[0119] In one feasible implementation, the existence of a legal solution to the subgraph isomorphism problem means that, during the current loop start period, the data flow graph is a subgraph of the coarse-grained reconfigurable chip structure diagram expanded in the time domain. This means that there exists a legal solution to running this data flow graph on the coarse-grained reconfigurable chip during the current loop start period. If there is no legal solution to the subgraph isomorphism problem, it indicates that, due to timing or resource constraints, a legal mapping solution cannot be found during the current loop start period. Increasing the loop start interval will increase program execution time while utilizing more computing and storage resources within a single loop iteration.

[0120] In a feasible implementation, it is determined whether there is a legal solution to the subgraph isomorphism problem, and the loop start interval is gradually increased from the minimum possible value until a legal mapping solution can be obtained. The minimum legal loop start interval can be obtained to ensure that the program can achieve optimal performance on a coarse-grained reconfigurable chip.

[0121] In a feasible implementation, in S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period, and a mapping solution is obtained using a heuristic search method, further comprising:

[0122] S44: Based on the legal solutions to the subgraph isomorphism problem, a mapping scheme of the data flow graph on the coarse-grained reconfigurable chip is generated.

[0123] In a feasible implementation, Figure 6 , which shows a schematic diagram of a mapping solution of a data flow graph provided by an embodiment of the present invention on a coarse-grained reconfigurable chip.

[0124] like Figure 6 The generated mapping scheme includes the loop start interval; the number of the processing unit that executes each operation; the data transmission method; and the time period in which each operation on the data flow graph starts to execute in one loop.

[0125] It should be noted that through the solution of the subgraph isomorphism problem, a one-to-one correspondence between the nodes of the data flow graph and the coarse-grained reconfigurable chip structure diagram expanded in the time domain can be obtained, thereby obtaining an accurate coarse-grained reconfigurable chip mapping scheme to guide the data calculation and transmission of the processing units of the coarse-grained reconfigurable chip in each time period, effectively improving the utilization of chip resources and reducing energy consumption.

[0126] S5. Based on the mapping solution, generate configuration information executed on the coarse-grained reconfigurable chip, and complete the coarse-grained reconfigurable chip mapping based on pre-scheduling.

[0127] In a feasible implementation, in S5, the configuration information includes: execution information of the operation on the processing unit, operation execution timing information, memory access information, register access information and data transmission information.

[0128] In an embodiment of the present invention, by pre-analyzing and scheduling complex data flow graphs, the search space of the mapping problem is effectively narrowed, and the mapping solution speed of the loop on the coarse-grained reconfigurable chip is significantly improved; by modeling the data flow graph and the coarse-grained reconfigurable chip structure information, it can be flexibly optimized in the scheduling and mapping stages, significantly improving the execution performance of the loop on the coarse-grained reconfigurable chip, effectively improving the utilization of chip resources, and reducing energy consumption; through the mapping method based on subgraph isomorphism search, high-quality mapping solutions can be efficiently generated, significantly accelerating the compilation speed, effectively improving the system performance, and enhancing the flexibility and scalability of the system.

[0129] Figure 7 1 is a block diagram of a coarse-grained reconfigurable chip mapping apparatus 300 based on pre-scheduling according to an exemplary embodiment. The apparatus 300 is used for a coarse-grained reconfigurable chip mapping method based on pre-scheduling. Figure 7 The device includes a data pre-processing module 310, a data flow graph construction module 320, a pre-scheduling module 330, a mapping scheme confirmation module 340 and a coarse-grained reconfigurable chip mapping module 350.

[0130] The data preprocessing module 310 is used to input a preset input program into the compiler front end and output an intermediate representation of the source code in the preset input program;

[0131] A data flow graph construction module 320 is used to construct a data flow graph structure based on the intermediate representation;

[0132] A pre-scheduling module 330 is configured to obtain the coarse-grained reconfigurable chip structure information and pre-schedule each operation in the data flow graph according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation;

[0133] A mapping scheme confirmation module 340 is configured to perform mapping on the coarse-grained reconfigurable chip based on the data flow graph structure according to a pre-assigned time period and obtain a mapping scheme using a heuristic search method;

[0134] The coarse-grained reconfigurable chip mapping module 350 is configured to generate configuration information executed on the coarse-grained reconfigurable chip based on the mapping solution, and complete the coarse-grained reconfigurable chip mapping based on pre-scheduling.

[0135] Optionally, the data preprocessing module 310 is used for S11, obtaining a preset input program; the preset input program is a high-level language code written in C, C++, or Python, and annotates loops that need to be accelerated on the coarse-grained reconfigurable chip;

[0136] S12, inputting the preset input program into the compiler front end and outputting an intermediate representation;

[0137] Among them, the intermediate representation is the LLVM intermediate representation in .ll format. The preset input program is input to the compiler front end and the intermediate representation is output.

[0138] Optionally, the data flow graph construction module 320 is used to construct the program operations and the dependencies between the operations into a data flow graph structure based on the intermediate representation; wherein the data flow graph structure includes: nodes in the data flow graph and edges in the data flow graph.

[0139] Optionally, nodes in the data flow graph include: corresponding operations in the LLVM intermediate representation, including addition, multiplication, reading, writing, bitwise operations, and other operations, complex tasks or simple tasks;

[0140] The edges in the data flow graph represent the dependency information between computing operations.

[0141] Optionally, the coarse-grained reconfigurable chip structure information includes:

[0142] Processing unit information, including the number of processing units in the chip and how they are connected to each other;

[0143] Memory cell information, including the number of memory cells in the chip and the cache hierarchy;

[0144] And operation computing information, including whether the operation is supported by the processing unit, the number of execution cycles of the operation on the processing unit, whether the operation supports parallel computing, and the input and output information of the operation.

[0145] Optionally, the pre-scheduling module 330 is configured to: S31 establish a group of inequalities related to time and resource constraints for mapping the data flow graph on the coarse-grained reconfigurable chip;

[0146] S32. Solve the inequality group based on the integer linear programming method to obtain the operation scheduling plan under the minimum cycle start interval and obtain the pre-allocated time period of the operation.

[0147] Optionally, a group of inequalities related to time and resource constraints of mapping a data flow graph on a coarse-grained reconfigurable chip is established, including:

[0148] The inequality of the time constraint describes the dependency between operations and is defined as:

[0149] TE Y ≤ TS X

[0150] Where X and Y represent two dependent operations, T represents the time period, E represents the end time of the operation, and S represents the start time of the operation.

[0151] Resource constraint inequalities describe the constraints on the use of computing and storage resources by operations. The inequalities for computing resource constraints are defined as:

[0152]

[0153] Inequality defining storage resource constraints: U T ≤ M i

[0154] Among them, M i Indicates the number of available storage resources of type i, U T is the number of operations using storage resource i during time period T.

[0155] Optionally, the mapping scheme confirmation module 340 is used for S41, based on the pre-allocated time period, generating a data flow graph to be mapped and a coarse-grained reconfigurable chip structure graph expanded in the time domain, and modeling the subgraph isomorphism problem;

[0156] S42. Solve the subgraph isomorphism problem between the data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain based on the heuristic search method;

[0157] S43, determining whether there is a legal solution to the subgraph isomorphism problem: If there is a legal solution to the subgraph isomorphism problem, determining that the current loop start interval is legal; otherwise, increasing the loop start interval, and repeating steps S42 to S43 until a legal solution to the subgraph isomorphism problem is found;

[0158] S44: Based on the legal solutions to the subgraph isomorphism problem, a mapping scheme of the data flow graph on the coarse-grained reconfigurable chip is generated.

[0159] Optionally, in the coarse-grained reconfigurable chip mapping module 350 , the configuration information includes: execution information of operations on the processing unit, operation execution timing information, memory access information, register access information, and data transmission information.

[0160] In the embodiment of the present invention, the present invention effectively narrows the search space of the mapping problem by pre-analyzing and scheduling complex data flow graphs, and significantly improves the mapping solution speed of the loop on the coarse-grained reconfigurable chip; by modeling the data flow graph and the coarse-grained reconfigurable chip structure information, it can be flexibly optimized in the scheduling and mapping stages, significantly improving the execution performance of the loop on the coarse-grained reconfigurable chip, effectively improving the utilization of chip resources, and reducing energy consumption; through the mapping method based on subgraph isomorphism search, high-quality mapping solutions can be efficiently generated, significantly accelerating the compilation speed, effectively improving the system performance, and enhancing the flexibility and scalability of the system.

[0161] Figure 8 is a structural diagram of a coarse-grained reconfigurable chip mapping device based on pre-scheduling provided by an embodiment of the present invention, such as Figure 8 As shown, the coarse-grained reconfigurable chip mapping device based on pre-scheduling may include the above Figure 7 The coarse-grained reconfigurable chip mapping apparatus based on pre-scheduling is shown. Optionally, the coarse-grained reconfigurable chip mapping apparatus based on pre-scheduling 410 may include a first processor 2001 .

[0162] Optionally, the pre-scheduling-based coarse-grained reconfigurable chip mapping device 410 may further include a memory 2002 and a transceiver 2003 .

[0163] The first processor 2001, the memory 2002 and the transceiver 2003 may be connected via a communication bus.

[0164] The following combination Figure 8 The components of the pre-scheduled coarse-grained reconfigurable chip mapping device 410 are described in detail:

[0165] The first processor 2001 is the control center of the pre-scheduled coarse-grained reconfigurable chip mapping device 410 and can be a single processor or a collective term for multiple processing elements. For example, the first processor 2001 can be one or more central processing units (CPUs), or application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of the present invention, such as one or more digital signal processors (DSPs) or one or more field programmable gate arrays (FPGAs).

[0166] Optionally, the first processor 2001 may execute various functions of the pre-scheduled coarse-grained reconfigurable chip mapping device 410 by running or executing a software program stored in the memory 2002 and calling data stored in the memory 2002 .

[0167] In a specific implementation, as an embodiment, the first processor 2001 may include one or more CPUs, such as Figure 8 CPU0 and CPU1 are shown in FIG.

[0168] In a specific implementation, as an embodiment, the pre-scheduled coarse-grained reconfigurable chip mapping device 410 may also include multiple processors, such as Figure 8 1 and 2. The first processor 2001 and the second processor 2004 are shown in FIG. Each of these processors can be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0169] The memory 2002 is used to store the software program for executing the solution of the present invention, and is controlled by the first processor 2001 for execution. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0170] Alternatively, the memory 2002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, a random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but not limited thereto. The memory 2002 may be integrated with the first processor 2001 or exist independently and accessed through an interface circuit ( Figure 8 (not shown) is coupled to the first processor 2001, which is not specifically limited in this embodiment of the present invention.

[0171] The transceiver 2003 is used to communicate with a network device or a terminal device.

[0172] Optionally, the transceiver 2003 may include a receiver and a transmitter ( Figure 8 The receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0173] Optionally, the transceiver 2003 may be integrated with the first processor 2001 or may exist independently and be mapped to the first processor 2001 through the interface circuit ( Figure 8 (not shown) is coupled to the first processor 2001, which is not specifically limited in this embodiment of the present invention.

[0174] It should be noted that Figure 8 The structure of the pre-scheduling-based coarse-grained reconfigurable chip mapping device 410 shown in the figure does not constitute a limitation on the router. The actual knowledge structure recognition device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0175] In addition, the technical effects of the pre-scheduling-based coarse-grained reconfigurable chip mapping device 410 can refer to the technical effects of the pre-scheduling-based coarse-grained reconfigurable chip mapping method described in the above method embodiment, which will not be repeated here.

[0176] It should be understood that the first processor 2001 in the embodiment of the present invention may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc.

[0177] It should also be understood that the memory in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0178] The above embodiments can be implemented in whole or in part via software, hardware (e.g., circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable sensor. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0179] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " as used herein generally indicates an "or" relationship between the associated objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0180] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0181] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0182] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0183] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0184] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for causing a computer device (such as a personal computer, server, or network device) to execute all or part of the steps of the methods described in various embodiments of the present invention.

[0185] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A coarse-grained reconfigurable chip mapping method based on pre-scheduling, characterized in that: The method comprises: S1. Input a preset input program into the compiler front end, and output an intermediate representation of the source code in the preset input program; S2. Based on the intermediate representation, a data flow graph structure is constructed. Through the construction of the data flow graph, the complex loop mapping problem is abstracted into a graph subgraph isomorphism matching problem. The subgraph isomorphism problem is the subgraph isomorphism problem between the scheduled data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain. S3. Obtaining coarse-grained reconfigurable chip structure information; pre-scheduling each operation in the data flow graph structure according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation; In S3, each operation in the data flow graph is pre-scheduled according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation, including: S31, establishing a group of inequalities related to time and resource constraints of mapping a data flow graph on a coarse-grained reconfigurable chip; S32. Solve the inequality group based on integer linear programming to obtain an operation scheduling scheme with a minimum cycle start interval, and obtain a pre-allocated time period for the operation; The said establishing a group of inequalities related to time and resource constraints for mapping a data flow graph on a coarse-grained reconfigurable chip includes: The inequality of the time constraint describes the dependency between operations and is defined as: THE Y ≤TS X ; Where X and Y represent two dependent operations, T represents the time period, E represents the end time of the operation, and S represents the start time of the operation. Resource constraint inequalities describe the constraints on the use of computing and storage resources by operations. The inequalities for computing resource constraints are defined as: Inequality defining storage resource constraints: U T ≤M i Among them, Mi represents the number of available storage resources of type i, U T is the number of operations using storage resource i in time period T; S4. Mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-assigned time period, and a mapping solution is obtained using a heuristic search method; the heuristic search method is to start from an empty set and gradually add node pairs consisting of nodes in the data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain to the matched subgraph until a complete match is achieved; S5. Based on the mapping solution, generate configuration information executed on the coarse-grained reconfigurable chip, and complete the coarse-grained reconfigurable chip mapping based on pre-scheduling.

2. The method for coarse-grained reconfigurable chip mapping based on pre-scheduling according to claim 1, characterized in that: In S1, the preset input program is input into the compiler front end, and the intermediate representation of the source code in the preset input program is output, including: S11. Obtain a preset input program; the preset input program is a high-level language code written in C, C++, or Python, and annotates loops that need to be accelerated on the coarse-grained reconfigurable chip; S12, inputting the preset input program into the compiler front end, and outputting an intermediate representation of the source code in the preset input program; The intermediate representation is the LLVM intermediate representation in .ll format.

3. The method for coarse-grained reconfigurable chip mapping based on pre-scheduling according to claim 2, characterized in that: In S2, a data flow graph structure is constructed based on the intermediate representation, including: Based on the intermediate representation, the operations of the program and the dependencies between the operations are constructed into a data flow graph structure; wherein the data flow graph structure includes: nodes in the data flow graph and edges in the data flow graph.

4. The method for coarse-grained reconfigurable chip mapping based on pre-scheduling according to claim 3, characterized in that: The nodes in the data flow graph include: operations corresponding to the LLVM intermediate representation, including addition, multiplication, reading, writing, bitwise operations and other operations, complex tasks or simple tasks; The edges in the data flow graph represent dependency information between computing operations.

5. The method for coarse-grained reconfigurable chip mapping based on pre-scheduling according to claim 4, characterized in that: The coarse-grained reconfigurable chip structure information includes: Processing unit information, including the number of processing units in the chip and how they are connected to each other; Memory cell information, including the number of memory cells in the chip and the cache hierarchy; and operation computing information, including whether the operation is supported by the processing unit, the number of execution cycles of the operation on the processing unit, whether the operation supports parallel computing, and the input and output information of the operation.

6. The method for coarse-grained reconfigurable chip mapping based on pre-scheduling according to claim 5, characterized in that: In S4, mapping is performed on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period, and a mapping solution is obtained using a heuristic search method, including: S41. Based on the pre-allocated time period, generate a data flow graph that needs to be mapped and a coarse-grained reconfigurable chip structure graph expanded in the time domain, and model the subgraph isomorphism problem; S42. Solve the subgraph isomorphism problem between the data flow graph and the coarse-grained reconfigurable chip structure graph expanded in the time domain based on the heuristic search method; S43, determining whether there is a legal solution to the subgraph isomorphism problem: If there is a legal solution to the subgraph isomorphism problem, determining that the current loop start interval is legal; otherwise, increasing the loop start interval, and repeating steps S42 to S43 until a legal solution to the subgraph isomorphism problem is found; S44: Based on the legal solutions to the subgraph isomorphism problem, a mapping scheme of the data flow graph on the coarse-grained reconfigurable chip is generated.

7. The method for coarse-grained reconfigurable chip mapping based on pre-scheduling according to claim 6, characterized in that: In S5, the configuration information includes: execution information of the operation on the processing unit, operation execution timing information, memory access information, register access information and data transmission information.

8. A coarse-grained reconfigurable chip mapping device based on pre-scheduling, wherein the coarse-grained reconfigurable chip mapping device based on pre-scheduling is used to implement the coarse-grained reconfigurable chip mapping method based on pre-scheduling according to any one of claims 1 to 7, characterized in that: The device comprises: A data preprocessing module, configured to input a preset input program into the compiler front end and output an intermediate representation of the preset input program; A data flow graph construction module, configured to construct a data flow graph structure based on the intermediate representation; A pre-scheduling module is used to obtain coarse-grained reconfigurable chip structure information; pre-scheduling each operation in the data flow graph according to the data flow graph structure and the coarse-grained reconfigurable chip structure information to obtain a pre-allocated time period for the operation; A mapping scheme confirmation module is used to perform mapping on the coarse-grained reconfigurable chip based on the data flow graph structure according to the pre-allocated time period and obtain a mapping scheme using a heuristic search method; The coarse-grained reconfigurable chip mapping module is used to generate configuration information executed on the coarse-grained reconfigurable chip based on a mapping scheme, and complete the coarse-grained reconfigurable chip mapping based on pre-scheduling.

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