Method and system for automatically generating matching codes based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a method and system for automatically generating a matching code based on an FPGA, and the method comprises the steps: compiling a Verilog test code and a test vector, and storing the Verilog test code and the test vector in a table, the test code supporting dynamic parameterization setting; reading software and hardware information to be tested, executing a code output process based on the test code and the test vector, and generating code matching data corresponding to the software and hardware information; generating a corresponding verification step for each process in the code output processes, verifying the code matching data and the test vector generated by each process in the code output processes in sequence, if verification succeeds, performing the next code output process, and storing the verification steps and the verification result in a basic test plan; and automatically generating a code configuration file corresponding to the software and hardware information in combination with the basic test plan for the test vector of which the code is successfully output. According to the method and the device, the FPGA design verification is comprehensively optimized intelligently and automatically, and the efficiency and the accuracy of generating the code configuration file in the FPGA design are improved.

Description

Technical Field

[0001] The present application belongs to the field of electronic design automation technology, and in particular, relates to a method and system for automatically generating matching codes based on FPGA. Background Art

[0002] With the development of integrated circuit technology, FPGA (Field Programmable Gate Array) EDA (Electronics Design Automation) software is particularly important. EDA software covers all technologies in the entire process of electronic design, simulation, verification, and manufacturing, such as: FPGA functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.), etc.

[0003] In the traditional process of FPGA design and verification, manual coding or other inefficient and low-reuse coding methods dominate. This method is not only time-consuming and labor-intensive, but also prone to errors, resulting in inaccurate verification results and incomplete coverage, which seriously affects the efficiency and quality of FPGA design. With the rapid development of FPGA technology, higher requirements are placed on the accuracy and efficiency of design verification.

[0004] Therefore, it is particularly important to develop a system that can automatically, efficiently and accurately complete the coding work. Summary of the invention

[0005] The present application discloses an automatic code generation method and system based on FPGA, which can automatically generate codes for different devices through the same test code and test vector, and accurately verify each code generation result, thereby solving the problems of low efficiency, poor reusability, inaccurate and unstable verification results, etc. in the traditional FPGA verification process, realizing intelligent and automated comprehensive optimization of FPGA design verification, and improving the efficiency and accuracy of FPGA design code generation.

[0006] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0007] To achieve one or part or all of the above purposes or other purposes, in the first aspect, the present application provides a method for automatically generating coding based on FPGA, the method comprising: writing Verilog test code and test vectors, and storing them in a table, wherein the test code supports dynamic parameterization settings; reading the software and hardware information to be tested, executing the coding process based on the test code and the test vector, and generating the coding data corresponding to the software and hardware information; generating corresponding verification steps for each process in the coding process, and verifying the coding data and test vectors generated by each process in the coding process in turn; if the verification is successful, proceeding to the next coding process, and storing the verification steps and verification results in the basic test plan; for the test vectors with successful coding, combining the basic test plan, automatically generating the coding file corresponding to the software and hardware information.

[0008] In one implementation, the table is an Excel worksheet, and different Excel worksheets store test vector data of different test types; wherein the Excel worksheet includes at least a header and vector information, each row represents a test vector, and each column represents a value corresponding to the test vector header, and the Excel worksheet includes at least a serial number, a vector name, a parameter name, a parameter value, a packing rule, a layout rule, and a wiring rule.

[0009] In one implementation, the test code is used to dynamically adjust parameter values ​​in the test vector according to software and hardware information.

[0010] In one implementation, the code output process includes synthesis, boxing, layout, routing, and code stream generation. The method for verifying the code data generated by each code output process includes: after executing the synthesis process, performing an initial verification on the synthesized netlist file, and after the verification passes, executing the subsequent code output process; after executing the boxing process, matching the pcblock file generated by the boxing result with the boxing rule, if the match is successful, the boxing verification passes, and executing the subsequent code output process; after executing the layout process, matching the place file generated by the layout result with the layout rule, if the match is successful, the layout verification passes, and executing the subsequent code output process; after executing the routing process, matching the route file generated by the routing result with the routing rule, if the match is successful, the routing verification passes, and executing the subsequent code output process.

[0011] In one implementation, the boxing includes primary boxing and secondary boxing. After the primary boxing is completed, secondary boxing is performed according to the corresponding boxing rules in the Excel worksheet, and the boxing result is the result after the secondary boxing.

[0012] In one implementation, the verification result is confirmed by the high and low levels of the signal, and the signal is marked in a set form.

[0013] In one implementation, the method further includes: for a test vector that has successfully produced code, automatically extracting a code stream and pin information associated with the code stream to generate a coding file; combining the coding file and a basic test plan to automatically generate a batch test plan, wherein the batch test plan includes an input level or input frequency, and an output level or output frequency of the test vector, and replacing the signals involved in the batch test plan with the corresponding pin information in the coding file.

[0014] In the second aspect, the present application provides an FPGA-based automatic coding generation system, the system is used to implement the FPGA-based automatic coding generation method as any one of the first aspect, the system includes: a vector data module, used to write Verilog test code and test vectors, and store them in a table, wherein the test code supports dynamic parameterization settings; a configuration reading module, reading the software and hardware information to be tested; an automatic coding module, used to execute the coding process based on the test code and test vector, and generate the coding data corresponding to the software and hardware information; generate a corresponding verification step for each process in the coding process, and verify the coding data and test vector generated by each process in the coding process in turn. If the verification is successful, the next coding process is carried out, and the verification step and verification result are stored in the basic test plan; an automatic coding file generation module, for the test vector with successful coding, combined with the basic test plan, automatically generates a coding file corresponding to the software and hardware information.

[0015] In a third aspect, the present application provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute any one of the FPGA-based automatic code generation methods of the first aspect.

[0016] In a fourth aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an FPGA-based automatic code generation method as described in any one of the first aspects.

[0017] The above-mentioned FPGA-based automatic coding generation method automatically generates coding for different devices through the same test code and test vector, and accurately verifies each coding data, thereby solving the problems of low efficiency of manual coding, poor reusability, inaccurate and unstable verification results in the traditional FPGA verification process. At the same time, there is no need for interface operation and no need to consider the impact of interface changes, thus realizing intelligent and automatic comprehensive optimization of FPGA design verification, and improving the efficiency and accuracy of FPGA design coding file generation.

[0018] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 A schematic diagram of the process flow of the FPGA-based automatic code generation method provided in this application.

[0021] Figure 2 A schematic diagram of the process of sequentially verifying the code generation process provided by this application.

[0022] Figure 3 A schematic diagram of the process of automatically generating a coding file provided for this application.

[0023] Figure 4 This is a structural block diagram of the FPGA-based automatic coding system provided in this application. DETAILED DESCRIPTION

[0024] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0025] Example 1 Embodiment 1 provides an FPGA-based automatic coding generation method, which includes data preparation, configuration reading and verification, step-level coding process, step-level verification process and automatic generation of coding results. The method specifically includes: writing Verilog test code and test vectors, and storing them in a table, wherein the test code supports dynamic parameterization setting; reading the software and hardware information to be tested, executing the coding process based on the test code and the test vector, and generating coding data corresponding to the software and hardware information; generating corresponding verification steps for each process in the coding process, and verifying the coding data generated by each process in the coding process and the test vector in turn. If the verification is successful, the next coding process is performed, and the verification steps and verification results are stored in the basic test plan; for the test vectors with successful coding, the coding file corresponding to the software and hardware information is automatically generated in combination with the basic test plan. The present application method can automatically generate matching codes for different devices through the same test code and test vector, and accurately verify each matching code data, thereby solving the problems of low manual coding efficiency, poor reusability, inaccurate and unstable verification results in the traditional FPGA verification process. At the same time, there is no need for interface operation and no need to consider the impact of interface changes, thus realizing intelligent and automated comprehensive optimization of FPGA design verification, and improving the efficiency and accuracy of FPGA design coding work.

[0026] Moreover, by binding the test vector with the chip's hardware and software information, the same test vector can cover different chips. At the same time, after the test vector is verified to be valid once, all subsequent chip and EDA software changes will not affect the accuracy of the test vector.

[0027] The solution of the present application is described in detail below with reference to the accompanying drawings.

[0028] refer to Figure 1 The embodiment of the present application provides a method for automatically generating matching codes based on FPGA, comprising the following steps: Step S1: Write Verilog test code and test vectors and store them in a table, wherein the test code supports dynamic parameterization settings.

[0029] Among them, the Verilog test code and related test vector data can be written and stored in an Excel worksheet, and different worksheets can be used to store test vector data of different test types. The Excel worksheet contains the following key data: serial number, vector name, parameter name, parameter value, and related rules for boxing, layout and routing, so that when some test vectors need to be boxed twice or use specific rules for layout and routing, the vector requirements can be retrieved and the corresponding rules can be automatically applied. The Excel worksheet contains headers and vector information to display these key data more intuitively and quickly filter various data. Refer to Table 1 for a part of the key data.

[0030] Table 1 At the same time, Excel worksheets are relatively flexible and controllable. When the system needs functional expansion, it can be quickly adapted by modifying the Excel worksheet without a lot of modifications. Each row of the Excel worksheet represents a test vector, and each column refers to the parameters or parameter values ​​of the test vector for the header. These parameter values ​​will be used in the subsequent code generation process. The test code supports parameterized settings, and the specified parameters can be dynamically modified later to achieve the purpose of supporting different devices, thereby verifying the correctness of different hardware designs.

[0031] In this embodiment, a basic test plan form can also be established through an Excel worksheet. The basic test plan form is used to record the verification steps of the test vector and the subsequent verification results, and the results are confirmed by the high and low levels of the signal. The signal is wrapped in a form similar to curly brackets "{}" for special marking to facilitate identification and replacement. For example, if the signal is at a high level, it means the test passed, and if the signal is at a low level, it means the test failed. It should be noted that the basic test plan can be set in advance, and it can also be set when it is needed later.

[0032] Step S2: Read the software and hardware information to be tested.

[0033] Specifically, the test code is used to dynamically adjust the parameters in the test vector according to the software and hardware information to support the code generation process corresponding to different software and hardware information. Software and hardware information includes device information and package information. The test code converts the software and hardware information into parameters in the test vector to support the code generation process of different devices and different packages. Among them, the device information includes the selected chip, the code stream download speed, and the related information of disabling / enabling pins; the package information includes the chip package form, package size, number of pins, etc.

[0034] Software and hardware information also includes EDA design software path, constraints of each process in the code generation process, etc. EDA design software path is used to set the installation path of different versions of EDA software. In the subsequent process of generating code matching data, this information can be automatically extracted to obtain the required code matching; constraints are set to generate specific types of code streams and time limits for each process of generating code matching data, etc. After setting, you can first conduct a preliminary check, and you can also choose to display key information to the operator in the form of an interface and remind the operator to make a second confirmation, and then proceed with subsequent work after confirmation.

[0035] Step S3: Execute the code generation process based on the test code and the test vector to generate matching code data corresponding to the software and hardware information.

[0036] Specifically, according to the read software and hardware type information, the device information and packaging information of the FPGA chip tested by the current EDA design software are determined, and the corresponding code data is generated. The code data refers to the code file generated by the code output process, which is generally in .jpsk format and can also be called a code stream file. This will not be described in detail below.

[0037] In this embodiment, the code output process includes synthesis, boxing, layout, routing, and code stream generation. There is no specific restriction on the specific process of each process. For example, synthesis includes parsing the Verilog code through the EDA design tool, optimizing, mapping and outputting the synthesized netlist; boxing includes primary boxing and secondary boxing, and the primary boxing includes allocating the logic resources to the corresponding logic blocks, such as CLB, according to the boxing rules; secondary boxing optimizes the results of the primary boxing according to the corresponding boxing rules in the Excel worksheet; layout includes placing the logic blocks at specific locations on the FPGA chip; routing includes path allocation, channel allocation, delay optimization, etc.; code stream generation includes generating a code stream file according to the layout and routing results, converting the code stream file into a format recognizable by the FPGA (.bit or .rbf), and outputting the final code data file.

[0038] Step S4: Generate a corresponding verification step for each process in the code output process, and verify the matching data and test vectors generated by each process in the code output process in turn. If the verification is successful, proceed to the next code output process, and store the verification steps and verification results in the basic test plan.

[0039] Specifically, a corresponding verification step is generated for each process in the code generation process. After each process in the above code generation process is completed, verification will be performed according to the verification step. Only after the verification is passed can the next step be performed. The verification process is fully automatic, and the verification results will be reflected in the form of logs. Figure 2 , verifying the matching data and test vector of each process in the code output process in turn includes the following processes: a. Verify synthesis results: After the synthesis process, the synthesized netlist is initially verified, and the subsequent code generation process is executed after the verification passes. Among them, the netlist file can be generated according to the test vector data, and the parameter data in the test vector can be applied to generate the netlist under different hardware. The initial verification can use EDA design tools to automatically perform syntax checking, design rule checking, timing analysis, etc., or manually verify the synthesis report.

[0040] b. Verify the packing result: After the second packing, the pcblock file generated by the packing result is matched with the packing rules. A successful match means that the specified rules are applied to the packing. The packing verification passes and the subsequent code output process is executed.

[0041] c. Verify layout results: After layout, the place file generated by the layout result is matched with the layout rules. A successful match means that the layout applies the specified rules, and the layout verification passes, and the subsequent code output process is executed.

[0042] d. Verify the wiring results: After wiring, the system will match the route file generated by the wiring results with the wiring rules. A successful match means that the wiring applies the specified rules, then the wiring verification passes and the subsequent code output process is executed.

[0043] After the verification is completed, the verification results are stored in the basic test plan for subsequent use.

[0044] Step S5: For the test vectors that have successfully generated the code, combined with the basic test plan, automatically generate the code file corresponding to the software and hardware information.

[0045] Among them, reference Figure 3 , the method of automatically generating a code file includes: a. For the test vectors that have successfully generated codes, the code stream file and the PIN pin information associated with the code stream are automatically extracted to generate the matching code file. Specifically, after the code is generated, a large number of redundant files will be generated. By extracting key information, the matching code JPSK file can be extracted, and the IO pin information can be extracted to generate the corresponding matching code file, which can be classified and stored in the designated directory for easy submission to the manufacturing department.

[0046] b. Combine the basic test plan with the actual code file to automatically generate a batch test plan for the manufacturing department to verify the chip according to the batch test plan. The batch test plan contains the input level or frequency and output level or frequency of the test vector. The signals involved in the test vector are uniformly read from the code file and replaced with the corresponding pin information.

[0047] In order to explain the present application more clearly, the chip EQ6HL9 is taken as a device and the clearing vector of the programmable logic block CLB is tested as an example for explanation.

[0048] The test vector Excel worksheet includes: vector name (aclr1_pos); vector function (covering the functions of signal nclr0 and signal nclr1 of the programmable logic block CLB, and covering part of the code block CB test); vector design (implemented through a netlist, nclr are all positive signals, there are 10 logic units LE in a programmable logic block CLB, numbered from 0 to 9, the outputs of the 10 logic units LE in CLB1 are connected to the datad ports of the 10 logic units LE in CLB2, the arrangement order of the logic units LE corresponds to the signal connection order, CLB1 and CLB2 have the same vertical coordinates, and the horizontal coordinates differ by 3).

[0049] Automatic code output steps: a. Read the chip information and obtain that the programmable logic blocks CLB in the chip are arranged as x rows and y columns. b. Generate the vector aclr1_pos netlist based on the row and column information of the programmable logic blocks CLB of the chip. c. Perform synthesis, layout and routing, generate code stream and other operations according to the netlist of step b, and perform corresponding verification for each step to ensure the correctness of the final result. d. Parse the engineering file of step c, generate the code output result, and generate the test plan for this batch. This batch test plan will generate the verification method of the vector. Taking this vector as an example, the generated verification method is: signal1 clock is given 1M, signal2 and signal3 are both low, signal4 input is 1K square wave, and signal5 output is 1k square wave. The signal will generate the actual PIN pin information according to step c.

[0050] In summary, the FPGA-based automatic coding generation method of the present application realizes the comprehensive optimization of the FPGA design verification process through intelligent and automated methods, and can support the rapid coding of hundreds of test vectors, dozens of devices, and packaging combinations, without the need to modify the test vectors. Each time the code is generated, it is only necessary to set the device and package to be coded. The use of the same test vector reduces the workload of the code generator and the verification work of the chip verification personnel, greatly saving the time of the design department and the verification department. At the same time, it improves the accuracy and consistency of the verification results. Compared with the traditional manual coding method, this method has the advantages of high execution efficiency, support for multi-suite automatic coding, intelligent identification and adaptation, and underlying command execution. These advantages make this method have broad application prospects and important practical value in the field of FPGA design.

[0051] Example 2 Embodiment 2 provides an FPGA-based automatic code generation system, which can implement any of the above-mentioned FPGA-based automatic code generation methods, such as Figure 4 As shown, the system includes: The vector data module is used to write Verilog test code and test vectors and store them in a table, wherein the test code supports dynamic parameterization settings.

[0052] Configure the reading module to read the software and hardware information to be tested.

[0053] The automatic coding module is used to execute the coding process based on the test code and the test vector, generate the coding data corresponding to the software and hardware information; generate a corresponding verification step for each process in the coding process, and verify the coding data generated by each process in the coding process and the test vector in turn. If the verification is successful, the next coding process is carried out, and the verification step and verification result are stored in the basic test plan.

[0054] The module for automatically generating a code file automatically generates a code file corresponding to the software and hardware information based on the test vectors that have successfully generated the code and in combination with the basic test plan.

[0055] It should be noted that it should be understood that the division of the various modules of the above system is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. And these modules can all be implemented in the form of software calling through processing elements; they can also be all implemented in the form of hardware; some modules can also be implemented in the form of software calling through processing elements, and some modules can be implemented in the form of hardware. In addition, all or part of these modules can be integrated together, or they can be implemented independently. The processing element here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or the above modules can be completed by the hardware integrated logic circuit in the processor element or the instructions in the form of software.

[0056] Example 3 Embodiment 3 provides a computer-readable storage medium, in which a program code is stored. The program code is called by a processor to execute any of the above-mentioned FPGA-based automatic code generation methods.

[0057] Example 4 Embodiment 4 provides an electronic device, which includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute any of the above-mentioned FPGA-based automatic code generation methods.

[0058] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A method for automatically generating matching codes based on FPGA, characterized in that: The method comprises: Writing Verilog test code and test vectors, and storing them in a table, wherein the test code supports dynamic parameterization settings; Read the software and hardware information to be tested, execute the code generation process based on the test code and the test vector, and generate the matching code data corresponding to the software and hardware information; Generate a corresponding verification step for each process in the code output process, and verify the matching data generated by each process in the code output process and the test vector in turn. If the verification is successful, proceed to the next code output process, and store the verification step and verification result in the basic test plan; For the test vectors that have successfully produced the code, combined with the basic test plan, the coding file corresponding to the software and hardware information is automatically generated.

2. The method for automatically generating matching codes based on FPGA according to claim 1, characterized in that: The table is an Excel worksheet, and different Excel worksheets store test vector data of different test types; wherein, the Excel worksheet includes at least a header and vector information, each row represents a test vector, and each column represents the value corresponding to the test vector header, and the Excel worksheet includes at least a serial number, a vector name, a parameter name, a parameter value, a packing rule, a layout rule, and a wiring rule.

3. The method for automatically generating matching codes based on FPGA according to claim 2, characterized in that: The test code is used to dynamically adjust the parameter values ​​in the test vector according to the software and hardware information.

4. The method for automatically generating matching codes based on FPGA according to claim 2, characterized in that: The code generation process includes synthesis, packaging, layout, wiring, and code stream generation. The method for verifying the code matching data generated by each code generation process includes: After executing the synthesis process, the synthesized netlist file is initially verified. After the verification passes, the subsequent code output process is executed; After the packing process is executed, the pcblock file generated by the packing result is matched with the packing rules. If the match is successful, the packing verification is passed and the subsequent code output process is executed; After executing the layout process, the place file generated by the layout result is matched with the layout rules. If the match is successful, the layout verification passes and the subsequent code output process is executed; After executing the wiring process, the route file generated by the wiring result is matched with the wiring rules. If the match is successful, the wiring verification passes and the subsequent coding process is executed.

5. The method for automatically generating matching codes based on FPGA according to claim 4, characterized in that: The packing includes primary packing and secondary packing. After the primary packing is completed, secondary packing is performed according to the corresponding packing rules in the Excel worksheet, and the packing result is the result after the secondary packing.

6. The method for automatically generating matching codes based on FPGA according to claim 1, characterized in that: The verification result is confirmed by the high and low levels of the signal, and the signal is marked in a set form.

7. The method for automatically generating matching codes based on FPGA according to claim 6, characterized in that: The method further comprises: for the test vector that has successfully generated the code, automatically extracting the code stream and the pin information associated with the code stream, and generating a code configuration file; Combine the coding file and the basic test plan to automatically generate this batch test plan, wherein the current batch test plan includes the input level or input frequency of the test vector, and the output level or output frequency, and the signals involved in the current batch test plan are replaced with the corresponding pin information in the coding file.

8. An automatic code generation system based on FPGA, characterized in that: The system is used to implement the FPGA-based automatic code generation method according to any one of claims 1 to 7, and the system includes: A vector data module is used to write Verilog test code and test vectors and store them in a table, wherein the test code supports dynamic parameterization settings; Configure the reading module to read the software and hardware information to be tested; An automatic coding module is used to execute a coding process based on the test code and the test vector to generate coding data corresponding to the software and hardware information; generate a corresponding verification step for each process in the coding process, and sequentially verify the coding data generated by each process in the coding process with the test vector. If the verification is successful, the next coding process is performed, and the verification step and verification result are stored in the basic test plan; The module for automatically generating a code file automatically generates a code file corresponding to the software and hardware information based on the test vectors that have successfully generated the code and in combination with the basic test plan.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the FPGA-based automatic code generation method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA-based automatic code generation method as described in any one of claims 1 to 7.

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