A standard cell layout external pin automatic leading-out method based on graph search

Abstract

The application discloses a standard cell layout external pin automatic leading-out method based on graph search, which is characterized in that a Hungarian algorithm is used to solve a pin leading-out assignment problem abstracted from a standard cell circuit layout pin leading-out, and then pin leading-out positions of different networks are obtained, so that network routing optimization is realized. The method specifically comprises the following steps of data preparation, data preprocessing, cost matrix calculation, optimal strategy solving, routing result generation and the like. The application solves the problem that it is difficult to lead out network ports in the standard cell layout routing process based on graph search, and improves the pin accessibility and layout quality of the generated standard cell layout.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a method for pin routing in an automatic generator of standard cell circuit layout, namely, a method for automatic pin routing of external pins in a standard cell layout based on graph search. Background Technology

[0002] Automated generation of standard cell circuit layouts has become a core component of modern digital integrated circuit design. As semiconductor process nodes continue to advance towards the nanometer scale, the complexity of chip design is increasing exponentially. Against this backdrop, traditional manual design methods, due to their inherent limitations, are completely unable to meet the increasingly stringent requirements of chip design regarding power consumption, timing, and area. Automated layout generation technology, with its powerful algorithms, can accurately adapt to design rules and efficiently complete functional verification, thus becoming a key means to solve current chip design challenges and playing a vital role in promoting the development of the semiconductor industry.

[0003] Automatic generation technology for standard cell circuit layouts plays a crucial role in the field of digital integrated circuit design. Through automated algorithmic processing, it can generate layout structures that both conform to strict design rules and possess correct functionality, significantly improving the efficiency and reliability of chip design. In recent years, with the continuous advancement of semiconductor processes and the gradual evolution of process nodes to the nanometer scale, the drawbacks of traditional manual layout design have become increasingly apparent. Faced with ever-increasing design complexity and stringent requirements for power consumption and timing, manual design is not only inefficient but also struggles to guarantee accuracy and consistency, making it unsuitable for industry development needs. This has made automated generation technology a core approach to solving this dilemma.

[0004] In standard cell design, the method of external pin routing has a direct and profound impact on the cell's routerability and overall circuit performance. Existing technologies present several problems with pin routing methods. For example, some methods rely on predefined routing templates, which lack flexibility and struggle to meet complex and ever-changing design requirements. They also fail to optimize pin routing for different circuit structures and layouts. While some mesh-based heuristic algorithms improve flexibility to some extent, they are prone to routing congestion, leading to signal transmission interference and signal integrity degradation. Furthermore, while methods like SMT and IPL can address these issues to some extent, they suffer from low routing efficiency, requiring significant time and computational resources, which is insufficient for the demands of modern chip manufacturing, which prioritizes high-efficiency design. Especially in high-density integration scenarios, optimizing pin placement and routing plays a crucial role in reducing interconnect latency and avoiding design violations (such as spacing conflicts and short circuits). Therefore, new pin routing methods are urgently needed to address these issues.

[0005] Graph search algorithms, such as the classic A* algorithm and Dijkstra's algorithm, have attracted many researchers to apply them to layout and routing due to their high efficiency in path planning. However, the task of pin routing for standard cells has unique complexities, requiring the simultaneous satisfaction of multiple objective constraints, including minimizing trace length to reduce signal transmission delay, balancing routing density to avoid local congestion, and meeting strict process rules to ensure chip manufacturing feasibility. Traditional graph search algorithms, due to their inherent design limitations, struggle to directly adapt to these complex constraints. While solving these constraints avoids such problems when using methods like SMT and IPL for routing, these methods suffer from low routing efficiency. Therefore, addressing these technical bottlenecks necessitates a pin routing method based on an improved graph search algorithm to achieve highly robust, low-coupling-noise automated layout generation, meeting the high standards of modern chip design. Summary of the Invention

[0006] To address the shortcomings of existing standard cell layout external pin routing methods, such as insufficient flexibility, susceptibility to routing congestion, poor signal integrity, low routing efficiency, and high computational resource consumption, this invention proposes an automatic external pin routing method for standard cells based on an improved graph search algorithm. This method automatically identifies available metal tracks, constructs a set of candidate routing locations, and combines this with an optimal matching strategy to optimize pin routing positions. This improves the routing feasibility of standard cells, reduces interconnect delay and routing congestion, avoids design rule violations (such as spacing conflicts and short circuits), and reduces coupling noise. Ultimately, it achieves highly robust, efficient, and process-compliant automated standard cell layout generation, meeting the stringent requirements of modern nanoscale chip design for power consumption, timing, area, and reliability.

[0007] This invention proposes a system that automatically scans standard cell layouts to identify all metal tracks (such as Metal 1, Metal 2, etc.) that can be used to bring out external pins. For each metal track, its center point coordinates are extracted. These coordinate points will be integrated to form a set of candidate pin take-off locations. At the same time, the system also records detailed physical constraint information such as the width and spacing of each metal track. This physical constraint information is crucial for subsequent pin lead-out operations, ensuring that the pin lead-out process strictly conforms to design rules and avoiding design errors and manufacturing problems caused by rule violations.

[0008] The specific technical solution for achieving the objective of this invention is as follows:

[0009] An automatic pin routing method for standard cell layouts based on graph search is proposed. This method uses the Hungarian algorithm to solve the assignment problem abstracted from the pin routing of standard cell circuit layouts, thereby determining the pin routing positions for different networks and optimizing network routing. The method specifically includes the following steps:

[0010] Step 1: Data Preparation

[0011] The standard cell circuit layout that has been laid out and is awaiting routing is analyzed; the coordinates of the transistors after layout and the net labels of their gate, drain, and source are obtained, and the precise coordinates of the ports are determined according to the transistor dimensions; based on the dimensions of the standard cell circuit layout after layout, a set of metal tracks that may serve as pin lead-out locations are obtained, wherein the metal tracks are parallel to the gate and located within the width of the standard cell circuit layout, and their width and spacing conform to the layout specifications of the pin lead-out layer of the standard cell circuit layout defined in the PDK;

[0012] Step 2: Data Preprocessing

[0013] The nodes containing the gate, drain, and source of the transistor are divided according to their network labels, and the specific coordinates of the ports under each network are recorded; for the set of metal tracks, the center point of each metal track is used as the coordinate node of the metal track.

[0014] Step 3: Calculate the cost matrix

[0015] Based on the specific coordinate set of ports under each network and the set of metal track coordinate nodes generated in step 2, the Prim algorithm is used to calculate the minimum spanning tree between each metal track coordinate node and all nodes under each network. The total path length of the minimum spanning tree formed by connecting each metal track to the corresponding network is used as the cost of the allocation strategy of assigning the network to the metal track for pin out. If the number of metal tracks is not equal to the number of networks, virtual metal tracks or virtual networks need to be added to make the two numbers equal. The allocation cost between virtual metal tracks and all networks is set to 0, and the allocation cost between virtual networks and all metal tracks is also set to 0. The final cost matrix is ​​a square matrix, with each row corresponding to a virtual metal track or an actual metal track, and each column corresponding to a virtual network or an actual network label.

[0016] Step 4: Solve for the optimal strategy

[0017] Based on the cost matrix obtained in step 3, the Hungarian algorithm is used to perform a one-to-one optimal matching between the metal track and the network, thereby determining the optimal pin lead-out position for each network.

[0018] Step 5: Generation of wiring results

[0019] Based on the matching results of step 4, the metal track nodes assigned to each network are added to the network's node set, forming an expanded network node set. Based on the expanded node set, the Prim algorithm is used to construct a minimum spanning tree, and the Dijkstra algorithm is used to search for the specific paths of each edge in the minimum spanning tree. During the path search process, switching between different metal layers and via electrical connections are supported, and inter-layer transition structures are automatically generated, ensuring that path direction, line width, spacing, corners, and coverage all meet the constraints of the process design rules. Finally, according to the process design rules, the optimized paths are converted into actual metal interconnects that meet the line width, spacing, overlap, via size, and layer definitions, completing the pin routing and generating the layout using the Python-based KLayout API.

[0020] Furthermore, step 3, which involves using the Prim algorithm to calculate the minimum spanning tree between each metal track coordinate node and all nodes in each network, specifically involves:

[0021] 3-1. Construct a weighted undirected graph

[0022] For any metal orbital coordinate node and any network label Construct a virtual weighted undirected graph. Among them, vertex set Contains the coordinate nodes of the metal track and network labels The specific coordinate nodes of all transistor ports included edge set For vertex set The set of fully connected edges between any two distinct vertices in the array, with each edge weighted by the Manhattan distance between the two corresponding vertices;

[0023] 3-2. Initialize Sets: Create two new sets: one for the vertices that have been visited. and the set of unvisited vertices ; Set the metal track coordinate nodes Add to the set of visited vertices In the middle, network label All port nodes are placed in the unvisited vertex set. In the middle; initialize the total path length of the current minimum spanning tree. =0;

[0024] 3-3. Iterative Growth

[0025] In each iteration, traverse all sets of the given set. Mid-vertices and the set Find the edge with the minimum weight formed by the middle vertices. ,in , The weight corresponding to this edge is added to the total path length. and the vertex From the set Move to the set middle;

[0026] 3-4. Termination and Output

[0027] Repeat steps 3-3 until the set of vertices has not been visited. The set is empty at this time. The total path length is calculated by including all vertices in the graph. That is, the coordinate node of the metal track. With network label The cost of constructing the minimum spanning tree is calculated and filled into the corresponding positions in the cost matrix. middle.

[0028] Furthermore, step 4, which involves using the Hungarian algorithm to perform a one-to-one optimal matching between the metal track and the network, specifically includes the following sub-steps:

[0029] 4-1 Matrix Row Reduction

[0030] Obtain the aforementioned cost matrix, which is For each row of the matrix, find the minimum element in that row and subtract that minimum element from all elements in that row, so that each row contains at least one zero element.

[0031] 4-2 Matrix Column Reduction

[0032] Based on the matrix processed in step 4-1, for each column of the matrix, find the minimum element of that column, and subtract the minimum element from all elements in that column, so that each column contains at least one zero element;

[0033] 4-3. Zero Coverage and Optimality Test

[0034] Cover all zero elements in the matrix using the minimum number of horizontal and vertical lines; calculate the minimum number of lines required. ;like Equal to the dimension of the matrix If the current matrix has reached its optimal state, proceed to steps 4-5; if Less than If the current matrix has not reached its optimal state, proceed to step 4-4.

[0035] 4-4. Matrix Adjustment and Iteration

[0036] Find the minimum value among the elements not covered by lines. Subtract all uncovered elements And add all the intersection elements that are covered twice by the horizontal and vertical lines. The elements that are covered once remain unchanged; use the adjusted matrix to return to step 4-3;

[0037] 4-5. Assignment and Mapping

[0038] Find the matrix that achieves the optimal state. Each row and column contains a unique zero element, ensuring that only one zero element is selected. The row and column indices of these zero elements in the matrix are recorded, where the row index corresponds to the selected metal track or virtual metal track, and the column index corresponds to the selected network or virtual network. Matching pairs involving virtual metal tracks or virtual networks are eliminated, while the matching relationship between actual metal tracks and actual networks is retained as the final optimal pinout position strategy.

[0039] Furthermore, step 5, which involves using Dijkstra's algorithm to search for the specific paths of each edge in the minimum spanning tree, specifically includes the following sub-steps:

[0040] 5-1 Initialization parameters

[0041] Mark the starting node of the path to be connected in the minimum spanning tree as the source node. The target node is marked as the endpoint. Establish distance sets and the set of predecessor nodes , will the source point In distance set The value in the [location] is set to 0, and the distance values ​​of all other nodes in the wiring mesh are set to infinity; a priority queue is created. and the source point Add to the queue;

[0042] 5-2 Node Selection

[0043] When priority queue If the node is not empty, select the node with the smallest current distance value as the current node. If the current node That is the end point If the search is successful, terminate the search and proceed to step 5-4; otherwise, move the node... Mark as visited and proceed to step 5-3;

[0044] 5-3. Relaxation

[0045] Traverse the current node All adjacent nodes in the wiring mesh For each adjacent node Calculate the nodes Reaching the node New path cost ,in For nodes With nodes The weight of the connection between them; if Less than distance set Nodes recorded in If the current distance value is updated, then update Set the predecessor node set Middle node Precursor direction and nodes Insert or update the priority queue with the updated distance value. In the middle; repeat step 5-2;

[0046] 5-4. Path Construction: From the Destination To begin, use the set of predecessor nodes. The pointer relationships in the graph are traced back in reverse order to find the predecessor node of each node, until the source node is reached. Connect all the nodes visited during the backtracking process in sequence to form a sequence starting from the source. To the finish line The shortest wiring path.

[0047] To illustrate this process more clearly, suppose there are five metal tracks in a specific standard cell layout that can be used for pin routing. The system scans the layout using advanced image recognition technology, identifies these five metal tracks, and then uses a coordinate extraction algorithm to obtain the coordinates of their center points, which are (10, 50), (30, 50), (50, 50), (70, 50), and (90, 50). These five coordinate points constitute the set of candidate pin routing locations. This provides an accurate basis for subsequent pin lead-out operations.

[0048] This invention proposes an automatic pin routing method for standard cell layouts based on graph search. By automatically identifying metal tracks and generating candidate pin positions, and combining this with process rule constraints for path searching, the method automates and optimizes pin routing. Compared to traditional methods, this invention offers greater flexibility and routing efficiency, effectively reducing routing congestion and design rule violations, lowering interconnect latency, and improving layout quality. It is suitable for standard cell designs at high-density, advanced process nodes. Attached Figure Description

[0049] Figure 1 This is a flowchart of the method of the present invention;

[0050] Figure 2 This is a schematic diagram of the metal track that can be led out using pins in this invention;

[0051] Figure 3 This is a flowchart of the Prim algorithm of the present invention;

[0052] Figure 4 This is a flowchart of the Hungarian algorithm of the present invention;

[0053] Figure 5 This is a flowchart of the Dijkstra algorithm of the present invention. Detailed Implementation

[0054] This invention constructs a minimum spanning tree and path using the Hungarian algorithm in conjunction with Prim's algorithm and Dijkstra's algorithm, and assigns pin lead-out positions to different networks, thus determining the pin lead-out positions for the automatically generated standard cell circuit layout based on the graph search method.

[0055] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] Example

[0057] See Figure 1 This embodiment of a method for automatically bringing out external pins of a standard cell layout based on graph search includes the following steps:

[0058] Step 1: Data Preparation

[0059] The standard cell circuit layout that has been laid out and is awaiting routing is analyzed; the coordinates of the transistors after layout and the net labels of their gate, drain, and source are obtained, and the precise coordinates of the ports are determined based on the transistor dimensions; based on the dimensions of the standard cell circuit layout after layout, a set of metal tracks that may serve as pin lead-out locations are obtained, wherein the metal tracks are parallel to the gate and located within the width of the standard cell circuit layout, and their width and spacing conform to the layout specifications of the pin lead-out layer of the standard cell circuit layout defined in the PDK; a schematic diagram of the selectable metal tracks is provided. Figure 2 ;

[0060] Step 2: Data Preprocessing

[0061] The nodes containing the gate, drain, and source of the transistor are divided according to their network labels, and the specific coordinates of the ports under each network are recorded; for the set of metal tracks, the center point of each metal track is used as the coordinate node of the metal track.

[0062] Step 3: Calculate the cost matrix

[0063] Based on the results of step 2, the Prim algorithm is used (see...). Figure 3 Calculate the minimum spanning tree between each metal track coordinate node and all nodes under each network; the total path length of the minimum spanning tree formed by the metal track and the network is used as the cost of this strategy; if the number of metal tracks is not equal to the number of networks, virtual metal tracks or virtual networks need to be added to make the two numbers equal; the allocation cost between virtual metal tracks and all networks is set to a preset minimum value, and the allocation cost between virtual networks and all metal tracks is also set to the preset minimum value; the final cost matrix is ​​a square matrix, where each row represents a (virtual) metal track and each column represents a (virtual) network label;

[0064] Step 4: Solve for the optimal strategy

[0065] Based on the cost matrix obtained in step 3, the Hungarian algorithm (see [reference]) is used. Figure 4 The metal track and the network are matched one-to-one to determine the optimal pinout position for each network.

[0066] Step 5: Generation of wiring results

[0067] Based on the matching results of step 4, the metal track nodes assigned to each network are added to the node set of that network, forming an expanded network node set. Based on the expanded node set, Prim's algorithm is used to construct a minimum spanning tree, and Dijkstra's algorithm (see [reference]) is then applied. Figure 5 The algorithm searches for specific paths along each edge of the minimum spanning tree. During the path search, it considers the via connections between different metal layers and ensures that the path direction meets the design rule constraints. Finally, it converts the optimized path into actual metal wiring that conforms to the design specifications according to the process design rules, completes the pin lead-out routing, and generates the layout using the Python-based klayout API.

Claims

1. A method for automatically bringing out external pins of a standard cell layout based on graph search, characterized in that, The method specifically includes the following steps: Step 1: Data Preparation The standard cell circuit layout that has been laid out and is awaiting routing is analyzed; the coordinates of the transistors after layout and the net labels of their gate, drain, and source are obtained, and the precise coordinates of the ports are determined according to the transistor dimensions; based on the dimensions of the standard cell circuit layout after layout, a set of metal tracks that may serve as pin lead-out locations are obtained, wherein the metal tracks are parallel to the gate and located within the width of the standard cell circuit layout, and their width and spacing conform to the layout specifications of the pin lead-out layer of the standard cell circuit layout defined in the PDK; Step 2: Data Preprocessing The nodes containing the gate, drain, and source of the transistor are divided according to their network labels, and the specific coordinates of the ports under each network are recorded; for the set of metal tracks, the center point of each metal track is used as the coordinate node of the metal track. Step 3: Calculate the cost matrix Based on the specific coordinate set of ports under each network and the set of metal track coordinate nodes generated in step 2, the Prim algorithm is used to calculate the minimum spanning tree between each metal track coordinate node and all nodes under each network. The total path length of the minimum spanning tree formed by connecting each metal track to the corresponding network is used as the cost of the allocation strategy of assigning the network to the metal track for pin out. If the number of metal tracks is not equal to the number of networks, virtual metal tracks or virtual networks are added to make the two numbers equal. The allocation cost between virtual metal tracks and all networks is set to 0, and the allocation cost between virtual networks and all metal tracks is also set to 0. The final cost matrix is ​​a square matrix, with each row corresponding to a virtual metal track or an actual metal track, and each column corresponding to a virtual network or an actual network label. Step 4: Solve for the optimal strategy Based on the cost matrix obtained in step 3, the Hungarian algorithm is used to perform a one-to-one optimal matching between the metal track and the network, thereby determining the optimal pin lead-out position for each network. Step 5: Generation of routing results Based on the matching results of step 4, the metal track nodes assigned to each network are added to the network's node set, forming an expanded network node set. Based on the expanded node set, the Prim algorithm is used to construct a minimum spanning tree, and the Dijkstra algorithm is used to search for the specific paths of each edge in the minimum spanning tree. During the path search process, switching between different metal layers and via electrical connections are supported, and inter-layer transition structures are automatically generated, ensuring that path direction, line width, spacing, corners, and coverage all meet the constraints of the process design rules. Finally, according to the process design rules, the optimized paths are converted into actual metal interconnects that meet the line width, spacing, overlap, via size, and layer definitions, completing the pin routing and generating the layout using the Python-based KLayout API.

2. The method for automatically bringing out external pins in a standard cell layout according to claim 1, characterized in that, Step 3 involves using Prim's algorithm to calculate the minimum spanning tree between each metal track coordinate node and all nodes in each network. Specifically: 3-1. Construct a weighted undirected graph For any metal orbital coordinate node and any network label Construct a virtual weighted undirected graph. Among them, vertex set Contains the coordinate node of the metal track and network labels The specific coordinate nodes of all transistor ports included Edge set For vertex set The set of fully connected edges between any two distinct vertices in the array, with each edge weighted by the Manhattan distance between the two corresponding vertices; 3-2. Initialize Sets: Create two new sets: one for the vertices that have been visited. and the set of unvisited vertices ; Set the metal track coordinate nodes Add to the set of visited vertices In the middle, network label All port nodes are placed in the unvisited vertex set. In the middle; initialize the total path length of the current minimum spanning tree. =0; 3-3. Iterative Growth In each iteration, traverse all sets of the given set. Mid-vertices and the set Find the edge with the minimum weight formed by the middle vertices. ,in , The weight corresponding to this edge is added to the total path length. and the vertex From the set Move to the set middle; 3-4. Termination and Output Repeat steps 3-3 until the set of vertices has not been visited. The set is empty at this time. The total path length is calculated by including all vertices in the graph. That is, the coordinate node of the metal track. With network label The cost of constructing the minimum spanning tree is calculated and filled into the corresponding positions in the cost matrix. middle.

3. The method for automatically bringing out external pins in a standard cell layout according to claim 1, characterized in that, Step 4, which describes using the Hungarian algorithm to perform a one-to-one optimal matching between the metal track and the network, specifically includes the following sub-steps: 4-1 Matrix Row Reduction Obtain the aforementioned cost matrix, which is For each row of the matrix, find the minimum element in that row and subtract that minimum element from all elements in that row, so that each row contains at least one zero element. 4-2 Matrix Column Reduction Based on the matrix processed in step 4-1, for each column of the matrix, find the minimum element of that column, and subtract the minimum element from all elements in that column, so that each column contains at least one zero element; 4-3. Zero Coverage and Optimality Test Cover all zero elements in the matrix using the minimum number of horizontal and vertical lines; calculate the minimum number of lines required. ;like Equal to the dimension of the matrix If the current matrix has reached its optimal state, proceed to steps 4-5; if Less than the dimension of the matrix If the current matrix has not reached its optimal state, proceed to step 4-4. 4-4. Matrix Adjustment and Iteration Find the minimum value among the elements not covered by lines. Subtract all uncovered elements And add all the intersection elements that are covered twice by the horizontal and vertical lines. The elements that are covered once remain unchanged; use the adjusted matrix to return to step 4-3; 4-5. Assignment and Mapping Find the matrix that achieves the optimal state. Each row and column contains a unique zero element, ensuring that only one zero element is selected. The row and column indices of these zero elements in the matrix are recorded, where the row index corresponds to the selected metal track or virtual metal track, and the column index corresponds to the selected network or virtual network. Matching pairs involving virtual metal tracks or virtual networks are eliminated, while the matching relationship between actual metal tracks and actual networks is retained as the final optimal pinout position strategy.

4. The method for automatically bringing out external pins in a standard cell layout according to claim 1, characterized in that, Step 5, which involves using Dijkstra's algorithm to search for the specific paths of each edge in the minimum spanning tree, includes the following sub-steps: 5-1 Initialization parameters Mark the starting node of the path to be connected in the minimum spanning tree as the source node. The target node is marked as the endpoint. Establish distance sets and the set of predecessor nodes , will the source point In distance set The value in the [location] is set to 0, and the distance values ​​of all other nodes in the wiring mesh are set to infinity; a priority queue is created. and the source point Add to the queue; 5-2 Node Selection When priority queue If the node is not empty, select the node with the smallest current distance value as the current node. If the current node That is the end point If the search is successful, terminate the search and proceed to step 5-4; otherwise, move the node... Mark as visited and proceed to step 5-3; 5-3. Relaxation Operation Traverse the current node All adjacent nodes in the wiring mesh For each adjacent node Calculate the nodes Reaching the node New path cost ,in For nodes With nodes The weight of the connection between them; if Less than distance set Nodes recorded in If the current distance value is updated, then update Set the predecessor node set Middle node Precursor direction and nodes Insert or update the priority queue with the updated distance value. In the middle; repeat step 5-2; 5-4. Path Construction: From the Destination To begin, use the set of predecessor nodes. The pointer relationships in the graph are traced back in reverse order to find the predecessor node of each node, until the source node is reached. Connect all the nodes visited during the backtracking process in sequence to form a sequence starting from the source. To the finish line The shortest wiring path.

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