Macro model, circuit design simulation program including macro model, and circuit design simulator capable of executing circuit design simulation program

Abstract

The invention provides a macro model, a circuit design simulation program including the macro model, and a circuit design simulator capable of executing the circuit design simulation program. A macro model is used in a circuit design simulator based on a node method. The macro model is configured to include a behavioral model, the function of which is defined by one conditional branch including a plurality of conditional branches as options.

Description

Technical Field

[0001] The present disclosure relates to a macro model, a circuit design simulation program including the macro model, and a circuit design simulator capable of executing the circuit design simulation program. Background Art

[0002] Generally, a macro model is referred to as a model for circuit design simulation, which combines a plurality of behavioral models to simulate the response of a circuit using a nodal method. Summary of the invention

[0003] The macro model disclosed in this specification is used in a circuit design simulator based on a node method. The macro model is configured to include a behavior model whose function is defined by a conditional branch including a plurality of conditional branches as options.

[0004] The circuit design simulation program disclosed in this specification is a circuit design simulation program configured to be executed by a computer including a computing unit and to cause the computer to function as a circuit design simulator. The circuit design simulation program includes a macro model configured as described above, and operates the computer so as to simulate the response of a semiconductor integrated circuit device on the circuit design simulator.

[0005] The circuit design simulator disclosed in this specification is realized by causing a computer to execute the circuit design simulation program configured as described above.

[0006] In the macro model disclosed in this specification, the occurrence of convergence problems in calculation results can be suppressed.

[0007] In the circuit design simulation program disclosed in this specification, it is possible to provide a circuit design simulation program capable of suppressing the occurrence of convergence problems in calculation results.

[0008] In the circuit design simulator disclosed in this specification, it is possible to provide a circuit design simulator that can suppress the occurrence of convergence problems in calculation results. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing the internal structure of a semiconductor integrated circuit device;

[0010] Figure 2 is a circuit diagram showing the structure of a semiconductor integrated circuit device;

[0011] Figure 3 is a block diagram showing the structure of a conventional macro model;

[0012] Figure 4 is a block diagram showing the structure of a macro model of the present disclosure;

[0013] Figure 5 is a block diagram showing a structural example of a circuit design simulator using the macro model of the present disclosure; and

[0014] Figure 6 is a schematic diagram showing a structural example of a circuit design simulation program. DETAILED DESCRIPTION

[0015] <Parts used as simulation objects>

[0016] A description will first be given of a semiconductor integrated circuit device 2 as a simulation target of a macro model X of the present disclosure and a macro model Y as a comparison target. Here, a description will be given using an operational amplifier as an example of the semiconductor integrated circuit device 2 .

[0017] Figure 1 2 is a block diagram showing the internal structure of the semiconductor integrated circuit device 2. Figure 1 As shown, the semiconductor integrated circuit device 2 includes an input stage 3 , a gain stage 4 , an output stage 5 , and a phase compensation capacitor 6 .

[0018] The input stage 3 includes an inverting input terminal (+) and a non-inverting input terminal (-). The gain stage 4 is connected between the input stage 3 and the output stage 5. A first end of a phase compensation capacitor 6 is connected to the input end of the gain stage 4. A second end of the phase compensation capacitor 6 is connected to the output end of the gain stage 4. The phase compensation capacitor 6 prevents oscillation of the semiconductor integrated circuit device 2.

[0019] Figure 2 2 is a circuit diagram showing the structure of the semiconductor integrated circuit device 2. Figure 2 As shown, the input stage 3 includes a PNP bipolar transistor having a base connected to the non-inverting input terminal (+) and a PNP bipolar transistor having a base connected to the inverting input terminal (-). The input stage 3 generates an internal signal by amplifying the differential voltage between the non-inverting input terminal (+) and the inverting input terminal (-), and inputs the internal signal to the gain stage 4.

[0020] The gain stage 4 receives the internal signal from the input stage 3 to generate a high-side signal and a low-side signal. The high-side signal is input to the base of a transistor t1 to be described later. The low-side signal is input to the base of a transistor t2 to be described later.

[0021] The output stage 5 includes transistors t1 and t2 and resistors r1 and r2. Transistor t1 is an NPN bipolar transistor. Transistor t2 is a PNP bipolar transistor. The collector of transistor t1 is connected to a positive power supply VCC. The emitter of transistor t1 is connected to a first end of resistor r1. The emitter of transistor t2 is connected to a first end of resistor r2. The collector of transistor t2 is connected to a negative power supply VEE. The second ends of resistors r1 and r2 are both connected to an output terminal for outputting a signal Vout.

[0022] The output stage 5 generates an output signal Vout corresponding to the high-side signal and the low-side signal.

[0023] <Macro Model>

[0024] Then, a macro model for simulating the function of the above-mentioned semiconductor integrated circuit device 2 (more specifically, the output current Iout of the semiconductor integrated circuit device 2) will be described in detail. Figure 3 A macro model Y is described as a comparative example of the macro model X of the present disclosure (=a structure to be compared with an embodiment of the present disclosure to be described later).

[0025] <Comparative Example Macro Model Y>

[0026] The macro model Y is a SPICE (Simulation Program with Integrated Circuit Emphasis) model based on a node method.

[0027] Figure 3 is a block diagram showing the structure of macro model Y. Figure 3 As shown, the macro model Y includes a behavior model a1, a Zo calculation unit 7y, a behavior model a2, and a behavior model a3. The behavior models a1 to a3 and the Zo calculation unit 7y (more specifically, the conditional branch model ify1, the conditional branch model ify2, the conditional branch model ify3, and the behavior models a4 to a14 to be described later) are connected to each other via nodes.

[0028] The behavior model a1 calculates the difference between the output current Iout and the input current Iin, and inputs the calculation result to the Zo calculation unit 7y and the behavior model a2. The output current Iout is fed back to the behavior model a1.

[0029] The Zo calculation unit 7y calculates the impedance Zo based on the output values ​​of I1, I2, I3, and I4, and inputs the calculation result to the behavior model a2 and the behavior model a3. The details of the Zo calculation unit 7y will be described later.

[0030] The behavior model a2 calculates the output current Iout based on the impedance Zo and the input current Iin. The behavior model a3 calculates the drive current Idout based on the output value of the behavior model a1 and the impedance Zo.

[0031] The Zo calculation unit 7y includes a conditional branch model ify1, a conditional branch model ify2, a conditional branch model ify3, and behavior models a4 to a14.

[0032] The conditional branch model ify1 includes a node L1, a node R1, a node T1, a node F1, and a node O1. The ground terminal is connected to the node L1. In other words, a value of 0 is input to the node L1. The output terminal of the behavior model a1 is connected to the node R1. The node O2 of the conditional branch model ify2 is connected to the node T1. The node O3 of the conditional branch model ify3 is connected to the node F1. The node O1 is connected to the behavior models a2 and a3.

[0033] The conditional branch model ify2 includes a node L2, a node R2, a node T2, a node F2, and a node O2. The output end of the behavior model a4 is connected to the node L2. The output end of the behavior model a5 is connected to the node R2. The output end of the behavior model a6 is connected to the node T2. The output end of the behavior model a7 is connected to the node F2. Node O2 is connected to the node T1 of the conditional branch model ify1.

[0034] The conditional branch model ify3 includes a node L3, a node R3, a node T3, a node F3, and a node O3. The output end of the behavior model a10 is connected to the node L3. The output end of the behavior model a11 is connected to the node R3. The output end of the behavior model a12 is connected to the node T3. The output end of the behavior model a13 is connected to the node F3. The node O3 is connected to the node F1 of the conditional branch model ify1.

[0035] When the input value to node L1 (in this figure, value 0) is greater than the input value to node R1 (in Figure 3 In the case of the output value of the behavior model a1), the conditional branch model ify1 outputs the input value of the input to the node T1 (in Figure 3 In contrast, when the input value to node L1 is equal to or less than the input value to node R1, the conditional branch model ify1 outputs the input value to node F1 (in Figure 3 , the output value of conditional branch model ify3).

[0036] When the input value to node L2 (in this figure, the output value of behavior model a4) is greater than the input value to node R2 (in Figure 3 In the case of the output value of the behavior model a5), the conditional branch model ify2 outputs the input value of the input to the node T2 (in Figure 3 In contrast, when the input value to node L2 is equal to or less than the input value to node R2, conditional branch model ify2 outputs the input value to node F2 (in Figure 3 , the output value of behavioral model a7).

[0037] The behavior model a9 calculates the absolute value of the output value of the behavior model a1 and inputs the calculation result to the behavior model a4 and the behavior model a10. The behavior model a4 outputs the calculation result obtained by dividing the output value of the behavior model a9 by the output value of the behavior model a7. The behavior model a7 outputs the calculation result obtained by multiplying the output value of the behavior model a8 by the gain value (here, 100). The behavior model a8 calculates and outputs the absolute value of the output value of I1.

[0038] The behavior model a5 calculates and outputs the absolute value of I2. The behavior model a6 outputs a calculation result obtained by multiplying the output value of the behavior model a7 by maglimit (predetermined parameter value).

[0039] When the input value to the node L3 (in this figure, the output value of the behavior model a10) is greater than the input value to the node R3 (in Figure 3 In the case of the output value of the behavior model a11), the conditional branch model ify3 outputs the input value to the node T3 (in Figure 3 In contrast, when the input value to node L3 is equal to or less than the input value to node R3, conditional branch model ify3 outputs the input value to node F3 (in Figure 3 , the output value of behavioral model a13).

[0040] The behavior model a10 outputs a calculation result obtained by dividing the output value of the behavior model a9 by the output value of the behavior model a13. The behavior model a11 calculates and outputs the absolute value of the output value of I4. The behavior model a13 calculates and outputs a value obtained by multiplying the output result of the behavior model a13 by maglimit.

[0041] The behavior model a13 outputs a result obtained by multiplying the output of the behavior model a14 by a gain value (here, 100). The behavior model a14 calculates and outputs the absolute value of the output value of I3.

[0042] <Convergence Problem>

[0043] Incidentally, in the simulation performed using the above-mentioned macro model, convergence is problematic. Convergence problems refer to problems in which the calculation results do not converge to the expected results even when the simulation is performed. Specifically, for example, a simulation analysis error occurs, thereby preventing the start of the calculation or stopping the calculation midway, so the calculation result may be unstable.

[0044] In particular, in a macro model constructed according to the node method, when the model includes a feedback path or when there are discontinuous nodes, convergence problems are likely to occur. In addition, when there are discontinuous nodes, logical inconsistencies are likely to occur, and therefore simulation results (calculation results) may not converge. An example of a discontinuous node is a node included in a conditional branch. When so-called model-based development (MBD) is performed using a macro model including discontinuous nodes as described above, convergence problems are likely to occur.

[0045] The above-mentioned macro model Y is constructed by connecting a plurality of behavioral models according to the node method. The behavioral model a1 receives the output current Iout as a feedback input, and thus constitutes a feedback path in the macro model Y. In addition, the output terminal of the behavioral model a1 is directly connected to the discontinuous node L1. The output terminal of the behavioral model a1 is also connected to the discontinuous node L2 via behavioral models a9 and a4. In addition, the output terminal of the behavioral model a1 is also connected to the discontinuous node L3 via behavioral models a9 and a10. As described above, the Zo calculation unit 7y is constructed to calculate the impedance Zo by repeatedly passing through any one of the discontinuous nodes L1 to L3. Then, the above-mentioned convergence problem easily occurs.

[0046] In contrast, the macro model X according to the present disclosure can suppress the occurrence of convergence problems. The macro model X according to an embodiment of the present disclosure will be described in detail below. The macro model X according to an embodiment of the present disclosure includes the same structure as the above-mentioned macro model Y. Therefore, the same structure is identified with the same symbol, and its description is omitted.

[0047] <Macro Model X According to Embodiment>

[0048] Macromodel X is a SPICE model based on the nodal method.

[0049] Figure 4 is a block diagram showing the structure of the macro model X. Figure 4 As shown, the macro model X includes a Zo calculation unit 7x and behavioral models a1 to a3. The Zo calculation unit 7x is a behavioral model whose function (more specifically, the function of calculating the impedance Zo) is simulated by a conditional branch (first conditional branch ifx1). The Zo calculation unit 7x is defined by the following formula (1).

[0050] [Mathematical formula 1]

[0051]

[0052] As shown in formula (1), the calculation formula of Zo calculation unit 7x is composed of a plurality of conditional branches (in Figure 4 In the example, one of the two conditional branches, i.e., the second conditional branch ifx2 and the third conditional branch ifx3) (in Figure 4 Here, the highest defined conditional branch in formula (1) is set to the first conditional branch ifx1. In the options of the first conditional branch ifx1, the conditional branch selected when the first conditional branch ifx1 is true is set to the second conditional branch ifx2. In the options of the first conditional branch ifx1, the conditional branch selected when the first conditional branch ifx1 is false is set to the third conditional branch ifx3.

[0053] like Figure 4 As shown in formula (1), the first conditional branch ifx1 determines whether the first conditional branch ifx1 is true or false based on the output Vo_Vin (first input) of the behavior model a1. As mentioned above, the value of the output Vo_Vin is the difference between the output current Iout and the input current Iin.

[0054] Whether the second conditional branch ifx2 is true or false is determined based on the output Vo_Vin, I1 (second input) and I2 (third input). In the options of the second conditional branch ifx2, the formula (=I1×100×maglimit) selected when the second conditional branch ifx2 is true is called the first formula. In the options of the second conditional branch ifx2, the formula selected when the second conditional branch ifx2 is false is called the second formula (=I1×100).

[0055] The third conditional branch ifx3 determines whether the third conditional branch ifx3 is true or false based on the output V0_VI, I3 (fourth input) and I4 (fifth input). In the options of the third conditional branch ifx3, the formula (=I3×100×maglimit) selected when the third conditional branch ifx3 is true is called the third formula. In the options of the third conditional branch ifx3, the formula (=I3×100) selected when the third conditional branch ifx3 is false is called the fourth formula.

[0056] The first conditional branch ifx1 will be described in detail. When the value of the output Vo_Vi is negative, in the options of the first conditional branch ifx1 (either of the second conditional branch ifx2 and the third conditional branch ifx3), the second conditional branch ifx2 is selected. Here, when the output current Iout is greater than I2 (more specifically, when Vo_Vi / (I1×100) is greater than I2), in the options of the second conditional branch ifx2 (either of the first formula and the second formula), the first formula is selected. In this case, the impedance Zo is a value obtained by calculating the absolute value of I1×100×maglimit.

[0057] When the value of the output Vo_Vi is negative and the output current Iout is equal to or less than I2 (more specifically, when Vo_Vi / (I1×100) is equal to or less than I2), the second formula is selected in the option of the second conditional branch ifx2. In this case, the impedance Zo is a value obtained by calculating the absolute value of I1×100.

[0058] On the other hand, when the value of the output Vo_Vi is positive, in the options of the first conditional branch ifx1, the third conditional branch ifx3 is selected. Here, when the output current Iout is greater than I4 (more specifically, when Vo_Vi / (I3×100) is greater than I4), in the options of the third conditional branch ifx3 (either the third formula or the fourth formula), the third formula is selected. In this case, the impedance Zo is a value obtained by calculating the absolute value of I3×100×maglimit.

[0059] When the value of the output Vo_Vi is positive and the output current Iout is equal to or less than I4 (more specifically, when Vo_Vi / (I3×100) is equal to or less than I4), the fourth formula is selected in the options of the third conditional branch ifx3. In this case, the impedance Zo is a value obtained by calculating the absolute value of I3×100.

[0060] As described above, the Zo calculation unit 7x is composed of one behavior model (first conditional branch ifx1). Therefore, a relatively small number of nodes are provided in the Zo calculation unit 7x, and thus convergence problems are less likely to occur.

[0061] As described above, the Zo calculation unit 7x is composed of a behavior model (first conditional branch ifx1) including a plurality of conditional branches (second conditional branch ifx2 and third conditional branch ifx3) as options. Therefore, convergence problems are unlikely to occur.

[0062] The Zo calculation unit 7x selects one of the calculation formulas of the four modes (one of the first to fourth formulas) according to the output current Iout to calculate the impedance Zo. Therefore, the impedance Zo can be calculated more accurately according to the output current Iout. Therefore, the macro model X can perform more accurate simulation while suppressing the convergence problem as described above.

[0063] <Circuit Design Simulator>

[0064] Figure 5 is a block diagram showing a structural example of a circuit design simulator using the above-mentioned macro model X. The circuit design simulator 210 in this structural example is a computer including a calculation unit 211, a storage unit 212, an operation unit 213, a display unit 214, and a communication unit 215, and the circuit design simulation program 300 stored in the storage unit 212 is executed by the calculation unit 211 to realize the circuit design simulator 210.

[0065] The calculation unit 211 comprehensively controls the operation of the circuit design simulator 210. For example, the calculation unit 211 executes the circuit design simulation program 300 stored in the storage unit 212 to perform various types of calculation processing for realizing the functions of the circuit design simulator 210, and also performs recognition processing of user operations input from the operation unit 213, display control of various types of screens on the display unit 214, etc. As the calculation unit 211, for example, a CPU (Central Processing Unit) can be used.

[0066] The storage unit 212 is used as a storage area for an OS (operating system) program and various types of software (including the circuit design simulation program 300), and is also used as a storage area for various types of data generated by a user and an operation area for various types of software. As the storage unit 212, a hard disk drive, a solid state drive, a USB (Universal Serial Bus) memory, etc. can be used.

[0067] The operation unit 213 receives various types of user operations such as circuit generation operation, component reference operation, and probe mounting operation, and sends them to the calculation unit 211. As the operation unit 213, a keyboard, a mouse, a trackball, an input tablet, a touch panel, or the like can be used.

[0068] The display unit 214 displays various types of screens such as a circuit generation column, a parts tray, and a waveform drawing window based on instructions from the calculation unit 211. As the display unit 214, a liquid crystal display or the like can be used.

[0069] The communication unit 215 performs information communication via an electrical communication line 220 such as the Internet or a LAN (Local Area Network) based on an instruction from the calculation unit 211. For example, the communication unit 215 performs information communication with servers 230X to 230Z of a manufacturer that manufactures and sells semiconductor integrated circuit devices via the electrical communication line 220, and downloads a macro model file (*.mod) or the like.

[0070] The circuit design simulator 210 as described above is used, and thus simulation verification (such as characteristic evaluation and operation check) can be performed on the simulation circuit before the simulation circuit is actually manufactured as a prototype.

[0071] <Circuit Design Simulation Program>

[0072] Figure 6 300. The circuit design simulation program 300 (for example, a circuit design simulation program based on SPICE) is a program executed by a computer to cause the computer to function as a circuit design simulator 210 (see Figure 5 ) is a software that plays a role. The circuit design simulation program 300 in this structural example includes a main program 310 and a model library 320. The circuit design simulation program 300 is transmitted or distributed via a physical medium such as an optical disk (such as a CD-ROM or DVD-ROM) or a semiconductor memory (such as a USB memory) or via an electrical communication line such as the Internet.

[0073] The main program 310 is the core part for enabling the computer to function as a circuit design simulator 210, and is formed as a collection of various types of module programs (for example, a circuit generation module 311, a component reference module 312, a probe installation module 313, a waveform drawing module 314, and a waveform analysis module 315).

[0074] The circuit generation module 311 is a component program for causing the calculation unit 211 and the display unit 214 to function in such a manner that a circuit is generated on the circuit design simulator 210 based on the input from the operation unit 213. When the user arranges the component symbols (such as resistors, capacitors, transistors, diodes, operational amplifiers, voltage sources, current sources, and wiring) displayed on the display unit 214 in the circuit generation column using the operation unit 213, the circuit generation module 311 generates a text-based code corresponding to the details of the arrangement. In this way, the user can intuitively generate an arbitrary simulation circuit without directly editing the text-based code.

[0075] The component reference module 312 is a component program for causing the calculation unit 211 and the display unit 214 to function in such a manner as to refer to the model library 320 based on an input from the operation unit 213. For example, when the user selects a symbol of an operational amplifier from the component tray displayed on the display unit 214 using the operation unit 213, the component reference module 312 refers to a macro model 323 (which corresponds to the previously described macro model X) for the operational amplifier included in the model library 320.

[0076] The probe installation module 313 is a component program for causing the calculation unit 211 and the display unit 214 to function in such a manner that a probe (a measurement point of voltage or current) is installed on the circuit diagram based on an input from the operation unit 213. For example, when a user clicks a specific node on the circuit diagram displayed on the display unit 214 with a mouse using the operation unit 213, the probe installation module 313 installs a probe on the clicked node.

[0077] The waveform drawing module 314 is an element program for causing the calculation unit 211 and the display unit 214 to function in such a manner as to draw a waveform of a node on which a probe is mounted based on an input from the operation unit 213. For example, when a user mounts a probe on an output terminal of an operational amplifier displayed on the display unit 214 using the operation unit 213, the waveform drawing module 314 displays an output waveform (pseudo oscilloscope waveform) of the operational amplifier on the waveform drawing window.

[0078] The waveform analysis module 315 is an element program for causing the calculation unit 211 and the display unit 214 to function in such a manner as to perform waveform analysis on the node on which the probe is mounted based on the input from the operation unit 213. Examples of waveform analysis that can be performed by the waveform analysis module 315 include transient analysis, DC analysis, small signal AC analysis, noise analysis, and the like.

[0079] The model library 320 includes various simulation models (such as a passive component model 321, an active component model 322, and a macro model 323) used in the circuit design simulator 201, and is referred to by the main program 310 (particularly, the component reference module 312) as a component of the circuit design simulation program 300. The passive component model 321 is a program that operates a computer to simulate the response of passive components (such as resistors and capacitors) on the circuit design simulator 210. The active component model 322 is a program that operates a computer to simulate the response of active components (such as transistors and diodes) on the circuit design simulator 210. The macro model 323 for an operational amplifier (which corresponds to the previously described macro model X) is a program that operates a computer to simulate the response of an operational amplifier on the circuit design simulator 210. The above-mentioned simulation models (passive component model 321, active component model 322, and macro model 323) include simulation models that can be downloaded free of charge from servers 230X to 230Z of a supplier that manufactures and sells semiconductor integrated circuit devices via the electrical communication line 220.

[0080] The circuit design simulation program 300 as described above is used, and thus a general-purpose computer such as a personal computer or a workstation can be used as the circuit design simulator 210 .

[0081] <Other variants>

[0082] In addition to the above-mentioned embodiments, the various technical features disclosed in this specification can be changed in various ways without departing from the spirit of its technical creation. In other words, the above-mentioned embodiments should be considered to be illustrative rather than restrictive in all aspects, and the technical scope of the present invention is not limited to the above-mentioned embodiments, and the meaning equivalent to the scope of the claims and all changes within the scope should be understood to be included therein.

[0083] For example, the first to fourth formulas described above may include conditional branches as options. In this way, various functions can be defined by one behavioral model. Thus, a macromodel consisting of a relatively small number of nodes is used, and thus relatively complex functions can be highly simulated while suppressing the convergence problem described previously.

[0084] Although it is assumed that the macro model X is a SPICE model according to the node method, the macro model X is not limited to the SPICE model and may be another simulation model as long as the macro model X is a simulation model using the method according to the node method.

[0085] The Zo calculation unit 7x may be constructed to include another behavior model instead of the first conditional branch ifx1. In this way, a macro model X capable of performing a more complex simulation may be provided.

[0086] The electronic component that is a simulation object of the above-mentioned macro model X is not limited to the above-mentioned operational amplifier, and may be another semiconductor integrated circuit device.

[0087] <<Notes>>

[0088] The macro model (X) disclosed in the present specification is a macro model (X) used in a circuit design simulator (210) based on a node method, and the macro model (X) is constructed to include a behavioral model (7x), the function of which is defined by a conditional branch (ifx1) including multiple conditional branches (ifx2 and ifx3) as options (first structure).

[0089] Preferably, in the macro model (X) according to the first structure, the behavioral model (7x) includes a first conditional branch (ifx1), a second conditional branch (ifx2) and a third conditional branch (ifx3), the first conditional branch (ifx1) determines whether the first conditional branch (ifx1) is true or false, and when the first conditional branch (ifx1) is true, the second conditional branch (ifx2) is selected, and when the first conditional branch (ifx1) is false, the third conditional branch (ifx3) is selected, the second conditional branch (ifx2) is constructed to include a first formula and a second formula, when the second conditional branch (ifx2) is true, the first formula is selected, and when the second conditional branch (ifx2) is false, the second formula is selected, the third conditional branch (ifx3) is constructed to include a third formula and a fourth formula, when the third conditional branch (ifx3) is true, the third formula is selected, and when the third conditional branch (ifx3) is false, the fourth formula is selected (second structure).

[0090] Preferably, in the macro model (X) according to the second structure, the first conditional branch (ifx1) is defined as determining whether the first conditional branch (ifx1) is true or false based on the first input (Vo_Vi), the second conditional branch (ifx2) is defined as determining whether the second conditional branch (ifx2) is true or false based on the first input (Vo_Vi), the second input (I1) and the third input (I2), the third conditional branch (ifx3) is defined as determining whether the third conditional branch (ifx3) is true or false based on the first input (Vo_Vi), the fourth input (I3) and the fifth input (I4), the first formula is a calculation formula based on the second input (I1) and a predetermined parameter value (maglimit), the second formula is a calculation formula based on the second input (I1), the third formula is a calculation formula based on the fourth input (I3) and the parameter value (maglimit), and the fourth formula is a calculation formula based on the fourth input (I3) (third structure).

[0091] Preferably, in the macro model (X) according to any one of the first to third structures, the behavior model (7x) is configured to receive a feedback input corresponding to an output (Iout) of the behavior model (7x) (fourth structure).

[0092] Preferably, in the macro model (X) according to the fourth structure, the macro model is configured to simulate the function of an operational amplifier (fifth structure).

[0093] The circuit design simulation program (300) disclosed in this specification is a circuit design simulation program (300) configured to be executed by a computer including a computing unit and to cause the computer to function as a circuit design simulator (210), the circuit design simulation program including a macro model (X) according to any one of the first to fifth structures, and the circuit design simulation program is configured to operate the computer so as to simulate the response of a semiconductor integrated circuit device (2) on the circuit design simulator (210) (seventh structure).

[0094] The circuit design simulator (210) disclosed in this specification is configured to be realized by causing a computer to execute the circuit design simulation program (300) according to the sixth configuration (seventh configuration).

[0095] In the macro model (X) of the first structure, a macro model (X) including multiple conditional formulas in the options (ifx2 and ifx3) of the conditional branch (ifx1) can be defined. Therefore, the number of nodes can be reduced to define a more complex calculation formula. In this way, a macro model (X) capable of performing more complex simulations while suppressing convergence problems can be configured.

[0096] In the macromodel (X) of the second structure, more complex simulations can be performed while suppressing convergence problems.

[0097] In the macro model (X) of the third structure, a predetermined parameter value (maglimit) is defined, and thus the macro model (X) corresponding to various simulations can be configured.

[0098] In the macro model (X) of the fourth structure, it is possible to suppress a convergence problem in the macro model (X) simulating the control circuit including feedback control.

[0099] In the macro model (X) of the fifth structure, the convergence problem in the macro model (X) simulating the operational amplifier function can be suppressed.

[0100] In the circuit design simulation program (300) of the sixth structure, simulation verification can be performed on the simulated circuit before the simulated circuit is actually manufactured as a prototype.

[0101] In the circuit design simulator (210) of the seventh structure, a general-purpose computer can be used as the circuit design simulator (210).

Claims

1. A macro model for use in a circuit design simulator based on a node approach, The macro model is configured to include a behavior model, and the function of the behavior model is defined by a conditional branch including a plurality of conditional branches as options.

2. The macro model according to claim 1, The behavior model includes: a first conditional branch, the first conditional branch determining whether the first conditional branch is true or false, a second conditional branch, selected when the first conditional branch is true, and a third conditional branch, selected when the first conditional branch is false, The second conditional branch is constituted to include: a first formula, wherein the first formula is selected when the second conditional branch is true, and a second formula, which is selected when the second conditional branch is false, and The third conditional branch is constituted to include: a third formula, which is selected when the third conditional branch is true, and A fourth formula is selected when the third conditional branch is false.

3. The macro model according to claim 2, wherein the first conditional branch is defined as determining whether the first conditional branch is true or false based on a first input, The second conditional branch is defined as determining whether the second conditional branch is true or false based on the first input, the second input, and the third input, The third conditional branch is defined as determining whether the third conditional branch is true or false based on the first input, the fourth input, and the fifth input, The first formula is a calculation formula based on the second input and a predetermined parameter value, The second formula is a calculation formula based on the second input, The third formula is a calculation formula based on the fourth input and the parameter value, and The fourth formula is a calculation formula based on the fourth input.

4. The macro model according to claim 1, The behavior model is configured to receive a feedback input corresponding to an output of the behavior model.

5. The macro model according to claim 4, The macromodel is designed to simulate the function of an operational amplifier.

6. A circuit design simulation program, which consists of: is executed by a computer comprising a computing unit, and causing the computer to function as the circuit design simulator, wherein the circuit design simulation program comprises a macro model according to any one of claims 1 to 5, and The circuit design simulation program operates a computer so that the response of a semiconductor integrated circuit device is simulated on the circuit design simulator.

7. A circuit design simulator, which is realized by causing a computer to execute the circuit design simulation program according to claim 6.

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