A method, apparatus, device, and medium for violation elimination based on a cost function.

Abstract

The present application discloses a violation elimination method, device, equipment and medium based on a cost function, which relates to the field of chip manufacturing, including: for the current chip design graphic after optical proximity correction, traverse each edge in the current chip design graphic, and determine several groups of edges based on the traversed current edge and several surrounding candidate edges; determine the corresponding cost function based on the mask rules to which the several groups of edges belong respectively to calculate the cost value of the corresponding group of edges; determine violations from the several groups of edges based on the cost value; move the position of the violation to update the current chip design graphic, and return to the step of traversing each edge in the current chip design graphic until there are no violations in the several groups of edges. The present application searches the entire solution space to determine violations from the several groups of edges based on the cost value of each group of edges, and re-searches the entire solution space after eliminating the violations until all violations are eliminated, so that all violations can be eliminated more easily through a larger search space.

Description

Technical Field

[0001] The present invention relates to the field of chip manufacturing, and in particular to a violation elimination method, device, equipment and medium based on a cost function. Background Art

[0002] After the chip design graphics are processed by OPC (Optical Proximity Correction) and sent to the mask production factory, the OPC-processed graphics need to be subjected to a mask rule check (MRC) to ensure that there are no MRC violations in the graphics sent to the mask production factory.

[0003] The prior art generally eliminates MRC violations based on rules. Specifically, the method is: first query MRC violations from the graph after OPC processing, then traverse each MRC violation in turn, and eliminate the currently traversed MRC violation by moving the related edges of the MRC violation. However, this method may generate new MRC violations while eliminating the currently traversed MRC violation. In particular, when an edge involves multiple MRC violations, the solutions to these multiple MRC violations may conflict with each other, resulting in one or more MRC violations being unable to be eliminated. Therefore, how to eliminate all violations in the graph after OPC processing is a problem to be solved by those skilled in the art. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a method, device, equipment and medium for eliminating violations based on a cost function, which can determine violations from a plurality of groups of edges based on the cost value of each group of edges by searching the entire solution space, and re-search the entire solution space after eliminating the violations until all violations are eliminated, so that all violations can be eliminated more easily through a larger search space. The specific scheme is as follows:

[0005] In a first aspect, the present application provides a violation elimination method based on a cost function, comprising:

[0006] Acquire a chip design pattern after optical proximity correction to obtain a current chip design pattern;

[0007] Traversing each edge in the current chip design graph, and determining a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the current edge and one of the candidate edges;

[0008] Determining cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong, so as to calculate cost values ​​of the corresponding group of edges according to the cost functions;

[0009] Determine a target group of edges from the plurality of groups of edges based on the cost value; the target group of edges is a violation in the plurality of groups of edges that satisfies a preset violation condition;

[0010] The position of the target group of edges is moved to update the current chip design graph, and the step of traversing each edge in the current chip design graph is jumped again until the several groups of edges do not meet the preset violation conditions to eliminate all violations in the current chip design graph.

[0011] Optionally, before determining a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges, the method further includes:

[0012] Based on a preset search distance and the current edge traversed, determine a target search range in the current chip design graph, and determine a plurality of candidate edges in the opposite direction of the current edge from the target search range;

[0013] Wherein, the direction of each edge in the current chip design graph is determined based on a preset clockwise rotation direction.

[0014] Optionally, determining the cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong includes:

[0015] Based on whether projections of any group of edges among the plurality of groups of edges on the same plane overlap and whether the any group of edges is located in the same figure in the current chip design figure, determine the mask rule to which the any group of edges belongs, and determine the cost function corresponding to the any group of edges based on the mask rule to which the any group of edges belongs;

[0016] Wherein, the same plane and any set of edges are parallel to each other.

[0017] Optionally, determining the mask rule to which any group of edges belongs based on whether projections of any group of edges among the plurality of groups of edges on the same plane overlap and whether the any group of edges are located in the same figure in the current chip design figure includes:

[0018] If the any group of edges are located in the same graph in the current chip design graph, determining that the mask rule to which the any group of edges belongs is a first mask rule;

[0019] If the projections of any group of edges on the same plane overlap, and the any group of edges are not located in the same figure in the current chip design figure, determining that the mask rule to which the any group of edges belongs is the second mask rule;

[0020] If the projections of any group of edges on the same plane do not overlap, and the any group of edges are not located in the same figure in the current chip design figure, it is determined that the mask rule to which the any group of edges belongs is the third mask rule.

[0021] Optionally, calculating the cost value of a corresponding set of edges according to the cost function includes:

[0022] When the cost function is a first cost function corresponding to the first mask rule to which the arbitrary group of edges belongs, substituting a target weight corresponding to the arbitrary group of edges, a first preset distance threshold, and a target distance between two edges included in the arbitrary group of edges into the first cost function to calculate a cost value of the arbitrary group of edges;

[0023] When the cost function is a second cost function corresponding to the second mask rule to which the arbitrary group of edges belongs, substituting the target weight, the second preset distance threshold, and the target distance into the second cost function to calculate the cost value of the arbitrary group of edges;

[0024] When the cost function is a third cost function corresponding to the third mask rule to which the arbitrary group of edges belongs, the target weight, the third preset distance threshold, and the point spacing are substituted into the third cost function to calculate the cost value of the arbitrary group of edges; the point spacing is the minimum value of the distances between two points on different edges included in the arbitrary group of edges;

[0025] Among them, the target weight is a weight determined based on the weights corresponding to the two edges included in any group of edges; the first preset distance threshold, the second preset distance threshold and the third preset distance threshold are thresholds corresponding to the first mask rule, the second mask rule and the third mask rule respectively.

[0026] Optionally, the preset violation condition includes that the cost value is not zero.

[0027] Optionally, the moving the position of the target group edge includes:

[0028] Based on the sum of the cost values ​​of the target group edges, the moving direction and moving amount of each edge in the target group edges are determined to move the position of each edge in the target group edges.

[0029] In a second aspect, the present application provides a violation elimination device based on a cost function, comprising:

[0030] A graphics acquisition module, used to acquire a chip design graphic after optical proximity correction to obtain a current chip design graphic;

[0031] A traversal module, used to traverse each edge in the current chip design graph, and determine a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the current edge and one of the candidate edges;

[0032] A cost value calculation module, used for determining cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong, so as to calculate the cost value of a corresponding group of edges according to the cost function;

[0033] A violation determination module, configured to determine a target group of edges from the plurality of groups of edges based on the cost value; the target group of edges being the violations in the plurality of groups of edges that meet a preset violation condition;

[0034] A violation elimination module is used to move the position of the target group of edges to update the current chip design graph, and jump back to the step of traversing each edge in the current chip design graph until the several groups of edges do not meet the preset violation conditions, so as to eliminate all violations in the current chip design graph.

[0035] In a third aspect, the present application provides an electronic device, including:

[0036] Memory, used to store computer programs;

[0037] A processor is used to execute the computer program to implement the aforementioned violation elimination method based on the cost function.

[0038] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned violation elimination method based on a cost function.

[0039] In the present application, a chip design graphic after optical proximity correction is obtained to obtain a current chip design graphic; each edge in the current chip design graphic is traversed, and a plurality of groups of edges are determined based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the traversed current edge and a candidate edge; cost functions corresponding to the plurality of groups of edges are determined based on mask rules to which the plurality of groups of edges belong, so as to calculate the cost value of the corresponding group of edges according to the cost function; a target group of edges is determined from the plurality of groups of edges based on the cost value; the target group of edges is a violation in the plurality of groups of edges that meets a preset violation condition; the position of the target group of edges is moved to update the current chip design graphic, and the step of traversing each edge in the current chip design graphic is jumped again until the plurality of groups of edges do not meet the preset violation condition, so as to eliminate all violations in the current chip design graphic. It can be seen that the present application searches the entire solution space by traversing each edge in the current chip design graph, and determines the corresponding cost function based on the mask rule to which each group of edges belongs to calculate the cost value of each group of edges, and then determines violations from several groups of edges based on the cost value of each group of edges, eliminates the violations, and re-searches the entire solution space after elimination, until all violations in the current chip design graph are eliminated. In this way, the present application can more easily eliminate all violations in the chip design graph according to the cost function through a larger search space. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0041] Figure 1 A schematic diagram of an MRC rule between edges in a graph disclosed in the present application;

[0042] Figure 2 A schematic diagram of an MRC rule between points in a graph disclosed in the present application;

[0043] Figure 3 A schematic diagram of the MRC rule for the area of ​​a graphic disclosed in this application;

[0044] Figure 4 A flow chart of a violation elimination method based on a cost function disclosed in this application;

[0045] Figure 5 A schematic diagram of the edge direction of a graph disclosed in this application;

[0046] Figure 6 A schematic diagram of the edge direction of another type of graphic disclosed in this application;

[0047] Figure 7 A schematic diagram of a current edge and a candidate edge in a chip design graph disclosed in the present application;

[0048] Figure 8 A schematic diagram of a current edge and a candidate edge in another chip design graph disclosed in the present application;

[0049] Fig. 9 A schematic diagram of a current edge and a candidate edge in another chip design graph disclosed in the present application;

[0050] Fig.10 A schematic diagram of the structure of a violation elimination device based on a cost function disclosed in this application;

[0051] Fig.11 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Before the chip design graphics are processed by OPC and sent to the mask production factory, the OPC-processed graphics need to be checked for mask rules to ensure that there are no MRC violations in the graphics sent to the mask production factory. To this end, the present application provides a violation elimination method based on a cost function, which searches the entire solution space to determine violations from a number of groups of edges based on the cost value of each group of edges, and re-searches the entire solution space after eliminating the violations until all violations are eliminated, so that all violations can be eliminated more easily through a larger search space.

[0054] Generally speaking, MRC rules mainly include the following three types: Figure 1 As shown in the figure, the minimum value of the line width and line spacing between the two edges of the graphic (edge-to-edge) can be set. The minimum value of the line width and line spacing between the two edges of the sub-resolution auxiliary graphic (SRAF, Sub-Resolution Assist Feature) can also be set. That is, the line width and line spacing between the two edges of the graphic must not be less than the specified minimum value. Figure 2As shown in the figure, the minimum value of the point spacing (space) between the two corner points of the graphic (corner-to-corner) is limited. The minimum value of the point spacing between the two corner points of the sub-resolution auxiliary graphic and the main graphic can also be limited. That is, the point spacing between the two corner points of the graphic must not be less than the minimum value. The third type is Figure 3 As shown, a minimum value is limited to the area of ​​the sub-resolution auxiliary pattern, that is, the area of ​​the sub-resolution auxiliary pattern must not be less than the limited minimum value.

[0055] See also Figure 4 As shown, the embodiment of the present invention discloses a violation elimination method based on a cost function, comprising:

[0056] Step S11, obtaining the chip design pattern after optical proximity correction to obtain the current chip design pattern.

[0057] In this embodiment, the original chip design pattern is obtained, and optical proximity correction is performed on the original chip design pattern to obtain a chip design pattern after optical proximity correction, and then the chip design pattern after optical proximity correction is determined as the current chip design pattern for mask rule checking, thereby eliminating violations in the chip design pattern.

[0058] Step S12, traverse each edge in the current chip design graph, and determine a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the current edge and one of the candidate edges.

[0059] In this embodiment, each edge in the current chip design graph is traversed, and based on the traversed current edge, several candidate edges around the current edge are determined from the current chip design graph, so as to determine several groups of edges based on the current edge and the several surrounding candidate edges. It should be noted that each group of edges includes the traversed current edge and a surrounding candidate edge; wherein, for the same current edge, different groups of edges include the same current edge and different candidate edges.

[0060] Specifically, for each edge traversed from the current chip design graph, it is necessary to determine several candidate edges around the edge from the current chip design graph, and construct a corresponding group of edges based on the edge and a different surrounding candidate edge, thereby obtaining several groups of edges.

[0061] For several candidate edges around the current edge in the current chip design graph, it is first necessary to determine a target search range in the current chip design graph based on a preset search distance and the current edge traversed, and then determine several candidate edges in the opposite direction of the current edge from the target search range. It should be noted that the direction of each edge in the current chip design graph is determined based on a preset clockwise rotation direction.

[0062] like Figure 5 As shown, when the preset clockwise rotation direction is the clockwise rotation direction, the side 1 of the pattern 1 in the current chip design pattern faces left, the side 2 faces upward, the side 3 faces right, and the side 4 faces downward. Figure 6 As shown, when the preset clockwise rotation direction is the counterclockwise rotation direction, the side 1 of the graphic 1 in the current chip design graphic faces right, the side 2 faces downward, the side 3 faces left, and the side 4 faces upward.

[0063] like Figure 7 As shown, when the preset clockwise rotation direction is clockwise, if edge No. 1 of Figure 1 in the current chip design figure is the current edge, since the current edge is facing left, it is necessary to determine several candidate edges facing right from the target search range of the current chip design figure. At this time, the several candidate edges include edge No. 3 of Figure 1 (candidate edge 1) and edge No. 3 of Figure 2 (candidate edge 2).

[0064] Step S13: determining cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong, so as to calculate cost values ​​of a corresponding group of edges according to the cost functions.

[0065] In this embodiment, after determining a plurality of groups of edges from the current chip design graph, it is necessary to further determine the mask rule to which each group of edges belongs, and determine the cost function corresponding to each group of edges based on the mask rule to which each group of edges belongs, so as to calculate the cost value of each group of edges according to the cost function corresponding to each group of edges. It should be noted that different mask rules correspond to different cost functions.

[0066] Taking any group of edges among several groups of edges as an example, based on whether the projections of any group of edges on the same plane overlap and whether any group of edges are located in the same figure in the current chip design figure, the mask rule to which any group of edges belongs is determined, and the cost function corresponding to any group of edges is determined based on the mask rule to which any group of edges belongs; wherein the same plane is parallel to any group of edges.

[0067] Among them, as to whether any group of edges is located in the same figure in the current chip design figure, one method can directly determine whether two edges in any group of edges are located in the same figure in the current chip design figure. Another method can use a preset clockwise rotation direction and based on the position of a candidate edge in any group of edges relative to the current edge to determine whether any group of edges is located in the same figure in the current chip design figure; specifically, based on the direction of the current edge, the position of the candidate edge relative to the current edge is determined, and then using a preset clockwise rotation direction and based on the position of the candidate edge relative to the current edge, it is determined whether any group of edges is located in the same figure in the current chip design figure.

[0068] like Figure 7As shown, when the preset clockwise rotation direction is the clockwise rotation direction, if any set of edges includes the current edge and candidate edge 1, since the direction of the current edge is to the left, the position of candidate edge 1 relative to the current edge is on the right, and at this time, it is determined that the current edge and candidate edge 1 are located in the same figure in the current chip design figure. If any set of edges includes the current edge and candidate edge 2, since the direction of the current edge is to the left, the position of candidate edge 2 relative to the current edge is on the left, and at this time, it is determined that the current edge and candidate edge 2 are not located in the same figure in the current chip design figure.

[0069] like Figure 8 As shown, when the preset clockwise rotation direction is the counterclockwise rotation direction, if any set of edges includes the current edge and candidate edge 1, since the direction of the current edge is facing right, the position of candidate edge 1 relative to the current edge is on the left, and at this time, it is determined that the current edge and candidate edge 1 are located in the same figure in the current chip design figure. If any set of edges includes the current edge and candidate edge 2, since the direction of the current edge is facing right, the position of candidate edge 2 relative to the current edge is on the right, and at this time, it is determined that the current edge and candidate edge 2 are not located in the same figure in the current chip design figure.

[0070] The mask rule for any group of edges in the plurality of groups of edges may include the following three cases:

[0071] The first case is: if any group of edges is located in the same figure in the current chip design figure, then regardless of whether the projections of any group of edges on the same plane overlap, the mask rule to which any group of edges belongs is determined to be the first mask rule. The first mask rule is that the distance between two edges of the same figure must be no less than a first preset distance threshold.

[0072] like Figure 7 As shown, taking any group of edges including the current edge and the candidate edge 1 as an example, since the current edge and the candidate edge 1 are located in the same graph in the current chip design graph, the mask rule to which the any group of edges belongs is determined to be the first mask rule.

[0073] The second case is: if the projections of any group of edges on the same plane overlap, and any group of edges are not located in the same figure in the current chip design figure, then the mask rule to which any group of edges belongs is determined to be the second mask rule. The second mask rule is that the distance between two edges of different figures must be no less than a second preset distance threshold.

[0074] like Figure 7 As shown, taking any group of edges including the current edge and candidate edge 2 as an example, since the projections of the current edge and candidate edge 2 on the same plane overlap and are not located in the same figure in the current chip design figure, the mask rule to which any group of edges belongs is determined to be the second mask rule.

[0075] The third case is: if the projections of any group of edges on the same plane do not overlap, and any group of edges are not located in the same figure in the current chip design figure, then the mask rule to which any group of edges belongs is determined to be the third mask rule. The third mask rule is that the distance between two points of different figures must be no less than a third preset distance threshold.

[0076] like Fig. 9 As shown, taking any group of edges including the current edge and candidate edge 3 as an example, since the projections of the current edge and candidate edge 3 on the same plane do not overlap and are not located in the same figure in the current chip design figure, the mask rule to which any group of edges belongs is determined to be the third mask rule.

[0077] It should be noted that the first preset distance threshold, the second preset distance threshold and the third preset distance threshold are the thresholds corresponding to the first mask rule, the second mask rule and the third mask rule respectively, and the first preset distance threshold, the second preset distance threshold and the third preset distance threshold can be set to the same value or to different values, which is not limited here.

[0078] It should also be noted that the preset search distance for searching for candidate edges can be determined based on a first preset distance threshold, a second preset distance threshold, and a third preset distance threshold; for example, the preset search distance is set to a preset multiple of the minimum value among the first preset distance threshold, the second preset distance threshold, and the third preset distance threshold.

[0079] On this basis, since different masking rules correspond to different cost functions, the cost value of a set of edges calculated according to the cost function can also be divided into the following three cases:

[0080] The first case is: when the cost function is the first cost function corresponding to the first mask rule to which any group of edges belongs, the target weight corresponding to any group of edges, the first preset distance threshold, and the target distance between two edges included in any group of edges are substituted into the first cost function to calculate the cost value of any group of edges.

[0081] Specifically, the target weight corresponding to any group of edges, the first preset distance threshold, and the target distance between two edges included in any group of edges are substituted into the first cost function to first determine the minimum value from the first preset distance threshold and the target distance, and determine the difference between the first preset distance threshold and the minimum value, and then calculate the cost value based on the product between the target weight and the difference. The formula involved is:

[0082] cost=weight×[mrc_min_width-MIN(width, mrc_min_width)] power ;

[0083] cost represents the cost value, weight represents the target weight, mrc_min_width represents the first preset distance threshold, MIN represents the function used to find the minimum value, width represents the target distance, and power represents the exponent, which is usually 2.

[0084] It should be noted that when the target distance between two edges included in any group of edges is not less than the first preset distance threshold, the cost value calculated based on the first cost function is zero; when the target distance between two edges included in any group of edges is less than the first preset distance threshold, the cost value calculated based on the first cost function is not zero.

[0085] The second case is: when the cost function is a second cost function corresponding to the second mask rule to which any group of edges belongs, the target weight corresponding to any group of edges, the second preset distance threshold, and the target distance between two edges included in any group of edges are substituted into the second cost function to calculate the cost value of any group of edges.

[0086] Specifically, the target weight corresponding to any group of edges, the second preset distance threshold, and the target distance between two edges included in any group of edges are substituted into the second cost function to first determine the minimum value from the second preset distance threshold and the target distance, and determine the difference between the second preset distance threshold and the minimum value, and then calculate the cost value based on the product between the target weight and the difference. The formula involved is:

[0087] cost=weight×[mrc_min_space-MIN(space,mrc_min_space)] power ;

[0088] cost represents the cost value, weight represents the target weight, mrc_min_space represents the second preset distance threshold, MIN represents the function used to find the minimum value, space represents the target distance, and power represents the exponent, which is usually 2.

[0089] It should be noted that when the target distance between two edges included in any group of edges is not less than the second preset distance threshold, the cost value calculated based on the second cost function is zero; when the target distance between two edges included in any group of edges is less than the second preset distance threshold, the cost value calculated based on the second cost function is not zero.

[0090] The third case is: when the cost function is the third cost function corresponding to the third mask rule to which any group of edges belongs, the target weight, the third preset distance threshold, and the point spacing corresponding to any group of edges are substituted into the third cost function to calculate the cost value of any group of edges; the point spacing is the minimum value of the distances between two points on different edges contained in any group of edges.

[0091] Specifically, the target weight, the third preset distance threshold, and the point spacing corresponding to any set of edges are substituted into the third cost function to first determine the minimum value from the third preset distance threshold and the point spacing, and determine the difference between the third preset distance threshold and the minimum value, and then calculate the cost value based on the product between the target weight and the difference. The formula involved is:

[0092] cost=weight×[mrc_min_space-MIN(space,mrc_min_space)] power ;

[0093] cost represents the cost value, weight represents the target weight, mrc_min_space represents the third preset distance threshold, MIN represents the function used to find the minimum value, space represents the point spacing, and power represents the exponent, which is usually 2.

[0094] It should be noted that when the point spacing is not less than the third preset distance threshold, the cost value calculated based on the third cost function is zero; when the point spacing is less than the third preset distance threshold, the cost value calculated based on the third cost function is not zero.

[0095] One way to determine the point spacing is to calculate the distance between two points on different edges included in any set of edges, and determine the minimum value of the distance as the point spacing. Fig. 9 As shown, taking any set of edges including the current edge and candidate edge 3 as an example, the distances between two points on the current edge and two points on candidate edge 3 are calculated respectively, and the minimum value of the distances is determined as the point spacing.

[0096] Another way to determine the point spacing is to determine the directions of the two edges involved by any point in the graph where the current edge is located for any point on the current edge included in any set of edges, and determine another point on the candidate edge, where the directions of the two edges involved by another point in the graph where the candidate edge is located are opposite to the directions of the two edges involved by any point in the graph where the current edge is located, and then calculate the distance between any point on the current edge and another point on the candidate edge, and determine the minimum value of the distance as the point spacing. Fig. 9As shown, if the two edges involved by any point in the graph where the current edge is located are edge 1 and edge 4, then the two edges involved by another point in the graph where the candidate edge is located are edge 3 and edge 2, and then the distance between the two points is calculated; if the two edges involved by any point in the graph where the current edge is located are edge 1 and edge 2, then the two edges involved by another point in the graph where the candidate edge is located are edge 3 and edge 4, and then the distance between the two points is calculated; finally, the minimum value of the two calculated distances is determined as the point spacing.

[0097] For the target weight corresponding to any set of edges, the target weight corresponding to any set of edges can be determined based on the weights corresponding to the two edges included in any set of edges; for example, the product of the weights corresponding to the two edges included in any set of edges is calculated to obtain the target weight corresponding to any set of edges. It should be noted that the weight of each edge in the current chip design graph can be opened to the user in advance for setting, or the length of each edge can be simply selected as the weight of each edge.

[0098] Step S14: determining a target group of edges from the plurality of groups of edges based on the cost value; the target group of edges is a violation in the plurality of groups of edges that meets a preset violation condition.

[0099] In this embodiment, after calculating the cost value of each group of edges, a target group of edges that meet a preset violation condition is determined from the plurality of groups of edges based on the cost value, and the target group of edges at this time is the violation in the current chip design graph. Specifically, when the preset violation condition includes that the cost value is not zero, a target group of edges whose cost value is not zero is determined from the plurality of groups of edges.

[0100] Step S15, move the position of the target group of edges to update the current chip design graph, and jump back to the step of traversing each edge in the current chip design graph until the several groups of edges do not meet the preset violation conditions to eliminate all violations in the current chip design graph.

[0101] In this embodiment, after the target group of edges is determined, the moving direction and movement amount of each edge in each target group of edges are determined based on the sum of the cost values ​​of each target group of edges, so as to move the position of each edge in the target group of edges, thereby updating the current chip design graph, and then jumping back to step S12 until several groups of edges do not meet the preset violation conditions, that is, the cost values ​​of several groups of edges are all zero, thereby eliminating all violations in the current chip design graph.

[0102] Specifically, for the moving direction and moving amount of each edge in each target group of edges, the sum of the cost values ​​of each target group of edges can be calculated first, and then the moving direction and moving amount of each edge in each target group of edges can be calculated using an iterative optimization algorithm. The iterative optimization algorithm includes but is not limited to a stochastic gradient descent algorithm.

[0103] It can be seen that the present application searches the entire solution space by traversing each edge in the current chip design graph, and determines the corresponding cost function based on the mask rule to which each group of edges belongs to calculate the cost value of each group of edges, and then determines violations from several groups of edges based on the cost value of each group of edges, eliminates the violations, and re-searches the entire solution space after elimination, until all violations in the current chip design graph are eliminated. In this way, the present application can more easily eliminate all violations in the chip design graph according to the cost function through a larger search space.

[0104] by Figure 7 and Fig. 9 Taking as an example, a violation elimination method based on a cost function disclosed in the present application is elaborated in detail, which may specifically include:

[0105] Obtain the chip design graph after optical proximity correction to obtain the current chip design graph. Traverse each edge in the current chip design graph, and based on the traversed current edge, determine from the current chip design graph a number of candidate edges (candidate edge 1, candidate edge 2, and candidate edge 3) at a certain distance around the current edge, so as to determine a number of groups of edges (current edge and candidate edge 1, current edge and candidate edge 2, current edge and candidate edge 3) based on the current edge and a number of surrounding candidate edges.

[0106] Then, the cost function corresponding to each group of edges is determined based on the mask rule to which each group of edges belongs, and the cost value of each group of edges is calculated according to the cost function corresponding to each group of edges, where the cost value is either equal to zero or greater than zero; then the cost value of each group of edges is accumulated to obtain the sum of the cost values, and it is determined whether the sum of the cost values ​​is zero. If the sum of the cost values ​​is zero, it indicates that there is no violation in the current chip design graphics, and the current chip design graphics can be sent to the mask production factory for production.

[0107] If the sum of the cost values ​​is not zero, a target group of edges with non-zero cost values ​​is determined from several groups of edges, and the target group of edges is the violation in the current chip design graph. The iterative optimization algorithm and the sum of the cost values ​​are used to determine the moving direction and amount of each edge in each target group of edges, so as to move the position of each edge in the target group of edges, thereby updating the current chip design graph, and then returning to the step of traversing each edge in the current chip design graph until the sum of the cost values ​​is zero, that is, the cost values ​​of several groups of edges are all zero, thereby eliminating all violations in the current chip design graph.

[0108] It can be seen that the present application searches the entire solution space by traversing each edge in the current chip design graph, and determines the corresponding cost function based on the mask rule to which each group of edges belongs to calculate the cost value of each group of edges, and then determines violations from several groups of edges based on the cost value of each group of edges, eliminates the violations, and re-searches the entire solution space after elimination, until all violations in the current chip design graph are eliminated. In this way, the present application can more easily eliminate all violations in the chip design graph according to the cost function through a larger search space.

[0109] See also Fig.10 As shown, the embodiment of the present invention discloses a violation elimination device based on a cost function, comprising:

[0110] A pattern acquisition module 11 is used to acquire a chip design pattern after optical proximity correction to obtain a current chip design pattern;

[0111] A traversal module 12, configured to traverse each edge in the current chip design graph, and determine a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the current edge and one of the candidate edges;

[0112] A cost value calculation module 13, configured to determine cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong, so as to calculate the cost value of a corresponding group of edges according to the cost function;

[0113] A violation determination module 14, configured to determine a target group of edges from the plurality of groups of edges based on the cost value; the target group of edges is a violation in the plurality of groups of edges that satisfies a preset violation condition;

[0114] The violation elimination module 15 is used to move the position of the target group of edges to update the current chip design graph, and jump back to the step of traversing each edge in the current chip design graph until the several groups of edges do not meet the preset violation conditions, so as to eliminate all violations in the current chip design graph.

[0115] It can be seen that the present application searches the entire solution space by traversing each edge in the current chip design graph, and determines the corresponding cost function based on the mask rule to which each group of edges belongs to calculate the cost value of each group of edges, and then determines violations from several groups of edges based on the cost value of each group of edges, eliminates the violations, and re-searches the entire solution space after elimination, until all violations in the current chip design graph are eliminated. In this way, the present application can more easily eliminate all violations in the chip design graph according to the cost function through a larger search space.

[0116] In some specific embodiments, the traversal module 12 further includes:

[0117] A candidate edge determination unit, configured to determine a target search range in the current chip design graph based on a preset search distance and a current edge traversed, and determine a plurality of candidate edges in the opposite direction of the current edge from the target search range;

[0118] Wherein, the direction of each edge in the current chip design graph is determined based on a preset clockwise rotation direction.

[0119] In some specific embodiments, the cost value calculation module 13 includes:

[0120] A determination submodule, configured to determine a mask rule to which any group of edges among the plurality of groups of edges belongs based on whether projections of the any group of edges on the same plane overlap and whether the any group of edges is located in the same figure in the current chip design figure, and determine a cost function corresponding to the any group of edges based on the mask rule to which the any group of edges belongs;

[0121] Wherein, the same plane and any set of edges are parallel to each other.

[0122] In some specific embodiments, the determining submodule includes:

[0123] A first rule determination unit, configured to determine that the mask rule to which the any group of edges belongs is a first mask rule if the any group of edges is located in the same graph in the current chip design graph;

[0124] A second rule determination unit, configured to determine that the mask rule to which the any group of edges belongs is a second mask rule if the projections of the any group of edges on the same plane overlap and the any group of edges are not located in the same figure in the current chip design figure;

[0125] The third rule determination unit is used to determine that the mask rule to which any group of edges belongs is the third mask rule if the projections of any group of edges on the same plane do not overlap and the any group of edges are not located in the same figure in the current chip design figure.

[0126] In some specific embodiments, the cost value calculation module 13 includes:

[0127] a first cost value calculation unit, configured to substitute a target weight corresponding to the arbitrary group of edges, a first preset distance threshold, and a target distance between two edges included in the arbitrary group of edges into the first cost function when the cost function is a first cost function corresponding to the first mask rule to which the arbitrary group of edges belongs, so as to calculate a cost value of the arbitrary group of edges;

[0128] a second cost value calculation unit, configured to substitute the target weight, the second preset distance threshold, and the target distance into the second cost function when the cost function is a second cost function corresponding to the second mask rule to which the arbitrary group of edges belongs, so as to calculate the cost value of the arbitrary group of edges;

[0129] a third cost value calculation unit, configured to substitute the target weight, the third preset distance threshold, and the point spacing into the third cost function to calculate the cost value of the arbitrary group of edges when the cost function is a third cost function corresponding to the third mask rule to which the arbitrary group of edges belongs; the point spacing is the minimum value of the distances between two points on different edges included in the arbitrary group of edges;

[0130] Among them, the target weight is a weight determined based on the weights corresponding to the two edges included in any group of edges; the first preset distance threshold, the second preset distance threshold and the third preset distance threshold are thresholds corresponding to the first mask rule, the second mask rule and the third mask rule respectively.

[0131] In some specific embodiments, the violation elimination module 15 includes:

[0132] The position moving unit is used to determine the moving direction and moving amount of each edge in the target group of edges based on the sum of the cost values ​​of each edge in the target group of edges, so as to move the position of each edge in the target group of edges.

[0133] Furthermore, the present application also discloses an electronic device. Fig.11 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be considered as any limitation on the scope of use of the present application.

[0134] Fig.11 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the violation elimination method based on the cost function disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0135] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0136] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0137] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the violation elimination method based on the cost function performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.

[0138] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the violation elimination method based on the cost function disclosed above is implemented. The specific steps of the method can refer to the corresponding contents disclosed in the above embodiments, and will not be repeated here.

[0139] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0140] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0141] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0142] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0143] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A violation elimination method based on cost function, characterized in that: include: Acquire a chip design pattern after optical proximity correction to obtain a current chip design pattern; Traversing each edge in the current chip design graph, and determining a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the current edge and one of the candidate edges; Determining cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong, so as to calculate cost values ​​of the corresponding group of edges according to the cost functions; Determine a target group of edges from the plurality of groups of edges based on the cost value; the target group of edges is a violation in the plurality of groups of edges that satisfies a preset violation condition; The position of the target group of edges is moved to update the current chip design graph, and the process jumps back to the step of traversing each edge in the current chip design graph until the plurality of groups of edges do not satisfy the preset violation condition, so as to eliminate all violations in the current chip design graph; The step of determining the cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong comprises: Based on whether projections of any group of edges among the plurality of groups of edges on the same plane overlap and whether the any group of edges is located in the same figure in the current chip design figure, determine the mask rule to which the any group of edges belongs, and determine the cost function corresponding to the any group of edges based on the mask rule to which the any group of edges belongs; Wherein, the same plane and any set of edges are parallel to each other.

2. The violation elimination method based on cost function according to claim 1, characterized in that: Before determining a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges, the method further includes: Based on a preset search distance and the current edge traversed, determine a target search range in the current chip design graph, and determine a plurality of candidate edges in the opposite direction of the current edge from the target search range; Wherein, the direction of each edge in the current chip design graph is determined based on a preset clockwise rotation direction.

3. The violation elimination method based on cost function according to claim 1, characterized in that: The determining of the mask rule to which any group of edges belongs based on whether projections of any group of edges among the plurality of groups of edges on the same plane overlap and whether any group of edges are located in the same figure in the current chip design figure includes: If the any group of edges are located in the same graph in the current chip design graph, determining that the mask rule to which the any group of edges belongs is a first mask rule; If the projections of any group of edges on the same plane overlap, and the any group of edges are not located in the same figure in the current chip design figure, determining that the mask rule to which the any group of edges belongs is the second mask rule; If the projections of any group of edges on the same plane do not overlap, and the any group of edges are not located in the same figure in the current chip design figure, it is determined that the mask rule to which the any group of edges belongs is the third mask rule.

4. The violation elimination method based on cost function according to claim 3, characterized in that: The calculating the cost value of a corresponding set of edges according to the cost function comprises: When the cost function is a first cost function corresponding to the first mask rule to which the arbitrary group of edges belongs, substituting a target weight corresponding to the arbitrary group of edges, a first preset distance threshold, and a target distance between two edges included in the arbitrary group of edges into the first cost function to calculate a cost value of the arbitrary group of edges; When the cost function is a second cost function corresponding to the second mask rule to which the arbitrary group of edges belongs, substituting the target weight, the second preset distance threshold, and the target distance into the second cost function to calculate the cost value of the arbitrary group of edges; When the cost function is a third cost function corresponding to the third mask rule to which the arbitrary group of edges belongs, the target weight, the third preset distance threshold, and the point spacing are substituted into the third cost function to calculate the cost value of the arbitrary group of edges; the point spacing is the minimum value of the distances between two points on different edges included in the arbitrary group of edges; Among them, the target weight is a weight determined based on the weights corresponding to the two edges included in any group of edges; the first preset distance threshold, the second preset distance threshold and the third preset distance threshold are thresholds corresponding to the first mask rule, the second mask rule and the third mask rule respectively.

5. The violation elimination method based on cost function according to claim 1, characterized in that: The preset violation condition includes that the cost value is not zero.

6. The violation elimination method based on cost function according to any one of claims 1 to 5, characterized in that: The moving the position of the target group edge includes: Based on the sum of the cost values ​​of the target group edges, the moving direction and moving amount of each edge in the target group edges are determined to move the position of each edge in the target group edges.

7. A violation elimination device based on cost function, characterized in that: include: A graphics acquisition module, used to acquire a chip design graphic after optical proximity correction to obtain a current chip design graphic; A traversal module, used to traverse each edge in the current chip design graph, and determine a plurality of groups of edges based on the traversed current edge and a plurality of surrounding candidate edges; each group of edges includes the current edge and one of the candidate edges; A cost value calculation module, used for determining cost functions corresponding to the plurality of groups of edges respectively based on the mask rules to which the plurality of groups of edges respectively belong, so as to calculate the cost value of a corresponding group of edges according to the cost function; A violation determination module, configured to determine a target group of edges from the plurality of groups of edges based on the cost value; the target group of edges being the violations in the plurality of groups of edges that meet a preset violation condition; A violation elimination module, used for moving the position of the target group of edges to update the current chip design graph, and re-jumping to the step of traversing each edge in the current chip design graph until the plurality of groups of edges do not satisfy the preset violation condition, so as to eliminate all violations in the current chip design graph; Among them, the cost value calculation module is specifically used to: determine the mask rule to which any group of edges among the several groups of edges belongs based on whether the projections of the any group of edges on the same plane overlap, and whether the any group of edges is located in the same figure in the current chip design figure, and determine the cost function corresponding to the any group of edges based on the mask rule to which the any group of edges belongs; wherein the same plane and the any group of edges are parallel to each other.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the violation elimination method based on the cost function as claimed in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the violation elimination method based on a cost function as described in any one of claims 1 to 6.

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