A chip verification system and method

Abstract

This application provides a chip verification system and method. The chip verification system includes a switching chip, multiple device connectors, and multiple PCIe devices. The multiple device connectors are all connected to the switching chip, and the multiple PCIe devices are respectively connected to the switching chip through corresponding device connectors. The PCIe devices are also used to connect to an external control terminal, and serve as both an incentive initiator and an incentive receiver. This application uses PCIe devices to send and receive incentive data to verify the rationality of the incentive data, thereby quickly obtaining the chip verification results. The hardware architecture for chip verification mainly uses PCIe devices, a switching chip, and device connectors, effectively saving the hardware resources required for verification. The relevant parameters of the device connectors and PCIe devices can be flexibly set to match the needs of different verification scenarios, effectively improving the verification efficiency of different scenarios.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a chip verification system and method. Background Technology

[0002] Prototyping and system testing are crucial in chip design, ensuring the production of high-quality and reliable chip products. Prototyping involves simulating the chip's real-world operating environment before tape-out to verify chip functionality and reduce tape-out risks. A common method is to burn the chip's netlist (logic design) into an FPGA, using the FPGA as the object to be verified. System testing involves performing functional tests on the chip in a real-world operating environment after tape-out, analyzing and resolving any problems encountered during testing, and improving chip yield.

[0003] PCIe switching chips are high-speed mixed-signal chips with large gate scale and complex functions, thus placing extremely high demands on prototype verification and system testing. The high R&D cost of switching chips is largely concentrated on prototype verification and system testing. This is because chip verification presents challenges such as numerous prototype verification and system testing points, long testing times, and substantial hardware and software resources required for these processes. Summary of the Invention

[0004] The main purpose of this application is to provide a chip verification system and method that can at least solve the problems of low efficiency and large amount of testing resources required for chip verification in related technologies.

[0005] To achieve the above objectives, a first aspect of this application provides a chip verification system, comprising: a switching chip, multiple device connectors, and multiple PCIe devices. The multiple device connectors are all connected to the switching chip, and the multiple PCIe devices are respectively connected to the switching chip through corresponding device connectors. Each PCIe device serves as both an incentive initiator and an incentive receiver. A first PCIe device serving as the incentive initiator is configured to: generate incentive data and transmit it to a corresponding first device connector. The first device connector is configured to: transmit the incentive data to the switching chip. The switching chip is configured to: transmit the incentive data to a second PCIe device through a corresponding second device connector. The second PCIe device serves as the incentive receiver. The second PCIe device is configured to: perform a validity verification on the incentive data. When the validity verification is successful, the switching chip verification is successful.

[0006] A second aspect of this application provides a chip verification method, comprising: a first PCIe device, acting as an incentive initiator, generating incentive data and transmitting it to a corresponding first device connector; the first device connector transmitting the incentive data to a switching chip; the switching chip transmitting the incentive data to a second PCIe device via a corresponding second device connector; wherein the second PCIe device acts as an incentive receiver; the second PCIe device performs a validity verification on the incentive data, and when the validity verification is passed, the switching chip is successfully verified.

[0007] As can be seen from the above, in the chip verification system provided by this application, the hardware architecture for chip verification mainly uses PCIe devices, switching chips, and device connectors, which can effectively save the resources required for verification. The PCIe devices can be selected according to the verification needs, and the types of PCIe devices connected to the device connectors can also be set according to the verification needs, thereby flexibly matching the needs of different verification scenarios and improving verification efficiency. The first PCIe device, as the incentive initiator, sends incentive data, which is transmitted to the switching chip through the device connector corresponding to the first PCIe device. Then, the switching chip transmits the data to the second PCIe device, as the incentive receiver, through the corresponding device connector. The second PCIe device parses the received incentive data to determine its rationality, thereby determining whether the chip has been successfully verified. There can be multiple verification links, and the PCIe devices at the incentive initiator and incentive receiver can be selected according to the verification needs, thereby obtaining the verification results of different verification links and improving the accuracy of verification. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of the first chip verification system provided in the embodiments of this application;

[0010] Figure 2 This is a schematic diagram of the structure of the second chip verification system provided in the embodiments of this application;

[0011] Figure 3 This is a schematic diagram of the structure of the third chip verification system provided in the embodiments of this application;

[0012] Figure 4 A schematic diagram of the first PCIe link topology provided in the embodiments of this application;

[0013] Figure 5 This is a schematic diagram of a second PCIe link topology provided in an embodiment of this application;

[0014] Figure 6 This is a schematic diagram of a third PCIe link topology provided in an embodiment of this application;

[0015] Figure 7 A schematic diagram of the structure of a PCIe device simulator provided in an embodiment of this application;

[0016] Figure 8 A schematic diagram of a simulator parameter configuration instruction provided in an embodiment of this application;

[0017] Figure 9 A schematic diagram of a test sequence configuration instruction provided in an embodiment of this application;

[0018] Figure 10 A schematic diagram of the test pattern transmission path provided in the embodiments of this application;

[0019] Figure 11 A schematic diagram of a test pattern configuration instruction provided in an embodiment of this application;

[0020] Figure 12 This is a basic flowchart illustrating a chip verification method provided in an embodiment of this application. Detailed Implementation

[0021] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0023] To address the issues of low efficiency and high resource requirements in chip verification in related technologies, one embodiment of this application provides a chip verification system, such as... Figure 1 The diagram shown is a structural schematic of the first type of chip verification system provided in this embodiment. Please refer to [link / reference]. Figure 1The chip verification system includes: a switching chip, multiple device connectors and multiple PCIe devices. The multiple device connectors are all connected to the switching chip, and the multiple PCIe devices are connected to the switching chip through their respective device connectors. The PCIe devices are used as stimulus initiators and stimulus receivers.

[0024] The first PCIe device, acting as the incentive initiator, is used to: generate incentive data and transmit it to the corresponding first device connector; the first device connector is used to: transmit the incentive data to the switching chip; the switching chip is used to: transmit the incentive data to the second PCIe device through the corresponding second device connector; the second PCIe device acts as the incentive receiver; the second PCIe device is used to: verify the rationality of the incentive data, and when the rationality verification is passed, the switching chip verifies successfully.

[0025] Specifically, in this embodiment, the hardware architecture for chip verification mainly uses PCIe devices, a switching chip, and device connectors. The switching chip can connect to multiple device connectors simultaneously. Each device connector can choose to connect to or not connect to a PCIe device. The PCIe device can be selected according to the verification requirements, and the type of PCIe device connected to the device connector can also be set according to the verification needs, thereby flexibly matching the requirements of different verification scenarios and improving verification efficiency. The first PCIe device, acting as the incentive initiator, sends incentive data, which is transmitted to the switching chip through its corresponding device connector. The switching chip then transmits the data to the second PCIe device through its corresponding device connector, acting as the incentive receiver. The second PCIe device parses the received incentive data to determine its rationality based on incentive configuration instructions, thereby determining whether the chip verification is successful. Multiple verification links can be established, improving verification efficiency. The PCIe devices at the incentive initiator and incentive receiver ends can be selected according to verification needs, thereby obtaining verification results from different verification links and improving verification accuracy.

[0026] Furthermore, such as Figure 2 , Figure 3 The figures shown are schematic diagrams of the second and third chip verification systems provided in this embodiment. Please refer to [link / reference]. Figure 2 , 3PCIe devices include any of the following device types: RC device, EP device, NT device, and Fabric device. These device types can be simulated by the PCIe device simulator in the PCIe device. The device connector can be connected to any type of PCIe device among RC, EP, NT, and Fabric devices, or the device connector can be connected to any type of PCIe device among RC, EP, and NT devices, or the device connector can be connected to any type of PCIe device among RC, EP, and Fabric devices, or the device connector can be connected to any type of PCIe device among RC and EP devices.

[0027] Specifically, taking a common PCIe link topology as an example, such as Figure 4 As shown, PCIe links use an end-to-end data transmission method, meaning there is only one link between two devices. Data flows between upstream and downstream devices through this link, serving RC (Root Complex) and EP (End Point) devices, i.e., serving the master and slave devices. A switch, or SW for short, is a switching chip. The SW expands the link topology and completes data exchange. The port of the switching chip connecting upstream is called the USP (Upstream Port), and the port connecting downstream is called the DSP (Downstream Port).

[0028] In this embodiment, the number of connected PCIe devices, the data transmission link width of the PCIe devices, and the location of the PCIe devices can be configured. It is also possible to configure whether the device connector is an NT port or a Fabric port to quickly configure a hardware architecture that meets the requirements of the verification scenario. Specifically, the number of connected PCIe devices should be less than or equal to the total number of device connectors in the system (i.e., the total number of external interfaces of the switching chip), and the total link width of the connected PCIe devices should be less than or equal to the total number of path resources of the switching chip. The locations of the n device connectors are numbered from 1 to n, so the location of a connected PCIe device L∈{1, n}, meaning the PCIe device can access any existing physical interface resource. NT ports and Fabric ports need to be configured based on whether the device connector has NT and Fabric support capabilities. Depending on the device capabilities, the link width of the PCIe link, i.e., the negotiated number of paths, can be X1, X2, X4, X8, X16, X32, etc. NT ports refer to non-transparent ports. These ports belong to a different system domain and can only transmit partial data with switches in the local domain. They cannot freely transmit data like devices in the local domain. The corresponding transmission links are as follows: Figure 5As shown; Fabric ports are generally used for interconnecting switching chips in the same or different system domains in a network topology, which can break through the traditional tree topology, and the corresponding transmission links are, for example Figure 6 As shown. In this embodiment, each device connector can be optionally connected to EP devices or RC devices, and can be optionally configured as an NT port or Fabric port. This allows for the selection of whether to connect to NT devices or Fabric devices, enabling the connection of PCIe devices of different widths based on the switching chip's path resources. This facilitates the rapid and convenient construction of different switching chip application scenarios, serving as a prototype verification and system testing environment. For example... Figure 2 As shown, the first device connector is connected to the EP1 device, with a link width of X1; the second device connector is connected to the NT device, with a link width of X2; the fourth device connector is connected to the Fabric device, with a link width of X8; the (n-1)th device connector is connected to the RC device, with a link width of X16; the nth device connector is connected to the EP2 device, with a link width of X4; other device connectors are not connected to any devices. Figure 3 In the chip verification system shown, the first device connector is connected to the RC device with a link width of X32; the fourth device connector is connected to the EP1 device with a link width of X16; the (n-1)th device connector is connected to the NT device with a link width of X2; no fabric device is connected to the system; and no devices are connected to other ports. Therefore, the device connectors in this embodiment can be freely configured with the type of connected device. The number of devices connected to the system, the data transmission link width of the devices, and the device connection location can all be freely configured, meaning that the relevant variables of the device connectors in this embodiment are reconfigurable. Furthermore, Figure 2 The DUT (Design Under Test) in this example refers to the exchange chip (for prototype verification, it is an FPGA with a chip netlist programmed; for system testing, it is the chip after actual fabrication and return). In other words, the chip verification system in this embodiment can be applied to prototype verification scenarios and system testing scenarios.

[0029] Furthermore, the PCIe device includes a PCIe device simulator and a conventional PCIe device. The PCIe device simulator is also connected to an external control terminal. The stimulus data includes first sub-stimulus data and second sub-stimulus data. The PCIe device simulator in the first PCIe device is used to: generate corresponding first sub-stimulus data according to the stimulus configuration instructions sent by the control terminal, and transmit it to the corresponding first device connector. The conventional PCIe device in the first PCIe device is used to: generate corresponding second sub-stimulus data according to a preset PCIe protocol, and transmit it to the corresponding first device connector.

[0030] Furthermore, conventional PCIe devices are specifically used to: generate corresponding transaction messages according to the PCIe protocol, and generate second sub-stimulus data based on the transaction messages.

[0031] Specifically, in this embodiment, the stimulus data generated by the PCIe device is mainly generated by the PCIe device simulator and the conventional PCIe device. The PCIe device simulator generates the first sub-stimulus data based on the stimulus configuration instructions transmitted by the control terminal, while the conventional PCIe device generates the second sub-stimulus data according to a preset PCIe protocol. That is, the stimulus data sent by the PCIe device includes both the first and second sub-stimulus data. The second sub-stimulus data mainly consists of a conventional transaction message generated by the conventional PCIe device. This transaction message is generated through the internal logic circuits and controller of the PCIe device. These internal logic circuits and controller can process the protocol stack of the PCIe bus to generate and / or parse PCIe transaction messages. Transaction messages in the PCIe protocol can be categorized by function into read transactions, write transactions, configuration transactions, etc. The format of a transaction message includes fields such as a start marker, address, data, and checksum information, used to determine the transaction type, target address, and carried data.

[0032] Furthermore, such as Figure 7 The diagram shown is a structural schematic of a PCIe device simulator provided in this embodiment. Please refer to [link / reference]. Figure 7 The PCIe device simulator includes a debug interface, an instruction parser, and a device behavior simulator. The debug interface is used to receive stimulus configuration instructions and transmit them to the instruction parser. The instruction parser is used to parse the stimulus configuration instructions and transmit the parsed configuration information to the device behavior simulator. The device behavior simulator is used to generate corresponding first sub-stimulus data based on the configuration information and transmit it to the first device connector.

[0033] Specifically, in this embodiment, the PCIe device simulator mainly consists of a debug interface, an instruction parser, and a device behavior simulator. The debug interface is used to receive stimulus configuration instructions sent by the control terminal and transmit them to the instruction parser. The debug interface can be a serial port or JTAG interface. The instruction parser is used to parse the stimulus configuration instructions and transmit the parsed stimulus configuration information to the device behavior simulator. The device behavior simulator is used to generate the first sub-stimulus data and transmit it to the corresponding first device connector.

[0034] Furthermore, the configuration information includes test sequence configuration information, test pattern configuration information, and simulator parameter configuration information; the device behavior simulator is specifically used to: set the corresponding parameters of the PCIe device simulator according to the simulator parameter configuration information, then generate test sequences and test patterns according to the test sequence configuration information and test pattern configuration information, generate the first sub-excitation data according to the test sequence and test pattern, and transmit it to the first device connector.

[0035] Further, in one embodiment, generating a test sequence and a test pattern according to the test sequence configuration information and the test pattern configuration information includes: generating a test sequence according to the test sequence configuration information; wherein the test sequence includes multiple transactions whose transaction headers are arranged in a preset order, and the transactions include standard transactions and / or abnormal transactions; generating a test pattern according to the test pattern configuration information; wherein the test pattern includes target transactions of multiple target transaction types, pattern initiation information, pattern destination information, algorithm type, and number of target transactions, the algorithm is used to control the multiple target transactions to make corresponding changes, and the algorithm is pre-programmed in the device behavior simulator.

[0036] Specifically, in this embodiment, the stimulus configuration instructions sent by the control terminal include test sequence configuration instructions, test pattern configuration instructions, and simulator parameter configuration information. After receiving the stimulus configuration information transmitted by the instruction parser, the device behavior simulator first configures the PCIe device simulator according to the simulator parameter configuration information. The simulator parameter configuration instructions contain the parameters to be configured and their values. The parameters are represented by a preset number of bits, and the desired setting value for the parameter is input in the instruction. For example, 5 bits are used. The form of the simulator parameter configuration instructions is as follows: Figure 8 As shown. In this embodiment, the simulator's parameters can include the simulator's data transmission link width, electrical parameters, link behavior to be negotiated (such as rate, whether it is balanced, etc.), and the type of the simulated device (RC / EP), so that the PCIe device simulator can function as a PCIe device access device connector. Parameter values ​​can be set according to the needs of prototype verification and system testing to perform prototype verification and system testing under extreme and non-extreme, abnormal and non-abnormal scenarios. After configuring the relevant parameters, the PCIe device simulator generates corresponding test sequences and test patterns based on the test sequence configuration information and test pattern configuration information. The test sequence includes multiple transactions, with the packet headers of the multiple transactions arranged in a preset order. The transaction type in the test sequence can be a single type or a combination of types, such as all standard transactions or abnormal transactions, or a combination of standard and abnormal transactions. Standard transactions refer to transactions that conform to the protocol specifications, while abnormal transactions are transactions that do not conform to the protocol standards. The PCIe protocol specifies header and payload requirements for standard transactions. Standard transactions include memory transactions, configuration transactions, I / O transactions, message transactions, and completion transactions, as shown in Table 1 below. These transactions are distinguished by the `fmt` and `type` fields in the header. Furthermore, other fields in the header must also comply with the protocol requirements.

[0037] Table 1

[0038]

[0039] Transactions that do not conform to the protocol are considered exceptions. By constructing exception stimuli, the functional robustness of the switching chip can be confirmed during prototype verification and system testing. Exceptions are further subdivided into exceptions in the fmt / type field and exceptions in other packet header fields. For example, exceptions include transactions where the type field is 0b11111, and exceptions where the data payload length field does not match the actual payload length. When multiple transactions form a sequence, the corresponding transaction sequence can be in the form T = {T1, T2, T3, ..., Ti, ..., Tn}, where Ti can be a standard transaction or an exception transaction. The number and order of transactions can be arbitrary. For example, sequence 1: {MRd32, IORd, Msg1, Msg2, CAS64, T_abn}, consists of six transactions: 32-bit memory read request, IO read request, message transaction 1, message transaction 2, 64-bit CAS atomic operation, and exception transaction T_abn; sequence 2: {CfgRd0_1, CfgRd0_2, CfgRd0_3, CfgRd0_4, CfgRd0_5, T_abn_1, T_abn_2}, consists of seven transactions: Type 0 configuration read requests 1 to 5, and exception transactions T_abn_1 to 2. The form of the test sequence configuration instruction is as follows: Figure 9 As shown, the test sequence configuration instruction includes the transaction type, quantity, and transaction header (128 bits) arrangement order of the constituent transactions in the sequence, instructing the device behavior simulator to generate the corresponding test sequence. That is, the test sequence in this embodiment can be flexibly reconstructed and defined to define the transaction type and transaction sequence of the stimulus to be generated.

[0040] In this embodiment, the test pattern consists of a set of special transactions with agreed-upon initiating and destination points. This set is characterized by a large number of transactions, a single transaction type, minimal changes in transaction content, and a consistent algorithmic pattern. This facilitates rapid generation of initiating points and rapid parsing of destinations, enabling fast and comprehensive prototype verification and system testing. Figure 3Taking the chip verification system architecture shown as an example, the test pattern is transmitted from the initiating location (e.g., the device corresponding to the first device connector) to the destination (e.g., the device corresponding to the fourth device connector) via the DUT. The test pattern can be a large number (e.g., more than 10,000) of single CfgRd0 transactions. The target register address field (or other fields required for verification) of these transactions changes according to a certain algorithm (e.g., increasing or decreasing by 4 steps, or other functional changes). Before verification begins, this algorithm is communicated to the sending and destination locations, allowing the sending location to quickly generate the pattern according to the algorithm, and the destination to quickly parse the pattern according to the algorithm. The speed here is mainly reflected in the fact that only the changes in the transaction need to be checked to see if they follow the pre-agreed algorithm, without needing to check whether the transaction is standard or abnormal. The transmission paths of these test patterns are reconfigurable; that is, the transaction initiating location and destination can be arbitrarily combined to maximize the completeness of verification and testing.

[0041] In this embodiment, the transmission path types of the test pattern mainly include: DSP→DSP, USP→DSP, and DSP→USP, for example... Figure 10 As shown, each type of transmission path is illustrated with three paths. Since the number of DSPs in a switching chip is often greater than one, the DSP→DSP type includes unidirectional transmission (e.g., DSP4→DSPn) and bidirectional transmission between two DSPs (e.g., the transmission path corresponding to DSP2 and DSP3). That is, the origin and destination of different transmission paths in the DSP→DSP transmission path type can be different, and the same origin can correspond to multiple destinations; USP→DSP and DSP→USP include transmission between USP and different DSPs.

[0042] The test pattern configuration instructions in this embodiment include the transaction type encoding, origin encoding, destination encoding, algorithm type encoding, and transaction quantity encoding of the test pattern. These encodings can be several bits, such as... Figure 11 In the test pattern configuration instructions shown, the bit lengths of each code are 8 bits, 16 bits, 16 bits, 8 bits, and 32 bits, respectively. The algorithm type is pre-programmed in the device behavior simulator of the PCIe device simulator, and different types can be selected according to the configuration commands. For example... Figure 11The test pattern configuration command shown indicates that a test pattern is sent from the device corresponding to 0x0100, and the test pattern arrives at the device corresponding to 0x0502. The transaction type used in the test pattern is 0x04 (assuming it is a CfgRd0 transaction), the algorithm used in the test pattern is 0x05 (assuming the address increments by 4), and the number of transactions in the test pattern is 0x2710, i.e., 10,000. After this command is input to the originating location, the originating location begins to generate and send out the pattern; at the same time, the command is also input to the destination, and the destination checks the addresses in the received test pattern according to the command to determine whether they conform to the expected algorithm pattern.

[0043] Furthermore, the conventional PCIe device in the second PCIe device, which serves as the stimulus receiver, is used to: parse the second sub-stimulus data and detect whether the parsed transaction message meets the preset protocol requirements; the PCIe device simulator in the second PCIe device is used to: parse the first sub-stimulus data and the test pattern configuration instructions sent by the control terminal, and detect the parsed test pattern according to the algorithm type in the parsed test pattern configuration information to determine whether the test pattern changes according to the algorithm type; the PCIe device simulator in the second PCIe device is also used to: parse the first sub-stimulus data and detect whether the parsed test sequence meets the protocol requirements. When the transaction message, test pattern, and test sequence all meet the corresponding requirements, the switching chip verification is successful.

[0044] Specifically, the test sequence obtained from the parsing is checked to see if it meets the protocol requirements. This includes checking whether the feature fields of each transaction in the test sequence meet the protocol requirements, and determining whether the abnormal transactions have completed the preset processing when the test sequence contains abnormal transactions.

[0045] In this embodiment, when the second PCIe device, acting as the stimulus receiver, receives stimulus data, the conventional PCIe device within the second PCIe device parses the transaction message and determines whether the transaction message meets preset protocol requirements to determine whether the switching chip can normally send and receive transaction messages. The PCIe device simulator within the second PCIe device parses the stimulus configuration instructions sent by the control terminal, as well as the test patterns and test sequences, to determine whether the received test patterns meet preset algorithm rules based on the test pattern configuration instructions in the stimulus configuration instructions. For test sequences, the characteristic fields of their transactions need to be checked to determine whether the transactions and transaction sequences are complete and correct. For test sequences containing abnormal transactions, it is also necessary to determine whether the abnormal transactions have been pre-processed (e.g., marked or discarded). By verifying the reasonableness of the received transaction messages, test sequences, test patterns, and abnormal transactions, the correctness of the switching chip's performance can be determined when all verifications pass.

[0046] This application also provides a chip verification method, such as... Figure 12 The diagram shown is a basic flowchart of a chip verification method provided in an embodiment. Please refer to [link / reference]. Figure 12 The chip verification method includes:

[0047] Step 1201: The first PCIe device, acting as the incentive initiator, generates incentive data and transmits it to the corresponding first device connector;

[0048] Step 1202: The first device connector transmits the excitation data to the switching chip;

[0049] Step 1203: The switching chip transmits the excitation data to the second PCIe device, which serves as the excitation receiver, through the corresponding second device connector;

[0050] Step 1204: The second PCIe device verifies the rationality of the stimulus data. When the rationality verification is successful, the switching chip verification is successful.

[0051] Specifically, in this embodiment, the chip verification method can be used for chip prototype verification and chip system testing. Chip verification is based on the hardware platform resources of the aforementioned chip verification system and is completed through stimulus data generated by a reconfigurable PCIe device. The reconfigurable PCIe device includes a conventional PCIe device and a PCIe device simulator. The stimulus data includes transaction messages, test sequences, and test patterns. The conventional PCIe device is used to send and receive transaction messages, while the PCIe device simulator is used to send and receive test sequences and test patterns. By parsing the stimulus data transmitted by the stimulus sender, it is determined whether the transaction messages in the stimulus data meet the preset protocol, whether the test sequences meet the preset protocol, and whether the test patterns are transformed according to the preset algorithm. This verifies whether the chip can normally send, receive, and process stimulus data, thereby verifying the correctness and stability of its performance.

[0052] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0053] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0054] The above is a description of the chip verification system and method provided in this application. For those skilled in the art, based on the ideas of the embodiments of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip verification system, characterized in that, include: The device includes a switching chip, multiple device connectors, and multiple PCIe devices. The multiple device connectors are all connected to the switching chip, and the multiple PCIe devices are respectively connected to the switching chip through their respective device connectors. The PCIe devices are used as incentive initiators and incentive receivers. The first PCIe device, serving as the incentive initiator, is used to: generate incentive data and transmit it to the corresponding first device connector; the first PCIe device can be any of the PCIe devices mentioned above. The first device connector is used to: transmit the excitation data to the switching chip; The switching chip is used to: transmit the excitation data to a second PCIe device through a corresponding second device connector; wherein the second PCIe device serves as the excitation receiving end, the second PCIe device is any of the PCIe devices, and the first PCIe device is different from the second PCIe device; The second PCIe device is used to: perform a validity verification on the stimulus data; when the validity verification is passed, the switching chip verification is successful. The PCIe device includes a PCIe device simulator and a conventional PCIe device. The PCIe device simulator is also connected to an external control terminal. The stimulus data includes first sub-stimulus data and second sub-stimulus data. The PCIe device simulator in the first PCIe device is used to: generate corresponding first sub-stimulus data according to the stimulus configuration instruction sent by the control terminal, and transmit it to the corresponding first device connector; The conventional PCIe device in the first PCIe device is used to: generate corresponding second sub-excitation data according to a preset PCIe protocol and transmit it to the corresponding first device connector; The conventional PCIe device in the second PCIe device is used to: parse the second sub-stimulus data and detect whether the parsed transaction message meets the preset protocol requirements; The PCIe device simulator in the second PCIe device is used to: parse the first sub-excitation data and the test pattern configuration instruction sent by the control terminal, and detect the parsed test pattern according to the algorithm type in the parsed test pattern configuration information to determine whether the test pattern changes according to the algorithm type; The PCIe device simulator in the second PCIe device is further used to: parse the first sub-stimulus data and detect whether the parsed test sequence meets the protocol requirements. When the transaction message, the test pattern and the test sequence all meet the corresponding requirements, the switching chip is successfully verified.

2. The chip verification system according to claim 1, characterized in that, The PCIe device simulator includes a debug interface, an instruction parser, and a device behavior simulator. The debugging interface is used to: receive the stimulus configuration instruction and transmit it to the instruction parser; The instruction parser is used to: parse the stimulus configuration instruction and transmit the parsed configuration information to the device behavior simulator; The device behavior simulator is used to: generate corresponding first sub-excitation data according to the configuration information and transmit it to the first device connector.

3. The chip verification system according to claim 2, characterized in that, The configuration information includes test sequence configuration information, test pattern configuration information, and simulator parameter configuration information; The device behavior simulator is specifically used to: set the corresponding parameters of the PCIe device simulator according to the simulator parameter configuration information, then generate a test sequence and a test pattern according to the test sequence configuration information and the test pattern configuration information, generate the first sub-excitation data according to the test sequence and the test pattern, and transmit it to the first device connector.

4. The chip verification system according to claim 3, characterized in that, The step of generating test sequences and test patterns according to the test sequence configuration information and test pattern configuration information includes: A test sequence is generated based on the test sequence configuration information; wherein, the test sequence includes multiple transactions whose transaction headers are arranged in a preset order, and the transactions include standard transactions and / or abnormal transactions; A test pattern is generated based on the test pattern configuration information; wherein, the test pattern includes target transactions of multiple target transaction types, pattern origin information, pattern destination information, algorithm type, and number of target transactions, the algorithm is used to control the multiple target transactions to make corresponding changes, and the algorithm is pre-programmed in the device behavior simulator.

5. The chip verification system according to claim 1, characterized in that, The conventional PCIe device is specifically used to: generate corresponding transaction messages according to the PCIe protocol, and generate second sub-stimulus data according to the transaction messages.

6. The chip verification system according to claim 1, characterized in that, Whether the test sequence obtained from the detection and parsing meets the protocol requirements includes: The system detects whether the feature fields of each transaction in the test sequence meet the protocol requirements, and when the test sequence contains abnormal transactions, it determines whether the abnormal transactions have completed the preset processing.

7. The chip verification system according to claim 1, characterized in that, The PCIe device type includes any of the following: RC device, EP device, NT device, and Fabric device.

8. A chip verification method, characterized in that, The chip verification method, applied to the chip verification system as described in any one of claims 1 to 7, comprises: The first PCIe device, acting as the incentive initiator, generates incentive data and transmits it to the corresponding first device connector. The first device connector transmits the excitation data to the switching chip; The switching chip transmits the excitation data to the second PCIe device through a corresponding second device connector; wherein the second PCIe device serves as the excitation receiving end. The second PCIe device performs a validity verification on the stimulus data. When the validity verification is successful, the switching chip is successfully verified. The PCIe device includes a PCIe device simulator and a conventional PCIe device, and the stimulus data includes a first sub-stimulus data and a second sub-stimulus data. In the first PCIe device, the PCIe device simulator generates corresponding first sub-stimulus data according to the stimulus configuration instruction sent by the control terminal, and transmits it to the corresponding first device connector; The conventional PCIe device in the first PCIe device generates corresponding second sub-excitation data according to a preset PCIe protocol and transmits it to the corresponding first device connector; The conventional PCIe device in the second PCIe device parses the second sub-stimulus data and detects whether the parsed transaction message meets the preset protocol requirements; In the second PCIe device, the PCIe device simulator parses the first sub-excitation data and the test pattern configuration command sent by the control terminal, and detects the parsed test pattern according to the algorithm type in the parsed test pattern configuration information to determine whether the test pattern changes according to the algorithm type; In the second PCIe device, the PCIe device simulator parses the first sub-stimulus data and detects whether the parsed test sequence meets the protocol requirements. When the transaction message, the test pattern, and the test sequence all meet the corresponding requirements, the switching chip is successfully verified.

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