Heterogeneous multi-core distributed brain-like bionic architecture based on neural mimicry and working method thereof

Abstract

The invention relates to a heterogeneous multi-core distributed brain-like bionic architecture based on neural mimicry and a working method thereof. The heterogeneous multi-core distributed brain-like bionic architecture comprises a neural mimicry processor, a multi-node matrix processor, a memristive neural mimicry unit, a neural plastic unit, a neural mimicry routing system, a pulsation coupling unit and a whole-brain space simulation processing unit. The method is inspired by a working mechanism of each brain component and a neuron plasticity mechanism in a brain thinking process, and knowledge such as functional analysis and a graph group theory in mathematics are combined with related theories such as graph reinforcement learning and group decision in artificial intelligence; a bionic chip is constructed by using a hardware technology, and biological components such as thalamus and basal nerve knots are comprehensively simulated; the problems that an artificial intelligence algorithm in the market is low in speed, complex and low in efficiency; the architecture and the method are mainly applied to multi-AI scenes such as image scene analysis, voice recognition, sentiment analysis, intelligent driving, root analysis, risk prediction, decision analysis and safety confrontation.

Description

Technical Field

[0001] The present invention belongs to the field of brain-like neural networks, computer architecture and artificial intelligence software and hardware collaboration, and specifically relates to a heterogeneous multi-core distributed brain-like bionic architecture based on neuromorphism and its working method; it is mainly used in hardware solutions for multiple AI scenarios such as image scene analysis, speech recognition, emotion analysis, intelligent driving, root cause analysis, risk prediction, decision analysis, and security confrontation. Background Art

[0002] The heterogeneous multi-core distributed brain-like bionic architecture of neuromorphic and its working method are inspired by the working mechanisms of various brain components in the brain's thinking process and the neuronal plasticity mechanism. They use matrix theory, functional analysis, group theory, graph theory, wave function and other techniques in mathematics combined with artificial intelligence related algorithms to fully simulate the human brain's thinking process. The functions of various brain regions in the brain's thinking process are constructed using mathematics, hardware circuits, communication networks, artificial intelligence algorithms and other technologies to create a neuromorphic bionic chip with human-like thinking, allowing the chip to simulate thinking processes similar to those of the human brain.

[0003] This architecture uses hardware programming to simulate a neuromorphic neuron processor, and uses simple microinstructions to simulate the logical control functions of neurons. It combines the principles of vector machines, pulse machines, parallel processors, matrix controllers, and generative programming to simulate a neuroplastic neuron processor, which serves as the core component of this architecture. Other components in the architecture combine with this functional component to construct brain-like functions.

[0004] Mathematics, matrix theory, functional analysis, group theory, graph theory, wave function, etc., combined with artificial intelligence related algorithms such as deep learning, graph learning, reinforcement learning, neural computing, chaotic dynamics, bio-inspired computing, generative function programming, isomorphic emergence, signals and systems, memristors and other related theories, combined with computer architecture, integrated CPU, TPU, GPU, IPU, FPGA, SOC, NOC, C2C, D2D, parallel computing, group core decision-making, storage and computing integration, near storage computing, dynamic reconstruction, multimodality, large models, RAG, and the neural circuits of the human brain nervous system (especially the parietal lobe, temporal lobe, frontal lobe, occipital lobe) and the thalamus, globus pallidus, cingulate gyrus, striatum, basal ganglia, nucleus accumbens, dentate gyrus, hippocampus, amygdala, locus coeruleus, neurons, DNA, microtubules and other biological components related knowledge provide a reference blueprint for solving the above problems. Summary of the invention

[0005] In order to solve brain-like functions such as rapid thinking, reasoning, memory, and decision-making, the present invention proposes to construct neuromorphic heterogeneous processors, multi-node matrix processors, memristor neuromorphic units, neuroplasticity units, neuromorphic routing systems, pulsation coupling units, whole-brain spatial simulation processing units and other mechanisms and components to achieve the above-mentioned brain-like functions.

[0006] In order to achieve the above object, the present invention adopts the following technical scheme:

[0007] A neuromorphic-based brain-like bionic architecture and its working method include a neuromorphic heterogeneous processor, a multi-node matrix processor, a memristor neuromorphic unit, a neuroplasticity unit, a neuromorphic routing system, a pulsation coupling unit, and a whole-brain spatial simulation processing unit.

[0008] The neuromorphic heterogeneous processor includes a central control unit, various registers, various storage areas, ALU, neuroplasticity unit, parallel processing unit, various buses, and SNI instruction set; it uses hardware language to implement the above functional components and simulates a CPU similar to the brain architecture. The neuromorphic heterogeneous processor is not a fixed processor of the same type, but different brain regions have different neuromorphic processors. The neuromorphic heterogeneous processor customizes its components according to the human thinking process to complete the relevant thinking process. Its working steps are as follows:

[0009] Step 1: The central control unit mainly receives neuromorphic microinstructions. After receiving the neuromorphic microinstructions, the central control unit mobilizes relevant registers including time registers, space registers, reasoning registers, value registers, strategy registers, matching registers, perception registers, emotion registers, association registers, abstract registers, synthesis registers, routing registers and ALU (logical processor) to complete corresponding functions through data bus, decision bus, control bus and pulsation bus (synthesis bus);

[0010] Step 2: Various storage areas save data for various registers, such as perception area, time area, space area, reasoning area, value area, strategy area, matching area, emotion area, association area, abstract area, synthesis area, etc., and cooperate with the central control unit to save and extract data from various registers. There is an internal storage unit in each storage area, which includes a logic area, which stores the logic that the central control unit needs to run continuously. The components in the logic area are divided into two major functional components: one is the operation logic area and the other is the simulation logic area. The logic in the operation logic area can be modified at any time-similar to the human consciousness area. The simulation logic area stores the processing data generated by the central processing unit on each register for data processing. It is used by the operation logic area, the central control unit and the logic processor. The simulation logic area is similar to the human subconscious area. When a certain matching mode is reached, it is submitted to the operation logic area (consciousness area), allowing the operation logic area to receive the current logic combination. The central controller receives the current logic combination and then runs it, thereby achieving a dynamic thinking process.

[0011] Step 3: The ALU (logic processor) receives the microinstructions sent by the central controller for processing; the logical processor not only completes the current mathematical logic operations but also includes value operations, timing operations, spatial operations, strategy operations, etc. The central controller is the scheduling center and the ALU is the logic center. It works closely with the central controller, registers, and memory to complete the processing of related tasks.

[0012] Step 4: The integration of neuromorphic heterogeneous processor components communicates with various components through bus controllers, including data bus, decision bus, control bus, and pulsation bus (synthetic bus); the data bus and control bus are in parallel to improve the processing speed; the decision bus uses AXI to input and output the processed execution logic; the pulsation bus is controlled by a pulsation matrix controller and is used to generate a pulsation algorithm, which is an important part of simulating the human thinking process. It logically combines various neurons or various neuromorphic processors.

[0013] Step 5: The SNI neuromorphic instruction set runs through all aspects of the neuromorphic processor. It mainly includes various simple instructions such as conventional microinstructions, decision microinstructions, spatial microinstructions, time microinstructions, and combined microinstructions. Different neuromorphic heterogeneous processors have different microinstructions. The SNI neuromorphic instruction set is the basis of neuromorphic system programming and the logical basis of various neurons. It communicates with engineers through upper-level high-level instructions.

[0014] Step 6: The neuromorphic heterogeneous processor serves as the basis for subsequent regions. The regional groups use feedback technology for two-way communication. At the same time, the neurons generated by it (flat layer, upper layer, and lower layer) also use feedback technology for two-way communication.

[0015] The multi-node matrix processor includes a multi-node matrix processor including a neuromorphic heterogeneous processor, a matrix processor, a matrix external module, a function storage area, a routing information storage, a decision storage area, and an inference synthesis unit; the multi-node matrix processor is implemented in a hardware programming language, and is mainly a management unit for managing the communication and coordination between multiple and various neuromorphic processors. The connection between the neuromorphic processors is mainly realized by the matrix processor to realize the matrix connection module. The matrix external module couples the processing modules through the bus according to the custom protocol. The matrix processor mainly uses the pulsation coupling unit to manage and respond to each neuromorphic processor to work as required. The working steps are as follows:

[0016] The pulse coupling unit in the multi-node matrix processor mobilizes multiple neuromorphic processors and coordinates multiple neurons to deal with specific problems. It is the core of the multi-node matrix processor. The multi-node matrix processor mainly includes neuromorphic heterogeneous processors, matrix processors, matrix external modules, functional storage areas, routing information storage, decision storage areas, and reasoning synthesis units. The main function of the functional storage area is to have a number for each neuromorphic processor that participates in or does not participate in processing, as well as newly generated neuromorphic processors. The functional storage area mainly manages and registers these numbers, and records the functions of the neuromorphic processors for easy mobilization; the reasoning synthesis unit mainly sends and receives information processing requests (information sent and received by the whole brain simulation space processing unit), and mobilizes the neuroplastic algorithm and the reasoning synthesis algorithm to generate various pulse machines according to the request, and coordinates the calculation of various requirements; the main operation of the reasoning synthesis algorithm is similar to generative function programming, which mobilizes relevant resources after receiving information analysis to meet different processing requirements each time, thereby forming a brain-like thinking processing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without creative work.

[0018] Figure 1 The overall block diagram of a neuromorphic heterogeneous multi-core processor based on a neuromorphic heterogeneous multi-core distributed brain-like bionic architecture and its working method provided by the present invention

[0019] Figure 2 External schematic diagram of a neuromorphic heterogeneous multi-core processor based on a neuromorphic heterogeneous multi-core distributed brain-like bionic architecture and its working method in an embodiment of the present invention

[0020] Figure 3 Schematic diagram of the internal structure of a neuromorphic processor based on a heterogeneous multi-core distributed brain-like bionic architecture and its working method in an embodiment of the present invention

[0021] Figure 4 A memristor neuromorphic network diagram of a heterogeneous multi-core distributed brain-like bionic architecture based on neuromorphism and its working method in an embodiment of the present invention

[0022] Figure 5 A neuromorphic routing system diagram of a heterogeneous multi-core distributed brain-like bionic architecture based on neuromorphism and its working method in an embodiment of the present invention

[0023] Figure 6Schematic diagram of a multi-node matrix processor based on a neuromorphic heterogeneous multi-core distributed brain-like bionic architecture and its working method in an embodiment of the present invention

[0024] Figure 7 Schematic diagram of a pulsating coupling unit of a heterogeneous multi-core distributed brain-like bionic architecture based on neuromorphism and its working method in an embodiment of the present invention

[0025] Figure 8 Schematic diagram of a neuroplasticity unit of a heterogeneous multi-core distributed brain-like bionic architecture and its working method based on neuromorphic in an embodiment of the present invention Figure 1 - Reasoning logic is dynamic and malleable

[0026] Fig. 9 Schematic diagram of a neuroplasticity unit of a heterogeneous multi-core distributed brain-like bionic architecture and its working method based on neuromorphic in an embodiment of the present invention Figure 2 —Lenovo Plastic Processor

[0027] Fig.10 A whole-brain spatial simulation processing unit based on a heterogeneous multi-core distributed brain-like bionic architecture and its working method in an embodiment of the present invention - overall block diagram

[0028] Fig.11 Internal structure diagram of a whole-brain spatial simulation processing unit based on a heterogeneous multi-core distributed brain-like bionic architecture and its working method in an embodiment of the present invention In the figure:

[0029] Figure 1 This is the overall block diagram of the present invention, where 02 various neuromorphic processors, 1000 whole brain space simulation processing unit, 800 neuroplasticity processing unit, 700 pulse coupling processing unit, 401 memristor neuromorphic unit, 600 multi-node matrix control unit, 500 neuromorphic routing system

[0030] Figure 2 This is the overall external diagram of the neuromorphic processor of the present invention, wherein 02 various neuromorphic processors, 600 multi-node matrix processors, 1103 various brain area interfaces, 1100 information synthesis generation unit

[0031] Figure 3The overall internal diagram of the neuromorphic processor of the present invention, wherein 300 is the central controller of the neuromorphic processor, 301 is the perception register, 302 is the indication register, 303 is the synthesis register, 304 is the logic processing unit, 305 is the reasoning register, 306 is the buffer register, 307 is the visual register, 308 is the sound register, 309 is the motion register, 310 is the abstract register, 312 is the time register, 313 is the space register, 314 is the association register, 315 is the emotion register, 316 is the strategy register, 317 is the value register; 321 is the perception category storage area, 322 is the synthesis strategy storage area, 323 is the central controller ability storage area, 324 is the five senses storage area, 325 is the high-level thinking storage area, 331 is the association reasoning bus, 332 is the synthesis bus, 333 is the analysis and understanding bus, 360 is the temporal space logic generation storage area

[0032] Figure 4 The memristor neuromorphic network diagram of the present invention includes 401 the internal structure diagram of the memristor neuron, 402 the logic pulse generator, 403 the memristor neuron array, 404 the memristor post-logic analyzer, 405 the logic reasoning area, and 406 the neural protrusion connecting each neuron with the logic reasoning area.

[0033] Figure 5 The neuromorphic routing system diagram of the present invention, wherein 500 is a router core, connected to each functional processor, 501 is a space processor, 502 is a time processor, 503 is a motion processor, 504 is an inference processor, 505 is a synthesis processor, 511 is an information DNA routing processor, 512 is a routing distribution processor, 513 is a routing information storage area, 514 is a routing strategy storage area, 515 is a routing decision processor, and 516 is a routing chain generator.

[0034] Figure 6 It is a multi-node matrix processor diagram of the present invention, wherein 600 is a matrix processor core, 601 is a matrix external module, 606 is a function storage area, 610 is a neuromorphic processor, 612 is a routing information storage, 614 is a decision storage area, 615 is an inference synthesis unit 602 inputs time information, 603 is input space information, 607 is input logic information, 608 is input view information, 609 is input text information, 611 is an input decoding selector, 613 is an output multiplexer,

[0035] Figure 7 Schematic diagram of the pulsation coupling processing unit of the present invention, wherein 700 is a neuromorphic processor pulsator array, 701 various neuromorphic processors, 702 data, logic bus, 703 matrix memory, 704 matrix management unit, 705 reasoning combination generation unit

[0036] Figure 8This is a schematic diagram of the neuroplasticity of the present invention - dynamic plasticity of logical reasoning, wherein 800 is a neuroplasticity unit, 801 is a spatial neuron, 802 is a synthesis analysis neuron, 803 is a time neuron, 804 is a decision neuron, 805 is a logic neuron, 806 is a judgment neuron, 807 is an aggregation neuron, 808 is a causal neuron, 809 is a feedback neuron, 810 is a bus between neurons, 811 is a thought chain generator, 812 is a DNA identifier generator, 813 is an AI information processing unit, and 814 is an association unit

[0037] Fig. 9 This is a schematic diagram of the neuroplasticity of the present invention - associative plasticity, wherein 901 is a neuron synthesizer, 903 is an associative neuron, 904 is a value neuron, 902 is an associative dendrite

[0038] Fig.10 The whole brain space simulation processing unit - overall block diagram, where 1000 is the whole brain space simulation processing unit, 200 is the space processor, 300 is the time controller, 400 is the visual controller, and 500 is the motion controller

[0039] Fig.11 It is the internal structure diagram of the whole brain space simulation processing unit, in which 1100 is the information synthesis generation unit, 1101 is various types of mimicry processor matrices, 1102 is the matrix registration table, 1103 is various types of brain area interfaces, 1104 is heterogeneous many-core storage unit, 1105 is heterogeneous many-core management unit, 1106 is reasoning combination generator, 1107 is multi-node matrix processor, 1108 is various types of mimicry processors DETAILED DESCRIPTION

[0040] The technical scheme and method of use of the present invention are clarified below in conjunction with the accompanying drawings in the implementation of the present invention. Specific implementation process:

[0041] When external information such as video information is processed by the video brain area processor to extract different factors such as motion factors, object factors, space factors, time factors, semantic factors, etc., the thinking chain DNA processor 812 of the neuroplasticity unit 800 is called to mark the DNA tag and send it to the neuromorphic routing system 500. The information DNA routing processor 511 of the routing system calls the routing decision processor 515 to process the thinking chain DNA and then sends it to the relevant brain area for processing. The brain area thinking chain DNA tags and routing strategies mobilized by various factors of this analysis are saved in the routing strategy storage area 514 for subsequent services, and information is sent to the whole brain space simulation processing unit 1000 at the same time; the whole brain space simulation processing unit 1000 receives the relevant information and mobilizes the information synthesis unit 1100 according to the thinking chain DNA to analyze the information and then calls the reasoning combination generator 1106 to generate a mobilization strategy. The multi-node matrix processor 600 generates a pulsation coupling algorithm (pulsation coupling includes various types of heterogeneous neuromorphic processors 02, and various types of heterogeneous processors 02 respectively call their own brain area service microinstructions for related processing); each brain area is a receiver, a sender, and a generator; after analysis, each brain area calls the neuroplasticity unit 800 to generate a logic strategy, which is sent to the memristor neural network 05 and fed back to the whole-brain workspace unit 1000; the whole-brain workspace processing unit 1000 again synthesizes the analysis results according to the strategy (the analysis results have positive and negative rewards, and the reward strategy is fed back to the memristor neural network 401, and the memristor neural network 401 modifies the state of the memristor network according to the feedback strategy) and communicates in multiple directions, repeating the above process many times to form one's own thinking and decision-making, and finally reporting the thinking and decision-making structure to the customer (similar to the reasoning at the subconscious level, reporting to the conscious level), and the relevant request ends.

Claims

1. A heterogeneous multi-core distributed brain-like bionic architecture based on neuromorphism and its working method, including a neuromorphic heterogeneous processor, a multi-node matrix processor, a memristor neuromorphic unit, a neuroplasticity unit, a neuromorphic routing system, a pulsation coupling unit, and a whole-brain spatial simulation processing unit; characterized in that: The neuromorphic heterogeneous processor includes a central control unit, various registers, various storage areas, ALU, a neuroplasticity unit, a parallel processing unit, various buses, and an SNI instruction set; the multi-node matrix processor includes a neuromorphic heterogeneous processor, a matrix processor, and a matrix external module; the neuroplasticity unit includes a neuron DNA identifier generator, a thought chain generator, an AI information processing unit, and a neuron association unit; the pulsation coupling unit mainly includes a pulsation machine array, a matrix memory, a matrix management unit, an inference combination generation unit, and various buses; The whole-brain spatial simulation processing unit is mainly connected to various types including synthesis generation unit, mimetic processor matrix, multi-node matrix processor, heterogeneous many-core memory, heterogeneous many-core management unit, matrix registration table, various brain area interfaces, and various mimetic processors; the memristor neuromorphic unit mainly includes memristor neurons, logic pulse generators, memristor neuron arrays, memristor post-logic analyzers, logic reasoning areas, and neural protrusions; the neuromorphic routing system mainly includes router core, information DNA routing processor, routing distribution processor, routing information storage area, routing strategy storage area, routing decision processor, and routing chain generator.

2. The neuromorphic heterogeneous processor according to claim 1 comprises a central control unit, various registers, various storage areas, ALUs, various buses, neuroplasticity units, parallel processing units, and an SNI instruction set. The central control unit connects various registers, various storage areas, ALUs, neuroplasticity units, and parallel processing units through various buses; each neuromorphic heterogeneous processor realizes the interconnection between the above units through the SNI instruction set; the entire neuromorphic heterogeneous processor gets rid of the bloated instruction set and uses SNI microinstructions to simulate the processing process of neurons; the neuromorphic processor constructs N neurons based on the SNI microinstructions, and each neuron is similar to an independent processing program.

3. According to claim 1, the multi-node matrix processor includes a neuromorphic heterogeneous processor, a matrix processor, a matrix external module, a function storage area, a routing information storage area, a decision storage area, and an inference synthesis unit; the multi-node matrix processor is mainly a management unit for managing multiple and various neuromorphic processors for communication and coordination processing, and the connection between the neuromorphic processors is mainly achieved by coupling various heterogeneous processors through a bus according to a custom protocol using a matrix external module, and the matrix processor mainly uses a pulsation coupling unit to manage and respond to each neuromorphic heterogeneous processor to work as required.

4. The neuroplasticity unit according to claim 1 comprises a neuron DNA identifier generator, a thought chain generator, an AI information processing unit, and a neuron association unit; each neuron DNA identifier adopts a structure similar to biological DNA to make it have a unique identifier, and the information sent by the neuron carries relevant identification information; the AI ​​information processing unit processes the information sent by each neuron; the thought chain generator dynamically generates reasoning logic according to the information sent, and dynamically generates different processing programs for different logic requirements; the neuron association unit performs fuzzy matching according to the reasoning logic generated by the thought chain generator, and associates it with each neuromorphic brain area, so that it can collaboratively complete related tasks, similar to the self-reproduction and self-construction of neurons to generate various types of neurons; neurons are microinstruction programs based on neuromorphic processors, and are processed by the AI ​​information processing unit and then processed by the thought chain generator to generate various types of microinstructions, simulating the self-generation and self-construction of related neurons. The AI ​​information processing unit uses a similar AI intelligent compiler to generate microinstruction programs, and the AI ​​information processing unit customizes a set of intelligent intention images that interpret the neuromorphic instruction set based on microinstructions to serve the subsequent association and thought chain generation; the neuromorphic instruction set includes a microinstruction set and a bionic instruction set.

5. According to claim 1, the pulsation coupling unit mainly includes a pulsation machine array, a matrix memory, a matrix management unit, an inference combination generation unit, and various buses; the pulsation coupling unit is to process various types of data in parallel and provide relevant corresponding processing strategies, so as to combine various neuromorphic processors; the inference combination generation unit provides a relevant pulsation machine array solution to generate a corresponding processing solution, and at the same time matches the relevant matrix memory to form a matrix management unit, provides management and monitoring for subsequent logical reasoning, and coordinates multiple neuromorphic processors to handle specific problems. The main function of the matrix memory is to number each neuromorphic processor that participates in or does not participate in processing, as well as the newly generated one. The matrix memory mainly manages and registers these numbers, and records the functions of the neuromorphic processor for easy mobilization. The matrix memory mainly serves the pulsator, and the multi-core heterogeneous processing pulsator array uses the matrix memory for data interaction; the matrix management mainly manages the neuromorphic processor, and manages and monitors the multi-core heterogeneous pulsator; the reasoning combination generation unit is mainly to generate related heterogeneous multi-core pulsators to complete related business processing, and the neural plasticity mentioned earlier is to generate related instruction sets; the whole-brain simulation space processing unit receives and sends information, and performs AI intelligent matching based on the information to generate related multi-core heterogeneous processor pulsation arrays.

6. According to claim 1, the whole-brain space simulation processing unit mainly includes an information synthesis generation unit, a mimetic processor matrix, an inference combination generator, a multi-node matrix processor, a heterogeneous many-core memory, a heterogeneous many-core management unit, a matrix registration table, various brain area interfaces, and various mimetic processors; Information synthesis generation unit: The whole-brain space simulation processing unit is mainly used to process, receive and send various input and output information. It is the core of the brain-like bionic architecture. It mobilizes the various components of the brain-like bionic architecture to coordinate work and simulate brain-like processing processes; The inference combination generator mainly generates relevant matrix units according to the business logic of the received input and output information; The matrix The registration table mainly completes the registration and management of various mimetic processing generated by the reasoning combination generator, which is similar to the thalamus in the human brain. It summarizes and processes and then distributes it to relevant functional areas. The multi-node matrix processor controls the communication and information processing of the units connected to it according to the relevant information of the reasoning combination generator and the matrix registration table; various brain area interfaces mainly collect and distribute data through the bus; the multi-node matrix processor is a programmable processing program, which can be automatically or manually programmed to continuously upgrade, and then reward the feasible correct results of processing. The feasible processing strategy can be solidified into the processing unit for subsequent use, which is equivalent to generating strategy memory. The information synthesis generation unit is similar to the current artificial intelligence algorithm, but it is based on the microinstruction level, which is equivalent to the chain microinstruction path. Each processing strategy has a corresponding thinking trace, that is, the ins and outs of thinking, which prepares for subsequent thinking reasoning, thinking emergence, and thinking combination.

7. According to claim 1, the memristor neuromorphic unit mainly comprises a memristor neuron, a logic pulse generator, a memristor neuron array, a memristor post-logic analyzer, a logic reasoning area, and a neural protrusion connecting each neuron and the logic reasoning area; the memristor neuron memorizes the pulse information energy sent historically to prepare for subsequent matching of related pulses; The logic pulse transmitter generates relevant pulse signals according to the received information. Pulse signals of different amplitudes represent different thinking logics. The logic analyzer after the memristor performs logical matching on the received information to generate logical inferences, and then triggers the relevant neural protrusions.

8. According to claim 1, the neuromorphic routing system mainly includes a router core, an information DNA routing processor, a routing distribution processor, a routing information storage area, a routing strategy storage area, a routing decision processor, and a routing chain generator; the neuromorphic routing system receives information sent from each brain region, and the information also contains an information DNA identifier. The information DNA routing processor matches the relevant paths in the routing information storage area, and then the routing chain generator generates a routing strategy, which is finally distributed to each interface by the routing distribution processor. After the interface is established, each brain region communicates.

Images