Image data superposition method, system, electronic device and storage medium

Abstract

The present application discloses an image data superposition method, system, electronic device and storage medium, and relates to the field of data processing. The present application provides a system hardware structure for TDI data superposition, which uses the ratio of the pixel row interval to the pixel in the image sensor and the number of light sources to calculate the total number of cache levels; the row pixel data output by the image sensor is superimposed with the data in the final cache or the intermediate cache in the data cache module, and the superimposed data is input into the next data cache module; after each row of pixels is superimposed, the data in the cache flows downward step by step, the data in the final cache is input into the intermediate cache module, and each data cache module corresponds to different pixel rows one by one. In this way, TDI superposition of row pixel data in the image sensor can be achieved without calculating the spatial position corresponding to the cache, thereby improving the efficiency of image data superposition.

Description

Technical Field

[0001] The present invention belongs to the field of data processing, and in particular relates to an image data superposition method, system, electronic equipment and storage medium. Background Art

[0002] In the field of machine vision, as the requirements for detection accuracy and detection efficiency continue to increase, the application of multi-line TDI cameras is becoming more and more widespread. Compared with ordinary line array cameras that generally only have one row of pixels, the typical feature of multi-line TDI cameras is that there are multiple rows of photosensitive pixels inside their image sensors (i.e., TDI sensors). For example, multi-line TDI cameras with 2 or 4 rows of pixels are already relatively common, and there are even more multi-line TDI cameras with 12 or even 16 rows of photosensitive pixels.

[0003] Compared with multi-line TDI cameras with a higher number of rows (for example, 256 rows), multi-line TDI cameras with low-order pixel rows are characterized in that their image sensors themselves usually do not have the TDI overlay function. It is necessary to read the image data corresponding to all rows of pixels from the TDI sensor and then complete the TDI data overlay in the back-end processor, which places high demands on the cache space of the back-end processor.

[0004] In order to reduce the cache space of the back-end processor, the Chinese patent "CN118784994A A TDI data caching method, system, electronic device and storage medium" proposed a solution. During the TDI data overlay process, by reusing the same buffer, the image data to be overlaid is read, overlaid and rewritten at the same time. Compared with the traditional multi-line cache parallel overlay method, the RAM cache resources can be reduced by more than half.

[0005] However, in the above-mentioned TDI data caching scheme, during each overlay process, the cache address of each row of pixel data needs to be calculated based on factors such as the reading cycle, the total number of sensor rows, and the total number of light sources. When the number of TID sensor lines (i.e., the number of pixel rows) and the number of light source partitions increase, the cache address calculation process will become complicated and the consumption of logical resources will also increase greatly. Therefore, on the basis of reducing the TDI cache space, there is still room for improvement in the overlay efficiency of TDI data. Summary of the invention

[0006] The present application proposes an image data superposition method, system, electronic device and storage medium, which are used to further improve the efficiency of TDI data superposition on the basis of reducing TDI cache space.

[0007] To achieve the above objectives, this application proposes the following technical solutions:

[0008] In a first aspect of the present application, an image data overlay system is provided, comprising:

[0009] A data selector, used for inputting a plurality of rows of pixel data output by the image sensor into a corresponding adder and / or a data buffer module;

[0010] N-1 adders, connected to the output end of the data selector, are used to superimpose the plurality of rows of pixel data with the data in the final level buffer area in the data buffer module or the data in the intermediate buffer module, and input the superimposed data into the data buffer module or as the superimposed data; wherein N represents the total number of rows of pixels in the image sensor, and N≥2;

[0011] N-1 data cache modules are respectively connected to the output ends of different adders and each includes an M-level cache area for receiving the superimposed data; for the data cache module receiving the superimposed data, the data in each level of the cache area is sequentially moved into the next level of the cache area, and the data in the last level of the cache area is moved into the intermediate cache module; wherein M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to an integer plus one, and B represents the number of light sources;

[0012] The intermediate cache module is used to cache the data output by the final cache area, and input the cached data into the adder when the plurality of rows of pixels are input into the corresponding adder.

[0013] Optionally, the data selector is connected to an output end of the image sensor, and is used to input the plurality of rows of pixel data into a corresponding adder and / or data cache module;

[0014] Among them, the data of the first row of pixels in the image sensor is input into the first-level data cache area of ​​the first row of data cache module, and the data of the remaining rows of pixels are respectively input into their corresponding adders; the first row of pixels means that in the image sensor, a row of pixels of the object to be measured is first photographed; the first row of data cache module means a data cache module used to fixedly receive and cache the data of the first row of pixels.

[0015] Optionally, in the image sensor, except for the first row of pixels, the remaining rows of pixels correspond one-to-one to the adders; except for the last row of pixels, the remaining rows of pixels correspond one-to-one to the data cache module; wherein the last row of pixels represents a row of pixels of the object to be measured that is last captured in the image sensor.

[0016] Optionally, if the image sensor outputs data of a row of pixels at a time, when the data of the row of pixels is input into the corresponding adder, the data in the intermediate cache module is simultaneously input into the corresponding adder to obtain superimposed data, and the superimposed data is input into the first-level cache area of ​​the data cache module corresponding to the row of pixels;

[0017] Wherein, inside the corresponding data cache module, the data in each level of cache area is moved into the next level of cache area in sequence, and the data in the last level of cache area is moved into the intermediate cache module.

[0018] Optionally, if the image sensor outputs data of multiple rows of pixels at a time, during the process of inputting the front row of data into the corresponding adder, the data in the intermediate cache module is simultaneously input into the corresponding adder to obtain superimposed data, and the superimposed data is input into the first-level cache area of ​​the data cache module corresponding to the front row of data;

[0019] In the process of inputting the subsequent row data into the corresponding adder, the data in the last level buffer area in the data buffer module of the previous row is simultaneously input into the corresponding adder to obtain superimposed data, and the superimposed data is input into the first level buffer area of ​​the data buffer module corresponding to the subsequent row data;

[0020] In the process of inputting the superimposed data into the data cache module corresponding to the subsequent row data, the data in each level of cache area inside the corresponding data cache module is moved into the next level of cache area in sequence, and the data in the last level of cache area in the data cache module corresponding to the last row of data is moved into the intermediate cache module;

[0021] Among them, the front row data represents data generated by the front row pixels; the front row pixels represent a row of pixels of the object to be measured that is first photographed in a single output of multiple rows of pixels; the subsequent row data represents data generated by subsequent row pixels; the subsequent row pixels represent the remaining row pixels except the front row pixels in a single output of multiple rows of pixels; the last row data represents data generated by the last row pixels; the last row pixels represent a row of pixels of the object to be measured that is last photographed in a single output of multiple rows of pixels.

[0022] Optionally, the data cache module is composed of one or more data caches;

[0023] Among them, one cache is used as a first-level cache area; or, the cache space in one cache is divided to form a multi-level cache area.

[0024] Optionally, each level of cache area caches data of a row of pixels, and the intermediate cache module includes only one cache area.

[0025] In a second aspect of the present application, an image data superposition method is provided, characterized in that it is applied to any system described in the first aspect, and the image data superposition method includes:

[0026] In each row pixel reading cycle, a plurality of rows of pixel data output by the image sensor are obtained;

[0027] Based on the data selector, the plurality of rows of pixel data are input into corresponding adders and / or data buffer modules;

[0028] Acquire the data in the final cache area or the intermediate cache module in the data cache module, and input the data into the corresponding adder for superimposing with the plurality of lines of pixel data to obtain superimposed data;

[0029] Input the superimposed data into a data buffer module or as the superimposed data;

[0030] In the process of inputting the superimposed data into the data cache module, the data in each level of cache area inside the data cache module are moved into the next level of cache area in sequence, and the data in the last level of cache area are moved into the intermediate cache module or adder.

[0031] In a third aspect of the present application, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0032] Memory, used to store computer programs;

[0033] The processor is used to implement the image data superposition method described in the second aspect when executing the program stored in the memory.

[0034] In a fourth aspect of the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the image data superposition method described in the second aspect is implemented.

[0035] The beneficial effects of this application are as follows:

[0036] The present application provides an image data overlay system, comprising:

[0037] A data selector, used for inputting a plurality of rows of pixel data output by the image sensor into a corresponding adder and / or a data buffer module;

[0038] N-1 adders, connected to the output end of the data selector, are used to superimpose the plurality of rows of pixel data with the data in the final level buffer area in the data buffer module or the data in the intermediate buffer module, and input the superimposed data into the data buffer module or as the superimposed data; wherein N represents the total number of rows of pixels in the image sensor, and N≥2;

[0039] N-1 data cache modules are respectively connected to the output ends of different adders and each includes an M-level cache area for receiving the superimposed data; for the data cache module receiving the superimposed data, the data in each level of the cache area is sequentially moved into the next level of the cache area, and the data in the last level of the cache area is moved into the intermediate cache module; wherein M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to an integer plus one, and B represents the number of light sources;

[0040] The intermediate cache module is used to cache the data output by the final cache area, and read the cached data into the adder when the plurality of rows of pixels are input into the corresponding adder.

[0041] Based on the above settings, the present application provides a system hardware structure that can be used for TDI data superposition, and uses the ratio of the pixel row interval to the pixel in the image sensor and the numerical value calculated by the number of light sources to obtain the total number of cache levels in the data cache module; the row pixel data output by the image sensor is superimposed with the data in the last-level cache area or the data in the intermediate cache area in the data cache module, and the superimposed data is input into the next data cache module, and the data in the cache area flows downward step by step, and each data cache module corresponds one-to-one to different pixel rows.

[0042] Therefore, based on the hardware structure design provided by the above system, it is possible to achieve TDI superposition of row pixel data in the image sensor by completing the superposition of image data, inputting it into the data cache module, flowing out step by step, and inputting it into the intermediate cache module in each row pixel reading cycle in a fixed order. There is no need to calculate the spatial position corresponding to the cache area, thereby improving the efficiency of image data superposition. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0044] Figure 1 It is a structural diagram of an image data superposition system in a single-row pixel readout scenario provided by the present application;

[0045] Figure 2 is a structural diagram of another image data superposition system in a single-row pixel readout scenario provided by the present application;

[0046] Figure 3 It is a structural diagram of an image data superposition system in a multi-row pixel readout scenario provided by the present application;

[0047] Figure 4 is a structural diagram of another image data superposition system in a multi-row pixel readout scenario provided by the present application;

[0048] Figure 5 It is a structural diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0050] TDI (Time Delay Integration) technology can take advantage of the multiple rows of pixels in the linear array sensor (i.e., the image sensor of the present application) and can achieve imaging of the same position of the object to be measured on different rows of pixels of the linear array sensor at different times by matching the relationship between the object's motion speed and the line frequency. Further, by superimposing the imaging results of different rows of pixels, a higher image signal-to-noise ratio can be achieved.

[0051] Existing multi-line TDI sensors usually read out the image data corresponding to all rows of pixels and then complete the TDI data superposition in the back-end processor, which takes up a lot of cache space. In order to reduce the cache space of the back-end processor, the Chinese patent "CN118784994A A TDI data cache method, system, electronic device and storage medium" proposes a solution. In the TDI data superposition process, by reusing the same buffer and reading, superimposing and rewriting the image data to be superimposed, compared with the traditional multi-line cache parallel superposition method, the RAM cache resources are reduced by more than half.

[0052] However, in the above TDI data cache solution, in each superposition process, the cache address of each row of pixel data (i.e., the image data or data of the present application) needs to be calculated based on factors such as the reading cycle, the total number of sensor rows, the total number of light sources, etc. When the number of sensor lines and the number of light source partitions increase, the calculation process of the cache address will become complicated, and the consumption of logic resources will also increase greatly, reducing the superposition efficiency of the image data generated by the TDI sensor.

[0053] In order to solve the above problems, the present application proposes an image data overlay system, comprising:

[0054] The data selector is used to input a plurality of rows of pixel data output by the image sensor into corresponding adders and / or data buffer modules.

[0055] N-1 adders are connected to the output end of the data selector, and are used to superimpose the plurality of rows of pixel data with the data in the final level buffer area in the data buffer module or the data in the intermediate buffer module, and input the superimposed data into the data buffer module or as the superimposed data. Wherein, N represents the total number of rows of pixels in the image sensor, and N≥2.

[0056] N-1 data cache modules are connected to the output ends of different adders, and each includes an M-level cache area for receiving the superimposed data. For the data cache module receiving the superimposed data, the data in each level of cache area is moved to the next level of cache area in sequence, and the data in the last level of cache area is moved to the intermediate cache module or adder. Wherein, M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to an integer plus one, and B represents the number of light sources.

[0057] The intermediate cache module is used to cache the data output by the final cache area, and read the cached data into the adder when the plurality of rows of pixels are input into the corresponding adder.

[0058] Based on the above processing, the present application provides a system structure that can be used for TDI data superposition, using the ratio of the pixel row interval to the pixel in the image sensor and the numerical value calculated by the number of light sources as the total number of cache levels in the data cache module, and superimposing the row pixel data output by the image sensor with the data in the last-level cache area or the data in the intermediate cache area in the data cache module, and inputting the superimposed data into the next data cache module, and at the same time, the data in the cache area flows downward step by step, and each data cache module corresponds one-to-one to different pixel rows.

[0059] Therefore, based on the hardware structure design provided by the above system, it is possible to achieve TDI superposition of row pixel data in the image sensor by completing the superposition of image data, inputting it into the data cache module, flowing out step by step, and inputting it into the intermediate cache module in each row pixel reading cycle in a fixed order. There is no need to calculate the spatial position corresponding to the cache area, thereby improving the efficiency of image data superposition.

[0060] In the technical solution provided in the present application, the total number of pixel rows in the image sensor is N, and the pixel rows are sorted according to the order in which different pixel rows capture the same area to be measured, and are divided into the first row, the second row to the Nth row.

[0061] Among them, the pixel data generated by the first row of pixels is used as the first row of pixel data in this application; the pixel data generated by the Nth row of pixels is used as the last row of pixel data in this application.

[0062] The row pixel reading cycle represents the time taken by the image sensor to output a row of pixel data (or, referred to as acquiring the data of a row of pixels in the image sensor). In the technical solution provided by the present application, in a row pixel reading cycle, the image sensor can output a single row or P rows of pixel data. Wherein, 2≤P≤N. Generally, the ratio between the total number of rows N and the number of rows read at a single time P is a positive integer.

[0063] In actual work, after one exposure, all pixels in the image sensor generate pixel values ​​(i.e., image data of the present application) to form a frame of image. The back-end processor successively acquires the data of one row or P rows of pixels in the above frame of image data in each row pixel reading cycle. Successive acquisition means acquiring the data of one row or P rows of pixels in sequence based on the arrangement order of the pixel rows.

[0064] In some embodiments, the data selector has an input terminal connected to the image sensor and has at least N output terminals. The output terminals of the data selector correspond to pixel rows in the image sensor one by one, and each output terminal is used to output pixel data of a different row.

[0065] Among them, according to the pixel row order of the output data, the output end of the data selector can be divided into the first row output end, the second row output end, and so on until the Nth row output end. That is, the first row output end is used to output the data generated by the first row of pixels, the second row output end is used to output the data generated by the second row of pixels, and so on.

[0066] In some embodiments, based on the data selector, the data of the first row of pixels in the image sensor is input into the first-level data cache area of ​​the first row of data cache module, and the data of the remaining rows of pixels are respectively input into the corresponding adders. The first row of pixels means that in the image sensor, a row of pixels of the object to be measured is first photographed; the first row of data cache module means a data cache module for fixedly receiving and caching the data of the first row of pixels.

[0067] Specifically, the first row output end is directly connected to the first row data cache module, and is used to input the first row pixel data (ie, the first row pixel data) into the first level cache area in the first row data cache module.

[0068] For the output end of the data selector, except for the output end of the first row, the remaining output ends are connected to an adder. Among them, the adder connected to the output end of the second row is used as the second adder; the adder connected to the output end of the third row is used as the third adder, and so on, the adder connected to the output end of the Nth row is used as the adder of the Nth row. It can be seen that the image data superposition system provided by the present application includes N-1 adders.

[0069] In one implementation, the adder represents an electronic device that can perform data superposition, and a lookup table may also be used instead.

[0070] In the image sensor, except for the first row of pixels, the remaining rows of pixels correspond to adders one by one. That is, the corresponding adders are used to receive and add data generated by the corresponding pixel rows.

[0071] Except for the adders in the Nth row, the output ends of the other adders are connected to a data buffer module, wherein the connected data buffer module is used to receive and buffer the superimposed data.

[0072] It can be seen that in the image data superposition system provided in the present application, N-1 data cache modules are included. For the image sensor, except for the last row of pixels, the remaining rows of pixels correspond to the data cache modules one by one. Specifically, the first row of data cache modules are used to cache the data generated by the first row of pixels.

[0073] Except for the first row data cache module, the remaining data cache modules are used to cache the data generated by the corresponding pixel rows and the superimposed data. Specifically, the second row data cache module is used to cache the data generated by the second row of pixels, and the superimposed data is the data in the final cache area or the intermediate cache module in the first row of data cache module; the third row data cache module is used to cache the data generated by the third row of pixels, and the superimposed data is the data in the final cache area or the intermediate cache module in the second row of data cache module; and so on, the N-1 row data cache module is used to cache the data generated by the N-1 row of pixels, and the superimposed data is the data in the final cache area or the intermediate cache module in the N-2 row of data cache module.

[0074] For the data of the Nth row of pixels, the data is superimposed in the Nth row adder with the data in the final cache area of ​​the N-1th row of data cache module or the data in the intermediate cache module, as the row pixel data that completes the data superposition, and is directly input into the next processor.

[0075] Each data cache module contains M cache areas, and one cache area corresponds to a first-level cache area. One cache area is used to store image data generated by a row of pixels. The intermediate cache module may contain only one cache area.

[0076] When the image sensor outputs one row of pixel data at a time (i.e., within one row of pixel reading cycle, the image sensor only outputs one row of pixel data), in the image data overlay system provided in the present application, each data cache module is connected to the intermediate cache module, and the intermediate cache module is connected to the adder.

[0077] In the image data superposition system provided by the present application, the first row of pixel data in the image sensor is directly input into the first level cache area of ​​the first row data cache module via the first row output end of the data selector. In addition, while receiving the first row of pixel data, the first row data cache module sequentially moves the data in each level of cache area inside it into the next level of cache area, and moves the data in the last level of cache area into the intermediate cache module.

[0078] The second row of pixel data in the image sensor is input into the second row adder through the second row output end of the data selector. At the same time, the data in the intermediate cache module is obtained and sent to the second row adder. The superimposed data is input into the first level cache area of ​​the second row data cache module. At the same time, for the second row data cache module, the data in each level of cache area in the second row data cache module is sequentially moved into the next level of cache area, and the data in the last level of cache area is moved into the intermediate cache module.

[0079] By analogy, in the subsequent row pixel reading cycle, the above processing is performed on the third row pixel data, the fourth row pixel data, and up to the N-1th row pixel data.

[0080] For the Nth row of pixel data in the image sensor, it is input into the Nth row adder through the Nth row output end of the data selector. At the same time, the data in the intermediate cache module is obtained to the Nth row adder. The superimposed data of the two is used as the superimposed data and is directly output.

[0081] Each data cache module contains M-level cache areas, and the total number of levels M is obtained by rounding the ratio of the pixel row interval to the pixel in the TDI sensor plus one, and multiplying it by the number of light sources. Among them, the ratio rounding means that when the ratio is an integer, the rounding is its own value, and when the ratio is a non-integer, the ratio value can be rounded up or down according to the needs.

[0082] The number of light sources can be used to represent the number of exposures when the TDI sensor moves a single row of pixels. For example, in single-light mode, the ratio of the TDI sensor's line rate to the object's motion rate is 1:1; in multi-light mode with multi-angle lighting, the number of light sources is B, and at this time, the ratio of the line rate to the object's motion rate is B:1.

[0083] Therefore, the total number of levels M of the buffer area in the data buffer module is obtained by multiplying the value A obtained by rounding the ratio of the pixel row interval to the pixel in the image sensor plus one by the number of light sources B, and after each row pixel data superposition, the data in each level of the buffer area in the data buffer module used to cache the superimposed data is transferred downward step by step. Therefore, when the row pixel data output by the image sensor and the data in the intermediate buffer module belong to the row pixel data of the same area photographed under the same light source, it meets the basic rules of row pixel data superposition in the TDI superposition field. Example 1

[0084] like Figure 1 As shown, when the image sensor reads out one line of pixel data at a time, the image data superposition system provided by the present application includes a data selector, N-1 adders, N-1 data cache modules and an intermediate cache module.

[0085] The hardware connection structure of the system is as follows: the input end of the data selector is connected to the image sensor, the first row output end is connected to the data cache module 1 (that is, the first row data cache module of the present application), and the remaining output ends are connected to N-1 adders. At the same time, the other input end of the adder is connected to the intermediate cache module, and the output end is connected to the data cache module corresponding to the row pixel. The N-1 data cache modules are all connected to the intermediate cache module. Among them, except for the first row of pixels, the remaining row pixels correspond to the adder one-to-one; except for the last row of pixels, the remaining row pixels correspond to the data cache module one-to-one. The total number of cache levels of each data cache module is M.

[0086] The process of row pixel data superposition is as follows: after one exposure, the image sensor generates an image frame containing N rows of pixels, and outputs the row pixel data in the image frame one by one in the order of row pixels. After the image sensor outputs (or reads the image sensor) the first row of pixel data, the first row of pixel data is directly input into the cache area 1 (i.e., the first-level cache area of ​​the present application) of the data cache module 1 through the data selector. Among them, while receiving the first row of pixel data, the data cache module 1 moves the data in the internal cache area 1 to the cache area M step by step to the next-level cache area in the order of the cache area levels. For example, the data in cache area 1 is moved into cache area 2, the data in cache area 2 is moved into cache area 3, and so on. Among them, the data in cache area M (i.e., the last-level cache area) is moved into the intermediate cache module.

[0087] After the image sensor outputs the second row of pixel data, the second row of pixel data is input into the adder (i.e., the second row of adder of the present application) through the second row output port of the data selector. At the same time, the data in the intermediate cache module is obtained and input into the adder, so that the second row of pixel data is superimposed with the data in the intermediate cache module, and the superimposed data is input into the cache area 1 of the data cache module 2 (i.e., the second row of data cache module of the present application). It should be noted that while the superimposed data is input into the data cache module 2, the data in the internal cache area of ​​the data cache module 2 is moved step by step into the cache area of ​​the next level, and the data in the cache area M is moved into the intermediate cache module.

[0088] After the image sensor outputs the third row of pixel data, the third row of pixel data is input into the third row adder through the data selector, and the data in the intermediate cache module is input into the third row adder. After the two are superimposed, the data in the internal cache area of ​​the data cache module 3 is moved step by step into the next level of cache area, and the data in the cache area M is moved into the intermediate cache module. Then, the superimposed data is input into the cache area 1 in the data cache module 4.

[0089] Similarly, when each row of pixel data is input to the corresponding adder, the data in the intermediate cache module is also input to the adder, the two are superimposed, and the superimposed data is input to the first-level cache area in the corresponding data cache module. When the corresponding data cache module receives the superimposed data, it moves the data in its internal cache area to the next-level cache area step by step, and the data in the final-level cache area is moved to the intermediate cache module.

[0090] After the image sensor outputs the Nth row pixel data (i.e., the last row pixel data of the present application), the Nth row pixel data is input to the Nth row adder, and the data in the intermediate buffer module is also input to the Nth row adder, and the superimposed data of the two are used as the row pixel data after superimposition (or the row pixel data after TDI superposition). Then, the superimposed row pixel data is directly output to the next level data processor.

[0091] In the application scenario where N=4 and M=2×2=4, the above-mentioned technical solution for reading out a row of pixels at a time is explained. For example, for an image sensor with a total number of 4 rows, a ratio of pixel row interval to pixel of 1, and a number of light sources of 2 (at this time, the ratio of row frequency to object motion rate is 2), this application scenario is met. Figure 2 As shown, Figure 2 A schematic diagram of the structure of another image data overlay system provided in this application.

[0092] Combined with the TDI superposition principle, it can be seen that in this application scenario, the data of the first pixel row at the first exposure is superimposed with the data of the second pixel row under the fifth exposure. According to the above scheme, after each row of pixels is output, the data in the buffer area in the data buffer module is transferred to the next buffer area, and the data in the last level buffer area is transferred to the intermediate buffer module. Therefore, according to the structural setting of this superposition system and the direction of data superposition flow, the data of the first pixel row at the first exposure can be superimposed with the data of the second pixel row under the fifth exposure, which conforms to the TDI superposition process.

[0093] After each exposure, the image sensor generates data for 4 rows of pixels. During the data reading process, each row pixel reading cycle only reads data for one row of pixels, and reads in the order of L1, L2, L3 and L4. The data selector is a 4-to-1 data selector, and the data cache modules include A1, A2 and A3. Among them, each data cache module includes 4 cache areas, namely cache areas 10 to 13, cache areas 20 to 23, and cache areas 30 to 33, and the middle cache module is the middle cache area B.

[0094] After the first exposure, the data generated by the pixel row L1 is valid data L11. In the first row pixel reading cycle, the pixel values ​​in the buffer area 13 are input to the intermediate buffer area B, and the valid data L11 is stored in the buffer area 10. The data in the buffer area 10 is moved to the buffer area 11, the data in the buffer area 11 is moved to the buffer area 12, and the data in the buffer area 12 is moved to the buffer area 13. The following is an example of valid data L11, and the rest of the row data can be understood by referring to this process. Among them, L11 represents the data generated by the pixel row L1 during the first exposure.

[0095] Similarly, in the next three row pixel reading cycles, the data of pixel rows L2 and L3 are superimposed with the data in the intermediate buffer area B and input into buffer areas 20 and 30 respectively, and the data of L4 is superimposed with the data in the intermediate buffer area B and output. It should be noted that after the first exposure, only the data generated by L1 is valid data, so before L11 completes TDI superposition, the directly output data can be directly discarded without being input into the next processor.

[0096] After the second exposure, the data generated by the pixel row L1 is valid data L12, which is input to the buffer area 10, and the valid data L11 is transferred to the buffer area 11. The data of the remaining pixel rows are invalid data, which will not be described in detail.

[0097] After the third exposure, the data in the original buffer area 11 is transferred to the intermediate buffer area, the data generated by pixel row L1 is valid data L13, which is input to buffer area 10, while the valid data L12 flows to buffer area 11, and the valid data L11 flows to buffer area 12.

[0098] After the fourth exposure, the data in the original buffer area 10 is transferred to the intermediate buffer area B, and the data generated by the pixel row L1 is the valid data L14, which is input into the buffer area 10, while the valid data L13 flows to the buffer area 11, the valid data L12 flows to the buffer area 12, and the valid data L11 flows to the buffer area 13.

[0099] After the fifth exposure, in the first row pixel reading cycle, the data L11 in the original buffer area 10 is transferred to the intermediate buffer area, and the data generated by the pixel row L1 is the valid data L15, which is input into the buffer area 10, while the valid data L14 flows to the buffer area 11, the valid data L13 flows to the buffer area 12, and the valid data L12 flows to the buffer area 13.

[0100] During the second row pixel reading cycle, the data L25 generated by the second row of pixels is superimposed with the data L11 in the intermediate buffer area, and then the data in each buffer area in the data buffer module A2 is transferred one by one to the next buffer area, and the data after the superposition of L25 and L11 is cached in the buffer area 20.

[0101] Similarly, after the 9th exposure, the superimposed data of L25 and L11 has been cached in the intermediate cache area B. In the reading process of the data generated after the 9th exposure, in the third row pixel reading cycle, the data L39 generated by the pixel row L3 is superimposed again with the superimposed data of L25 and L11, and then the data in each cache area in the data cache module A2 is transferred one by one to the next cache area, and the superimposed data of L39, L25 and L11 is cached in the cache area 30.

[0102] Similarly, after the 13th exposure, the superimposed data of L39, L25 and L11 have been cached in the intermediate cache area B. In the reading process of the data generated after the 13th exposure, in the fourth row pixel reading cycle, the data L413 generated by the pixel row L4 is superimposed again with the superimposed data of L39, L25 and L11, thereby obtaining the completed TDI superimposed data and directly outputting it to the next processor. In addition, the TDI superposition (i.e., image data superposition of the present application) process corresponding to the remaining rows of pixels can be understood with reference to the above process. Example 2

[0103] When the image sensor outputs P rows of pixel data at a time (i.e., in one row pixel reading cycle, the image sensor outputs P rows of pixel data), the row of pixels that first captures the object to be measured among the P rows of pixels is taken as the front row of pixels, and the remaining row of pixels is taken as the subsequent row of pixels. In addition, among the subsequent row of pixels, the row of pixels that last captures the object to be measured is taken as the last row of pixels. Figure 3 As shown, data cache module 1 and data cache module P+1 belong to the data cache modules corresponding to the front row of pixels; data cache module 2, data cache module P, data cache module P+2 and data cache module 2P belong to the data cache modules corresponding to the subsequent row of pixels, and data cache module P and data cache module 2P belong to the data cache modules corresponding to the last row of pixels.

[0104] For any of the P rows of pixels described above, except for the last row of pixels, the data cache modules corresponding to the remaining rows of pixels are all connected to the adders corresponding to the next row of pixels, so as to realize that when the data of the remaining rows of pixels are input to the corresponding adders, the data in the final-level cache area of ​​the data cache modules corresponding to the remaining rows of pixels are synchronously input to the adders corresponding to the next row of pixels. For example, data cache module 1 is connected to the adder of the second row, data cache module 2 is connected to the adder of the third row, etc.

[0105] The adder corresponding to the front row of pixels is connected to the intermediate cache module to obtain the data in the intermediate cache module when the data of the front row of pixels is input to the corresponding adder, so as to complete the superposition of the two rows of pixel data. Figure 3 The adders in the P+1th row are connected to the intermediate cache module.

[0106] If the front row of pixels is the first row of pixels, the data of the first row of pixels is directly input into the first level cache area of ​​the first row of data cache module. For the first row of data cache module, when receiving the first row of pixel data, the data in each level of internal cache area is moved into the next cache area step by step, and the data in the last level of cache area is moved into the second row of adders.

[0107] The data cache module corresponding to the last row of pixels is connected to the intermediate cache module, and is used to transfer the data in each level of the cache area in the data cache module corresponding to the last row of pixels downward step by step after the last row of pixel data is superimposed with the data in the last level of the cache area in the data cache module corresponding to the previous row of pixels, and the data in the last level of the cache area is input to the intermediate cache module. Figure 3 The data cache module P and the data cache module 2P shown are both connected to the intermediate cache module.

[0108] Specifically, when the image sensor reads out P rows of pixel data at a time, the image data superposition system structure provided by the present application is as follows: Figure 3 Compared with the system structure diagram when reading out one row of pixel data at a time, the hardware connection structure is different as follows: except that the data cache modules corresponding to the Pth row of pixels, 2P row of pixels, 3P row of pixels, etc. are all connected to the middle cache module, the data cache modules corresponding to the remaining rows of pixels are all connected to the adders corresponding to the next row of pixels.

[0109] The process of superimposing row pixel data is as follows: after one exposure, the image sensor generates an image frame containing N rows of pixels, and simultaneously outputs P rows of pixel data in the order of row pixels. After the image sensor outputs (or reads the image sensor) the first P rows of pixel data, the first row of pixel data is directly input into the buffer area 1 of the data buffer module 1 through the data selector, and the subsequent row pixel data are all input into the corresponding adder. At the same time, in the process of inputting the subsequent row pixel data into the adder, the data of the last-level buffer area in the data buffer module connected to the adder is input into the adder to complete the superposition of the subsequent row pixel data and the data of the last-level buffer area in the data buffer module corresponding to the previous row of pixels. For example, when the second row of pixel data is input into the second row adder, the data of the buffer area M in the data buffer module 1 is also input into the second row adder to complete the superposition of the two.

[0110] Then, the superimposed data is input into the first level buffer area of ​​the data buffer module corresponding to the subsequent row pixel data. After the last row pixel data is superimposed, while being input into the data buffer module corresponding to the last row pixel, the buffer area data in the data buffer module corresponding to the last row pixel is moved to the next level buffer area step by step, and the last level buffer area data is input into the intermediate buffer module. Figure 3 For example, after the pixel data of the Pth row is superimposed with the data in the buffer area M in the data buffer module P-1, the superimposed data is input into the buffer area 1 in the data buffer module P. While the superimposed data is input, the data in the buffer area of ​​the data buffer module P is moved to the next level buffer area step by step, and the data in the last level buffer area is input into the intermediate buffer module.

[0111] After the image sensor simultaneously outputs the pixel data of the P+1th to 2Pth rows, based on the data selector, the pixel data of the P+1th to 2Pth rows are respectively input into the corresponding adders. Then, the data in the intermediate cache module is input into the adder of the P+1th row, and the data in the final cache area of ​​the data cache module P+1 is input into the adder of the P+2th row. By analogy, for the subsequent row pixels, the data in the final cache area of ​​the data cache module corresponding to the previous row of pixels are all input into the adder corresponding to the subsequent row of pixels to perform row pixel superposition, and the superimposed data are input into the data cache module corresponding to the subsequent row of pixels. For example, after the pixel data of the P+2th row is superimposed with the data in the cache area M in the data cache module P+1, the superimposed data is input into the data cache module P+2. While the superimposed data is input into the data cache module 2P, the data in the cache area M in the data cache module 2P is input into the intermediate cache module.

[0112] And so on, until the superposition of N rows of pixel data in the image frame is completed. In addition, after the Nth row of pixel data is superimposed with the data in the buffer area of ​​the data buffer module N-1 in the Nth row adder, the superimposed data is used as the row pixel data that has completed the superposition, and is directly input into the data processor of the next level.

[0113] The following is an explanation of the above-mentioned technical solution for single readout of 2 rows of pixels in the application scenario of N=4 and M=2×2=4. Figure 4 As shown, Figure 4 A schematic diagram of the structure of another image data overlay system provided in this application.

[0114] Specifically, after each exposure, the image sensor generates 4 rows of pixel data. In the process of reading data, each row pixel reading cycle reads 2 rows of pixel data, and reads in the order of L1 and L2, and L3 and L4. The data selector is a 2-to-1 data selector, and the data cache module includes A1, A2 and A3. Among them, each data cache module includes 4 cache areas, namely cache areas 10 to 13, cache areas 20 to 23, and cache areas 30 to 33, and the middle cache module is the middle cache area B.

[0115] After the first exposure, the data generated by the pixel row L1 is valid data L11. In the first row pixel reading cycle, the pixel values ​​in the buffer area 13 are input to the second row adder, and the buffer area data in the data buffer module A1 is gradually moved to the next level buffer area, and the valid data L11 is input to the buffer area 10. At the same time, the data generated by the pixel row L2 is invalid data, which is superimposed with the data in the buffer area 13 and then moved to the buffer area 20, while the data in the buffer area 23 is moved to the intermediate buffer area B. The following content is explained by taking the valid data L11 as an example, and the rest of the row data can be understood by referring to this process.

[0116] Similarly, in the next row pixel reading cycle, the data of pixel row L3 is superimposed with the data and input into the buffer area 30, and the data of L4 is superimposed with the data in the buffer area 33 and output. Before the data generated by L1 completes TDI superposition, the back-end processor does not process the directly output data and directly discards it.

[0117] After the second exposure, the data generated by the pixel row L11 is valid data L12, which is input to the buffer area 10, and the valid data L11 is transferred to the buffer area 11. The data of the remaining pixel rows are invalid data, which will not be described in detail.

[0118] After the third exposure, the data in the original buffer area 11 is transferred to the buffer area 13, the data generated by the pixel row L1 is the valid data L13, which is input to the buffer area 10, while the valid data L12 flows to the buffer area 11, and the valid data L11 flows to the buffer area 12.

[0119] After the fourth exposure, the data in the original buffer area 10 is moved into the first row adder and superimposed with the data generated by the pixel row L2. The data generated by the pixel row L1 is the valid data L14, which is input into the buffer area 10, while the valid data L13 flows to the buffer area 11, the valid data L12 flows to the buffer area 12, and the valid data L11 flows to the buffer area 13.

[0120] After the fifth exposure, in the first row pixel reading cycle, the data L11 in the original buffer area 10 is transferred to the second row adder, the data generated by the pixel row L1 is the valid data L15, which is input to the buffer area 10, and the valid data L14 flows to the buffer area 11, the valid data L13 flows to the buffer area 12, and the valid data L12 flows to the buffer area 13. At the same time, the data L25 generated by the second row of pixels is superimposed with the data L11 in the middle buffer area and input to the buffer area 20, and the data in each buffer area in the data buffer module A2 is sequentially moved to the next buffer area. Among them, the data in the buffer area 23 is moved to the middle buffer area B.

[0121] Similarly, after the 9th exposure, the superimposed data of L25 and L11 has been cached in the intermediate cache area B. In the reading process of the data generated after the 9th exposure, in the second row pixel reading cycle, the data L39 generated by the pixel row L3 and the superimposed data of L25 and L11 are superimposed in the third row adder, and the data in each cache area in the data cache module A3 are transferred one by one to the next cache area, and the superimposed data of L39, L25 and L11 are cached in the cache area 30.

[0122] Similarly, after the 12th exposure, the superimposed data of L39, L25 and L11 has been cached in the cache area 33. When the 13th exposure is performed, in the second row pixel reading cycle, the data L413 generated by the pixel row L4 is superimposed with the superimposed data of L39, L25 and L11 again in the fourth row adder, thereby obtaining the completed TDI superimposed data and directly outputting it to the next level data processor. In addition, the TDI superimposition corresponding to the remaining rows of pixels can be understood by referring to the above process.

[0123] In some embodiments, the data cache module is composed of one or more data caches. For example, one cache is used as a first-level cache area, that is, one data cache module is composed of M caches.

[0124] Alternatively, the data cache module may be composed of a data cache, and the cache space in the cache may be divided to form an M-level cache area. The cache may be a FIFO (First Input First Output) cache. Based on the above processing, the utilization rate of the cache resources in the cache may be improved.

[0125] In one implementation, each level of buffer caches data of a row of pixels, wherein the data of the row of pixels includes data before superposition and data after superposition.

[0126] In some embodiments, only one cache area may be provided in the intermediate cache module. Based on the above processing, it can be known that in the working scenario of an image sensor with 4 pixel rows, a ratio of pixel row interval to pixel size of 1, and a number of light sources of 3, the total number of corresponding cache areas in the image data superposition system provided by the present application is 19, which is the same as the total amount of cache space (i.e., cache area) in the solution provided by the Chinese patent "CN118784994A A TDI data caching method, system, electronic device and storage medium". It can be seen that the image data superposition solution provided by the present application can also achieve the purpose of reducing the TDI cache space. Furthermore, since in the image data superposition solution provided by the present application, there is no need to calculate the cache address of each row of pixel data during the superposition and caching process, the time consumed in the logical operation process is greatly reduced, and the efficiency of data superposition is improved.

[0127] Based on the same invention communication, the present application also provides an image data superposition method, which is applied to the aforementioned image data superposition system, and the method comprises the following steps:

[0128] S1. In each row pixel reading cycle, a plurality of rows of pixel data output by the image sensor are obtained.

[0129] S2. Based on the data selector, the plurality of rows of pixel data are input into corresponding adders and / or data cache modules.

[0130] S3, obtaining data in the final cache area or the intermediate cache module in the data cache module, and inputting the data into the corresponding adder for superimposing with the row pixel data to obtain superimposed data.

[0131] S4. Input the superimposed data into a data buffer module or use it as the superimposed data.

[0132] Wherein, in the process of inputting the superimposed data into the data buffer module, the image data superimposition method further comprises the following steps:

[0133] S5. Move the data in each level of cache area inside the data cache module into the next level of cache area in sequence, and move the data in the last level of cache area into the intermediate cache module.

[0134] For step S2, if the row pixel data is the first row pixel data, it is input into the corresponding first row data buffer module. Except for the first row pixel data, the remaining row pixel data are input into the corresponding adder.

[0135] When the image sensor reads out one line of pixel data at a time, for step S3, the data in the intermediate buffer module is obtained and input into the corresponding adder in step S2 to obtain the superimposed data.

[0136] In step S4, if the pixel data of the non-last row is superimposed, the superimposed data is input into the data buffer module corresponding to the row pixel data. If the pixel data of the last row is superimposed, it is directly input into the next level processor as the superimposed data.

[0137] For step 5, the data in the final cache area is moved into the intermediate cache module.

[0138] When the image sensor reads out P rows of pixel data at a time, in step S3, the data in the intermediate cache module is obtained for the data of the front row of pixels, and input into the corresponding adder to obtain the superimposed data. For the data of the subsequent row of pixels, the data in the final cache area of ​​the data cache module corresponding to the previous row of pixels belonging to the subsequent row of pixels is obtained, and input into the corresponding adder to obtain the superimposed data.

[0139] Similarly, for step S4, if the non-last row pixel data is superimposed, the superimposed data is input into the data buffer module corresponding to the row pixel data. If the last row pixel data is superimposed, it is directly input into the next level processor as the superimposed data.

[0140] For step 5, the data in the final cache area is moved into the intermediate cache module.

[0141] When the image sensor reads out P rows of pixel data at a time, in step S3, the data in the intermediate cache module is obtained for the data of the front row of pixels, and is input into the corresponding adder to obtain the superimposed data. For the data of the subsequent rows of pixels, the data in the final cache area of ​​the data cache module corresponding to the previous row of pixels belonging to the subsequent row of pixels is obtained, and is input into the corresponding adder to obtain the superimposed data.

[0142] Similarly, for step S4, if the non-last row pixel data is superimposed, the superimposed data is input into the data buffer module corresponding to the row pixel data. If the last row pixel data is superimposed, it is directly input into the next level processor as the superimposed data.

[0143] With respect to step 5, for the data cache module corresponding to the last row of pixels, the data in the final-level cache area is moved into the intermediate cache module.

[0144] The present application also provides an electronic device, such as Figure 5 As shown, it includes a processor 501, a communication interface 502, a memory 503 and a communication bus 504, wherein the processor 501, the communication interface 502, and the memory 503 communicate with each other through the communication bus 504.

[0145] Memory 503, used for storing computer programs;

[0146] The processor 501 is used to implement any of the above-mentioned image data superposition methods when executing the program stored in the memory 503.

[0147] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0148] The communication interface is used for communication between the above electronic device and other devices.

[0149] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0150] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0151] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned image data superposition methods are implemented.

[0152] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute the steps of any one of the image data superimposition methods in the above embodiments.

[0153] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An image data superposition system, characterized in that: include: A data selector, used for inputting a plurality of rows of pixel data output by the image sensor into a corresponding adder and / or a data buffer module; N-1 adders, if the image sensor outputs one row of pixel data at a time, the input end of the adder is connected to the output end of the data selector and the intermediate cache module; if the image sensor outputs multiple rows of pixel data at a time, the input end of the adder is connected to the output end of the selector and the intermediate cache module, or connected to the output end of the data selector and the final cache area of ​​the data cache module, for superimposing the plurality of rows of pixel data with the data in the final cache area of ​​the data cache module or the data in the intermediate cache module, and inputting the superimposed data into the data cache module or as the superimposed data; wherein N represents the total number of rows of pixels in the image sensor, and N≥2; N-1 data cache modules are respectively connected to the output ends of different adders and the first row output end of the data selector, and each includes an M-level cache area for receiving the superimposed data; for the data cache module receiving the superimposed data, the data in each level of the cache area inside is sequentially moved into the next level of the cache area, and the data in the last level of the cache area is moved into the intermediate cache module or the adder; wherein the first row output end is used to output the data generated by the first row of pixels; M=A×B, A represents the ratio of the pixel row interval to the pixel in the image sensor, rounded to an integer plus one, and B represents the number of light sources; The intermediate cache module is used to cache the data output by the final cache area, and input the cached data into the adder when the plurality of rows of pixels are input into the corresponding adder.

2. The system according to claim 1, characterized in that The data selector is connected to the output end of the image sensor and is used to input the plurality of rows of pixel data into the corresponding adder and / or data cache module; Among them, the data of the first row of pixels in the image sensor is input into the first-level data cache area of ​​the first row of data cache module, and the data of the remaining rows of pixels are respectively input into their corresponding adders; the first row of pixels means that in the image sensor, a row of pixels of the object to be measured is first photographed; the first row of data cache module means a data cache module used to fixedly receive and cache the data of the first row of pixels.

3. The system according to claim 1, characterized in that In the image sensor, except for the first row of pixels, the remaining rows of pixels correspond to the adders one by one; except for the last row of pixels, the remaining rows of pixels correspond to the data cache modules one by one; wherein the last row of pixels represents a row of pixels of the object to be measured that is last captured in the image sensor.

4. The system according to claim 3, characterized in that If the image sensor outputs data of one row of pixels at a time, during the process of inputting the data of the row of pixels into the corresponding adder, the data in the intermediate buffer module is simultaneously input into the corresponding adder to obtain superimposed data, and the superimposed data is input into the first-level buffer area of ​​the data buffer module corresponding to the row of pixels; Wherein, inside the corresponding data cache module, the data in each level of cache area is moved into the next level of cache area in sequence, and the data in the last level of cache area is moved into the intermediate cache module.

5. The system according to claim 3, characterized in that If the image sensor outputs data of multiple rows of pixels at a time, the data in the intermediate cache module is simultaneously input into the corresponding adder during the process of inputting the front row of data into the corresponding adder to obtain superimposed data, and the superimposed data is input into the first-level cache area of ​​the data cache module corresponding to the front row of data; In the process of inputting the subsequent row data into the corresponding adder, the data in the last level buffer area in the data buffer module of the previous row is simultaneously input into the corresponding adder to obtain superimposed data, and the superimposed data is input into the first level buffer area of ​​the data buffer module corresponding to the subsequent row data; In the process of inputting the superimposed data into the data cache module corresponding to the subsequent row data, the data in each level of cache area inside the corresponding data cache module is moved into the next level of cache area in sequence, and the data in the last level of cache area in the data cache module corresponding to the last row of data is moved into the intermediate cache module; Among them, the front row data represents data generated by the front row pixels; the front row pixels represent a row of pixels of the object to be measured that is first photographed in a single output of multiple rows of pixels; the subsequent row data represents data generated by subsequent row pixels; the subsequent row pixels represent the remaining row pixels except the front row pixels in a single output of multiple rows of pixels; the last row data represents data generated by the last row pixels; the last row pixels represent a row of pixels of the object to be measured that is last photographed in a single output of multiple rows of pixels.

6. The system according to claim 1, characterized in that The data cache module is composed of one or more data caches; Among them, one cache is used as a first-level cache area; or, the cache space in one cache is divided to form a multi-level cache area.

7. The system according to claim 1, characterized in that Each level of buffer caches data of a row of pixels, and the intermediate buffer module includes only one buffer.

8. A method for superimposing image data, characterized in that: Applied to the system according to any one of claims 1 to 7, the image data superposition method comprises: In each row pixel reading cycle, a plurality of rows of pixel data output by the image sensor are obtained; Based on the data selector, the plurality of rows of pixel data are input into corresponding adders and / or data buffer modules; Acquire the data in the final cache area or the intermediate cache module in the data cache module, and input the data into the corresponding adder for superimposing with the plurality of lines of pixel data to obtain superimposed data; Input the superimposed data into a data buffer module or as the superimposed data; In the process of inputting the superimposed data into the data cache module, the data in each level of cache area inside the data cache module are moved into the next level of cache area in sequence, and the data in the last level of cache area are moved into the intermediate cache module.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor is used to implement the image data superposition method described in claim 8 when executing the program stored in the memory.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the image data superimposition method described in claim 8 is implemented.

Images