Source driving chip, mode control method and display device

Abstract

The invention discloses a source electrode driving chip, a mode control method and a display device. The source electrode driving chip is connected with the time schedule controller and comprises a state detection module, a logic control module and a first mode control module. The state detection module is used for detecting whether a locking signal output by the source electrode driving chip to the time schedule controller is switched from a first level to a second level. The logic control module is used for controlling the first mode control module to start a first recognition mode when a locking signal is switched from a first level to a second level, and performing first correctness verification on driving information of an image frame; and after the target condition is met, the first mode control module is controlled to close the first recognition mode. Through the working state control of the first identification mode, the dynamic power consumption of the source electrode driving chip is reduced, so that the energy consumption of the display device is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a source driver chip, a mode control method and a display device. Background Art

[0002] With the development of display technology, users have higher and higher requirements for the energy consumption of display devices. Reducing the energy consumption of display devices helps to improve product competitiveness, promote environmental protection, extend service life, and improve power efficiency. Therefore, low-power display devices have become an important development direction of display technology. How to reduce the energy consumption of display devices is a topic that the industry has been committed to researching. Summary of the invention

[0003] The embodiments of the present application provide a source driver chip, a mode control method and a display device, which reduce the dynamic power consumption of the source driver chip through the working state control of the first recognition mode, thereby reducing the energy consumption of the display device.

[0004] The embodiment of the present application provides a source driver chip connected to a timing controller, wherein the source driver chip includes a state detection module, a logic control module and a first mode control module; wherein:

[0005] The state detection module is used to detect whether the lock signal output by the source driver chip to the timing controller is switched from the first level to the second level;

[0006] The logic control module is used for:

[0007] When the locking signal switches from the first level to the second level, controlling the first mode control module to start a first recognition mode to perform a first correctness check on the driving information of the image frame; and

[0008] After the target condition is met, the first mode control module is controlled to turn off the first recognition mode.

[0009] Accordingly, an embodiment of the present application provides a mode control method, which is applied to a source driver chip of a display device, wherein the source driver chip is connected to a timing controller of the display device, and the mode control method includes:

[0010] When the lock signal output by the source driver chip to the timing controller switches from the first level to the second level, the first recognition mode is started to perform a first correctness check on the driving information of the image frame;

[0011] After the target condition is met, the first recognition mode is turned off.

[0012] Accordingly, an embodiment of the present application provides a display device, which includes the above-mentioned source driver chip.

[0013] In summary, in the embodiment of the present application, when the source driver chip detects that the locking signal switches from the first level to the second level, such as from a low level to a high level, the first recognition mode is turned on to check the correctness of the driving information of the image frame; after the target condition is met, the source driver chip turns off the first recognition mode and no longer checks the correctness of the driving information of the image frame until the locking signal switches from the first level to the second level again. In the embodiment of the present application, the first recognition mode is not in a continuous working state, but the first recognition mode is turned on when the level state of the locking signal switches, and then the first recognition mode is turned off after the target condition is met. The embodiment of the present application reduces the dynamic power consumption of the source driver chip through the working state control of the first recognition mode, thereby reducing the energy consumption of the display device. In addition, the embodiment of the present application can be implemented based on the existing display device, without adding new devices in the display device, and has high compatibility with the existing display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of a source driver chip provided in an embodiment of the present application;

[0015] Figure 2 is a schematic diagram of at least part of the content contained in an image frame provided in an embodiment of the present application;

[0016] Figure 3 It is a schematic diagram of the meaning of an instruction provided in an embodiment of the present application;

[0017] Figure 4 is a flow chart of a mode control method provided in an embodiment of the present application;

[0018] Figure 5 is a flow chart of another mode control method provided in an embodiment of the present application;

[0019] Figure 6 is a schematic diagram of another source driver chip provided in an embodiment of the present application;

[0020] Figure 7 is a schematic diagram of a mode control method;

[0021] Figure 8 is a schematic diagram of a mode control method provided in an embodiment of the present application;

[0022] Fig. 9 It is a schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0024] In addition, the "plurality" in the embodiments of the present application refers to two or more. The "first" and "second" in the embodiments of the present application are used to distinguish different technical features, and do not indicate any order, quantity or importance.

[0025] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0026] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0027] See also Figure 1 , Figure 1 Schematic diagram of a source driver chip provided in an embodiment of the present application. The source driver chip can be connected to a timing controller (TCON) of a display device, see the following embodiment. The source driver chip is also called Source IC (Source Integrated Circuit) or Driver IC. Figure 1 As shown, the source driver chip 1100 includes a state detection module 1110 , a logic control module 1120 and a first mode control module 1130 .

[0028] The state detection module 1110 is used to detect whether the lock signal output by the source driver chip 1100 to the timing controller is switched from the first level to the second level.

[0029] The logic control module 1120 is used to: when the locking signal switches from the first level to the second level, control the first mode control module 1130 to turn on the first recognition mode and perform a first correctness check on the driving information of the image frame; and after the target condition is met, control the first mode control module 1130 to turn off the first recognition mode.

[0030] In an embodiment of the present application, the source driver chip 1100 can output a locking signal to the timing controller to indicate to the timing controller whether the source driver chip 1100 has successfully locked the clock signal from the timing controller. The locking signal is at the first level, indicating that the source driver chip 1100 has not yet locked or has not successfully locked the clock signal; the locking signal is at the second level, indicating that the source driver chip 1100 has successfully locked the clock signal, and the display device can work normally. Among them, the first level is different from the second level, and optionally, the first level is less than the second level, for example, the first level is a low level and the second level is a high level. The embodiment of the present application does not exclude the possibility that the first level is greater than the second level, for example, the first level is a high level and the second level is a low level. Usually, after the display device is powered on (Power On) and after the screen is abnormal and then returns to normal, the locking signal will switch from the first level to the second level.

[0031] The state detection module 1110 in the source driver chip 1100 can continuously detect the level state of the locking signal. In some embodiments, after the source driver chip 1100 is powered on, the state detection module 1110 starts to detect the level state of the locking signal. That is, the state detection module 1110 is used to continuously perform state detection on the locking signal after the source driver chip 1100 is powered on; wherein the state detection includes detecting whether the locking signal is switched from the first level to the second level and detecting whether the locking signal is switched from the second level to the first level. Optionally, the state detection module 1110 is used to: after the source driver chip 1100 is powered on, detect whether the locking signal is switched from the first level to the second level; after the locking signal is switched from the first level to the second level, detect whether the locking signal is switched from the second level to the first level; after the locking signal is switched from the second level to the first level, detect whether the locking signal is switched from the first level to the second level; and so on. In an embodiment of the present application, the status detection module 1110 can continuously detect the level state switching of the lock signal. When the lock signal is at the first level, it detects whether the lock signal switches from the first level to the second level; when the lock signal is at the second level, it detects whether the lock signal switches from the second level to the first level.

[0032] When the state detection module 1110 detects that the lock signal switches from the first level to the second level, the logic control module 1120 in the source driver chip 1100 controls the first mode control module 1130 to start the first recognition mode. The first recognition mode includes performing a first correctness check on the drive information of the image frame. In some embodiments, the drive information includes at least one of a data start instruction and a polarity indication instruction. The data start instruction is used to indicate the start display time of the image data, and the polarity indication instruction is used to indicate the drive polarity of the image data, and the drive polarity includes positive polarity and negative polarity. Exemplarily, Figure 2is a schematic diagram of at least part of the content contained in an image frame provided by an embodiment of the present application, and the meaning of each instruction in the image frame is as follows Figure 3 The driving information of the image frame may include Figure 2 and Figure 3 The CS instruction and CMD instruction shown in the figure include the data start instruction and the polarity indication information. Of course, the driving information of the image frame may also include other instructions, such as Figure 2 and Figure 3 The CE instructions shown in the embodiment of the present application are not limited to this.

[0033] In some embodiments, the logic control module 1120 is further used to control the first mode control module 1130 to start the first recognition mode for the first image frame when the lock signal is switched from the first level to the second level, so as to perform a first correctness check on the driving information of the first image frame. In some embodiments, the logic control module 1120 is further used to control the first mode control module 1130 to start the first recognition mode for the first row of data of the first image frame when the lock signal is switched from the first level to the second level, so as to perform a first correctness check on the first row of data of the first image frame. The first image frame refers to the first image frame output by the source driver chip 1100 after the lock signal is switched from the first level to the second level.

[0034] Of course, in actual applications, if the source driver chip 1100 detects that the locking signal switches from the first level to the second level, the first recognition mode can also be enabled for any one or more rows of data of the first image frame output by the source driver chip 1100 after the locking signal switches from the first level to the second level. For example, the first recognition mode is enabled for the second row of data of the first image frame, or the first recognition mode is enabled for the first row of data to the tenth row of data of the first image frame, and this is not limited to the embodiments of the present application. In addition, in actual applications, if the source driver chip 1100 detects that the locking signal switches from the first level to the second level, the first recognition mode can also be enabled for any one or more image frames output by the source driver chip 1100 after the locking signal switches from the first level to the second level. For example, the first recognition mode is enabled for the second image frame, or the first recognition mode is enabled for the first image frame to the third image frame. This is not limited to the embodiments of the present application.

[0035] After the source driver chip 1100 turns on the first identification mode, the source driver chip 1100 continuously detects whether the target condition is met. After the target condition is met, the logic control module 1120 in the source driver chip 1100 controls the first mode control module 1130 to turn off the first identification mode. In some embodiments, when the source driver chip 1100 turns on the first identification mode for the first row of data of the first image frame output by the source driver chip 1100 after the lock signal is switched from the first level to the second level, the logic control module 1120 in the source driver chip 1100 is further used to control the first mode control module 1130 to turn off the first identification mode after entering the line blanking period of the second row of data of the first image frame. The first image frame refers to the first image frame output by the source driver chip 1100 after the lock signal is switched from the first level to the second level.

[0036] The line blanking period can also be called the horizontal blanking (HBK) period, which refers to the time interval when the scanning point returns from the right edge of the image frame to the left edge during the scanning process to prepare for the start of a new line scan, which is used to ensure the correct display and synchronization of each line of data in the image frame. In the embodiment of the present application, the line blanking period of the second line of data may refer to the time interval when the first line of data is scanned and the second line of data is ready to be scanned, that is, the line blanking period of the second line of data may be located before the second line of data is scanned. After entering the line blanking period of the second line of data of the first image frame, the source driver chip 1100 turns off the first recognition mode, that is, the embodiment of the present application can only turn on the first recognition mode for the first line of data of the first image frame output by the source driver chip 1100 after the locking information is switched from the first level to the second level.

[0037] Of course, in practical applications, the target condition may also have other settings, and the target condition may be flexibly set according to the needs, and the embodiments of the present application do not limit this. For example, when the source driver chip 1100 turns on the first recognition mode for the first image frame output by the source driver chip 1100 after the locking signal is switched from the first level to the second level, the target condition may also be set to enter the second image frame output by the source driver chip 1100, that is, the source driver chip 1100 turns off the first recognition mode after entering the second image frame. For another example, the target condition may be set to the target on-time, and after the on-time of the first recognition mode reaches the target on-time, the source driver chip 1100 turns off the first recognition mode.

[0038] In addition to the first recognition mode, the source driver chip 1100 can also enable a second recognition mode. Figure 1As shown, the source driver chip 1100 further includes a second mode control module 1140. The logic control module 1120 is further used to control the second mode control module 1140 to start the second recognition mode after the source driver chip 1100 is powered on. The second recognition module includes performing a second correctness check on the image data of the image frame.

[0039] In some embodiments, the period of the first correctness check in the first recognition mode is less than the period of the second correctness check in the second recognition mode. For example, the first recognition mode may be a bit mode, and the second recognition mode may be a packet mode. In the first recognition mode, the first mode control module 1130 in the source driver chip 1100 performs a first correctness check on the driving information of the image frame with a period of 1UI, and in the second recognition mode, the second mode control module 1140 in the source driver chip 1100 performs a second correctness check on the image data of the image frame with a period of 9UI. Among them, 1UI refers to one unit period, and 9UI refers to nine unit periods. Generally, one unit period represents the time occupied by one bit of data, that is, one cycle of the clock. For example, the data size is 2G, and 1UI is the reciprocal of 2G. Of course, in practical applications, the period of the first correctness check on the driving information in the first recognition mode may also be greater than the period of the second correctness check on the image data in the second recognition mode. The embodiment of the present application is not limited to this.

[0040] In summary, in the embodiment of the present application, when the source driver chip detects that the locking signal switches from the first level to the second level, such as from a low level to a high level, the first recognition mode is turned on to check the correctness of the driving information of the image frame; after the target condition is met, the source driver chip turns off the first recognition mode and no longer checks the correctness of the driving information of the image frame until the locking signal switches from the first level to the second level again. In the embodiment of the present application, the first recognition mode is not in a continuous working state, but the first recognition mode is turned on when the level state of the locking signal switches, and then the first recognition mode is turned off after the target condition is met. The embodiment of the present application reduces the dynamic power consumption of the source driver chip through the working state control of the first recognition mode, thereby reducing the energy consumption of the display device. In addition, the embodiment of the present application can be implemented based on the existing display device, without adding new devices in the display device, and has high compatibility with the existing display device.

[0041] See also Figure 4 , Figure 4 : is a flow chart of a mode control method provided by an embodiment of the present application. The mode control method can be applied to a source driver chip of a display device, such as the above Figure 1The source driver chip shown is connected to the timing controller of the display device. Figure 4 As shown, the mode control method may include the following steps:

[0042] Step 410: when the lock signal output by the source driver chip to the timing controller switches from the first level to the second level, the first recognition mode is started to perform a first correctness check on the driving information of the image frame;

[0043] Step 420: After the target condition is met, turn off the first recognition mode.

[0044] In some embodiments, the step 410 includes: when the lock signal switches from the first level to the second level, starting the first recognition mode for the first image frame, wherein the first image frame is the first image frame output by the source driver chip after the lock signal switches from the first level to the second level.

[0045] In some embodiments, the above step 410 includes: when the lock signal switches from the first level to the second level, starting the first recognition mode for the first row of data of the first image frame; the above step 420 includes: after entering the row blanking period of the second row of data of the first image frame, turning off the first recognition mode.

[0046] In some embodiments, the mode control method further includes: after the source driver chip is powered on, continuously detecting the state of the lock signal, wherein the state detection includes detecting whether the lock signal switches from the first level to the second level and detecting whether the lock signal switches from the second level to the first level.

[0047] In some embodiments, the first level is a low level and the second level is a high level.

[0048] In some embodiments, the driving information includes at least one of a data start instruction and a polarity indication instruction, wherein the data start instruction is used to indicate the start display time of the image frame, and the polarity indication instruction is used to indicate the driving polarity of the image frame.

[0049] In some embodiments, the above-mentioned mode control method further includes: after the source driver chip is powered on, starting the second recognition mode and performing a second correctness check on the image data of the image frame.

[0050] In some embodiments, a period of the first correctness check is smaller than a period of the second correctness check.

[0051] In summary, in the embodiment of the present application, when the source driver chip detects that the locking signal switches from the first level to the second level, such as from a low level to a high level, the first recognition mode is turned on to check the correctness of the driving information of the image frame; after the target condition is met, the source driver chip turns off the first recognition mode and no longer checks the correctness of the driving information of the image frame until the locking signal switches from the first level to the second level again. In the embodiment of the present application, the first recognition mode is not in a continuous working state, but the first recognition mode is turned on when the level state of the locking signal switches, and then the first recognition mode is turned off after the target condition is met. The embodiment of the present application reduces the dynamic power consumption of the source driver chip through the working state control of the first recognition mode, thereby reducing the energy consumption of the display device. In addition, the embodiment of the present application can be implemented based on the existing display device, without adding new devices in the display device, and has high compatibility with the existing display device.

[0052] It should be understood that the above-mentioned mode control method is a method embodiment corresponding to the above-mentioned source driver chip. For a detailed description of the various steps in the above-mentioned mode control method and their beneficial effects, please refer to the embodiment of the above-mentioned source driver chip, which will not be elaborated here.

[0053] Below, the mode control method provided in the embodiment of the present application is introduced and explained with an example.

[0054] See also Figure 5 , Figure 5 is a flow chart of another mode control method provided in an embodiment of the present application. The mode control method can be applied to Figure 1 or Figure 6 The source driver chip 1100 is connected to the timing controller of the display device, and includes a state detection module 1110, a logic control module 1120, a first mode control module 1130 and a second mode control module 1140. Figure 6 As shown, the first mode control module 1130 and the second mode control module 1140 in the source driver chip 1100 input a digital voltage DVDD and output a digital signal. Figure 5 As shown, the mode control method may include the following steps 501 to 508.

[0055] Step 501 : Power on the source driver chip 1100 .

[0056] Step 502: The state detection module 1110 detects whether the lock signal switches from a low level to a high level. If yes, step 503 is executed, otherwise, step 502 is continued.

[0057] Step 503: The logic control module 1120 controls the first mode control module 1130 to turn on the bit mode (Bit mode) for the first row of data of the first image frame, and performs a first correctness check on the driving information of the first row of data. The first image frame refers to the first image frame output by the source driver chip 1100 after the lock signal is switched from a low level to a high level, and the driving information includes a CS instruction and a CMD instruction. The bit mode may refer to the above-mentioned first identification mode. In the bit mode, the first mode control module 1130 in the source driver chip 1100 performs a first correctness check on the driving information with a period of 1UI.

[0058] Step 504: After entering the line blanking period of the second line of data of the first image frame, the logic control module 1120 controls the first mode control module 1130 to turn off the bit mode.

[0059] Step 505: The state detection module 1110 detects whether the lock signal switches from a high level to a low level. If yes, step 502 is executed, otherwise, step 506 is continued. Step 505 can be executed simultaneously with step 503 or after step 504, which is not limited in the present embodiment.

[0060] Step 506: The logic control module 1120 controls the second mode control module 1140 to turn on the packet mode (Packet mode) to perform a second correctness check on the image data of the image frame. Step 506 may be performed after step 502 or after step 503, and this is not limited in the embodiment of the present application. The packet mode may be the above-mentioned second recognition mode. In the packet mode, the second mode control module 1140 in the source driver chip 1100 performs a second correctness check on the image data with a period of 9UI.

[0061] like Figure 7 As shown, in the related art, both the bit mode and the data packet mode are enabled for each row of data in the image frame. Figure 8 As shown, in the embodiment of the present application, when the locking signal is switched from a low level to a high level, the bit mode and the data packet mode are turned on for the first row of data of the first image frame output by the source driver chip 1100 after the locking signal is switched from a low level to a high level, and only the data packet mode is turned on and the bit mode is turned off for other row data in the first image frame and other image frames.

[0062] See also Fig. 9 , Fig. 9 is a schematic diagram of a display device provided in an embodiment of the present application. Fig. 9As shown, the display device 1000 includes a source driver chip 1100 and a timing controller 1200, and the source driver chip 1100 is connected to the timing controller 1200. Generally, a display device can be driven by multiple source driver chips 1100, and the embodiment of the application does not limit the number of source driver chips 1100 in the display device. Fig. 9 For the convenience of description, a source driver chip 1100 is taken as an example. For the steps performed by the source driver chip 1100, the modules included, and the beneficial effects that can be achieved, please refer to the following embodiments, which will not be described in detail here.

[0063] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0064] The above is a detailed introduction to a source driver chip, a mode control method and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A source driver chip connected to a timing controller, characterized in that: The source driver chip includes a state detection module, a logic control module and a first mode control module; wherein, The state detection module is used to detect whether the lock signal output by the source driver chip to the timing controller is switched from the first level to the second level; The logic control module is used for: When the locking signal switches from the first level to the second level, controlling the first mode control module to start a first recognition mode to perform a first correctness check on the driving information of the image frame; and After the target condition is met, the first mode control module is controlled to turn off the first recognition mode.

2. The source driver chip according to claim 1, characterized in that: The logic control module is also used to control the first mode control module to start the first recognition mode for a first image frame when the locking signal switches from the first level to the second level; wherein the first image frame refers to the first image frame output by the source driver chip after the locking signal switches from the first level to the second level.

3. The source driver chip according to claim 2, characterized in that: The logic control module is also used for: When the lock signal switches from the first level to the second level, for the first row of data of the first image frame, controlling the first mode control module to start the first recognition mode; as well as After entering a line blanking period of a second line of data of the first image frame, the first mode control module is controlled to turn off the first recognition mode.

4. The source driver chip according to claim 1, characterized in that: The status detection module is also used to continuously perform status detection on the lock signal after the source driver chip is powered on; wherein the status detection includes detecting whether the lock signal switches from the first level to the second level and detecting whether the lock signal switches from the second level to the first level.

5. The source driver chip according to claim 1, characterized in that: The first level is a low level, and the second level is a high level.

6. The source driver chip according to claim 1, characterized in that: The driving information includes at least one of a data start instruction and a polarity indication instruction; wherein the data start instruction is used to indicate a start display time of the image frame, and the polarity indication instruction is used to indicate a driving polarity of the image frame.

7. The source driver chip according to claim 1, characterized in that: The source driver chip also includes a second mode control module; The logic control module is further configured to control the second mode control module to start a second recognition mode after the source driver chip is powered on, so as to perform a second correctness check on the image data of the image frame.

8. The source driver chip according to claim 7, characterized in that: A period of the first correctness check is smaller than a period of the second correctness check.

9. A mode control method, applied to a source driver chip of a display device, wherein the source driver chip is connected to a timing controller of the display device, characterized in that: The mode control method comprises: When the lock signal output by the source driver chip to the timing controller switches from the first level to the second level, the first recognition mode is started to perform a first correctness check on the driving information of the image frame; After the target condition is met, the first recognition mode is turned off.

10. The mode control method according to claim 9, characterized in that: When the lock signal output by the source driver chip to the timing controller is switched from the first level to the second level, the first recognition mode is started to perform a first correctness check on the driving information of the image frame, including: When the locking signal switches from the first level to the second level, the first recognition mode is started for a first image frame; wherein the first image frame refers to the first image frame output by the source driver chip after the locking signal switches from the first level to the second level.

11. The mode control method according to claim 10, characterized in that: When the lock signal switches from the first level to the second level, starting the first recognition mode for the first image frame includes: When the lock signal switches from the first level to the second level, the first recognition mode is started for the first row of data of the first image frame; After the target condition is met, closing the first recognition mode includes: After entering a line blanking period of a second line of data of the first image frame, the first recognition mode is turned off.

12. The mode control method according to claim 9, characterized in that: The method further comprises: After the source driver chip is powered on, the state of the lock signal is continuously detected; wherein the state detection includes detecting whether the lock signal is switched from the first level to the second level and detecting whether the lock signal is switched from the second level to the first level.

13. The mode control method according to claim 9, characterized in that: The method further comprises: After the source driver chip is powered on, a second identification mode is started to perform a second correctness check on the image data of the image frame.

14. The mode control method according to claim 13, characterized in that: A period of the first correctness check is smaller than a period of the second correctness check.

15. A display device, characterized in that: The display device comprises the source driver chip according to any one of claims 1 to 8.

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