Display device, pixel circuit, and driving method thereof

Abstract

The application provides a display device, a pixel circuit and a driving method thereof. The method comprises: a first initialization circuit connected with a first node, a first voltage terminal, a first control signal terminal and an input terminal of a driving circuit; a data writing circuit connected with a data line, the first node and a second scanning signal terminal; a light emitting control circuit connected with the driving circuit, a second control signal terminal and a light emitting unit; the driving circuit connected with the first node, a second node, the first initialization circuit and the light emitting control circuit; and a compensation auxiliary circuit connected with the second node, a third scanning signal terminal and a second voltage terminal, used for writing a threshold voltage of the first node, a second voltage provided by the second voltage terminal and the second voltage into the second node under control of a third scanning signal provided by the third scanning signal terminal. The application compensates the threshold voltage of the driving transistor, thereby improving the display stability and consistency of the pixel circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device, a pixel circuit and a driving method thereof. BACKGROUND

[0002] Low temperature polysilicon active matrix organic light emitting diode (LTPS AMOLED) is popular in the market due to its high performance in small size devices. However, with the increasing demand of large size, high resolution display panels in the market, the traditional LTPS AMOLED technology faces a series of challenges. The uniformity problem, high equipment cost, complex production process and high cost of equipment upgrade of LTPS AMOLED in large size applications limit its further expansion in the large size display market.

[0003] Oxide thin film transistor (Oxide TFT) has better uniformity, better stability, lower leakage current and simpler production process than LTPS, especially the partial process of Oxide TFT can be used with amorphous silicon thin film transistor (a-Si TFT), and the cost of equipment upgrade is lower. At the same time, the uniformity of Oxide TFT is good, which can be used for high generation and large size flat panel display. However, Oxide TFT also faces some technical problems, such as threshold voltage (Vth) negative bias and insufficient carrier mobility, which affect its application effect in AMOLED pixel driving circuit. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a display device, a pixel circuit and a driving method thereof to solve or partially solve the above problems.

[0005] As an aspect of the present application, a pixel circuit for a display device is provided, characterized in that the pixel circuit comprises:

[0006] a first initialization circuit, connected with the first node, the first scan signal end, the first voltage end, the first control signal end and the input end of the driving circuit, for providing an initialization voltage for the first node under the control of the first scan signal provided by the first scan signal end, the first voltage provided by the first voltage end and the first control signal provided by the first control signal end;

[0007] a data writing circuit, connected with the data line, the first node and the second scan signal end, for writing the data signal provided by the data line into the first node under the control of the second scan signal provided by the second scan signal end;

[0008] The light emitting control circuit is connected with the driving circuit, the second control signal terminal and the light emitting unit, and is used for controlling the driving circuit and the light emitting unit to be turned on or turned off under the control of the second control signal provided by the second control signal terminal.

[0009] The driving circuit is connected with the first node, the second node, the first initialization circuit and the light emitting control circuit, and is used for driving the light emitting unit to emit light.

[0010] The compensation auxiliary circuit is connected with the second node, the third scan signal terminal and the second voltage terminal, and is used for writing the threshold voltage of the driving transistor in the driving circuit and the second voltage provided by the second voltage terminal into the first node and writing the second voltage into the second node under the control of the third scan signal provided by the third scan signal terminal.

[0011] As a second aspect of the present application, a driving method of a pixel circuit is provided, which is applied to the pixel circuit and includes:

[0012] In the first stage, the initialization circuit is used to provide the initialization voltage for the first node under the control of the first scan signal provided by the first scan signal terminal, the first voltage provided by the first voltage terminal and the first control signal provided by the first control signal terminal.

[0013] In the second stage, the data writing circuit and the initialization circuit are used to write the threshold voltage and the second voltage provided by the second voltage terminal into the first node and write the second voltage into the second node under the control of the third scan signal provided by the third scan signal terminal.

[0014] In the third stage, the data writing circuit is used to write the data signal provided by the data line into the first node under the control of the second scan signal provided by the second scan signal terminal.

[0015] In the fourth stage, the driving circuit is used to drive the light emitting unit to emit light under the control of the first control signal provided by the first control signal terminal and the second control signal provided by the second control signal terminal.

[0016] As a third aspect of the present application, a display device is provided, which includes the pixel circuit.

[0017] It can be seen from the above that the display device, the pixel circuit and the driving method thereof provided by the application, the pixel circuit comprises a first initialization circuit, a data writing circuit, a light emitting control circuit, a driving circuit and a compensation auxiliary circuit. In the initialization stage, the first initialization circuit can provide an initialization voltage, ensuring that the pixel circuit is in an initialization state at the beginning of each display period. In the data writing stage, the compensation auxiliary circuit writes a threshold voltage to the first node and an initialization voltage to the second node, the data writing circuit writes a data signal to the first node, and the driving circuit compensates the threshold voltage of the driving transistor according to the voltages of the first node and the second node. In the light emitting stage, the light emitting control circuit adjusts the brightness or the switching state of the light emitting unit according to the driving current provided by the driving circuit, solves the problem of poor display effect caused by different threshold voltages, and improves the display stability and consistency of the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the application or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0019] Figure 1 A structural schematic diagram of a pixel circuit provided by an embodiment of the application is shown in the figure.

[0020] Figure 2 A structural schematic diagram of another pixel circuit provided by an embodiment of the application is shown in the figure.

[0021] Figure 3 A working timing diagram of a pixel circuit provided by an embodiment of the application is shown in the figure.

[0022] Figure 4A A structural schematic diagram of another pixel circuit provided by an embodiment of the application is shown in the figure.

[0023] Figure 4B A structural schematic diagram of another pixel circuit provided by an embodiment of the application is shown in the figure.

[0024] Figure 4C A structural schematic diagram of another pixel circuit provided by an embodiment of the application is shown in the figure.

[0025] Figure 4D A structural schematic diagram of another pixel circuit provided by an embodiment of the application is shown in the figure.

[0026] Figure 5 A structural schematic diagram of another pixel circuit provided by an embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to specific examples and drawings. Obviously, the described examples are only a part of the examples of the present application, but not all the examples of the present application. Based on the examples in the present application, all other examples obtained by those skilled in the art without creative effort should fall into the scope of the present application.

[0028] It should be noted that the words "exemplarily" or "for example" in the embodiments of the present application are used to represent as an example, illustration or description. Any example or design scheme described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other examples or design schemes. In fact, the words "exemplarily" or "for example" are used to present the related concept in a specific way. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the general meaning understood by those skilled in the art in the field of the present application.

[0029] It should be noted that the examples in the present application and the features in the examples can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the examples. In addition, the transistors adopted in all the examples of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors adopted in the examples of the present application are mainly switching transistors according to the role in the circuit. Since the source and the drain of the switching transistor used here are symmetrical, the source and the drain can be interchangeable. In the examples of the present application, the source is referred to as a signal input end, and the drain is referred to as a signal output end. According to the form in the drawings, the middle end of the transistor is defined as a control electrode, which can also be referred to as a gate, a first electrode as a source, and a second electrode as a drain. In addition, the switching transistor adopted in the examples of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level (i.e., for the P-type transistor, the transistor is turned on when the potential of the signal received by the gate is at a low potential, and the transistor is turned off when the potential of the signal received by the gate is at a high potential, i.e., the low potential is an effective potential, and the high potential is an ineffective potential), and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level (i.e., for the N-type transistor, the transistor is turned on when the potential of the signal received by the gate is at a high potential, and the transistor is turned off when the potential of the signal received by the gate is at a low potential, i.e., the high potential is an effective potential, and the low potential is an ineffective potential).

[0030] Figure 1 A structural schematic diagram of a pixel circuit provided by the embodiments of the present application is shown in FIG. 1. Figure 1As shown, in some embodiments, the pixel circuit can include: a first initialization circuit 01, a data writing circuit 02, a light emitting control circuit 03, a driving circuit 04, a compensation auxiliary circuit 05, a light emitting unit 06, a storage unit 07, and a second initialization circuit 08. Optionally, the light emitting unit 06 can be a light emitting diode (LED), an organic electroluminescent diode (OLED), a quantum dot light emitting diode (QLED), etc. Exemplarily, the light emitting unit 06 can be an OLED.

[0031] In some embodiments, the first initialization circuit 01 is connected with the first node N1, the first scan signal end S1, the first voltage end Vdd, the first control signal end EM1, and the input end of the driving circuit 04, for providing an initialization voltage for the first node N1 under the control of the first scan signal provided by the first scan signal end S1, the first voltage provided by the first voltage end Vdd, and the first control signal provided by the first control signal end EM1.

[0032] Optionally, the first initialization circuit 01 further includes: a compensation sub-circuit connected with the first node N1, the first scan signal end S1, and the input end of the driving circuit 04, for writing the threshold voltage of the driving transistor M1 in the driving circuit 04 for the first node N1 under the control of the first scan signal provided by the first scan signal end S1; and a light emitting control sub-circuit connected with the first voltage end Vdd and the input end of the driving circuit 04, for controlling the on-off of the first voltage end Vdd and the input end of the driving circuit 04 under the control of the first control signal provided by the first control signal end EM1.

[0033] Optionally, the compensation sub-circuit includes a first transistor T1, the control end of the first transistor T1 is connected with the first scan signal end S1, the first end of the first transistor T1 is connected with the first node N1, and the second end of the first transistor T1 is connected with the input end of the driving circuit 04; and the light emitting control sub-circuit includes a second transistor T2, the control end of the second transistor T2 is connected with the first control signal end EM1, the first end of the second transistor T2 is connected with the first voltage end Vdd, and the second end of the second transistor T2 is connected with the input end of the driving circuit 04.

[0034] In some embodiments, the data writing circuit 02 is connected with the data line DATA, the first node N1, and the second scan signal end S2, for writing the data signal provided by the data line DATA for the first node under the control of the second scan signal provided by the second scan signal end S2.

[0035] Optionally, the data writing circuit 02 includes a third transistor T3, the control end of the third transistor T3 is connected with the second scan signal end S2, the first end of the third transistor T3 is connected with the data line DATA, and the second end of the third transistor T3 is connected with the first node N1.

[0036] In some embodiments, the light emitting control circuit 03 is connected with the driving circuit 04, the second control signal terminal EM2 and the light emitting unit 06, and is configured to control the driving circuit 04 and the light emitting unit 06 under the control of the second control signal provided by the second control signal terminal EM2.

[0037] Optionally, the light emitting control circuit 03 comprises a fourth transistor T4, a control terminal of the fourth transistor T4 is connected with the second control signal terminal EM2, a first terminal of the fourth transistor T4 is connected with an output terminal of the driving circuit 04, and a second terminal of the fourth transistor T4 is connected with the light emitting unit 06.

[0038] In some embodiments, the driving circuit 04 is connected with the first node N1, the second node N2, the first initialization circuit 01 and the light emitting control circuit 03, and is configured to drive the light emitting unit 06 to emit light.

[0039] Optionally, the driving circuit 04 comprises a driving transistor M1, a control terminal of the driving transistor M1 is connected with the first node N1, a first terminal of the driving transistor M1 is connected with the first initialization circuit 01, and a second terminal of the driving transistor M1 is connected with the light emitting control circuit 03.

[0040] In some embodiments, the compensation auxiliary circuit 05 is connected with the second node N2, the third scan signal terminal S3 and the second voltage terminal Vd, and is configured to write the threshold voltage Vth of the driving transistor M1 and the second voltage provided by the second voltage terminal Vd into the first node N1 and write the second voltage into the second node N2 under the control of the third scan signal provided by the third scan signal terminal S3.

[0041] Optionally, the compensation auxiliary circuit 05 comprises a fifth transistor T5, a control terminal of the fifth transistor T5 is connected with the third scan signal terminal S3, a first terminal of the fifth transistor T5 is connected with the second node N2, and a second terminal of the fifth transistor T5 is connected with the second voltage terminal Vd.

[0042] In some embodiments, the storage circuit 07 is connected with the first node N1 and the second voltage terminal Vd, and is configured to store the potential of the first node N1.

[0043] In some embodiments, an output terminal of the light emitting control circuit 03 is connected with the third node N3, and the pixel circuit further comprises a second initialization circuit 08 connected with the third node N3, the third scan signal terminal S3 and a second initialization signal terminal Vinit1, and configured to write the second initialization signal provided by the second initialization signal terminal Vinit1 into the third node N3 under the control of the second scan signal provided by the second scan signal terminal S2.

[0044] Optionally, the second initialization circuit 08 further comprises a sixth transistor T6, a control terminal of the sixth transistor T6 is connected to the second scan signal terminal S2, a first terminal of the sixth transistor T6 is connected to the third node N3, and a second terminal of the sixth transistor T6 is connected to the second initialization signal terminal Vinit1.

[0045] In some embodiments, in combination with Figure 2 As shown in another pixel circuit, the first initialization circuit 01 can further comprise an initialization sub-circuit connected to the first node N1, the first initialization signal terminal Vinit2, the second scan signal terminal S2 and the compensation sub-circuit T1, for writing the first initialization signal provided by the first initialization signal terminal Vinit2 into the first node N1 under the control of the second scan signal provided by the second scan signal terminal S2. In this way, the voltage size and timing of the first initialization signal can be adjusted according to the actual situation when the threshold voltage Vth of the driving transistor M1 appears negative bias, thereby improving the problem of display failure caused by the negative bias of the threshold voltage Vth of the driving transistor M1.

[0046] Optionally, as Figure 2 shown, the initialization sub-circuit can further comprise a seventh transistor T7, a control terminal of the seventh transistor T7 is connected to the second scan signal terminal S2, a first terminal of the seventh transistor T7 is connected to the first initialization signal terminal Vinit2, and a second terminal of the seventh transistor T7 is connected to the first node N1. And not limited by the Vdd voltage. In this way, the first voltage is isolated by the seventh transistor T7, so that the initialization of the first node N1 can not be limited by the first voltage, and the initialization voltage of the first node N1 can be adjusted by the first initialization signal. When the threshold voltage Vth of the driving transistor M1 appears negative bias, it can improve the effect of display failure caused by the negative bias of the threshold voltage Vth of the driving transistor M1.

[0047] In some embodiments, as Figure 2 shown, the driving circuit 04 comprises a first control terminal and a second control terminal, the first control terminal is connected to the first node N1, and the second control terminal is connected to the third control signal terminal VBG, and the third control signal terminal VBG is used to provide a third control signal for the driving circuit 04 to improve the carrier mobility of the driving transistor M1. In this way, by adding a third control signal to the driving circuit 04, the carrier mobility of the driving transistor M1 can be improved by adjusting the control voltage provided by the third control signal to the driving circuit 04.

[0048] Optionally, the driving transistor M1 is a double-gate structure, and the two gates of the double-gate structure are respectively used to provide the first control terminal and the second control terminal. In this way, by adopting the double-gate structure, the carrier mobility of the driving transistor M1 can be more easily adjusted by changing the control voltage of the second control terminal. In particular, when the driving transistor M1 is an oxide transistor, the carrier mobility of the oxide transistor can be improved by this method, so that it is more suitable for large-size display devices.

[0049] As an optional embodiment, the driving transistor M1 of the double-gate structure can set the newly added gate as the back gate of the driving transistor M1, that is, the original gate of the driving transistor M1 adopts a top gate, and the newly added back gate is located on the side of the active layer of the driving transistor M1 opposite to the top gate. Such a design can enable the control signal to be applied from both sides of the active layer, thereby further improving the carrier mobility.

[0050] In some embodiments, at least one of the driving transistor M1, the first transistor T1 to the seventh transistor T7 can be connected in parallel with one or more auxiliary transistors, thereby improving the response rate of the pixel circuit.

[0051] In summary, the pixel circuit provided by the embodiments of the present disclosure includes a first initialization circuit, a data writing circuit, a light-emitting control circuit, a driving circuit, and a compensation auxiliary circuit. In the initialization stage, the first initialization circuit can provide an initialization voltage, ensuring that the pixel circuit is in an initialized state at the beginning of each display period. Then, in the data writing stage, the compensation auxiliary circuit writes a threshold voltage to the first node and an initialization voltage to the second node, the data writing circuit writes a data signal to the first node, and the driving circuit compensates for the threshold voltage of the driving transistor according to the voltages of the first node and the second node. In the light-emitting stage, the light-emitting control circuit adjusts the brightness or switching state of the light-emitting unit according to the driving current provided by the driving circuit, thereby solving the problem of poor display effect caused by different threshold voltages and improving the display stability and consistency of the pixel circuit.

[0052] The working process of the pixel circuit in Figure 3 will be described in detail below with reference to the working timing diagram of the pixel circuit shown in Figure 1 , where the above-mentioned transistors are N-type transistors, and the conduction level is high.

[0053] As shown in Figure 4A and Figure 3 , stage 1: input high-level signals to the first control signal end EM1 and the first scan signal end S1, and input low-level signals to the second control signal end EM2, the second scan signal end S2, and the third scan signal end S3.

[0054] In some embodiments, in the first stage, the initialization circuit is used to provide the initialization voltage for the first node N1 under the control of the first scan signal provided by the first scan signal terminal S1, the first voltage provided by the first voltage terminal Vdd and the first control signal provided by the first control signal terminal EM1, at this time the first node is charged to the first voltage terminal Vdd.

[0055] As shown in Figure 4B and Figure 3 , stage 2: high level signals are input to the first scan signal terminal S1 and the third scan signal terminal S3, and low level signals are input to the first control signal terminal EM1, the second control signal terminal EM2 and the second scan signal terminal S2.

[0056] In some embodiments, in the second stage, the data write circuit and the initialization circuit are used to write the threshold voltage for the first node N1 and the second voltage provided by the second voltage terminal Vd for the second node N2 under the control of the third scan signal provided by the third scan signal terminal S2, that is, at this time the first node voltage is Vd+Vth, and the second node voltage is Vd, and the second initialization signal provided by the second initialization signal terminal Vinit1 is written for the third node N3 under the control of the second scan signal provided by the second scan signal terminal S2.

[0057] As shown in Figure 4C and Figure 3 , stage 3: high level signals are input to the second scan signal terminal S2 and the third scan signal terminal S3, and low level signals are input to the first scan signal terminal S1, the first control signal terminal EM1 and the second control signal terminal EM2.

[0058] In some embodiments, in the third stage, the data write circuit is used to write the data signal provided by the data line DATA for the first node under the control of the second scan signal provided by the second scan signal terminal S2, at this time the first node voltage is Vd+Vth+Vdata, the second node voltage is Vd, and the voltage difference (Vgs voltage) from the gate to the source of the driving transistor M1 is the voltage difference between the N1 and N2 nodes, that is, Vgs=(Vdata+Vth+Vd)-Vd=Vdata+Vth.

[0059] As shown in Figure 4D and Figure 3 , stage 4: high level signals are input to the first control signal terminal EM1 and the second control signal terminal EM2, and low level signals are input to the first scan signal terminal S1, the second scan signal terminal S2 and the third scan signal terminal S3.

[0060] In some embodiments, in the fourth stage, the light emitting unit is driven to emit light by the driving circuit under the control of the first control signal provided by the first control signal terminal EM1 and the second control signal provided by the second control signal terminal EM2, and Vgs is stabilized, and the driving current is:

[0061]

[0062] wherein K is a parameter related to the mobility of the transistor.

[0063] By bringing the Vgs voltage in stage three into the equation, the driving current is:

[0064]

[0065] As can be seen, the threshold voltage Vth has been cancelled in the calculation formula of the driving current, that is, the luminance of the light emitting unit will no longer be affected by the change of the threshold voltage of the driving transistor.

[0066] Embodiments of the present disclosure provide a pixel circuit, which comprises a first initialization circuit, a data writing circuit, a light emitting control circuit, a driving circuit and a compensation auxiliary circuit. In the initialization stage, the first initialization circuit can provide an initialization voltage, ensuring that the pixel circuit is in a known state at the beginning of each display period. Then, in the data writing stage, the threshold voltage is written to the first node by the compensation auxiliary circuit, and the initialization voltage is written to the second node, the data signal is written to the first node by the data writing circuit, and the driving circuit compensates the threshold voltage of the driving transistor according to the voltages of the first node and the second node. In the light emitting stage, the light emitting control circuit adjusts the luminance or the switching state of the light emitting unit according to the driving current provided by the driving circuit, solving the problem of poor display effect caused by different threshold voltages, thereby improving the display stability and consistency of the pixel circuit.

[0067] In some embodiments, Figure 1 The first initialization circuit in the first initialization circuit can also be as shown in part ① of Figure 2 The first initialization circuit can be increased in the first initialization circuit, and the first initialization signal provided by the first initialization signal terminal Vinit2 can be written to the first node N1 under the control of the second scan signal provided by the second scan signal terminal S2, that is, the initialization voltage is applied to the first node. The voltage size and timing of the first initialization signal terminal can be adjusted according to the actual situation, and is not limited by the voltage of the first voltage terminal Vdd. In other words, when the negative bias is serious, the first node can be initialized by adjusting the first initialization signal terminal Vinit2 to improve the negative bias problem.

[0068] In some embodiments, Figure 1 The driving circuit in the driving circuit can also be as shown in Figure 2As shown in part ②, a back gate structure is added in the driving transistor M1, that is, the driving transistor M1 is a double-gate structure, thereby introducing an additional third control signal terminal VBG, and the carrier mobility of the driving transistor M1 can be improved by increasing the gate voltage of the driving circuit.

[0069] In some embodiments, as shown in Figure 5 any pixel circuit provided by the present application can be connected in parallel with one or more transistors (for example, Figure 5 the fourth transistor T4 in FIG. 4 is connected in parallel with an auxiliary transistor), so as to improve the response rate.

[0070] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than those described above and still achieve desirable results. In addition, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order, to achieve the desired results. In certain implementations, multitasking and parallel processing can be advantageous.

[0071] Based on the same inventive concept, the present application also provides a display device corresponding to any of the above-mentioned embodiments.

[0072] Optionally, the display device provided by the embodiments of the present application can include a display, a mobile phone, a television, a notebook computer, and / or a navigator, etc. Other essential components of the display device are understood by those skilled in the art and will not be described here.

[0073] It should be understood that the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implying the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features.

[0074] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary and is not intended to limit the scope of the present application (including claims) to these examples; the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the aspects of the embodiments of the present application as described above. In order to be brief, they are not provided in detail.

[0075] Embodiments of the present application are intended to embrace all such alterations, modifications, and variations that fall within the broad scope of the appended claims. Accordingly, any one or more features of a given embodiment are intended to be illustrative only and not limiting of the scope of the application.

Claims

1. A pixel circuit for a display device, characterized in that: The pixel circuit comprises: a first initialization circuit (01) connected to a first node (N1), a first scan signal terminal (S1), a first voltage terminal (Vdd), a first control signal terminal (EM1), and an input terminal of a driving circuit, and configured to provide an initialization voltage to the first node (N1) under the control of a first scan signal provided by the first scan signal terminal (S1), a first voltage provided by the first voltage terminal (Vdd), and a first control signal provided by the first control signal terminal (EM1); a data writing circuit (02) connected to a data line (DATA), the first node (N1) and a second scanning signal terminal (S2), and configured to write a data signal provided by the data line (DATA) into the first node under the control of a second scanning signal provided by the second scanning signal terminal (S2); a light emitting control circuit (03), connected to the driving circuit, the second control signal terminal (EM2) and the light emitting unit (06), and configured to control the on / off switching of the driving circuit (04) and the light emitting unit (06) under the control of a second control signal provided by the second control signal terminal (EM2); The driving circuit (04) is connected to the first initialization circuit via the first node (N1) and to the light-emitting control circuit via the second node (N2), and is used to drive the light-emitting unit (06) to emit light; a compensation auxiliary circuit (05), connected to the second node (N2), a third scan signal terminal (S3) and a second voltage terminal (Vd), for writing the threshold voltage of the driving transistor (M1) in the driving circuit (04) and the second voltage provided by the second voltage terminal (Vd) into the first node (N1) under the control of a third scan signal provided by the third scan signal terminal (S3), and for writing the second voltage into the second node (N2); In which, in the initialization stage, the threshold voltage is written to the first node and the initialization voltage is written to the second node through the compensation auxiliary circuit; in the data writing stage, the data signal is written to the first node through the data writing circuit, and the driving circuit compensates for the threshold voltage of the driving transistor according to the voltages of the first node and the second node.

2. The pixel circuit according to claim 1, wherein: The first initialization circuit further comprises: a compensation subcircuit connected to the first node (N1), the first scan signal terminal (S1) and the input terminal of the drive circuit, and configured to write the threshold voltage of the drive transistor (M1) in the drive circuit into the first node (N1) under the control of the first scan signal provided by the first scan signal terminal (S1); A light emitting control subcircuit is connected to the first voltage terminal (Vdd) and the input terminal of the driving circuit, and is used to control the on / off of the first voltage terminal (Vdd) and the input terminal of the driving circuit under the control of a first control signal provided by the first control signal terminal (EM1).

3. The pixel circuit according to claim 2, wherein: The first initialization circuit further includes: An initialization subcircuit is connected to the first node (N1), the first initialization signal terminal (Vinit2), the second scan signal terminal (S2) and the compensation subcircuit, and is used to write the first initialization signal provided by the first initialization signal terminal (Vinit2) to the first node (N1) under the control of the second scan signal provided by the second scan signal terminal (S2).

4. The pixel circuit according to claim 1, wherein: The driving circuit (04) comprises a first control terminal and a second control terminal, the first control terminal being connected to the first node (N1), the second control terminal being connected to a third control signal terminal (VBG), the third control signal terminal (VBG) being used to provide a third control signal to the driving circuit to improve the carrier mobility of the driving transistor (M1).

5. The pixel circuit according to claim 4, wherein: The driving transistor (M1) has a dual-gate structure, and the dual-gate structure provides the first control terminal and the second control terminal.

6. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: A storage circuit (07) is connected to the first node (N1) and the second voltage terminal (Vd), and is used to store the potential of the first node (N1).

7. The pixel circuit according to claim 1, wherein: The output end of the light emitting control circuit (03) is connected to a third node (N3); The pixel circuit further includes: A second initialization circuit (08) is connected to the third node (N3), the third scan signal terminal (S3) and the second initialization signal terminal (Vinit1), and is used to write the second initialization signal provided by the second initialization signal terminal (Vinit1) to the third node (N3) under the control of the second scan signal provided by the second scan signal terminal (S2).

8. The pixel circuit according to claim 2, wherein: The compensation sub-circuit comprises a first transistor (T1), a control terminal of the first transistor (T1) is connected to the first scanning signal terminal (S1), a first terminal of the first transistor (T1) is connected to the first node (N1), and a second terminal of the first transistor (T1) is connected to the input terminal of the driving circuit (04); and / or The light emitting control subcircuit comprises a second transistor (T2), a control end of the second transistor (T2) is connected to the first control signal end (EM1), a first end of the second transistor (T2) is connected to the first voltage end (Vdd), and a second end of the second transistor (T2) is connected to the input end of the driving circuit (04).

9. The pixel circuit according to claim 1, wherein: The data writing circuit (02) comprises a third transistor (T3), a control end of the third transistor (T3) is connected to the second scanning signal end (S2), a first end of the third transistor (T3) is connected to the data line (DATA), and a second end of the third transistor (T3) is connected to the first node (N1); and / or The light emitting control circuit (03) comprises a fourth transistor (T4), a control terminal of the fourth transistor (T4) is connected to the second control signal terminal (EM2), a first terminal of the fourth transistor (T4) is connected to the output terminal of the driving circuit (04), and a second terminal of the fourth transistor (T4) is connected to the light emitting unit (06); and / or The driving circuit comprises the driving transistor (M1), the control end of the driving transistor (M1) is connected to the first node (N1), the first end of the driving transistor (M1) is connected to the first initialization circuit (01), and the second end of the driving transistor (M1) is connected to the light emitting control circuit (03); and / or The compensation auxiliary circuit (05) comprises a fifth transistor (T5), a control end of the fifth transistor (T5) being connected to the third scanning signal end (S3), a first end of the fifth transistor (T5) being connected to the second node (N2), and a second end of the fifth transistor (T5) being connected to the second voltage end (Vd).

10. The pixel circuit according to claim 7, wherein: The second initialization circuit (08) comprises a sixth transistor (T6), a control end of the sixth transistor (T6) is connected to the second scan signal end (S2), a first end of the sixth transistor (T6) is connected to the third node (N3), and a second end of the sixth transistor (T6) is connected to the second initialization signal end (Vinit1).

11. The pixel circuit according to claim 3, wherein: The initialization sub-circuit comprises a seventh transistor (T7), a control end of the seventh transistor (T7) is connected to the second scan signal end (S2), a first end of the seventh transistor (T7) is connected to the first initialization signal end (Vinit2), and a second end of the seventh transistor (T7) is connected to the first node (N1).

12. The pixel circuit according to any one of claims 1 to 11, wherein: The pixel circuit includes a plurality of transistors, and the pixel circuit further includes one or more auxiliary transistors arranged in parallel with at least one of the plurality of transistors.

13. A method for driving a pixel circuit, characterized in that: Applied to the pixel circuit according to any one of claims 1 to 12, the method comprising: In a first stage, an initialization circuit is used to provide an initialization voltage to a first node (N1) under the control of a first scan signal provided by a first scan signal terminal (S1), a first voltage provided by a first voltage terminal (Vdd), and a first control signal provided by a first control signal terminal (EM1); In the second stage, under the control of the third scan signal provided by the third scan signal terminal (S3), a threshold voltage and a second voltage provided by the second voltage terminal (Vd) are written to the first node (N1) using the data writing circuit and the initialization circuit, and the second voltage is written to the second node (N2); In the third stage, the data signal provided by the data line (DATA) is written into the first node using the data writing circuit under the control of the second scanning signal provided by the second scanning signal terminal (S2); In the fourth stage, under the control of the first control signal provided by the first control signal terminal (EM1) and the second control signal provided by the second control signal terminal (EM2), the driving circuit is used to drive the light-emitting unit to emit light.

14. A display device, characterized in that: The pixel circuit comprises the pixel circuit according to any one of claims 1 to 12.

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