Memory sensing circuit based on unconventional counter and / or multiple reference voltages

Abstract

The present disclosure provides a memory sensing circuit including: a sensing circuit configured to sense a difference between a first current and a second current on a selected bit line of a memory cell array and generate an output of the bit line according to the difference; and a globally programmable unconventional counter configured to continuously provide a count value to each of the sensing circuits dependent on a clock signal, where each of the sensing circuits comprises: (i) a local detector circuit configured to detect a voltage (Vc) generated in accordance with the difference; and (ii) a reference voltage selector configured to receive a reference voltage from a source and to select a single reference voltage (Vref), and wherein each sensing circuit generates an output according to: (i) a difference between Vc and Vref; and (ii) a stored count value received from the counter.

Description

Technical Field

[0001] The present disclosure relates to local memory sensors (e.g., local sensing circuits of in-memory computing devices) using global non-conventional counters and / or global multiple reference voltages. More specifically, the present disclosure relates to in-memory computing for performing in-memory computing (CIM) operations that implement memory sensors that share global non-conventional counters and / or global multiple reference voltages (as opposed to global conventional counters and / or global fixed reference voltages). Background Art

[0002] Conventional compute in memory (CIM) components that perform compute in memory (CIM) operations implement thousands of different sensors (e.g., local sensing circuits) to detect analog currents and / or voltages on bit lines of a memory array. The local sensing circuits may add or subtract currents sensed across multiple pairs of selected bit lines (or a single bit line). For example, the local sensing circuit may add two currents sensed on two bit lines and / or may subtract one current sensed on the two bit lines from another current sensed on the two bit lines to provide an analog output current value. The local sensing circuit may further convert the analog output value into a digital signal that may be used by other portions of the compute in memory component. For example, each different local sensing circuit may include (i) a current / voltage manipulator for detecting the difference between the current / voltage on a pair of selected bit lines (or a single bit line) (e.g., addition or subtraction of current / voltage values) to provide an analog current or voltage measurement; (ii) a converter or detector for converting the analog measurement into a digital signal; and (iii) a storage device, such as a latch or a flip-flop, which can store a value triggered by the output of the converter / detector (e.g., a counter value) and provide a data output.

[0003] A problem with conventional in-memory computing components is that the time it takes for the internal circuitry of a local sensing circuit to reach sufficient current or voltage values ​​for triggering storage of a value (e.g., a counter value) varies greatly based on the current and / or voltage received from the pair of selected bit lines (or a single bit line). As such, lower currents and / or voltages may result in the internal circuitry requiring more time to reach the current and / or voltage values ​​necessary to trigger storage of a value (e.g., a counter value). Therefore, it is desirable to provide an in-memory computing device or other type of computing device that can account for the varying time intervals it takes for the internal circuitry to reach the current and / or voltage values ​​necessary to trigger storage of a value (e.g., a counter value). Summary of the invention

[0004] The disclosed technology provides a circuit and method for sensing current in a bit line of a memory cell array.

[0005] In an embodiment, a memory sensing circuit is provided, the memory sensing circuit comprising: a memory cell array including a plurality of bit lines and a plurality of word lines; a sensing circuit configured to sense a difference between a first current and a second current on a corresponding bit line of a selected bit line (or a plurality of selected pairs of bit lines) and generate an output of the selected bit line according to the difference; and a global programmable non-regular counter configured to continuously provide a count value to each of the sensing circuits in dependence on a clock signal. Each of the sensing circuits may include: (i) a local detector circuit configured to detect a voltage (V c ) for detection; and (ii) a reference voltage selector configured to receive one or more reference voltages from a global dynamic voltage reference source and select a single reference voltage (V ref ), and each of the sensing circuits generates an output depending on: (i) the detected voltage (V c ) and the selected single reference voltage (V ref ) between; and (ii) a stored count value received from a globally programmable non-regular counter, the count value being dependent on the detected voltage (V c ) and the selected single reference voltage (V ref ) and is stored.

[0006] In yet another embodiment, the reference voltage selector is a multiplexer that selects a single reference voltage (V ref ).

[0007] In another embodiment, the one or more switching signals are received from a globally programmable non-regular counter.

[0008] In an embodiment, the one or more switching signals are configured to select a single reference voltage (V ref ): (i) the operating conditions of the circuit; (ii) the timing scheme of the counter values ​​provided by the globally programmable non-regular counter; (iii) the location of the sensing circuit relative to the global dynamic voltage reference source; and (iv) the predefined level of the sensing current.

[0009] In yet another embodiment, the one or more reference voltages include at least four reference voltages.

[0010] In another embodiment, a global dynamic voltage reference source generates the one or more reference voltages dependent on at least one of: (i) operating conditions of the circuit; and (ii) a position of the sensing circuit relative to the global dynamic voltage reference source.

[0011] In an embodiment, the local detector circuit is configured to be dependent on the detected voltage (V c ) and the selected single reference voltage (V ref ) to generate a trigger signal.

[0012] In yet another embodiment, each of the sensing circuits includes a storage device configured to store a specific count value provided by the global programmable non-regular counter, and storing the specific count value is executable in dependence on a trigger signal.

[0013] In another embodiment, the local detector circuit includes a comparator configured to (i) detect the voltage (V c ) and the selected single reference voltage (V ref ) for comparison; and (ii) due to the detected voltage (V c ) reaches or exceeds the selected single reference voltage (V ref ) to generate a trigger signal.

[0014] In an embodiment, each of the sensing circuits comprises: a current manipulator circuit configured to sense a difference between a first sensing current (I0) and a second sensing current (I1) and output a current (I cell ); and a current mirror selector circuit system configured to receive a current (I cell ) and selecting one or more current mirrors from a plurality of current mirrors, the selected one or more current mirrors receiving the current (I cell ) to provide the detected voltage (V c ).

[0015] In yet another embodiment, the current mirror selector circuitry is configured to select the one or more current mirrors in dependence on one or more switching signals.

[0016] In another embodiment, the one or more switching signals are received from a globally programmable non-regular counter.

[0017] In an embodiment, the one or more switching signals are configured to select the one or more current mirrors in dependence on at least one of: (i) an operating condition of the circuit; (ii) a timing scheme of a counter value provided by a globally programmable non-regular counter; (iii) a position of the sensing circuit relative to a global dynamic voltage reference source; and (iv) a predefined level of the sensing current.

[0018] In yet another embodiment, each of the sensing circuits includes a capacitor configured to receive a current (I cell ), depends on the received current (I cell ) to store charge and to detect the voltage (V c ) is provided to a local detector circuit, which triggers the storage of a count value received from a global programmable non-regular counter.

[0019] In another embodiment, each of the sensing circuits includes: a plurality of capacitors; and a capacitor selector circuit system configured to select one or more capacitors from the plurality of capacitors, wherein the selected one or more capacitors are configured to receive a current (I cell ), depends on the received current (I cell ) to store charge and generate the detected voltage (V c ) is provided to a local detector circuit, which triggers the storage of a count value received from a global programmable non-regular counter.

[0020] In an embodiment, a capacitor selector circuitry selects the one or more capacitors in dependence on one or more switching signals.

[0021] In yet another embodiment, the one or more switching signals are received from a globally programmable non-regular counter.

[0022] In another embodiment, the one or more switching signals are configured to select the one or more current mirrors in dependence on at least one of: (i) operating conditions of the circuit; (ii) a timing scheme of counter values ​​provided by a globally programmable non-regular counter; (iii) a position of the sensing circuit relative to a global dynamic voltage reference source; and (iv) a predefined level of the sensing current.

[0023] In an embodiment, a memory sensing circuit is provided, comprising: a sensing circuit configured to sense a difference between a first current and a second current on a corresponding bit line among selected bit lines of a memory cell array and generate an output of the selected bit line according to the difference, wherein each sensing circuit in the sensing circuit comprises: (i) a local detector circuit configured to sense a voltage (V c ) for detection; and (ii) a reference voltage selector configured to receive one or more reference voltages from a global voltage reference source and select a single reference voltage (V ref ), and each of the sensing circuits generates an output dependent on: (i) a detected voltage (V c) and the selected single reference voltage (V ref ) and (ii) a stored count value received from a globally programmable non-regular counter, the globally programmable non-regular counter being configured to continuously provide count values ​​to each of the sensing circuits in dependence on a clock signal, the count values ​​being dependent on the detected voltage (V c ) and the selected single reference voltage (V ref ) and is stored.

[0024] In yet another embodiment, a globally programmable non-conventional counter circuit is provided, the globally programmable non-conventional counter circuit comprising: a memory configured to store configuration data; a clock circuit configured to receive a system clock signal; the non-conventional counter circuit configured to provide a dynamically timed and continuously changing count value to a sensing circuit in dependence on the stored configuration data and the received system clock signal, the sensing circuit being configured to sense a difference between a first current and a second current to generate an output of a selected bit line according to the difference; and a selection signal output circuit configured to output one or more switching signals in dependence on the stored configuration data, the received system clock signal and the dynamically timed and continuously changing count value to control the operation of at least one of the following: (i) a current mirror selector circuit system configured to receive a current (I cell ) and select one or more current mirrors from a plurality of current mirrors to receive the current (I cell ); (ii) a capacitor selector circuit system configured to select one or more capacitors from a plurality of capacitors, the selected one or more capacitors receiving current (I cell ) and stores charge to provide a voltage (V c ); and (iii) a reference voltage selector configured to select a single reference voltage (V ref ).

[0025] The structures and operating methods described in this section of this document are implemented in the form of a non-transitory computer-readable recording medium that stores computer code and causes one or more processors to implement the operations.

[0026] Other forms and advantages of the present invention can be seen upon reading the following drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a simplified block diagram of an integrated circuit device including a memory array arranged for in-memory computations using, for example, signed inputs and weights according to an embodiment of the present disclosure.

[0028] Figure 2 is a schematic diagram of a set of memory cells and local sensing circuits arranged to store and output data for in-memory computation according to an embodiment of the present disclosure.

[0029] Figure 3 is a schematic diagram of a memory array for in-memory computing, local sensing circuits, and a global conventional counter utilized by each of the local sensing circuits according to an embodiment of the present disclosure.

[0030] Figure 4 The local sensing circuit, the global conventional counter and the global fixed V for in-memory computing according to the embodiment of the present disclosure are ref A more detailed diagram of the source.

[0031] Figure 5A The embodiment of the present disclosure is shown when the operation according to the global conventional counter is implemented. Figure 4 The voltage V detected by the local sensing circuit shown c At different currents I cell When the fixed threshold voltage V ref A graph of the time taken.

[0032] Figure 5B The embodiment of the present disclosure is shown when the operation according to the global conventional counter is implemented. Figure 4 As the local sensing circuit shown, with the current I cell As the value increases, the capacitor charges to a fixed threshold voltage V ref A graph of the time taken.

[0033] Figure 5C The present invention is a diagram showing the operation of the global conventional counter according to the embodiment of the present invention. Figure 4 The local sensing circuit shown in Figure 1 is changing the current I cell The voltage detected under the value V c A fixed threshold voltage V is reached at capacitor C ref Table of time spent.

[0034] Figure 6 is a schematic diagram of a local sensing circuit and a global non-conventional counter for in-memory computing according to an embodiment of the present disclosure.

[0035] Figure 7 A graph and a table are shown according to an embodiment of the present disclosure, wherein the graph identifies the current I when a local sensing circuit is used to change the current I cell The detected voltage V c To dynamically adjust the reference voltage V ref The time spent.

[0036] Figure 8 A memory array for in-memory computing, a local sensing circuit and a global dynamic V according to an embodiment of the present disclosure ref Schematic diagram of the source.

[0037] Fig. 9 The local sensing circuit according to the embodiment of the present disclosure and the solution reference Figure 8 The global dynamics of setting time difference V ref The schematic diagram of the source also includes the reference voltage V in the local sensing circuit ref Multiplexer and includes globally programmable out-of-band counters.

[0038] Fig.10 According to the embodiment of the present disclosure Figure 8 A schematic diagram of a local sensing circuit is shown, which also includes current mirror selector circuitry.

[0039] Fig.11 According to the embodiment of the present disclosure Fig.10 A schematic diagram of a local sensing circuit is shown, which also includes capacitor selector circuitry.

[0040] Fig.12 is a globally programmable non-conventional counter according to an embodiment of the present disclosure, a reference voltage V ref Schematic diagram of a multiplexer, current mirror selector circuitry, and capacitor selector circuitry.

[0041]

Explanation of symbols

[0042] 100: Integrated circuit devices / devices

[0043] 105: Input / output circuit

[0044] 110: Controller

[0045] 120: Block

[0046] 140: Driver circuit / word line driver circuit

[0047] 141: Input buffer

[0048] 142: Decoder

[0049] 145: Word Line

[0050] 160: Memory array

[0051] 165: Global bit line

[0052] 170, 220, 302, 302i, 302n: Local sensing circuit

[0053] 180: Page Cache

[0054] 185, 191: Bus

[0055] 190: Cache

[0056] 193: Bus / Line

[0057] 200, 201: Storage unit

[0058] 200-1: First storage unit / storage unit

[0059] 200-2: Second storage unit / storage unit

[0060] 200-3: Third storage unit / storage unit

[0061] 200-4: Fourth storage unit / storage unit

[0062] 210: Common source line (SL)

[0063] 222, 304, 304n: Current manipulator circuit system

[0064] 223: Analog output

[0065] 224: Detector circuit system

[0066] 225: Digital output

[0067] 226: Latch

[0068] 227: Data output

[0069] 300: Global general counter

[0070] 301: Global counter output data / count value

[0071] 304i: (Partial) Current manipulator circuit system

[0072] 305i, 305n: Output

[0073] 306, 306n: Detector circuit system

[0074] 306i: (Partial) Detector Circuit System

[0075] 307i, 307n: Output / trigger signal

[0076] 308, 308n, L0, L1, L2, L3: latch

[0077] 308i: (local) latch

[0078] 309i, 309n: Data output

[0079] 400: Global fixed V ref source

[0080] 402: (Partial) Charging Circuit System

[0081] 404: Switch

[0082] 406: Capacitor

[0083] 408: Comparator

[0084] 500, 502, 504, 506, 508, 510, 700, 702, 704, 706, 708; line

[0085] 600: Global irregular counter

[0086] 800: Global Dynamic V ref source

[0087] 801: (Global) Dynamically adjust reference voltage V ref

[0088] 900: Reference voltage V ref Multiplexer

[0089] 902: Globally programmable non-routine counter

[0090] 1000: Current mirror selector circuit system

[0091] 1100: Capacitor Selector Circuit System

[0092] 1200: CLK counter

[0093] 1202: Dial-in code latch

[0094] 1204: Comparison (timer)

[0095] 1206: Counter (Compare)

[0096] 1208: Select signal output

[0097] a0, a1, a2, a3: bit value / bit / binary data output / counter output code / counter code / output

[0098] BL01: First bit line / bit line

[0099] BL11: Second bit line / bit line

[0100] C: Capacitor

[0101] C1: First capacitor

[0102] C2: Second capacitor

[0103] C3: The third capacitor

[0104] I cell ,I cell0 ,I cell0i ,I cell0n ,I celll ,I cellli ,I cellln : Current

[0105] m1, m2: current mirror

[0106] s1: First switching signal / binary data output / switching signal

[0107] s2: Second switching signal / binary data output / switching signal

[0108] V c : Capacitor voltage / voltage

[0109] V ref : Reference voltage / fixed reference voltage / dynamically adjusted reference voltage / dynamic reference voltage

[0110] V refl : First reference voltage / reference voltage

[0111] V ref2 : Second reference voltage / reference voltage

[0112] V ref3 : Third reference voltage / reference voltage

[0113] V ref4 : Fourth reference voltage / reference voltage

[0114] VT1, VT2, VT3, VT4: Threshold

[0115] W i [1]: Weight value

[0116] WL01: First word line / word line

[0117] WL11: Second word line / word line

[0118] WL0 M 、WL1 M : Word line

[0119] X i [1] X i [M]: variable value DETAILED DESCRIPTION

[0120] Reference Figures 1 to 12 A detailed description of embodiments of the present invention is provided.

[0121] Figure 1 is a simplified block diagram of an integrated circuit device including a memory array arranged for in-memory computations using, for example, signed inputs and weights according to an embodiment of the present disclosure.

[0122] Specifically, Figure 1 is a simplified block diagram of an integrated circuit device 100 including a memory array 160 arranged for in-memory computation for computation-in-memory (CIM) operations such as, for example, signed sum-of-products operations. The integrated circuit device 100 may be implemented on a single die or on a multi-die module.

[0123] The device 100 includes input / output circuits 105 for communicating control signals, data, addresses, and commands with other data processing resources (eg, a central processing unit (CPU) or a memory controller).

[0124] Input / output data is applied to the controller 110 and to the cache 190 on bus 191. In addition, addresses are applied to the decoder 142 and to the controller 110 on bus 193. In addition, bus 191 and bus 193 may be operably connected to a data source (such as a general-purpose processor or a dedicated application circuit system) within the integrated circuit device 100 or to a combination of modules that provide, for example, system chip functions.

[0125] The memory array 160 may include an array of memory cells in a NOR architecture or in an AND architecture, such that the memory cells are arranged in rows along bit lines and in columns along word lines, and the memory cells in a given row are connected in parallel between the bit lines and a source reference. The source reference may include a ground terminal or a source line connected to a source side bias source. The memory cells may include charge trap transistor memory cells arranged in a three-dimensional (3D) structure.

[0126] The bit lines may be connected through block selection circuits to global bit lines 165 , which are configured for selective connection to page buffers 180 and to local sensing circuits 170 (eg, CIM sensing circuits).

[0127] The page buffer 180 in the illustrated embodiment is connected to the cache 190 via a bus 185. The page buffer 180 may include storage elements and other sensing circuits for memory operations, including read operations and write operations. For flash memory including dielectric charge trapping memory and floating gate charge trapping memory, write operations include programming operations and erasing operations.

[0128] Driver circuit 140 is coupled to word lines 145 in memory array 160 and applies a word line voltage to a selected word line in response to decoder 142 decoding an address on bus / line 103 (or in computing operations, in response to input data stored in input register 141).

[0129] Controller 110 is coupled to cache 190 and memory array 160 , and to other peripheral circuits used in memory access and CIM operations.

[0130] The controller 110 controls (using, for example, a state machine) the application of supply voltages and currents generated or provided by voltage or current sources in the block 120 for memory operations and for CIM operations.

[0131] The controller 110 includes control and state registers and control logic, which may be implemented using dedicated logic circuitry including state machines and combinational logic as known in the art. In alternative embodiments, the control logic includes a general purpose processor that may be implemented on the same integrated circuit, the general purpose processor executing a computer program to control the operation of the device. In still other embodiments, the control logic may be implemented using a combination of dedicated logic circuitry and a general purpose processor.

[0132] The memory array 160 includes memory cells arranged in rows and columns, where the memory cells in the rows are connected to corresponding bit lines and the memory cells in the columns are connected to corresponding word lines. For CIM operation, the memory array 160 may be programmable to store signed coefficients (weights W) in multiple groups of memory cells. i ).

[0133] In CIM mode, the word line driver circuit 140 includes a driver configured to drive the signed input X by selecting a voltage pattern on the selected word line and the unselected word lines from the input buffer 141. iThe local sensing circuit 170 may be configured to sense the difference between the first current and the second current on the corresponding bit line of the selected bit line (or the selected plurality of pairs of bit lines) and generate an output of the selected bit line (or the selected plurality of pairs of bit lines) according to the difference. Sensing the difference may include subtracting the current value or voltage value from the corresponding bit line and may include adding the current value or voltage value from the corresponding bit line. The output may be applied to the storage element in the page buffer 180 and to the cache 190.

[0134] Implementations of the memory array 160 may be based on charge trapping memory cells, such as floating gate memory cells that may include a polysilicon charge trapping layer, or dielectric charge trapping memory cells that may include a silicon nitride charge trapping layer. Other types of memory technologies may also be used in various embodiments of the techniques described herein.

[0135] Figure 2 is a schematic diagram of a set of memory cells and local sensing circuits arranged to store and output data for in-memory computation according to an embodiment of the present disclosure.

[0136] Specifically, Figure 2 1. A set of memory cells 200, implemented in this example by charge trap memory transistors, are shown, configured to store bits (eg, signed bits or unsigned bits). Figure 2 The group of memory cells 200 in FIG. 1 may be one of a plurality of groups of memory cells for storing a plurality of bits in a memory array having a plurality of word lines and a plurality of bit lines. Figure 2 Many of the groups of memory cells 200 shown may be used to store the M coefficients W used in the product-sum operation. i (or weights) (where i ranges from 1 to M), or stores many coefficient arrays for efficient CIM operations.

[0137] Figure 2 The group of memory cells 200 in the vector W includes a first memory cell 200-1, a second memory cell 200-2, a third memory cell 200-3, and a fourth memory cell 200-4. Each of the first memory cell 200-1, the second memory cell 200-2, the third memory cell 200-3, and the fourth memory cell 200-4 may be implemented by a charge trap memory transistor. Other implementations will be apparent to those skilled in the art. For notation purposes, the group of memory cells 200 may be referred to as being in the vector W. iThe signed bit of coefficient W1 is stored in . Other implementations of CIM operations will be apparent to those skilled in the art.

[0138] A first memory cell 200-1 is located on a first bit line BL01 and a first word line WL01. A second memory cell 200-2 is located on a second bit line BL11 and a first word line WL01. A third memory cell 200-3 is located on a first bit line BL01 and a second word line WL11. A fourth memory cell 200-4 is located on a second bit line BL11 and a second word line WL11. The source side (source line or SL side) of the first memory cell 200-1, the second memory cell 200-2, the third memory cell 200-3, and the fourth memory cell 200-4 may be connected to a source reference circuit, which may include a ground terminal or source line (SL) connected to a source side bias resource operable for memory operations such as programming and erasing. In the example shown, the source reference circuit includes a common source line (SL) 210 connected to a source side bias circuit (not shown).

[0139] Another set of storage units 201 is identical in form and structure to the set of storage units 200, but is shown in less detail for clarity. Each of the plurality of sets of storage units 200 and 201 may be used to store a weight value W, respectively. i [1] and W i [N] Each of the plurality of storage units 200 and 201 is enabled to receive a corresponding variable value X i [1] and X i [M] Each of the variable values ​​is represented by a pair of word lines (for X i [1] is WL01 and WL11, and for X i [M] is WL0 M and WL1 M Each of the plurality of storage units 200 and 201 is enabled to perform arithmetic operations using the stored weight values ​​and the provided variable values, such as multiplication (X i [1]×W i [1]) and provide the result of the operation as reflected in I cell0 and I celll part of the current.

[0140] Any suitable encoding may be used to encode weight values ​​using thresholds (VT1, VT2, VT3, and VT4) on memory cells 200-1, 200-2, 200-3, and 200-4, respectively. Any suitable encoding may be used to encode variable values ​​using a particular pair of voltages on WL01 and WL11. Encoding weight values ​​and variable values ​​is the same for the set of memory cells 201. The set of memory cells 201 represents one or more such memory cells similarly connected in parallel to bit lines BL01 and BL11.

[0141] It will be apparent to those skilled in the art that CIM operation is implemented using VT1, VT2, VT3, and VT4 and currents and / or voltages on first bit line BL01, second bit line BL11, first word line WL01, and second word line WL11.

[0142] like Figure 2 As shown in FIG. 1 , the pair of bit lines BL01 and BL11 are connected to the local sensing circuit 220. The bit line BL01 can provide a current I to the local sensing circuit 220. cell0 The bit line BL11 can provide a current I to the local sensing circuit 220. celll In addition, the current I cell0 with I celll The current may be provided and / or detected on the same bit line (eg, BL01 or BL11). This applies to all descriptions of providing and / or detecting current on a bit line set forth herein.

[0143] In addition, the local sensing circuit 220 may include a current manipulator circuit system 222 that generates a current signal based on the current I cell0 and current I cell1 The value of provides an analog output 223 (current or voltage). For example, the current manipulator circuit system 222 can generate a current I cell0 With current I celll The local sensing circuit 220 may also include a detector circuit system 224 that converts this analog output 223 into a digital output 225 that is stored in a memory (e.g., a latch 226 of the local sensing circuit 220), which may then provide a digital output 227.

[0144] Figure 3 is a schematic diagram of a memory array for in-memory computing, local sensing circuits, and a global conventional counter utilized by each of the local sensing circuits according to an embodiment of the present disclosure.

[0145] Specifically, as shown, the global conventional counter 300 provides global counter output data 301 (which may be referred to as a count value) to local sensing circuits 302i to 302n (where n may be an integer up to hundreds of thousands or even more than hundreds of thousands). Figure 2 In the local sensing circuit 220 shown, the local sensing circuit 302i includes a (local) current manipulator circuit system 304i (e.g., a local current manipulator circuit), and the (local) current manipulator circuit system 304i provides an output 305i (e.g., an analog output) to a (local) detector circuit system 306i (e.g., a local detector circuit). The current manipulator circuit system 304i can be connected to Figure 2 The local sensing circuit 302i may operate in the same manner as the current manipulator circuit system 222 shown. For example, the local sensing circuit 302i may receive the current I from a pair of bit lines (or a single bit line) of the memory array 160. cell0i and current I cellli And the current I cell0i With current I cellli The difference between the current I cell0i with I cellli The difference between may be reflected as subtracting one current from the other or adding one current to the other. The current manipulator circuitry 304i may then provide an output 305i based on the sensed or detected difference.

[0146] The detector circuit system 306i receives the output 305i and can compare the output 305i with another known value (such as a reference voltage V ref ) for comparison. Once the detector circuit system 306i determines that the output 305i has reached, exceeded and / or fallen below another known value, the detector circuit system 306i may provide an output 307i (e.g., a trigger signal) to a (local) latch 308i that triggers storage of the global counter output data 301. Figure 3 The local sensing circuit 302i is shown as including a latch 308i, but other storage components such as flip-flops may be substituted for the latch 308i to store the global counter output data 301. The data stored in the latch 308i may be provided as a data output 309i generated by the CIM operation.

[0147] As shown in the figure, there may be n local sensing circuits. Specifically, Figure 3 A pair of bit lines (or a single bit line) of the memory array 160 receives a current I cell0n and current I celllnA local sensing circuit 302n, wherein the local sensing circuit 302n includes a current manipulator circuit system 304n that provides an output 305n to a detector circuit system 306n, and the detector circuit system 306n provides an output 307n to be stored by a latch 308n, which can provide a data output 309n such as a CIM operation.

[0148] The global conventional counter 300 can continuously provide the global counter output data 301 as the count value 301. As shown, the same count value 301 is received by each of the local sensing circuits 302i to 302n (e.g., the local sensing circuits 302i to 302n can operate according to the same global conventional counter 300 and the count value 301 provided thereby). Specifically, the count value 301 is received by the corresponding latches 308i to 308n, and the latches 308i to 308n can be triggered by the corresponding trigger signals 307i to 307n to respectively store the count value 301. The latches 308i to 308n can be any type of component that can store or latch data.

[0149] The global conventional counter 300 may provide the count value 301 in a binary value or other form. For example, the count value 301 may be received by the latches 308i to 308n as a 2-bit, 3-bit, 4-bit, 5-bit, etc. value. The latches 308i to 308n will have, for example, at least the same number of storage locations as the number of bits of the count value 301, so that the entire count value 301 received from the global conventional counter 300 can be stored. As the global conventional counter 300 continues to provide the count value 301 to the latches 308i to 308n, the count value 301 (e.g., a specific count value) may be stored (latched) by the latches 308i to 308n at different times when the latches 308i to 308n are triggered by the trigger signals 307i to 307n at different times, respectively. The count values ​​301 stored by the different latches 308i-308n are then provided at the data outputs 309i-309n of the local sensing circuits 302i-302n.

[0150] See below Figure 4 More details are provided regarding the specific structure and operation of local sensing circuits 302i-302n.

[0151] Figure 4 is a more detailed schematic diagram of a local sensing circuit for in-memory computing according to an embodiment of the present disclosure. An in-memory computing device may include thousands of local sensing circuits. Figure 4 The structure of only one of the local sensing circuits is shown, but all the local sensing circuits of the in-memory computing device may have the same structure as that of the local sensing circuits described herein. Figure 4 The same structure as discussed.

[0152] Specifically, Figure 4 302. More details about the output of the global conventional counter 300 and the circuit structure of the local sensing circuit 302 are shown. The global conventional counter 300 can output 4 bits as a count value. For example, the global conventional counter 300 can output bit a0, bit a1, bit a2, and bit a3 as a four-bit value. The latch 308 of the local sensing circuit 302 may include four latches, including latch L0, latch L1, latch L2, and latch L3. As shown, latch L0 can receive the bit value a0 provided by the global conventional counter 300, latch L1 can receive the bit value a1 provided by the global conventional counter 300, latch L2 can receive the bit value a2 provided by the global conventional counter 300, and latch L3 can receive the bit value a3 provided by the global conventional counter 300. The number of bits provided by the global conventional counter 300 and the number of latches included in the latch 308 are only examples. The techniques disclosed herein may utilize any number of bits and latches, wherein the number of latches included in latch 308 should be at least equal to the number of bits provided as the count value from global normal counter 300 .

[0153] like Figure 4 As shown in , the binary values ​​represented by bits a0, a1, a2, and a3 increment (count) between 0 and 15 as an unsigned integer (e.g., binary values ​​0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, and 1111). Figure 4 A count from 0 to 15 is shown that increases by one integer continuously over time. This is merely an example, as discussed herein, so that the global conventional counter 300 can count forward and / or backward in a conventional digital mode. The global conventional counter 300 can operate based on a clock (e.g., a high speed clock) or some other mechanism that will be apparent to one skilled in the art. The value output from the detector circuit system 306 can trigger the latch 308 to store the current count value provided by the global conventional counter 300.

[0154] In addition, if Figure 4 As shown in FIG. 1 , the local sensing circuit 302 includes a (local) charging circuit system 402 that receives a current I provided by the current manipulator circuit system 304. cell (As mentioned above for Figure 2 and Figure 3 Specifically, the current I cellis received as a current source to the charging circuit system 402. The charging circuit system 402 may also include an optional switch 404 and the one or more capacitors 406. The switch 404 may be used to allow the one or more capacitors 406 to fully discharge and / or prevent the one or more capacitors 406 from further charging. For example, when the switch 404 is turned on (allowing current to pass), the current I cell The one or more capacitors 406 may begin to charge to accumulate charge, thereby reaching a higher capacitor voltage V c For yet another example, in synchronization with the global conventional counter 300, the switch 404 is used to discharge the one or more capacitors 406 before counting begins. For another example, the switch 404 is used to enable the current I cell The one or more capacitors 406 are charged, for example, by combining the detected voltage V c For another example, switch 404 is used to switch the current I cell The further charging of the one or more capacitors 406 is disconnected (combined with the detected voltage V c For comparison). For another example, the switch 404 is used to release any charge stored in the one or more capacitors 406, thereby providing a current I cell Then switch 404 is used to make the current I cell The one or more capacitors 406 can be charged for a specific amount of time, for example, the switch 404 is closed at the beginning of the specific amount of time and then opened at the end of the specific amount of time. c will obtain the current I cell , the capacitance of the one or more capacitors 406, and a value proportional to a specific amount of time. The value of the one or more capacitors 406 may change. An example capacitor may be 50 femtofarads. When the one or more capacitors 406 receive a current I cell , they begin to charge and can provide a voltage V that can be detected by the detector circuit system 306. c (For example, the detected voltage V c ). As time goes by, as the one or more capacitors 406 draw current I cell Charging, the detected voltage V c The value will increase.

[0155] The in-memory computing device also includes a reference voltage V provided to the detector circuit system 306. ref The global fixed V ref Source 400. Reference voltage V ref It can be any voltage available to the in-memory computing device. refAn example value is 0.6 volts. The global fixed V ref Source 400 can provide a reference voltage V to all sensing circuits in the in-memory computing device. ref The detector circuit system 306 can be used to generate a reference voltage V ref The value of the detected voltage V c This comparison can be performed using comparator 408. Any other type of circuit system can be implemented to compare the reference voltage V eef The value of the detected voltage V c For example, the comparator 408 may be replaced by one or more differential amplifiers and / or one or more inverters. Figure 4 The structure of the detector circuit system 306 and the comparator 408 shown in FIG. c Less than the reference voltage V ref When the detected voltage V c Greater than the reference voltage V ref When , comparator 408 may provide a high output (eg, 1). Other types of logic may be implemented by detector circuitry 306, and this illustration is merely an example.

[0156] In this example, initially when the reference voltage V ref Higher than the detected voltage V c , the comparator 408 will output a value of 0, so that the latch 308 is not triggered to latch (store) the count value 301 (as provided by bits a0 to a3). cell The one or more capacitors 406 are charged, and the detected voltage V c will increase sufficiently so that the detected voltage V c Reaching and / or exceeding the reference voltage V ref The output of the detector circuit system 306 and / or the comparator 408 may be referred to as a trigger signal (which triggers the latch 308 to latch / store the count value 301). c Reach or exceed (or drop / fall below) the reference voltage V ref As a result, the trigger signal may change from a value of 0 to 1 or from a value of 1 to 0. The detector circuit system 306 may include a multi-comparator configuration. The comparator 408 may be configured to be edge-triggered or level-triggered or may have other configurations known to those skilled in the art.

[0157] although Figure 4The current manipulator circuit system 304, the charging circuit system 402, the detector circuit system 306, and the latch 308 are shown as being local to the local sensing circuit 302, but other configurations may be used such that each of the current manipulator circuit system 304, the charging circuit system 402, the detector circuit system 306, and the latch 308 need not be local to the local sensing circuit 302. In addition, as another option, the self current I cell The generated current or voltage can be used as the detected voltage V c (or simply as a detected current) is provided to the detector circuit system 306 without using the charging circuit system 402 and / or the one or more capacitors 406. For example, the detector circuit system 306 can directly detect the current I provided by the current manipulator circuit system 304. cell Alternatively, the detector circuit system 306 may detect the current I provided by the memory array 160 cell0 and / or I cell1 In addition, instead of providing a reference voltage V to the detector circuit system 306 ref , can provide a reference current I to the detector circuit system 306 ref , for current I cell 、Current I cell0 and / or current I celll Make a comparison.

[0158] exist Figure 4 The use of the global conventional counter 300 in the in-memory computing device shown may be problematic because the time taken for the one or more capacitors 406 to be sufficiently charged to trigger the storage of the count value 301 may depend on the current I cell (or the detected voltage) varies greatly. Therefore, latch 308 may need more time to store count value 301. In other words, global normal counter 300 may need to be set to a slow count time so that there is enough time for current I cell The low value of charges the one or more capacitors 406 to trigger the storage of a specific count value 301. FIG. 5A to FIG. 5C Explain in more detail.

[0159] Figure 5A The embodiment of the present disclosure is shown when the operation according to the global conventional counter is implemented. Figure 4 The voltage V detected by the local sensing circuit shown c At different currents I cell When the fixed threshold voltage V ref A graph of the time taken.

[0160] Specifically, Figure 5A Shows time (nanoseconds) versus the detected voltage Vc (Volts) curve. Figure 4 As discussed, since the detected voltage V c reaches or exceeds the fixed reference voltage V ref The value of triggers the storage of the count value 301. In this example, the fixed reference voltage V ref The value is 0.6 volts. Figure 5A The line 500 in the graph in FIG. 1 represents the fixed reference voltage V ref Line 502 is when the current I cell The voltage V detected when the current is 800 nanoamperes (nA) c The voltage versus time representation, line 504 is when the current I cell The voltage V detected when the current is 600 nanoamperes (nA) c The voltage versus time representation, line 506 is when the current I cell The voltage V detected when the current is 400 nanoamperes (nA) c The voltage versus time is represented by line 508, and line 509 is when the current I cell The voltage V detected when the current is 200 nanoamperes (nA) c As shown in the figure, when the current I cell When the current value is low (for example, 200 nanoamperes), the detected voltage V c Reaching the reference voltage V ref Therefore, the global normal counter 300 needs to be configured to allow line 508 to reach the fixed reference voltage V ref The rate at which longer durations (eg, 150 nanoseconds) are spent is counted.

[0161] Figure 5B The embodiment of the present disclosure is shown when the operation according to the global conventional counter is implemented. Figure 4 As the local sensing circuit shown, with the current I cell As the value increases, the capacitor charges to a fixed threshold voltage V ref A graph of the time taken.

[0162] Specifically, Figure 5B Shows the current I measured in nanoamperes cell A plot of the value of versus time measured in nanoseconds to show the Figure 5A The lines 502, 504, 506 and 508 in FIG. 5 represent the voltage V detected for different current values. c Reaching a fixed reference voltage V ref The time it takes to charge. Figure 5B The line 510 shows currents I of 200 nanoamperes, 400 nanoamperes, 600 nanoamperes, 800 nanoamperes, and 1000 nanoamperes. cellValue charging time.

[0163] Figure 5C The present invention is a diagram showing the operation of the global conventional counter according to the embodiment of the present invention. Figure 4 The local sensing circuit shown in Figure 1 is changing the current I cell The voltage detected under the value V c A fixed threshold voltage V is reached at capacitor C (in femtofarads) ref Table of time spent.

[0164] Specifically, Figure 5C (i) When the current I cell With a value of 200 nanoamperes, the detected V c Reaching a fixed reference voltage V ref takes 150 nanoseconds; (ii) when the current I cell With a value of 400 nanoamperes, the detected V c Reaching a fixed reference voltage V ref takes 75 nanoseconds; (iii) when the current I cell With a value of 600 nanoamperes, when charging a 50 femtofarad capacitor C, the detected V c Reaching a fixed reference voltage V ref takes 50 nanoseconds; and (iv) when the current I cell With a value of 800 nanoamperes, the detected V c Reaching a fixed reference voltage V ref takes 38 nanoseconds. In addition, the current I cell The time difference between the values ​​200 and 400 is 75 nanoseconds, and the current I cell The time difference between the values ​​400 and 600 is 25 nanoseconds, and the current I cell The time difference between the values ​​600 and 800 is 12 nanoseconds. Such varying time intervals caused by different currents (eg, 75 nanoseconds, 25 nanoseconds, and 12 nanoseconds) may make it difficult to operate the local sensing circuit 302 regularly.

[0165] In order for the global normal counter 300 to operate to take into account the current I cell It is obvious that the counter should be configured to accommodate at least 150 nanoseconds between increasing or decreasing the count value. cell For higher values ​​of I (e.g., 800 nanoamperes), this configuration can waste a lot of time and require much less time between counts. In addition, if the count time is not configured long enough, for lower currents I cellTherefore, it is desirable to implement a global counter that is not conventional but non-conventional (e.g., dynamic) so as to provide a low current I cell The value provides a longer count time and a higher current I cell Values ​​provide shorter count times.

[0166] Figure 6 is a schematic diagram of a local sensing circuit and a global non-conventional counter for in-memory computing according to an embodiment of the present disclosure.

[0167] Apart from Figure 4 In addition to the global regular counter 300 being replaced by the global irregular counter 600, Figure 6 Similar to Figure 4 The global irregular counter 600 may be capable of adjusting the duration (e.g., time interval) between sending count values. The global irregular counter 600 may be an irregular counter that increments or decrements the count value at irregular intervals, a bit number counter (e.g., a bit counter) that counts the number of bits received and increments or decrements the count value accordingly over time, etc. Other types of irregular counters that provide data at dynamic time intervals may be based on the measured current I cell and based on other factors that will be apparent to those skilled in the art.

[0168] like Figure 6 As shown in FIG. 1 , the global non-regular counter 600 may (i) wait 75 nanoseconds from when the count value 1100 is provided and when the count value 1101 is provided; (ii) wait 25 nanoseconds from when the count value 1101 is provided and when the count value 1110 is provided; and (iii) wait 12 nanoseconds from when the count value 1110 is provided and when the count value 1111 is provided. This timing scheme is only an example. The timing interval implemented by the global non-regular counter 600 may be based on the current I cell The measured value of the current I cell As the value of increases, the time between counts provided by the global non-regular counter 600 decreases, and if the current I cell As the value of decreases, the time between counts provided by the global non-regular counter 600 increases. The current I can be defined and known when programming various memory cells. cell , so that the time interval of the global irregular counter 600 can be adjusted and programmed accordingly, because the current I can be known / predicted when reading data from various memory cells. cell This timing scheme of the global non-conventional counter 600 is based only on the known I cell Value and known reference voltage V ref An instance of a value.

[0169] Although implementations of global non-regular counter 600 may address the following issues: cell The problem of latching the correct count value by using the current value is corrected, but the result may be that the performance of the in-memory computing device is longer than expected. Specifically, even for a higher current I of 800 nanoamperes cell The shortest time interval of the value is 12 nanoseconds, and other time intervals are also longer (e.g., 75 nanoseconds). Therefore, the total counting time of the global out-of-order counter 600 may be longer than desired. Therefore, it is desirable to provide an in-memory computing device that can further reduce the total counting time of the global out-of-order counter 600 cycling through the count value.

[0170] Figure 7 A graph and a table are shown according to an embodiment of the present disclosure, wherein the graph identifies the current I when a local sensing circuit is used to change the current I cell The detected voltage V c To achieve an example dynamically adjust the reference voltage V ref The time spent.

[0171] Specifically, Figure 7 The graph shows the time in nanoseconds (ns) versus the detected voltage V c (Volts). Since the detected voltage V c Reach or exceed the reference voltage V ref The value of triggers the storage of the count value 301. In this example, the reference voltage V ref The value of is dynamic because it changes over time. Figure 7 Line 700 in the figure represents the dynamic reference voltage V ref The value of is because it may change with time. Line 702 is when the current I cell The voltage V detected when the current is 800 nanoamperes (nA) c As shown, line 700 intersects line 702 at about 160 nanoseconds. Line 704 is when the current I cell The voltage V detected when the current is 600 nanoamperes (nA) c As shown, line 700 intersects line 704 at about 120 nanoseconds. Line 706 is when the current I cell The voltage V detected when the current is 400 nanoamperes (nA) c As shown, line 700 intersects line 706 at about 80 nanoseconds. Line 708 is when the current I cell The voltage V detected when the current is 200 nanoamperes (nA) cAs shown, line 700 intersects line 708 at approximately 40 nanoseconds.

[0172] Therefore, if Figure 7 As shown in the graph, for the reference voltage V ref The value of I can be adjusted dynamically to make the current I cell The detected voltage V c Reaching the dynamic reference voltage V ref The intervals are more consistent. In this figure, the intervals are about 40 nanoseconds. As shown in the figure, when the current I cell When the voltage V c Reaching the reference voltage V ref Takes a longer time.

[0173] Figure 7 The table in FIG. 1 shows (i) various times in nanoseconds; (ii) the time at which the corresponding time is in nanoseconds. cell The voltage V detected at different current values ​​(200 nanoamperes, 400 nanoamperes, 600 nanoamperes and 800 nanoamperes) c and (iii) dynamically adjusting the reference voltage V at the corresponding time in nanoseconds ref As shown in the figure: (I) At 40 nanoseconds, the detected voltage V is 0.16 volts c (For a current of 200 nanoamperes I cell value) and dynamically adjust the reference voltage V ref (ii) at 80 nanoseconds, the detected voltage V of 0.64 volts matches c (For a current of 400 nanoamperes I cell value) and dynamically adjust the reference voltage V ref (iii) at 120 nanoseconds, the detected voltage V of 1.44 volts matches c (For a current of 600 nanoamperes I cell value) and dynamically adjust the reference voltage V ref and (iv) at 160 nanoseconds, a detected voltage V of 2.56 volts. c (For a current of 800 nanoamperes I cell value) and dynamically adjust the reference voltage V ref Therefore, by using the dynamic reference voltage V ref , different I cell The detected voltage V at the current value cThe intervals of can remain the same. Such consistency between intervals (eg, same timing resolution between adjacent current levels) provides the benefit that the (temporal) sensing window is uniform and optimized for all adjacent current levels.

[0174] This dynamically adjusts the reference voltage V ref Global dynamic V ref The source is implemented in a similar manner as the global out-of-order counter 600 .

[0175] Figure 8 A memory array for in-memory computing, a local sensing circuit and a global dynamic V according to an embodiment of the present disclosure ref Schematic diagram of the source.

[0176] Apart from Figure 8 Including global dynamic V ref Source 800 for reference Figure 7 The dynamic adjustment of the reference voltage V ref In addition, Figure 8 Similar to Figure 3 As shown in the figure, the global dynamic V ref Source 800 can provide a (global) dynamically adjusted reference voltage V to each of the local sensing circuits 302i to 302n. ref 801. In addition, as shown in the figure, the local sensing circuit 302i is closer to the global dynamic V than the local sensing circuit 302n. ref Source 800. Closer to the global dynamic V ref The local sensing circuit of source 800 may be referred to as a "near-end sensing circuit" having a faster settling time and being further away from the global dynamic V ref The local sensing circuit of source 800 can be referred to as a "remote sensing circuit" with a longer setup time. The setup time refers to the dynamic adjustment of the reference voltage V ref The time it takes for the value of to reach the corresponding detector circuit system 306i-306n. The difference between the faster setup time and the longer setup time can be 10 nanoseconds, which is very valuable time for fast memory devices. The difference in setup time between the "near-end sensing circuit" and the "far-end sensing circuit" can cause the detector circuit system 306i-306n to receive different dynamic reference voltages V at any given time. ref Therefore, at any given time, the dynamic reference voltage V used by the detector circuit system 306i is ref The dynamic reference voltage V may be different from that utilized by the detector circuit system 306n. ref As discussed below, these setup time differences may be taken into account.

[0177] Fig. 9 The local sensing circuit according to the embodiment of the present disclosure and the solution reference Figure 8 The global dynamics of setting time difference V ref The schematic diagram of the source also includes the reference voltage V in the local sensing circuit. ref Multiplexer and includes globally programmable out-of-band counters.

[0178] Specifically, in addition to Fig. 9 Also includes Figure 8 The global dynamic V ref Source 800, global programmable non-regular counter 902 and reference voltage V ref In addition to the multiplexer 900, Fig. 9 With Figure 6 The components of the in-memory computing device are shown in a similar manner. The components will not be described in detail. Fig. 9 As shown in the figure, the global dynamic V ref Source 800 to the reference voltage V ref Multiplexer 900 provides four reference voltages. Global dynamic V ref Source 800 can provide only one reference voltage or multiple reference voltages. The first reference voltage is V refl , the second reference voltage is V ref2 , the third reference voltage is V ref3 , and the fourth reference voltage is V ref4 . The first reference voltage V ref1 Can be used for different I cell Values ​​(e.g., four different I cell value), the second reference voltage V ref2 Can be used for different I cell Values ​​(e.g., four different I cell value), the third reference voltage V ref3 Can be used for different I cell Values ​​(e.g., four different I cell value), the fourth reference voltage V ref4 Can be used for different I cell Values ​​(e.g., four different I cell value).

[0179] Global Dynamics V ref The source is not limited to providing only four reference voltages and it may provide more than four or less than four (eg, only one). ref The multiplexer 900 is configured to output a signal from a global dynamic V ref Select between any of the reference voltages received by source 800.

[0180] In this example, the global programmable out-of-order counter 902 provides Figure 6The global non-conventional counter 600 has the same or similar counting function and is more biased towards the reference voltage V ref The multiplexer 900 provides the one or more switching signals. The global programmable irregular counter 902 can be an irregular counter that increments or decrements a count value at irregular intervals, a bit number counter (e.g., a bit counter) that counts the number of received bits and increments or decrements the count value accordingly over time, etc. Other types of irregular counters that provide data at dynamic time intervals will be apparent to those skilled in the art.

[0181] Specifically, in this example, the global dynamic V ref Source 800 to the reference voltage V ref The multiplexer 900 provides a switching signal including a first switching signal s1 and a second switching signal s2, a reference voltage V ref The multiplexer 900 selects a single reference voltage V according to the switching signal. ref . Provided from the global programmable irregular counter 902 to the reference voltage V ref The number of switching signals of the multiplexer 900 may depend on the reference voltage V ref The first switching signal s1 and the second switching signal s2 can provide binary numbers representing values ​​from 0 to 3. The reference voltage V ref The multiplexer 900 can use a binary number to select the first reference voltage V refl , the second reference voltage V ref2 , the third reference voltage V ref3 and the fourth reference voltage V ref4 Any one of .

[0182] Fig. 9 This structure shown in the above reference will solve the problem Figure 8 The setup time difference discussed is due to the first reference voltage V ref1 , the second reference voltage V ref2 , the third reference voltage V ref3 and the fourth reference voltage V ref4 Each of the two voltages may be a constant value, which may be used as a reference voltage V ref is transmitted to the detector circuit system 306 and the detector circuit systems 306i to 306n. Specifically, the first switching signal s1 and the second switching signal s2 and the reference voltage V ref The multiplexer 900 can reduce the setup time difference between the “near-end sensing circuit” and the “far-end sensing circuit”.

[0183] The global programmable non-regular counter 902 can be programmed to make the reference voltage V refMultiplexer 900 selects the global dynamic V ref The different reference voltages received by the source 800. For example, Fig. 9 As shown in the binary count in the latch 308, for a particular number of count values, a different one of the first reference voltage to the fourth reference voltage may be implemented. In this example, the fourth reference voltage V may be selected for count values ​​from 0 to 3. ref4 , a third reference voltage V can be selected for a count value from 4 to 7 ret3 , the second reference voltage V can be selected for the count value from 8 to 11 ref2 , and the first reference voltage V can be selected for the count value from 12 to 15 ref1 The timing scheme can be obtained by dividing the total number of count values ​​(e.g., 16 count values ​​since the count values ​​are represented by 4 bits) by the global dynamic V ref The reference voltage V ref The multiplexer 900 switches to track the detected voltage V c Reach various reference voltages V ref1 、V ref2 、V ref3 、V ref4 The reference voltages may be used to reduce the variation in the time interval implemented by the globally programmable non-regular counter 902 depending on the desired charging time interval.

[0184] The global programmable out-of-order counter 902 can be configured to adjust the duration between each count value. Fig. 9 As shown in , durations of 10 nanoseconds, 10 nanoseconds, 10 nanoseconds, etc. may be implemented. Alternatively, unequal intervals may be implemented, such as 30 nanoseconds, 20 nanoseconds, 10 nanoseconds, etc. Other timing schemes will be apparent to those skilled in the art. Therefore, by using the global programmable non-conventional counter 902 to control the reference voltage V using the switching signals s1 and s2 ref The switching of the multiplexer 900, the reference voltage V ref The selection of the reference voltage signal by the multiplexer 900 can track the detected voltage V c The current I reaches various selected reference voltage signals cell In other words, the global programmable non-regular counter 902 can track the detected voltage V c To achieve different reference voltages V refl 、V ref2 、V ref3 、V ref4 Different current I cellThe binary data outputs (a0 to a3, s1 and s2) are toggled or changed at intervals of time with only one available reference voltage V ref Compared to the implementation of the present invention, the variation of the time interval implemented by the global programmable non-regular counter 902 can be reduced. This time interval tracking can be used to match the charging time of the one or more capacitors 406 to reach the selected reference voltage V ref .

[0185] Fig.10 According to the embodiment of the present disclosure Fig. 9 A schematic diagram of a local sensing circuit is shown, which also includes current mirror selector circuitry.

[0186] Specifically, Fig.10 The local sensing circuit 302 shown includes a current mirror selector circuit system 1000. The current mirror selector circuit system 1000 is configured to select different current mirrors to be applied to the current I cell Different current mirrors can be selected according to the first switching signal s1 and the second switching signal s2 provided by the global programmable non-regular counter 902. Fig. 9 As described above, the first switching signal s1 and the second switching signal s2 can provide binary numbers representing values ​​from 0 to 3, and the current mirror selector circuit system 1000 can use the binary numbers to select various combinations of current mirrors. The number of switching signals provided from the global programmable non-conventional counter 902 to the current mirror selector circuit system 1000 can depend on the number of current mirrors that can be selected by the current mirror selector circuit system 1000. The current mirror can be used to select the current I cell Applying different multiplication (or other) factors and based on the current I to which the multiplication (or other) factors have been applied cell The mirror current outputted from the one or more current mirrors charges the one or more capacitors 406 .

[0187] exist Fig.10 In the example shown in FIG. 1 , the current mirror selector circuit system 1000 may receive a current I cell , and then select various combinations of current mirrors (including no current mirrors) to apply to I cell , which is used to charge the one or more capacitors 406. The current mirror may be selected depending on at least one of: (i) the operating conditions of the in-memory computing device; (ii) the timing scheme of the counter value provided by the global programmable non-regular counter 902; (iii) the sensing circuit relative to the global fixed V ref Source 400 or global dynamic V ref the location of source 800; and (iv) a predefined level of the sensed current.

[0188] like Fig.10 As shown in the latch 308, the current mirror selector circuit system 1000 can implement the current mirror m1 and the current mirror m2. Fig.10 As shown in FIG. 1 , the current mirror selector circuit system 1000 can simply allow I cell By changing I cell The current mirror selector circuit system 1000 can also be configured by setting I cell The current mirror m1 is multiplied and the current mirror m2 is multiplied to obtain certain count values ​​(see the binary count values ​​0011, 0010, 0001 and 0000, where I cell and current mirror m1 and current mirror m2) to apply current mirror m1 and m2 to I cell In addition, the current mirror selector circuit system 1000 can be I cell The current mirror selector circuit 1000 can be multiplied by the current mirror m2 to obtain certain count values ​​(such as binary count values ​​0100, 0101, 0110, and 0111 (not shown)). cell The current mirror m1 is multiplied by the current mirror m2 to obtain certain count values ​​(e.g., binary count values ​​1000, 1001, 1010, and 1011 (not shown)). The selection and implementation of the current mirrors m1 and m2 can be used to achieve the same as for Fig. 9 The discussed reduction of time interval variation and selection of different reference voltages V ref1 、V ref2 、V ref3 、V ref4 In addition, if Fig. 9 As discussed, the global programmable non-regular counter 902 can be configured to adjust the duration between each count value (depending on the selection of the current mirror selector circuit system 1000). Fig.10 As shown in , durations of 10 nanoseconds, 10 nanoseconds, 10 nanoseconds, etc. (or 30 nanoseconds, 20 nanoseconds, 10 nanoseconds, etc.) may be implemented. Other timing schemes will be apparent to those skilled in the art. Fig.10 It will be apparent to those skilled in the art that the number of current mirrors selected and / or implemented by the current mirror selector circuit system 1000 and the schemes for implementing the current mirrors discussed are merely examples and the number of current mirrors and the schemes for implementing the current mirrors may vary from what is described herein.

[0189] Fig.11 According to the embodiment of the present disclosure Fig.10 A schematic diagram of a local sensing circuit is shown, which also includes capacitor selector circuitry.

[0190] Specifically, Fig.11 The local sensing circuit 302 shown includes a capacitor selector circuit system 1100. The capacitor selector circuit system 1100 is configured to select different combinations of capacitors to implement as the one or more capacitors 406. For example, the one or more capacitors 406 may include a first capacitor C1, a second capacitor C2, and a third capacitor C3. The selected capacitor combination may receive a current I cell , to detect the voltage V c The one or more capacitors 406 may be selected according to the first switching signal s1 and the second switching signal s2 provided from the global programmable non-regular counter 902. Fig. 9 and Fig.10 As described above, the first switching signal s1 and the second switching signal s2 may provide binary numbers representing values ​​from 0 to 3, and the capacitor selector circuit system 1100 may use the binary numbers to select various combinations of the first capacitor C1, the second capacitor C2, and the third capacitor C3 of the one or more capacitors 406. The number of switching signals provided from the global programmable non-conventional counter 902 to the capacitor selector circuit system 1100 may depend on the number of capacitors selectable by the capacitor selector circuit system 1100. Different implementations of various capacitors may change (increase and / or decrease) the detected voltage V c Reaching the reference voltage V ref charging time.

[0191] exist Fig.11 In the example shown in FIG. 1 , the capacitor selector circuit system 1100 may receive a current I cell (from the selected current mirror, if current mirror selector circuit system 1000 is implemented or without current mirror selector circuit system 1000, if current mirror selector circuit system 1000 is not implemented), and then various combinations of first capacitor C1, second capacitor C2 and third capacitor C3 are selected to receive current I cell to charge. In an embodiment, a specific capacitor may be selected for each current mirror so that each current mirror provides an output to a specific capacitor or one or more capacitors may be selected for a group of one or more current mirrors as a whole. The capacitors may be arranged in a series configuration or a parallel configuration or any other configuration. The capacitor may be selected in dependence on at least one of: (i) the operating conditions of the in-memory computing device; (ii) the timing scheme of the counter value provided by the global programmable non-regular counter 902; (iii) the sensing circuit relative to the global fixed V ref Source 400 or global dynamic V ref the location of source 800; and (iv) a predefined level of the sensed current.

[0192] like Fig.11 As shown in the latch 308 of , the capacitor selector circuit system 1100 can implement the first capacitor C1, the second capacitor C2 and / or the third capacitor C3. Fig.11 As shown in FIG. 1 , the capacitor selector circuit system 1100 may select (only) the first capacitor C1 to receive I cell (See binary count values ​​1111, 1110, 1101, and 1100). The capacitor selector circuit system 1100 may also implement a combination of (only) the first capacitor C1, the second capacitor C2, and the third capacitor C3 to obtain certain count values ​​(see binary count values ​​0011, 0010, 0001, and 0000, where I cell Used to charge the first capacitor C1, the second capacitor C2 and the third capacitor C3 to provide the detected voltage V c ). In addition, the capacitor selector circuit system 1100 may implement (only) the first capacitor C1 and the second capacitor C2 to obtain certain count values ​​(such as binary count values ​​0100, 0101, 0110, and 0111, where I cell Used to charge the first capacitor C1 and the second capacitor C2 to provide the detected voltage V c (not shown)). In addition, the capacitor selector circuit system 1100 may implement (only) the second capacitor C2 to obtain certain count values ​​(eg, binary count values ​​1000, 1001, 1010, and 1011), where I cell Used to charge the second capacitor C2 to provide the detected voltage V c (not shown). The selection and implementation of capacitor selector circuit system 1100 can be used to achieve the same Fig.10 The reduced time interval variation discussed above and the Fig. 9 Selection of current mirrors m1, m2 and different reference voltages V ref1 、V ref2 、V ref3 、V ref4 In addition, if Fig. 9 and Fig.10 As discussed, the global programmable non-regular counter 902 can be configured to adjust the duration between each count value (based on the selection of the capacitor selector circuit system 1100). Fig.11 As shown in , durations of 10 nanoseconds, 10 nanoseconds, 10 nanoseconds, etc. (or 30 nanoseconds, 20 nanoseconds, 10 nanoseconds, etc.) may be implemented. Other timing schemes will be apparent to those skilled in the art. Fig.11As discussed, the number of capacitors selected and / or implemented by capacitor selector circuitry 1100 and the schemes for implementing the capacitors are merely examples and the number of capacitors and the schemes for implementing the capacitors may vary from that described herein, which will be apparent to those skilled in the art.

[0193] The disclosed technology can be implemented as described above. Fig. 9 The reference voltage V ref Multiplexer 900, see above Fig.10 The current mirror selector circuit system 1000 discussed above with reference to Fig.11 Any combination of the capacitor selector circuit systems 1100 discussed.

[0194] Fig.12 is a global programmable non-conventional counter according to an embodiment of the present disclosure, a reference voltage V ref Schematic diagram of a multiplexer, current mirror selector circuitry, and capacitor selector circuitry.

[0195] Specifically, Fig.12 A globally programmable non-conventional counter 902 is shown, and the globally programmable non-conventional counter 902 includes: a CLK counter 1200 (e.g., a clock circuit), which receives a high frequency CLK (e.g., a system clock signal); a dial-in code latch (or other storage) 1202, which receives a dial-in code; a comparison (timer) 1204, which receives an output from the CLK counter 1200 and a latch output from the dial-in code latch 1202; a counter (comparison) 1206, which receives a CLK two-state flip-flop counter from the comparison (timer) 1204 and outputs bits a0, a1, a2, and a3 (e.g., a count value that is dynamically timed and continuously changed); and a selection signal output 1208 (e.g., a selection signal output circuit), which receives a control selection signal from the counter (comparison) 1206 (e.g., a non-conventional counter circuit) and outputs a first switching signal s1 and a second switching signal s2 to a reference voltage V ref Multiplexer 900 , current mirror selector circuitry 1000 , and / or capacitor selector circuitry 1100 .

[0196] Comparison (timer) 1204 receives the count value from CLK counter 1200 and compares the received count value with the latch output from the dial-in code latch 1202 to generate a toggle signal to trigger counter (compare) 1206. Therefore, based on the comparison, the comparison (timer) 1204 outputs a CLK toggle counter that instructs counter (compare) 1206 to count. When the CLK counter 1200 output hits (matches) one of the dial-in codes 1202, the comparison (timer) 1204 may be triggered once and toggle the CLK toggle counter signal. The triggered CLK toggle counter signal of the comparison (timer) 1204 may instruct the counter (compare) 1206 to count up or down once (since the counter output code is a0, a1, a2, a3) on the output of the counter (compare) 1206. The counter (compare) 1206 can also compare the counter codes a0, a1, a2, a3 with the pre-coded code, and when there is a hit (match), the control selection signal can be toggled. As described above, the counter 1206 can output the control selection signal according to the comparison result of the counter codes a0, a1, a2, a3 and the pre-coded code inside the counter (compare) 1206, so as to control the selection signal output 1208 to output the first switching signal s1 and the second switching signal s2.

[0197] Reference Fig.12 , a code (e.g., a dial-in code) can be dialed in to program the dynamic counting interval output by the counter (compare) 1206 to various local sensing circuits and can be based on different I cell The dial-in code is trained and optimized based on the conditions and field conditions such as the location of various local sensing circuits, predefined levels of sensing currents and processes, and process, voltage and temperature (PVT) variations. For example, in mass production, process parameters may be monitored and the disclosed technology may dial in optimized codes based on the monitored process parameters of the mass production environment to track process variations, etc. When a particular environment is different from the standard or changes thereto, the disclosed technology may calibrate the global programmable non-conventional counter 902 with the optimized codes, and then during use, the global programmable non-conventional counter 902 may "dial in" one of the optimized codes consistent with the monitored process parameters. For another example, during circuit operation, voltage and / or temperature conditions may be monitored and the disclosed technology may dial in optimized codes based on the monitored voltage and / or temperature conditions to track voltage and / or temperature variations.

[0198] The dial-in code can be used to program the timing scheme and conditions for outputting the first switching signal s1 and the second switching signal s2. cellvalue and / or reference voltage V ref The dial-in code is trained in the field (e.g., when used in the field) or in testing (e.g., during a specific test scenario) to learn and adopt the optimized code for the time interval of the global programmable irregular counter 902. cell The training can be done using the test pins or externally forced based on the internal current source. cell The training can use the reference memory cell current to track the memory cell variation of PVT changes / conditions for the counter interval and the reference voltage V ref Multiplexer 900, current mirror selector circuit system 1000 and / or capacitor selector circuit system 1100 implement dynamic feedback of different schemes. The use of CLK counter 1200, dial-in code latch 1202, compare (timer) 1204, latch output, CLK toggle counter, counter (compare) 1206, control signal and select signal output 1208 is only an example and other implementations can also be used to provide outputs a0 to a3, s1 and s2 based on programming code, clock signal and changing conditions of the in-memory computing device. The dial-in code can be referred to as configuration data for configuring the operation of the global programmable non-conventional counter 902.

[0199] The techniques disclosed herein are not limited to in-memory computing devices, but can be used to sense any type of memory cell, where different memory cell currents can represent different data values. In addition, the techniques disclosed herein are not limited to sensing current in memory devices but can be implemented in any device that senses current. In view of these additional configurations, the detector circuit system 306 can be any type of detector that can detect current and / or voltage. For example, the detector circuit system 306 can detect the memory cell current from the memory cell, the mirror current and / or the current from the charging voltage in the capacitor. The disclosed techniques (such as sensing circuits) can be implemented in a system process control block (PCB) and do not necessarily need to be implemented inside a memory chip or an in-memory computing device.

[0200] The global programmable non-conventional counter 902 and any other counter described herein do not necessarily need to be a binary counter. It can also be a circuit system that outputs any output signal at a dynamic time interval, so that the output signal can be used to (i) latch data according to different and changing time intervals to perform the same or similar functions as the non-conventional counter; and / or (ii) control any reference voltage V ref Multiplexer 900, current mirror selector circuit system 1000 and / or capacitor selector circuit system 1100 may be used to implement the same or similar functions as a programmable non-conventional counter.

[0201] Other embodiments of the methods described in this section may include a non-transitory computer-readable storage medium storing instructions executable by a processor to perform any of the methods described above. Yet another embodiment of the methods described in this section may include a system comprising a memory and one or more processors operable to execute the instructions stored in the memory to perform any of the methods described above.

[0202] Any of the data structures and codes described or mentioned above according to many embodiments are stored on a computer-readable storage medium, which can be any device or medium that can store code and / or data for use by a computer system, including but not limited to volatile memory, non-volatile memory, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), magnetic and optical storage devices (such as disk drives, tapes, compact discs (CDs), digital versatile discs or digital video discs (DVDs), or other media capable of storing computer-readable media now known or later developed.

[0203] Many of the diagrams described herein reflect logic executed by a memory controller or memory device. The logic can be implemented using a processor that is stored in a memory accessible by a computer system and executable by a processor, programmed by dedicated logic hardware (including field programmable integrated circuits), and by a combination of dedicated logic hardware and computer programs. For all flowcharts herein, it will be understood that many steps can be combined, implemented in parallel, or implemented in a different order without affecting the functions achieved. In some cases, as the reader will understand, the rearrangement of steps will achieve the same result only if certain other changes are made. In other cases, as the reader will understand, the rearrangement of steps will achieve the same result only if certain conditions are met. In addition, it will be understood that the flowcharts herein only show steps relevant to the understanding of the present invention, and it will be understood that before, after, and between the steps shown, many additional steps for achieving other functions can be implemented.

[0204] Although the present invention is disclosed by reference to the preferred embodiments and examples described above, it should be understood that these examples are intended to be illustrative rather than restrictive. It is expected that modifications and combinations will be easily conceived by those skilled in the art, and these modifications and combinations will be within the spirit of the present invention and the scope of the appended claims.

Claims

1. A memory sensing circuit, characterized in that: include: A memory cell array, comprising a plurality of bit lines and a plurality of word lines; a plurality of sensing circuits configured to sense a difference between a first current and a second current on corresponding ones of a plurality of selected ones of the plurality of bit lines and to generate a plurality of outputs for the plurality of selected bit lines based on the difference; as well as a globally programmable non-regular counter configured to provide a count value to each of the plurality of sensing circuits in dependence on a clock signal, Each of the plurality of sensing circuits comprises: (i) a local detector circuit configured to detect a voltage (V c ) for detection; and (ii) a reference voltage selector configured to receive one or more reference voltages from a global dynamic voltage reference source and select a single reference voltage (V ref ),and Each of the plurality of sensing circuits generates an output depending on: (i) the detected voltage (V c ) and the selected single reference voltage (V ref ) between; and (ii) a stored count value received from the global programmable non-regular counter, the count value being dependent on the detected voltage (V c ) and the selected single reference voltage (V ref ) and is stored.

2. The memory sensing circuit according to claim 1, characterized in that: wherein the reference voltage selector is enabled to select the single reference voltage (V ref ).

3. The memory sensing circuit according to claim 2, characterized in that: The one or more switching signals are generated dependent on the clock signal and are received from the global programmable non-regular counter.

4. The memory sensing circuit according to claim 3, characterized in that: wherein the one or more switching signals are configured to enable the single reference voltage (V ref ): (i) operating conditions of the circuit; (ii) a timing scheme for a plurality of counter values ​​provided by the global programmable non-regular counter; (iii) the locations of the plurality of sensing circuits relative to the global dynamic voltage reference source; and (iv) a predefined level of sensing current.

5. The memory sensing circuit according to claim 1, wherein: The one or more reference voltages include at least four reference voltages.

6. The memory sensing circuit according to claim 1, wherein: The global dynamic voltage reference source generates the one or more reference voltages depending on at least one of: (i) an operating condition of the circuit; and (ii) a position of the plurality of sensing circuits relative to the global dynamic voltage reference source.

7. The memory sensing circuit according to claim 1, wherein: wherein the local detector circuit is configured to be dependent on the detected voltage (V c ) and the selected single reference voltage (V ref ) to generate a trigger signal.

8. The memory sensing circuit according to claim 7, characterized in that: wherein each of the plurality of sensing circuits comprises a memory configured to store a specific count value provided by the global programmable non-regular counter, and The storing of the specific count value is performed depending on the trigger signal.

9. The memory sensing circuit according to claim 7, characterized in that: The local detector circuit includes a comparator configured to (i) detect the voltage (V c ) and the selected single reference voltage (V ref ) for comparison; and (ii) due to the detected voltage (V c ) reaches or exceeds the selected single reference voltage (V ref ) to generate the trigger signal.

10. The memory sensing circuit according to claim 1, wherein: Each of the plurality of sensing circuits comprises: A current manipulator circuit is configured to sense the difference between a first sensing current (10) and a second sensing current (I1) and output a current (I cell );as well as A current mirror selector circuit system is configured to receive the current (I cell ) and selecting one or more current mirrors from a plurality of current mirrors, the selected one or more current mirrors receiving a voltage for providing the detected voltage (V c ) of the current (I cell ).

11. The memory sensing circuit according to claim 10, characterized in that: The current mirror selector circuitry is configured to select the one or more current mirrors in dependence on one or more switching signals.

12. The memory sensing circuit according to claim 11, characterized in that: The one or more switching signals are generated dependent on the clock signal and are received from the global programmable non-regular counter.

13. The memory sensing circuit according to claim 12, wherein: wherein the one or more switching signals are configured to select the one or more current mirrors in dependence upon at least one of: (i) an operating condition of the circuit; (ii) a timing scheme of multiple counter values ​​provided by the global programmable non-regular counter; (iii) a position of the multiple sensing circuits relative to the global dynamic voltage reference source; and (iv) a predefined level of sensing current.

14. The memory sensing circuit according to claim 10, wherein: Each of the plurality of sensing circuits comprises a capacitor configured to receive the current (I cell ) of the mirror current, storing charges depending on the received mirror current and detecting the voltage (V c ) is provided to the local detector circuit, which triggers the storage of the count value received from the global programmable non-regular counter.

15. The memory sensing circuit according to claim 10, wherein: Each of the plurality of sensing circuits comprises: a plurality of capacitors; and a capacitor selector circuitry configured to select one or more capacitors from the plurality of capacitors, wherein the selected one or more capacitors are configured to receive the current (I cell ), depending on the received current (I cell ) to store charge and to detect the voltage (V c ) is provided to the local detector circuit, which triggers the storage of the count value received from the global programmable non-regular counter.

16. The memory sensing circuit according to claim 15, characterized in that: The capacitor selector circuitry selects the one or more capacitors in dependence on one or more switching signals.

17. The memory sensing circuit according to claim 16, wherein: The one or more switching signals are generated dependent on the clock signal and are received from the global programmable non-regular counter.

18. The memory sensing circuit according to claim 17, characterized in that: wherein the one or more switching signals are configured to enable selection of the one or more capacitors in dependence upon at least one of: (i) an operating condition of the circuit; (ii) a timing scheme of a plurality of counter values ​​provided by the globally programmable non-regular counter; and (iii) the locations of the plurality of sensing circuits relative to the global dynamic voltage reference source.

19. A memory sensing circuit, characterized in that: include: a plurality of sensing circuits configured to sense a difference between a first current and a second current on corresponding bit lines of a plurality of selected bit lines of a memory cell array and to generate a plurality of outputs of the plurality of selected bit lines according to the difference, Each of the plurality of sensing circuits comprises: (i) a local detector circuit configured to detect a voltage (V c ) for detection; and (ii) a reference voltage selector configured to receive one or more reference voltages from a global dynamic voltage reference source and select a single reference voltage (V ref ),and Each of the plurality of sensing circuits generates an output depending on: (i) the detected voltage (V c ) and the selected single reference voltage (V ref ) between the detected voltage (V c ) and the selected single reference voltage (V ref ) and is stored.

20. A globally programmable non-conventional counter circuit, characterized in that: include: a storage device configured to store configuration data; a clock circuit configured to receive a system clock signal; a non-conventional counter circuit configured to provide a dynamic timing count value to a plurality of sensing circuits dependent on the stored configuration data and the received system clock signal, the plurality of sensing circuits configured to sense a difference between a first current and a second current to generate a plurality of outputs for a plurality of selected bit lines based on the difference; as well as The selection signal output circuit is configured to output one or more switching signals depending on the stored configuration data, the received system clock signal and the dynamic timing count value to control the operation of at least one of the following: (i) a current mirror selector circuit system configured to receive a current (I cell ) and selects one or more current mirrors from a plurality of current mirrors to receive the current (I cell ); (ii) a capacitor selector circuit system configured to select one or more capacitors from a plurality of capacitors, the selected one or more capacitors receiving the current (I cell ) and stores charge to provide a voltage (V c ); and (iii) a reference voltage selector configured to select a single reference voltage (V ref ).

Images