Method for accessing flash memory module and related flash memory controller and memory device

Abstract

The invention discloses a method for accessing a flash memory module, a related flash memory controller and a memory device. The method for accessing the flash memory module comprises the following steps of: respectively reading a first logic data page of an entity data page in the flash memory module by using a first group of critical voltages, a first group of positively adjusted critical voltages and a first group of negatively adjusted critical voltages, respectively obtaining a piece of first read information, a piece of second read information and a piece of third read information; decoding the first read information, the second read information and the third read information to generate decoded data of the first logical data page; and generating an LLR mapping table according to the decoded data of the first logical data page, the first read information, the second read information and the third read information.

Description

Technical Field

[0001] The present invention relates to a flash memory controller. Background Art

[0002] Flash memory can be erased and written / programmed electronically to store data, and is widely used in memory cards, solid-state drives, portable multimedia players, etc. Since flash memory is non-volatile, no additional power is required to maintain the information stored in the flash memory. In addition, flash memory can provide fast data reading and better shock resistance, and these characteristics also explain why flash memory is so popular.

[0003] Flash memory can be divided into NOR flash memory and NAND flash memory. NAND flash memory has shorter erase and write time and each memory cell requires less chip area, so NAND flash memory allows higher storage density and lower cost per storage bit compared to NOR flash memory. Generally speaking, flash memory stores data in the form of a memory cell array, and the memory cell is implemented by a floating-gate transistor, and each memory cell can store a single bit of information or more than one bit of information by appropriately controlling the number of charges on the floating gate of the floating gate transistor to set the required threshold voltage for turning on the memory cell implemented by the floating gate transistor. In this way, when one or more predetermined gate control voltages are applied to the control gate of the floating gate transistor, the conduction state of the floating gate transistor will indicate one or more binary digits stored in the floating gate transistor.

[0004] However, due to certain factors, the number of charges originally stored in the memory cell may be affected / disturbed. For example, the disturbance in the flash memory may come from write disturbance (write / program disturbance), read disturbance (read disturbance) and / or retention disturbance (retention disturbance). Taking a NAND flash memory having memory cells each storing more than one bit of information as an example, a physical memory page (physical page) includes multiple logical data pages (logical page), and each logical data page is read using one or more gate control voltages. For example, for a memory cell for storing 4 bits of information, the memory cell will have one of 16 states (i.e., charge levels) corresponding to different numbers of charges (i.e., different threshold voltages). However, due to the program / erase count (P / E count) and / or data retention time, the threshold voltage distribution of the memory cell in the memory cell will change. Therefore, using the original gate control voltage setting (i.e., threshold voltage setting) to read the information stored in the memory cell may not correctly obtain the stored information due to the changed threshold voltage distribution. Summary of the invention

[0005] Therefore, one of the objectives of the present invention is to provide a flash memory controller and a related control method, which can efficiently establish / update a log-likelihood ratio (LLR) mapping table according to the read information of the flash memory for subsequent decoding, so as to solve the problems described in the prior art.

[0006] In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, which includes the following steps: using a first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read a first logical data page of a physical data page in the flash memory module to obtain a first readout information, a second readout information, and a third readout information, respectively; decoding the first readout information, the second readout information, and the third readout information to generate decoded data of the first logical data page; generating an LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information, and the third readout information for subsequent use in reading and decoding other logical data pages.

[0007] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read-only memory for storing a program code; a buffer memory; and a microprocessor for executing the program code to control access to the flash memory module; wherein the microprocessor is used to perform the following operations: respectively use a first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read a first logical data page of a physical data page in the flash memory module to obtain a first readout information, a second readout information, and a third readout information respectively; decode the first readout information, the second readout information, and the third readout information to generate a decoded data of the first logical data page; and generate an LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information, and the third readout information for subsequent use in reading and decoding other logical data pages.

[0008] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory controller performs the following operations: using a first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read a first logical data page of a physical data page in the flash memory module, respectively, to obtain a first readout information, a second readout information, and a third readout information, respectively; decoding the first readout information, the second readout information, and the third readout information to generate a decoded data of the first logical data page; generating an LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information, and the third readout information, for subsequent use in reading and decoding other logical data pages. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0010] Figure 2 A schematic diagram of a block included in a flash memory module.

[0011] Figure 3 FIG. 4 is a schematic diagram showing that each memory unit is used to store 4 bits according to an embodiment of the present invention.

[0012] Figure 4 Schematic diagram showing that the distribution of each state of a memory cell is shifted or broadened.

[0013] Figure 5FIG. 4 is a flow chart of a method for accessing a flash memory module according to an embodiment of the present invention.

[0014] Figure 6 FIG. 1 is a schematic diagram of using different threshold voltages to read data pages according to an embodiment of the present invention.

[0015]

Explanation of symbols

[0016] 100: Memory device

[0017] 103: Memory Unit

[0018] 110: Flash memory controller

[0019] 112: Microprocessor

[0020] 112M: Read-only memory

[0021] 112C: Program code

[0022] 114: Control Logic

[0023] 116: Buffer memory

[0024] 118: Interface Logic

[0025] 120: Flash memory module

[0026] 130: Main device

[0027] 132: Encoder

[0028] 134:Decoder

[0029] 136: Control unit

[0030] 138: LLR mapping table generation / update unit

[0031] 200: Block

[0032] 500~516: Steps

[0033] M_0~M_K: memory unit

[0034] P_0~P_N: Entity data page

[0035] VG_0~VG_N: Gate control voltage

[0036] B0~BK: bit value

[0037] S0~S15: Status

[0038] VT1~VT15: critical voltage

[0039] VT1', VT11': adjusted critical voltage DETAILED DESCRIPTION

[0040] Figure 1 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a control unit 136, and an LLR mapping table generation / update unit 138, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or Error Correction Code, ECC), and the decoder 134 is used to decode the data read from the flash memory module 120. In addition, the control unit 136 and the LLR mapping table generation / update unit 138 are implemented by circuit elements, and their specific operations will be described in the subsequent embodiments.

[0041] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a block. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.

[0042] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform a variety of control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.

[0043] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0044] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, no further explanation is given in the specification.

[0045] Figure 2 Schematic diagram of a block 200 included in a flash memory module 120, wherein the block 200 includes a plurality of physical data pages P_0, P_1, P_2, ..., P_N, and each of the physical data pages P_0-P_N includes a plurality of memory cells (e.g., floating gate transistors) 103. For example, for a target physical data page P_0 to be read, it includes memory cells M_0-M_K. In order to read the data stored in the memory cells M_0-M_K of the target physical data page P_0, the gate control voltages VG_0-VG_N should be appropriately set to read a plurality of bit values ​​B0-BK from the memory cells M_0-M_K, respectively. If each memory cell 103 is used to store N bits, that is, the target physical data page P_0 includes N logical data pages, the flash memory 102 sets the gate control voltage VG_0 to (2N-1) voltage levels to identify the N bits of each memory cell 103 in the target physical data page P_0.

[0046] Figure 3 FIG. 1 is a schematic diagram showing that each memory unit 103 is used to store 4 bits according to an embodiment of the present invention. Figure 3As shown, each memory cell can have sixteen states, and each state represents a different combination of four bits (named as top bit, upper bit, middle bit, and lower bit). Figure 3In the embodiment shown, when the memory cell is programmed to have state S0, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 1); when the memory cell is programmed to have state S1, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 0); when the memory cell is programmed to have state S2, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 1, 0); when the memory cell is programmed to have state S3, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 0, 0); ,0); when the memory cell is programmed to have state S4, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1,0,0,1); when the memory cell is programmed to have state S5, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,1); when the memory cell is programmed to have state S6, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,0); when the memory cell is programmed to have state S7, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,1,0); When the memory cell is programmed to have state S8, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 1, 0); when the memory cell is programmed to have state S9, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 0, 0); when the memory cell is programmed to have state S10, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 0); when the memory cell is programmed to have state S11, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 1); The memory cell is programmed to have a state S12, and the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (0, 1, 0, 1); when the memory cell is programmed to have a state S13, the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (0, 1, 1, 1); when the memory cell is programmed to have a state S14, the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (0, 0, 1, 1); and when the memory cell is programmed to have a state S15, the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (1, 0, 1, 1).

[0047] In the related art, taking data page P_0 as an example, when the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 having four threshold voltages VT5, VT10, VT12 and VT15 to read the memory cell. If the memory cell is conductive when the critical voltage VT5 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT5 is applied and the memory cell is conductive when the critical voltage VT10 is applied, the top bit is determined to be "0"; if the memory cell is non-conductive when the critical voltage VT10 is applied and the memory cell is conductive when the critical voltage VT12 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT12 is applied and the memory cell is conductive when the critical voltage VT15 is applied, the top bit is determined to be "0"; and if the memory cell is non-conductive when the critical voltage VT15 is applied, the top bit is determined to be "1". When the upper bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply the gate control voltage VG_0 having three threshold voltages VT2, VT8 and VT14 to read the memory cell. If the memory cell is conductive when the threshold voltage VT2 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the threshold voltage VT2 is applied and the memory cell is conductive when the threshold voltage VT8 is applied, the upper bit is determined to be "0"; if the memory cell is non-conductive when the threshold voltage VT8 is applied and the memory cell is conductive when the threshold voltage VT14 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the threshold voltage VT14 is applied, the upper bit is determined to be "0". When the middle bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 having four threshold voltages VT3, VT7, VT9 and VT13 to read the memory cell.If the memory cell is conductive when the critical voltage VT3 is applied, the intermediate bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT3 is applied and the memory cell is conductive when the critical voltage VT7 is applied, the intermediate bit is determined to be "0"; if the memory cell is non-conductive when the critical voltage VT7 is applied and the memory cell is conductive when the critical voltage VT9 is applied, the intermediate bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT9 is applied and the memory cell is conductive when the critical voltage VT13 is applied, the intermediate bit is determined to be "0"; and if the memory cell is non-conductive when the critical voltage VT13 is applied, the intermediate bit is determined to be "1". When the lower bit needs to be read by the flash memory controller 110 , the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 having four threshold voltages VT1 , VT4 , VT6 , and VT11 to read the memory cell. If the memory cell is conductive when the critical voltage VT1 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT1 is applied and the memory cell is conductive when the critical voltage VT4 is applied, the lower bit is determined to be "0"; if the memory cell is non-conductive when the critical voltage VT4 is applied and the memory cell is conductive when the critical voltage VT6 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT6 is applied and the memory cell is conductive when the critical voltage VT11 is applied, the lower bit is determined to be "0"; and if the memory cell is non-conductive when the critical voltage VT11 is applied, the lower bit is determined to be "1".

[0048] It should be noted that Figure 3 The gray code shown is for illustrative purposes only and is not intended to limit the present invention. Any suitable gray code can be used in the memory device 100, and the threshold voltages used to determine the top bit, the upper bit, the middle bit, and the lower bit can be changed accordingly.

[0049] However, the flash memory module 120 may be damaged due to some factors, such as an increase in the number of write / read times and / or data retention time. Figure 3 The distribution of each state shown is shifted or widened, so that the threshold voltage used to read the memory cell is no longer the most suitable threshold voltage. Figure 4For example, due to the influence of the number of write / read times and / or data retention time of the flash memory module 120, the state S0 and the state S1 become wider and shift to the left, and the best threshold voltage should correspond to the intersection of the distribution of the state S0 and the state S1, that is, VT1' shown in the figure; at this time, if the original threshold voltage VT1 is used to read the memory cell, the read data will have a higher error, which may cause problems in the processing of the decoder 134. Similarly, due to the influence of the number of write / read times and / or data retention time of the flash memory module 120, the state S10 and the state S11 become wider and shift to the right, and the best threshold voltage should correspond to the intersection of the distribution of the state S10 and the state S11, that is, VT11' shown in the figure; at this time, if the original threshold voltage VT11 is used to read the memory cell, the read data will have a higher error, which may cause problems in the processing of the decoder 134. Therefore, in order to solve the problem of state distribution deviation and / or widening of the above-mentioned memory unit, the present invention proposes a control method, which can generate / update the LLR mapping table according to the data that has been successfully decoded to increase the probability of successful decoding of the subsequently read data.

[0050] Figure 5 Flowchart of a method for accessing a flash memory module 120 according to an embodiment of the present invention. At step 500, the process starts. At step 502, the microprocessor 112 in the flash memory controller 110 receives a read instruction, such as a read instruction from the host device 130, to start reading a first logical data page in a physical data page. Specifically, the microprocessor 112 transmits a read request to the flash memory module 120 through the control logic 114 to request to read the first logical data page. After receiving the read request, the flash memory module 120 uses a first set of threshold voltages to read a segment of the first logical data page to obtain a readout information. For the convenience of the following description, the physical data page is represented by Figure 2 Taking the physical data page P_0 as an example, each memory cell in the physical data page P_0 can store 4 bits, that is, the physical data page P_0 includes four logical data pages, and the four logical data pages are used to store Figure 3 The top bit, upper bit, middle bit and lower bit are shown; in addition, in the following description, the first logical data page is a logical data page used to store the upper bit.

[0051] In step 504, the decoder 134 of the flash memory controller 110 performs a decoding operation on the readout information of a segment of the first logical data page. Figure 3The first set of threshold voltages for reading the first logical data page includes Figure 3 As shown or Figure 6 The threshold voltages VT2, VT8, and VT14 are shown. In addition, the segment in the first logical data page read may be a coding unit, the size of which may be 4 kilobytes (KB) or other suitable sizes, and the decoding process of the segment by the decoder 134 may be a hard decoding, wherein the hard decoding may be a decoding method of a BCH code (Bose-Chaudhuri-Hocquenghem code) or a low-density parity-check code (LDPC). Since the decoding operation of the decoder 134 is well known to those having ordinary knowledge in the art, the details of the decoding operation are not repeated here.

[0052] In step 506 , the decoder 134 determines whether the read information of the segment can be decoded successfully. If the decoding is successful, the process proceeds to step 518 to end the read operation of the segment of the first logical data page; if the decoding fails, the process proceeds to step 508 .

[0053] In step 508, the flash memory controller 110 obtains a first readout information, a second readout information, and a third readout information of the segment of the first logical data page, wherein the first readout information, the second readout information, and the third readout information are obtained by the flash memory module 120 using the first set of threshold voltages, the first set of threshold voltages adjusted positively, and the first set of threshold voltages adjusted negatively to read the segment of the first logical data page. In one embodiment, the first readout information may be the readout information mentioned in step 502, and the readout information temporarily stored in the control logic 114 may be directly used as the first readout information of step 508. Figure 6 For example, the control unit 136 of the flash memory controller 110 may send a read request to the flash memory module 120 to use the positively adjusted first set of threshold voltages, i.e., the threshold voltages (VT2+Δ), (VT8+Δ), (VT14+Δ) to read the first logical data page to obtain the second read information, where "Δ" may be any suitable adjustment value (voltage value); then, the control unit 136 of the flash memory controller 110 may send another read request to the flash memory module 120 to use the negatively adjusted first set of threshold voltages, i.e., the threshold voltages (VT2-Δ), (VT8-Δ), (VT14-Δ) to read the first logical data page to obtain the third read information. In this embodiment, the first read information, the second read information, and the third read information are temporarily stored in a buffer area in the control logic 114.

[0054] In this embodiment, assuming that the size of the segment of the first logical data page is 4 KB (ie, 32768 bits), each of the first read information, the second read information, and the third read information also includes 32768*3 bits.

[0055] In step 510, the decoder 134 uses a preset LLR mapping table to soft decode the segment of the first logical data page. Specifically, each bit in the first readout information can be regarded as a hard bit or a sign bit, and each bit in the second readout information and the third readout information is regarded as a soft bit. For each memory cell, it will have three bits of information, namely, a hard bit, a first soft bit and a second soft bit, which are represented by (BH, BS1, BS2) below. In addition, the above three bits of information (BH, BS1, BS2) can have eight combinations, which are (1, 1, 1), (1, 1, 0), (1, 0, 1), (1, 0, 0), (0, 1, 1), (0, 1, 0), (0, 0, 1), (0, 0, 0). The preset LLR mapping table includes (BH, BS1, BS2) and corresponding LLR values, wherein the LLR value is used to reflect the relative reliability. For example, if (BH, BS1, BS2) is equal to (1, 1, 1), it means that the upper bit of the memory cell has the highest reliability of "1" (for example, 99% reliability is "1"); if (BH, BS1, BS2) is equal to (1, 1, 0), it means that the upper bit of the memory cell has the second highest reliability of "1"; if (BH, BS1, BS2) is equal to (0, 1, 1), it means that the upper bit of the memory cell has the highest reliability of "0", ..., and so on. After the LLR value of each memory cell is determined according to the preset LLR mapping table, the LDPC decoding circuit in the decoder 134 can start to perform soft decoding on the segment of the first logical data page based on these LLR values. In addition, since the operations of the LLR mapping table and LDPC soft decoding are well known to those skilled in the art, these details are not described herein.

[0056] In step 512 , the decoder 134 determines whether the segment can be decoded successfully. If the decoding fails, the process proceeds to step 514 ; if the decoding succeeds, the process proceeds to step 516 .

[0057] In step 514, if the control logic 114 includes other LLR mapping tables, the decoder 134 uses the other LLR mapping tables to soft-decode the segment of the first logical data page. In addition, if all LLRs have been used and cannot successfully decode the segment of the first logical data page, the decoder 134 can perform decoding through other suitable decoding methods, such as redundant array of independent disks (RAID) decoding methods.

[0058] In step 516, the LLR mapping table generation / update unit 138 generates a new LLR mapping table according to the decoded data, the first read information, the second read information and the third read information of the segment of the first logical data page, for use by the subsequent decoder 134 when decoding other segments. Specifically, the decoded data, the first read information, the second read information and the third read information have the same number of bits, for example, 32768 bits, and for each memory cell, it has four bits of information, namely, the decoded bit, the hard bit, the first soft bit and the second soft bit, which are hereinafter represented by (DD, BH, BS1, BS2). In addition, the above four bits of information (DD, BH, BS1, BS2) can have 16 combinations, which are (1,1,1,1), (1,1,1,0), (1,1,0,1), (1,1,0,0), (1,0,1,1), (1,0,1,0), (1,0,0,1), (1,0,0,0), (0,1,1,1), (0,1,1,0), (0,1,0,1), (0,1,0,0), (0,0,1,1), (0,0,1,0), (0,0,0,1), (0,0,0,0,1), (0,0,0,0,0). The 16 combinations of the four-bit information (DD, BH, BS1, BS2) represent various combinations with different reliability and whether the decoded bit and the hard bit are the same. For example, (DD, BH, BS1, BS2) equals (1, 1, 1, 1) means that the decoded bit and the hard bit are both "1" and have the highest reliability, that is, the upper bit of the memory cell has the highest reliability of "1" in the read information before decoding, and the decoded bit is indeed "1"; (DD, BH, BS1, BS2) equals (0, 1, 1, 1) means that the upper bit of the memory cell has the highest reliability of "1" in the decoded information. The highest reliability of the read information before the code is "1", but the bit after decoding is "0"; (DD, BH, BS1, BS2) equals (0, 0, 1, 1) means that the decoded bit and the hard bit are both "0" and have the highest reliability, that is, the upper bit of the memory cell has the highest reliability of "0" in the read information before decoding, and the decoded bit is indeed "0"; (DD, BH, BS1, BS2) equals (1, 0, 1, 1) means that the upper bit of the memory cell has the highest reliability of "0" in the read information before decoding, but the decoded bit is "1". The LLR mapping table generation / update unit 138 counts the 16 combinations of the above four bits of information (DD, BH, BS1, BS2) according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information to calculate the number of each combination, and calculates the LLR value corresponding to (BH, BS1, BS2) in a new LLR mapping table accordingly.For example, assuming that the number of (DD, BH, BS1, BS2) equal to (1, 1, 1, 1) is N1, and the number of (DD, BH, BS1, BS2) equal to (1, 0, 1, 1) is N2, then in one embodiment, the LLR value corresponding to (BH, BS1, BS2) equal to (1, 1, 1) in the new LLR mapping table can be calculated as follows: ln(N1 / N2). In another example, assuming that the number of (DD, BH, BS1, BS2) equal to (0, 0, 1, 1) is N3, and the number of (DD, BH, BS1, BS2) equal to (1, 1, 1, 1) is N4, then in one embodiment, the LLR value corresponding to (BH, BS1, BS2) equal to (0, 1, 1) in the new LLR mapping table can be calculated as follows: ln(N3 / N4). Similarly, any of the other combinations of (BH, BS1, BS2) in the new LLR mapping table can also be obtained through the count values ​​of the two combinations of (DD, BH, BS1, BS2) (that is, dividing the count values ​​of the two combinations and taking the logarithm). Since a person with ordinary knowledge in the art should be able to understand how to calculate other LLR values ​​after reading the above embodiments, the calculation method of all LLR values ​​is not listed here.

[0059] Next, the LLR mapping table generation / update unit 138 temporarily stores the new LLR mapping table in the storage unit in the control logic 114. In one embodiment, if the LLR mapping table generation / update unit 138 has previously generated a certain number of LLR mapping tables and the storage unit has insufficient space, the LLR mapping table generation / update unit 138 may use the new LLR mapping table to replace the previously generated LLR mapping table for subsequent use by the decoder 134 in step 514 when decoding other segments of the first logical data page or decoding blocks of other logical data pages.

[0060] As described above, since the new LLR mapping table is generated through the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information, it can more accurately reflect the threshold voltage offset of the memory cell in the block 200 or the physical data page P_0. Therefore, by establishing the new LLR mapping table, the decoder 134 can have a higher success rate when decoding the subsequent segments.

[0061] In the above embodiment, the new LLR mapping table is used for the threshold voltages VT2, VT8, and VT14 used for reading the first logical data page of the physical data page P_0. However, since the distribution offset of each state S0-S15 of the memory cell is different, that is, the offset direction and offset amount of the threshold voltages VT1-VT15 are also different, the above new LLR mapping table is still limited in improving the decoding capability of the decoder 134. Therefore, in another embodiment of the present invention, the LLR mapping table generation / update unit 138 generates a new LLR mapping table for each of the threshold voltages VT2, VT8, and VT14 for use by each of the threshold voltages VT2, VT8, and VT14.

[0062] Specifically, in step 516, after obtaining the decoded data, the first readout information, the second readout information, and the third readout information of the segment of the first logical data page of the physical data page P_0, the control unit 136 transmits one or more read requests to obtain the decoded data of the segment of the second logical data page of the physical data page P_0 and the decoded data of the segment of the third logical data page of the physical data page P_0. In the present embodiment, the purpose of reading the decoded data of the segment of the second logical data page and the decoded data of the segment of the third logical data page is to identify which of the threshold voltages VT2, VT8, and VT14 the decoded data, the first readout information, the second readout information, and the third readout information of the segment of the first logical data page correspond to. Therefore, the selection of the second logical data page and the third logical data page needs to meet the following conditions: (1) The two states adjacent to each of the threshold voltages VT2, VT8, and VT14 in the first set of threshold voltages are located in the first set of threshold voltages. The second logical data page corresponds to the same bit value, and the third logical data page also corresponds to the same bit value; the two adjacent states of each of the threshold voltages VT2, VT8, and VT14 in the first set of threshold voltages have different (b1, b2) combinations in the bit value (b1) corresponding to the second logical data page and the bit value (b2) corresponding to the third logical data page, and each of the threshold voltages VT2, VT8, and VT14 corresponds to (b1, b2) equal to three of (1, 1), (1, 0), (0, 1), and (0, 0). Figure 3Taking an example for explanation, the second logical data page and the third logical data page can be used to store the logical data pages of the top bit and the bottom bit, respectively, wherein the two states S1 and S2 adjacent to the critical voltage VT2 have a first combination (1,0) in the bit values ​​corresponding to the second logical data page and the bit values ​​corresponding to the third logical data page, the two states S7 and S8 adjacent to the critical voltage VT8 have a second combination (0,0) in the bit values ​​corresponding to the second logical data page and the bit values ​​corresponding to the third logical data page, and the two states S13 and S14 adjacent to the critical voltage VT14 have a third combination (0,1) in the bit values ​​corresponding to the second logical data page and the bit values ​​corresponding to the third logical data page.

[0063] Next, when the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have the first combination (1,0), the LLR mapping table generation / update unit 138 generates a first LLR mapping table according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information for use by the subsequent decoder 134 when decoding other segments, wherein the first LLR mapping table is used by the decoder 134 when subsequently using the threshold voltages VT2, (VT2-Δ), (VT2+Δ) to read the memory cell. In addition, when the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a second combination (0,0), the LLR mapping table generation / update unit 138 generates a second LLR mapping table according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information for use by the subsequent decoder 134 when decoding other segments, wherein the second LLR mapping table is used by the decoder 134 when subsequently using the threshold voltages VT8, (VT8-Δ), (VT8+Δ) to read the memory cell. Finally, when the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a third combination (0, 1), the LLR mapping table generation / update unit 138 generates a third LLR mapping table according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information for use by the subsequent decoder 134 when decoding other segments, wherein the third LLR mapping table is used by the decoder 134 when subsequently using the threshold voltages VT14, (VT14-Δ), (VT14+Δ) to read the memory cell.

[0064] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for accessing a flash memory module, comprising: Using a first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read a first logical data page of a physical data page in the flash memory module, respectively, to obtain a first readout information, a second readout information, and a third readout information, respectively; Decoding the first read information, the second read information and the third read information to generate decoded data of the first logical data page; A log-likelihood ratio (LLR) mapping table is generated according to the decoded data of the first logical data page, the first read information, the second read information and the third read information for subsequent use in reading and decoding other logical data pages.

2. The method according to claim 13, characterized in that The first group of critical voltages at least includes a first critical voltage, a second critical voltage and a third critical voltage; the first group of critical voltages after positive adjustment includes the first critical voltage plus an adjustment value, the second critical voltage plus the adjustment value and the third critical voltage plus the adjustment value; and the first group of critical voltages after negative adjustment includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value and the third critical voltage minus the adjustment value.

3. The method according to claim 1, characterized in that The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; and the first readout information includes a hard bit of each memory cell, the second readout information includes a first soft bit of each memory cell, and the third readout information includes a first soft bit of each memory cell; and the step of generating the LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information and the third readout information includes: According to the decoded data, the first read information, the second read information and the third read information of the first logical data page, 16 combinations of the decoded data, the hard bit, the first soft bit and the second soft bit are counted to calculate the number of each combination of the decoded data, the hard bit, the first soft bit and the second soft bit for calculating the LLR mapping table.

4. The method according to claim 1, characterized in that The decoded data is a first decoded data, and the method further comprises: Using a second set of threshold voltages to read a second logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data; Using a third set of threshold voltages to read a third logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a third decoded data; and The step of generating the LLR mapping table according to the decoded data of the first logical data page, the first read information, the second read information and the third read information comprises: At least a first LLR mapping table, a second LLR mapping table, and a third LLR mapping table are generated according to the decoded data of the first logical data page, the first read information, the second read information, the third read information, the second decoded data of the second logical data page, and the third decoded data of the third logical data page.

5. The method according to claim 4, characterized in that The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; two states adjacent to each threshold voltage in the first set of threshold voltages correspond to the same bit value in the second logical data page and also correspond to the same bit value in the third logical data page; two states adjacent to each threshold voltage in the first set of threshold voltages correspond to different combinations of bit values ​​in the second logical data page and in the third logical data page; and the steps of generating at least the first LLR mapping table, the second LLR mapping table and the third LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information, the third readout information, the second decoded data of the second logical data page and the third decoded data of the third logical data page include: When the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a first combination, the first LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information; When the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a second combination, the second LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information; as well as When the bit values ​​corresponding to the second logical data page and the bit values ​​corresponding to the third logical data page have a third combination, the third LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information.

6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller comprises: A read-only memory for storing a program code; a buffer memory; and a microprocessor for executing the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: Using a first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read a first logical data page of a physical data page in the flash memory module, respectively, to obtain a first readout information, a second readout information, and a third readout information, respectively; Decoding the first read information, the second read information and the third read information to generate decoded data of the first logical data page; A log-likelihood ratio (LLR) mapping table is generated according to the decoded data of the first logical data page, the first read information, the second read information and the third read information for subsequent use in reading and decoding other logical data pages.

7. The flash memory controller according to claim 6, wherein: The first group of critical voltages at least includes a first critical voltage, a second critical voltage and a third critical voltage; the first group of critical voltages after positive adjustment includes the first critical voltage plus an adjustment value, the second critical voltage plus the adjustment value and the third critical voltage plus the adjustment value; and the first group of critical voltages after negative adjustment includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value and the third critical voltage minus the adjustment value.

8. The flash memory controller according to claim 6, wherein: The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; and the first readout information includes a hard bit of each memory cell, the second readout information includes a first soft bit of each memory cell, and the third readout information includes a first soft bit of each memory cell; and the step of generating the LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information and the third readout information includes: According to the decoded data, the first read information, the second read information and the third read information of the first logical data page, 16 combinations of the decoded data, the hard bit, the first soft bit and the second soft bit are counted to calculate the number of each combination of the decoded data, the hard bit, the first soft bit and the second soft bit for calculating the LLR mapping table.

9. The flash memory controller according to claim 6, wherein: The decoded data is a first decoded data, and the method further comprises: Using a second set of threshold voltages to read a second logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data; Using a third set of threshold voltages to read a third logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a third decoded data; and The step of generating the LLR mapping table according to the decoded data of the first logical data page, the first read information, the second read information and the third read information comprises: At least a first LLR mapping table, a second LLR mapping table, and a third LLR mapping table are generated according to the decoded data of the first logical data page, the first read information, the second read information, the third read information, the second decoded data of the second logical data page, and the third decoded data of the third logical data page.

10. The flash memory controller according to claim 9, wherein: The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; two states adjacent to each threshold voltage in the first set of threshold voltages correspond to the same bit value in the second logical data page and also correspond to the same bit value in the third logical data page; two states adjacent to each threshold voltage in the first set of threshold voltages correspond to different combinations of bit values ​​in the second logical data page and in the third logical data page; and the steps of generating at least the first LLR mapping table, the second LLR mapping table and the third LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information, the third readout information, the second decoded data of the second logical data page and the third decoded data of the third logical data page include: When the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a first combination, the first LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information; When the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a second combination, the second LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information; as well as When the bit values ​​corresponding to the second logical data page and the bit values ​​corresponding to the third logical data page have a third combination, the third LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information.

11. A memory device comprising: a flash memory module; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: Using a first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read a first logical data page of a physical data page in the flash memory module, respectively, to obtain a first readout information, a second readout information, and a third readout information, respectively; Decoding the first read information, the second read information and the third read information to generate decoded data of the first logical data page; A log-likelihood ratio (LLR) mapping table is generated according to the decoded data of the first logical data page, the first read information, the second read information and the third read information for subsequent use in reading and decoding other logical data pages.

12. The memory device according to claim 11, characterized in that The first group of critical voltages at least includes a first critical voltage, a second critical voltage and a third critical voltage; the first group of critical voltages after positive adjustment includes the first critical voltage plus an adjustment value, the second critical voltage plus the adjustment value and the third critical voltage plus the adjustment value; and the first group of critical voltages after negative adjustment includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value and the third critical voltage minus the adjustment value.

13. The memory device according to claim 11, characterized in that The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; and the first readout information includes a hard bit of each memory cell, the second readout information includes a first soft bit of each memory cell, and the third readout information includes a first soft bit of each memory cell; and the step of generating the LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information and the third readout information includes: According to the decoded data, the first read information, the second read information and the third read information of the first logical data page, 16 combinations of the decoded data, the hard bit, the first soft bit and the second soft bit are counted to calculate the number of each combination of the decoded data, the hard bit, the first soft bit and the second soft bit for calculating the LLR mapping table.

14. The memory device according to claim 11, wherein: The decoded data is a first decoded data, and the method further comprises: Using a second set of threshold voltages to read a second logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a second decoded data; Using a third set of threshold voltages to read a third logical data page of the physical data page in the flash memory module, and decoding the read information to obtain a third decoded data; and The step of generating the LLR mapping table according to the decoded data of the first logical data page, the first read information, the second read information and the third read information comprises: At least a first LLR mapping table, a second LLR mapping table, and a third LLR mapping table are generated according to the decoded data of the first logical data page, the first read information, the second read information, the third read information, the second decoded data of the second logical data page, and the third decoded data of the third logical data page.

15. The memory device according to claim 14, characterized in that The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; two states adjacent to each threshold voltage in the first set of threshold voltages correspond to the same bit value in the second logical data page and also correspond to the same bit value in the third logical data page; two states adjacent to each threshold voltage in the first set of threshold voltages correspond to different combinations of bit values ​​in the second logical data page and in the third logical data page; and the steps of generating at least the first LLR mapping table, the second LLR mapping table and the third LLR mapping table according to the decoded data of the first logical data page, the first readout information, the second readout information, the third readout information, the second decoded data of the second logical data page and the third decoded data of the third logical data page include: When the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a first combination, the first LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information; When the bit value corresponding to the second logical data page and the bit value corresponding to the third logical data page have a second combination, the second LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information; as well as When the bit values ​​corresponding to the second logical data page and the bit values ​​corresponding to the third logical data page have a third combination, the third LLR mapping table is generated according to the decoded data of the segment of the first logical data page, the first read information, the second read information and the third read information.

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