Flash Memory Controllers, Microcontrollers

Abstract

A flash memory controller and a microcontroller, the flash memory controller comprising: a bus interface, at least used to obtain a data read request from a bus, the data read request is used to request data in a target address in a flash memory, wherein the data bit width of the bus is N bytes, the data bit width of the flash memory is at least 2N bytes, and N is a positive integer greater than 1; a first register, used to cache first pre-fetched data, the address of the first pre-fetched data in the flash memory is located after the target address, and the interval between the address of the first pre-fetched data in the flash memory and the target address is N bytes. The solution of the present application can improve the pipeline efficiency of the processor in the microcontroller with lower hardware overhead.

Description

Technical Field

[0001] The present application relates to the technical field of microcontrollers, and in particular to a flash memory controller and a microcontroller. Background Art

[0002] In the prior art, the program of a microcontroller unit (MCU) can be stored in an embedded flash memory, and the processor of the MCU can read data from the flash memory, and then decode the data and execute it. Each time the processor reads data from the flash memory, it needs a waiting time, especially when the system clock frequency of the MCU is high, the data reading cannot be completed in a single cycle, which will cause the processor pipeline to pause, thereby making the processor pipeline efficiency low. Summary of the invention

[0003] One of the technical objectives of the embodiments of the present application is to provide a flash memory controller that can improve the pipeline efficiency of the processor in the MCU with lower hardware overhead.

[0004] In a first aspect, an embodiment of the present application provides a flash memory controller, comprising: a bus interface, at least used to obtain a data read request from a bus, the data read request being used to request data in a target address in a flash memory, wherein the data bit width of the bus is N bytes, the data bit width of the flash memory is at least 2N bytes, and N is a positive integer greater than 1; a first register, used to cache first prefetched data, the address of the first prefetched data in the flash memory being located after the target address, and the interval between the address of the first prefetched data in the flash memory and the target address is N bytes.

[0005] Optionally, it also includes: a second register for caching second pre-fetched data; wherein the address of the second pre-fetched data in the flash memory is located after the target address, and the interval between the address of the second pre-fetched data in the flash memory and the target address is 2N bytes.

[0006] Optionally, the flash memory controller further includes: a state machine and a control module; the control module is used to generate a control signal according to the state of the state machine, and the control signal is used to control the flash memory controller to read data from the flash memory and / or output data to the bus.

[0007] Optionally, the states of the state machine include: an idle state, a first state, a second state, a third state and a fourth state;.

[0008] Optionally, if the current state of the state machine is the idle state and the low-order read condition is met, the next state of the state machine is the first state; if the current state of the state machine is the first state and the first condition is met, the next state of the state machine is the second state; if the current state of the state machine is the second state and the first condition is met, the next state of the state machine is the third state; if the current state of the state machine is the third state and the first condition is met, the next state of the state machine is the fourth state; if the current state of the state machine is the fourth state and the first condition is met, the next state of the state machine is the the third state; if the current state of the state machine is the first state or the second state or the third state or the fourth state, and the second condition is satisfied, the next state of the state machine is the first state; if the current state of the state machine is the first state or the second state or the third state or the fourth state, and the third condition is satisfied, the next state of the state machine is the idle state; wherein the first condition refers to that the current target address is located after the previous target address, and the interval between the current target address and the previous target address is N bytes, and the low-order read condition refers to that the current data read request requests the address in the flash memory. wherein the second condition refers to that the first condition is not satisfied and the low-order read condition is satisfied; wherein the third condition refers to that the first condition is not satisfied and the low-order read condition is not satisfied; wherein, in the first state, the flash memory controller reads the data at the current target address from the flash memory, writes the N-bit data at the high-order address in the read data into the first register, and outputs the N-bit data at the low-order address in the read data to the bus; in the second state, the data in the first register is output to the bus, and the data at the next address of the current target address is read from the flash memory, and the N-byte data at the low-order address in the read data is written to the first register, and the N-byte data at the high-order address is written to the second register; in the third state, the data in the first register is output to the bus; in the fourth state, the data in the second register is output to the bus, and the data at the next address of the current target address is read from the flash memory, and the N-byte data at the low-order address in the read data is written to the first register, and the N-byte data at the high-order address is written to the second register.

[0009] Optionally, N is an integer multiple of 4.

[0010] Optionally, it also includes: an error correction code decoder, used to verify the data read from the flash memory.

[0011] In a second aspect, an embodiment of the present application provides a microcontroller, including: a flash memory controller provided in the first aspect.

[0012] Optionally, it also includes: a master device, used to send the data read request to the flash memory controller through the bus, and obtain the target data through the bus.

[0013] Optionally, the bus is an AHB bus.

[0014] Optionally, the master device is a processor whose core is Cortex-M3, Cortex-M0 or Cortex-M4.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] In the scheme of the embodiment of the present application, the flash memory controller includes: a bus interface and a first register, the bus interface is at least used to obtain a data read request from the bus, the data read request is used to request data in a target address in the flash memory, and the first register is used to cache the first pre-fetched data. The data bit width of the bus is N bytes, the data bit width of the flash memory is at least 2N bytes, the address of the first pre-fetched data in the flash memory is located after the target address, and the interval between the address of the first pre-fetched data in the flash memory and the target address is N bytes, and N is a positive integer greater than 1.

[0017] In the above scheme, the data bit width of the flash memory is greater than or equal to twice the data bit width of the bus, and a single read operation of the flash memory controller on the flash memory can fetch multiple data with adjacent addresses and a bit width equal to the data bit width of the bus. That is, a single read operation of the flash memory controller on the flash memory can obtain data requested by the processor multiple times. In the case where the processor runs certain programs with continuously increasing addresses and very few jumps, a single read of the flash memory by the flash memory controller can not only obtain the data requested by the processor this time, but also obtain the data needed by the processor next time. For this reason, in the scheme of the present application, the N bytes of data after the address of the data requested this time in the flash memory are cached in the first register as the first pre-fetched data. If the data at this address is requested next time, the flash memory controller can directly output the data in the first register without reading from the flash memory, thereby reducing the waiting time required to read data from the flash memory.

[0018] That is to say, in the above scheme, the data that the processor may need later is stored in the register of the flash memory controller. If the data requested by the processor next time is already in the register of the flash memory controller, the data can be returned in advance. Therefore, the scheme of the embodiment of the present application reduces the number of times the flash memory is accessed with low hardware overhead and avoids pipeline pauses. Especially when the processor runs certain programs with fewer address increments and jumps, the scheme provided by the embodiment of the present application can improve the working efficiency of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a pipeline of a processor;

[0020] Figure 2 It is a schematic diagram of another processor pipeline;

[0021] Figure 3 It is a schematic diagram of the hardware architecture of an MCU in an embodiment of the present application;

[0022] Figure 4 yes Figure 3 A schematic diagram of a hardware architecture of a flash memory controller;

[0023] Figure 5 This Figure 3 Another hardware architecture diagram of the flash memory controller;

[0024] Figure 6 yes Figure 5 State transition diagram of the state machine;

[0025] Figure 7 It is a schematic diagram of a pipeline of a processor in an embodiment of the present application. DETAILED DESCRIPTION

[0026] As described in the background technology, each time the MCU processor reads data from the flash memory, it needs a waiting time. When the system clock frequency of the MCU is high, the data reading cannot be completed in a single cycle, which will cause the processor pipeline to pause, making the processor pipeline efficiency low.

[0027] Reference Figure 1 , Figure 1 A schematic diagram of a processor pipeline. Figure 1An ideal pipeline schematic diagram is shown. Specifically, the processor can adopt a three-stage pipeline structure. For example, the ARM architecture processor adopts a three-stage pipeline. The three-stage pipeline divides the instruction process into three stages, each stage is processed in parallel by different hardware units in the processor, and the three stages are: fetch stage, decode stage and execute stage. Among them, in the fetch stage, the processor fetches instructions from the flash memory. In the decode stage, the processor decodes the fetched instructions to obtain operands and prepare for execution. In the execute stage, the processor executes instructions to complete the corresponding operation.

[0028] like Figure 1 As shown, the processor obtains the data of instruction 1 from the memory at time T0, decodes the data of instruction 1 at time T1, and executes instruction 1 at time T2. Since the data of instruction 1 has been obtained at time T1, the data of instruction 2 can be obtained at time T1, and the data of instruction 2 is decoded at time T2, and instruction 2 is executed at time T3. Similarly, since the data of instruction 2 has been obtained at time T2, the data of instruction 3 can be obtained at time T2, and the data of instruction 3 is decoded at time T3, and instruction 3 is executed at time T4.

[0029] When the MCU's system clock operating frequency (fsystem) is increased to above 1 / (tacc+tcomb), the reading of instructions in the flash memory cannot be completed in a single cycle, which will cause the processor pipeline to pause and generate bubbles. Among them, tacc is the data read time of the flash memory, and tcomb is the delay of the combinational logic between the processor's input data and the flash memory data output interface.

[0030] Reference Figure 2 , Figure 2 This is a schematic diagram of another processor pipeline. Figure 2 The situation shown is that the reading of instructions in the flash memory cannot be completed in a single cycle.

[0031] like Figure 2As shown, the processor reads the data of instruction 1 from the flash memory at time T0, but cannot complete the data reading of instruction 1 in a single cycle (that is, at time T0), so it needs to continue to wait for the flash memory to return data at time T1, decode the read data at time T2, and execute instruction 1 at time T3. Since the processor is still waiting for the data of instruction 1 at time T1, the processor can only read the data of instruction 2 at time T2. Similarly, the processor reads the data of instruction 2 from the flash memory at time T2, but cannot complete the data reading of instruction 2 in a single cycle (that is, at time T2), so it needs to continue to wait for the flash memory to return data at time T3, decode the read data at time T4, and execute instruction 2 at time T5. Since the processor is still waiting for the data of instruction 2 at time T3, the processor can only read the data of instruction 3 at time T4.

[0032] From the above, we can see that when the system clock operating frequency (fsystem) of the MCU is increased to above 1 / (tacc+tcomb), the reading of instructions in the flash memory cannot be completed within a single cycle, and the processor pipeline will pause, thereby reducing the pipeline efficiency of the processor.

[0033] In view of this, an embodiment of the present application provides a flash memory controller, the flash memory controller comprising: a bus interface and a first register, the bus interface is at least used to obtain a data read request from a bus, the data read request is used to request data in a target address in a flash memory, and the first register is used to cache first pre-fetched data. Wherein, the data bit width of the bus is N bytes, the data bit width of the flash memory is at least 2N bytes, the address of the first pre-fetched data in the flash memory is located after the target address, and the interval between the address of the first pre-fetched data in the flash memory and the target address is N bytes, and N is a positive integer greater than 1.

[0034] In the above scheme, the data bit width of the flash memory is greater than or equal to twice the data bit width of the bus, and the flash memory controller can fetch multiple data with adjacent addresses and a bit width equal to the data bit width of the bus in a single read operation on the flash memory. Since the processor usually requests data with a continuously increasing address, the flash memory controller can obtain data requested by the processor multiple times in a single read operation on the flash memory. For example, in addition to being able to obtain the data requested by the processor this time, it is also possible to obtain data that the processor may need next time. To this end, in the scheme of the present application, the N bytes of data after the address of the data requested this time in the flash memory are cached in the first register as the first pre-fetched data. If the next request is for data at this address, the flash memory controller can directly output the data in the first register without having to read from the flash memory, thereby reducing the waiting time required to read data from the flash memory.

[0035] In the above solution, the data that the processor may need later is stored in the register of the flash memory controller. If the data requested by the processor next time happens to be already in the register of the flash memory controller, the data can be returned in advance. Therefore, the solution of the embodiment of the present application reduces the number of accesses to the flash memory and avoids pipeline pauses with low hardware overhead.

[0036] In order to make the above-mentioned purposes, features and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0037] Reference Figure 3 , Figure 3 Schematic diagram of the architecture of an MCU in the embodiment of the present application. Figure 3 As shown, MCU30 includes: flash memory controller 301, flash memory 302, bus 303 and processor 304. The processor 304 sends a data read request to the flash memory controller 301 through the bus 303. The data read request includes a target address, which refers to the starting address of the data requested by the processor 304 in the flash memory.

[0038] It should be noted that the "processor" in the embodiments of the present application may also be referred to as a "master device". In one example, the processor 304 may be a processor with a Cortex-M3 core. In another example, the processor 304 may be a processor with a Cortex-M0 or Cortex-M0+ core. In another example, the processor 304 may be a processor with a Cortex-M4 core.

[0039] In the scheme of the embodiment of the present application, the data bit width of the bus 303 is N bytes, and the data bit width of the flash memory 302 is at least 2N bytes. That is, the bit width of the data transmitted by the flash memory controller 301 to the bus 303 each time is N bytes, and the bit width of the data obtained by the flash memory controller 301 from the flash memory 302 each time is at least 2N bytes. Wherein N is a positive integer greater than 1. Specifically, N is an integer multiple of 4. For example, N=4. Or, N=8. This article mainly describes N=4 as an example, but is not limited to N=4.

[0040] If N=4, it means that the data bit width of bus 303 is 32 bits. For example, bus 303 may be an Advanced High Performance Bus (AHB) bus, and the data bit width of the AHB bus is 32 bits. In addition, the data bit width of flash memory 302 is 64 bits or 72 bits. In other embodiments, bus 303 may also be an AXI (Advanced eXtensible Interface) bus, etc., which is not limited in this embodiment.

[0041] In addition, the processor 304 obtains the target data from the flash memory controller 301 through the bus 303. The target data refers to the data requested by the data read request. Specifically, the target data refers to the data in the flash memory whose starting address is the target address and whose bit width is N bytes.

[0042] In one case, the data requested by the data read request is N bytes of data at a lower address among data of the target address.

[0043] In another case, the data requested by the data read request is N bytes of data at a higher address among the data of the target address.

[0044] In a specific implementation, if the values ​​of the 0th and 1st bits of the target address in the data read request are 0 or 2, it means that the data requested by the data read request is the N bytes of data at the lower address among the 2N bytes of data at the target address. If the values ​​of the 0th and 1st bits of the target address in the data read request are 1 or 3, it means that the data requested by the data read request is the N bytes of data at the higher address among the data at the target address.

[0045] It should be noted that the "N bytes of data at the low address" in this article refers to the "8N bits of data at the low address", that is, the data from bit 0 to bit (8*N-1). The "N bytes of data at the high address" in this article refers to the "8N bits of data at the high address", that is, the data from bit 8N to bit (16N-1).

[0046] Reference Figure 4 , Figure 4 yes Figure 3 A schematic diagram of a hardware architecture of the flash memory controller 301 is shown in FIG. Figure 4 As shown, the flash memory controller 301 may include: a bus interface 401, a first register 402, and a control module 403. Figure 4 The embodiments of the present application are described in a non-limiting manner.

[0047] The bus interface 401 is used to communicate with the bus 303. Specifically, the flash memory controller 301 obtains a data read request from the bus 303 through the bus interface 401, and the flash memory controller 301 outputs target data to the bus 303 through the bus interface 401.

[0048] Furthermore, the control module 403 may be used to generate a control signal, where the control signal is used to control the flash memory controller 301 to read data from the flash memory 302 and / or to control the flash memory controller 301 to output data to the bus 303 .

[0049] In the solution of the embodiment of the present application, the first register 402 can be used to cache the first pre-fetched data, and the interval between the address of the first pre-fetched data in the flash memory 302 and the address of the target data is N bytes.

[0050] It should be noted that the register in the embodiment of the present application may be a first-in-first-out register.

[0051] In one example, the data read request obtained by the flash memory controller 301 requests data with addresses 0x10 to 0x13 in the flash memory 301, and the first register 402 also caches data with addresses 0x14 to 0x17. If the next data read request obtained requests data with addresses 0x14 to 0x17, the flash memory controller 301 can directly return the data in the first register 402 to the bus without performing a read operation on the flash memory 302 again.

[0052] In addition, in the solution of the embodiment of the present application, the flash memory controller 301 may also include: an error correction code decoder (not shown), which is used to verify the data read from the flash memory 302. Specifically, if the data read from the flash memory 302 is 72-bit data, the error correction code decoder verifies it, obtains 64-bit data, and uses the 64-bit data as the data read from the flash memory 302. If the data read from the flash memory 302 is 64-bit data, it is not necessary to use the error correction code decoder to verify it, that is, the error correction code decoder is bypassed.

[0053] Reference Figure 5 , Figure 5 yes Figure 3 FIG. 3 is a schematic diagram of the hardware architecture of the flash memory controller 301. Figure 4 The flash memory controller 301 is shown. Figure 5 The flash memory controller 301 shown also includes: a second register 404 and a state machine 405. Figure 5 The embodiments of the present application are described in a non-limiting manner.

[0054] The second register 404 can be used to cache the second pre-fetched data, and the interval between the address of the second pre-fetched data in the flash memory 302 and the target address is 2N bytes. In other words, the interval between the address of the second pre-fetched data in the flash memory 302 and the address of the target data is 2N bytes.

[0055] In one example, the data read request obtained by the flash memory controller 301 requests data with addresses of 0x0C to 0x0F in the flash memory. In addition to returning the data with addresses of 0x0C to 0x0F in the flash memory 302 to the bus 303, the flash memory controller 301 also caches data of 0x10 to 0x13 in the first register 402, and caches data of 0x14 to 0x17 in the second register 404. If the target addresses in the two subsequent data read requests are continuously incremented, the flash memory controller 301 does not need to perform a read operation on the flash memory 302 in the two subsequent requests, which further reduces the number of accesses to the flash memory 302 and further improves the efficiency of the pipeline.

[0056] In addition, the flash memory controller 301 also includes a state machine 405, and the control module 403 can generate a control signal according to the state of the state machine 405. Based on the control signal, the flash memory controller 301 reads data from the flash memory 302 and saves the read data into a register to ensure that the first pre-fetched data is always cached in the first register 402. Furthermore, the second pre-fetched data can also be cached in the second register 404.

[0057] Reference Figure 6 , Figure 6 yes Figure 5 A state transition diagram of the state machine 405. Figure 6 The operation process of the flash memory controller 301 is described in detail.

[0058] like Figure 6 As shown, the states of the state machine 405 may include: an idle state, a first state, a second state, a third state and a fourth state. Among them, the "idle state" may also be referred to as an "initial state".

[0059] In the idle state, the flash memory controller 301 may wait for a data read request. In the idle state, the first register 402 and the second register 404 may both be empty.

[0060] In the idle state, if a data read request is received, it can be determined whether the low-order read condition is satisfied, and if the low-order read condition is satisfied, the first state can be entered. In other words, if the current state of the state machine 405 is the idle state, and the low-order read condition is satisfied, the next state of the state machine 405 is the first state, that is, the state of the state machine 405 is transferred from the idle state to the first state.

[0061] The low-order read condition means that the data read request requests N bytes of data at the low address among the 2N bytes of data in the flash memory whose address is the current target address.

[0062] In the first state, the flash memory controller 301 reads 2N bytes of data at the current target address from the flash memory 302, outputs N bytes of data at the lower address of the read data to the bus, and writes N bytes of data at the higher address of the read data into the first register 402.

[0063] Specifically, the flash memory controller 301 outputs the data from the 0th bit to the (8*N-1)th bit of the read 2N bytes of data to the bus 303, and writes the data from the Nth bit to the (16N-1)th bit of the read data into the first register 402. In other words, the data from the 0th bit to the (8*N-1)th bit of the read data by the flash memory controller 301 is the current target data, and the data from the Nth bit to the (16N-1)th bit of the read data is the first pre-stored data.

[0064] Assuming that the current target address is cur_addr, N=4, in the first state, the flash memory controller 301 reads 64 bits of data with the starting address cur_addr from the flash memory 302, and outputs the data from bit 0 to bit 31 to the bus 303, and writes the data from bit 32 to bit 63 into the first register 402.

[0065] In the first state, if a data read request is received and the first condition is satisfied, the second state can be entered. In other words, if the current state of the state machine 405 is the first state and the first condition is satisfied, the next state of the state machine 405 is the second state, that is, the state of the state machine 405 is transferred from the first state to the second state.

[0066] The first condition means that the current target address is after the previous target address, and the interval between the current target address and the previous target address is N bytes. The current target address refers to the target address in the currently acquired data read request, and the previous target address refers to the target address in the last acquired data read request. Assuming that the previous target address is recorded as tar_addr and the current target address is cur_addr, if cur_addr=tar_addr+4, it can be determined that the first condition is met.

[0067] In the first state, if a data read request is received, if the second condition is satisfied, the first state is maintained, wherein the second condition means that the first condition is not satisfied, and the low-order read condition is satisfied.

[0068] Specifically, assuming that the previous target address is recorded as tar_addr, and the target address in the current data read request is cur_addr, if cur_addr!= tar_addr+4, it means that the first condition is not satisfied. Further, if the current data read request requests data from the 0th to the (8*N-1)th bit of the 2N bytes of data with the starting address cur_addr in the flash memory 302, the second condition is satisfied.

[0069] In the first state, if a data read request is received, if the third condition is met, it will migrate to the idle state. The third condition means that the first condition is not met and the low-order read condition is not met. The low-order read condition is not met, which means that the current data read request requests N bytes of data in the flash memory whose starting address is the high address of the current target address.

[0070] Specifically, assuming that the previous target address is recorded as tar_addr, and the target address in the current data read request is cur_addr, if cur_addr!= tar_addr+4, it means that the first condition is not satisfied. Further, if the current data read request requests data from the Nth bit to the (16N-1)th bit of the 2N bytes of data with the starting address cur_addr in the flash memory 302, the third condition is satisfied.

[0071] In the second state, the flash memory controller 301 outputs the first pre-stored data in the first register 402 to the bus 303, and reads data in the next address of the current target address from the flash memory 302. Further, after reading the data from the flash memory 303, the flash memory controller 301 writes N bytes of data at the lower address of the read data into the first register 402, and writes N bytes of data at the higher address into the second register 404.

[0072] It should be noted that, assuming that the current target address is cur_addr, in the solution of the embodiment of the present application, the next address of the current target address refers to cur_addr+4.

[0073] Specifically, the flash memory controller 301 writes the data from the 0th bit to the (8N-1th bit) of the read data into the first register 402, and writes the data from the 8Nth bit to the (16N-1th bit) of the read data into the second register 404. In other words, the data from the 0th bit to the (8N-1th bit) of the data read by the flash memory controller 301 is the first pre-fetched data, and the data from the 8Nth bit to the (16N-1th bit) of the read data is the second pre-stored data.

[0074] Assuming that the current target address is cur_addr, N=4, in the second state, the flash memory controller 301 outputs the data in the first register 402 to the bus 303, and reads 64 bits of data with a starting address of cur_addr+4 from the flash memory 302, and writes the data from the 0th to the 31st bits of the 64 bits read into the first register 402, and writes the data from the 32nd to the 63rd bits into the second register 404.

[0075] In the second state, if a data read request is received, if the first condition is satisfied, the third state can be entered. In other words, if the current state of the state machine 405 is the second state and the first condition is satisfied, the next state of the state machine 405 is the third state, that is, the state of the state machine 405 is transferred from the second state to the third state.

[0076] In the second state, if a data read request is received and the second condition is satisfied, the first state is entered. In other words, if the current state of the state machine 405 is the second state and the second condition is satisfied, the next state of the state machine 405 is the first state, that is, the state of the state machine 405 is transferred from the second state to the first state.

[0077] In the second state, if a data read request is received, if the third condition is satisfied, the state machine 405 is transferred to the idle state. In other words, if the current state of the state machine 405 is the second state and the third condition is satisfied, the next state of the state machine 405 is the idle state, that is, the state of the state machine 405 is transferred from the second state to the idle state.

[0078] In the third state, the flash controller 301 outputs the first pre-stored data in the first register 402 to the bus 303. That is, the first pre-stored data in the first register 402 is the current target data. It should be noted that in the third state, the flash controller 301 does not perform a read operation on the flash memory 302.

[0079] In the third state, if a data read request is received and the first condition is satisfied, the fourth state can be entered. In other words, if the current state of the state machine 405 is the third state and the first condition is satisfied, the next state of the state machine 405 is the fourth state, that is, the state of the state machine 405 is transferred from the third state to the fourth state.

[0080] In the third state, if a data read request is received and the second condition is satisfied, the first state is entered. In other words, if the current state of the state machine 405 is the third state and the second condition is satisfied, the next state of the state machine 405 is the first state, that is, the state of the state machine 405 is transferred from the third state to the first state.

[0081] In the third state, if a data read request is received and the third condition is satisfied, the state machine 405 is transferred to the idle state. In other words, if the current state of the state machine 405 is the third state and the third condition is satisfied, the next state of the state machine 405 is the idle state, that is, the state of the state machine 405 is transferred from the third state to the idle state.

[0082] In the fourth state, the flash memory controller 301 outputs the second pre-stored data in the second register 404 to the bus 303. That is, the second pre-stored data in the second register 404 is the current target data, and is output to the bus 303. In addition, in the fourth state, the flash memory controller 301 reads data in the next address of the current target address from the flash memory 302, and then writes N bytes of data at the lower address of the read data into the first register 402, and writes N bytes of data into the second register 404.

[0083] Specifically, the flash memory controller writes the data from the 0th bit to the (N-1th bit) of the read data into the first register 402, and writes the data from the Nth bit to the (2N-1th bit) of the read data into the second register 404. In other words, the data from the 0th bit to the (N-1th bit) of the data read by the flash memory controller is the first pre-fetched data, and the data from the Nth bit to the (2N-1th bit) of the read data is the second pre-stored data.

[0084] Assuming that the current target address is cur_addr, N=4, in the fourth state, the flash memory controller 301 outputs the data in the second register 404 to the bus 303, and reads 64 bits of data with a starting address of cur_addr+4 from the flash memory 302, and writes the data from the 0th to the 31st bits of the 64 bits read into the first register 402, and writes the data from the 32nd to the 63rd bits into the second register 404.

[0085] In the fourth state, if a data read request is received, if the first condition is satisfied, the third state can be entered. In other words, if the current state of the state machine 405 is the fourth state and the first condition is satisfied, the next state of the state machine 405 is the third state, that is, the state of the state machine 405 is transferred from the fourth state to the third state.

[0086] In the fourth state, if a data read request is received and the second condition is satisfied, the first state is entered. In other words, if the current state of the state machine 405 is the fourth state and the second condition is satisfied, the next state of the state machine 405 is the first state, that is, the state of the state machine 405 is transferred from the fourth state to the first state.

[0087] In the fourth state, if a data read request is received, if the third condition is satisfied, the state machine 405 is transferred to the idle state. In other words, if the current state of the state machine 405 is the fourth state and the third condition is satisfied, the next state of the state machine 405 is the idle state, that is, the state of the state machine 405 is transferred from the fourth state to the idle state.

[0088] Reference Figure 7 , Figure 7 is a pipeline diagram of a processor in an embodiment of the present application. Specifically, Figure 7 The following figure shows the pipeline of the processor after adopting the solution provided by the embodiment of the present application. Figure 7 The scheme of the embodiment of the present application is described.

[0089] Assume that at time T0, the state machine 405 is in an idle state. At time T0, the flash memory controller 301 receives the first data read request, that is, the data read request of instruction 1. The target address of the first data read request is 0x00, that is, the first data read request requests to read data from 0x00 to 0x03.

[0090] Furthermore, the flash memory controller 301 enters the first state, reads data 0x00-0x07 from the flash memory (this reading process requires waiting), returns data 0x00-0x03 to the bus 303, and stores data 0x04-0x07 in the first register 402.

[0091] At time T2, the flash controller 301 receives the second data read request, that is, the data read request of instruction 2. The second read request requests to read the data in 0x04-0x07, and the state machine 405 enters the second state from the first state. The flash controller 301 outputs the data in the first register 402 to the bus 303. In addition, at time T2, the flash controller 301 also reads the data in 0x08-0x0F from the flash memory 302, stores the data in 0x08-0x0B in the first register 402, and stores the data in 0x0C-0x0F in the second register 404.

[0092] At time T3, the flash controller 301 receives the third data read request, that is, the data read request of instruction 3. The third read request requests to read the data in 0x08-0x0B, and the state machine 405 enters the third state from the second state. The flash controller outputs the data in the first register 402 to the bus 303.

[0093] At time T4, the flash controller 301 receives the fourth data read request, that is, the data read request of instruction 4. The fourth read request requests to read the data in 0x0C~0x0F, and the state machine 405 enters the fourth state from the third state. The flash controller outputs the data in the second register 404 to the bus 303. In addition, at time T4, the flash controller 301 also reads the data in 0x10~0x17 from the flash memory 302, and stores the data in 0x10~0x13 in the first register 402, and stores the data in 0x14~0x17 in the second register 404.

[0094] As can be seen from the above, when the processor continuously reads the flash memory, except for the first data which requires a waiting cycle, the subsequent data to be read do not require a waiting cycle.

[0095] Therefore, the solution provided in the embodiment of the present application can improve the problem of pipeline pauses caused by the inability of the flash memory to read data in a single cycle under a high-speed clock, thereby improving the work efficiency of the processor. In addition, in the solution of the embodiment of the present application, only two 32-bit registers are used to reduce the situation of pipeline bubbles, and there is no need to set up a storage body (such as static random access memory, etc.) that occupies a lot of hardware resources, and the hardware overhead is low. In addition, the first register and the second register in the embodiment of the present application are both located inside the flash memory controller, rather than being independent of the flash memory controller, which is also conducive to avoiding the delay caused by data transmission between the flash memory controller and the first register and the second register.

[0096] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0097] The "multiple" appearing in the embodiments of the present application refers to two or more. The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor does it represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application. Although the present invention is disclosed as above, the present invention is not limited to this. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A flash memory controller, characterized in that: include: A bus interface, at least used to obtain a data read request from a bus, wherein the data read request is used to request data in a target address in a flash memory, wherein the data bit width of the bus is N bytes, the data bit width of the flash memory is at least 2N bytes, and N is a positive integer greater than 1; A first register is used to cache first pre-fetched data, where the address of the first pre-fetched data in the flash memory is located after the target address, and the interval between the address of the first pre-fetched data in the flash memory and the target address is N bytes; Also included: a second register and a state machine, the state of the state machine including an idle state, a first state, a second state, a third state and a fourth state; If the current state of the state machine is the idle state and the low-order read condition is satisfied, the next state of the state machine is the first state; If the current state of the state machine is the first state and the first condition is satisfied, the next state of the state machine is the second state; If the current state of the state machine is the second state and the first condition is satisfied, the next state of the state machine is the third state; If the current state of the state machine is the third state and the first condition is satisfied, the next state of the state machine is the fourth state; If the current state of the state machine is the fourth state and the first condition is satisfied, the next state of the state machine is the third state; If the current state of the state machine is the first state or the second state or the third state or the fourth state, and the second condition is satisfied, the next state of the state machine is the first state; If the current state of the state machine is the first state or the second state or the third state or the fourth state, and the third condition is satisfied, the next state of the state machine is the idle state; The first condition refers to that the current target address is located after the previous target address, and the interval between the current target address and the previous target address is N bytes, and the low-order read condition refers to that the current data read request requests N bytes of data at the lower address among the 2N bytes of data in the flash memory whose address is the current target address; The second condition means that the first condition is not satisfied, and the low-order read condition is satisfied; The third condition means that the first condition is not satisfied and the low-order reading condition is not satisfied; Wherein, in the first state, the flash memory controller reads the data at the current target address from the flash memory, writes N bytes of data at a high address in the read data into the first register, and outputs N bytes of data at a low address in the read data to the bus; In the second state, the data in the first register is output to the bus, and the data in the next address of the current target address is read from the flash memory, and the N bytes of data at the lower address of the read data are written into the first register, and the N bytes of data at the higher address are written into the second register; In the third state, the data in the first register is output to the bus; In the fourth state, the data in the second register is output to the bus, and the data in the next address of the current target address is read from the flash memory, and the N bytes of data at the low address of the read data are written to the first register, and the N bytes of data at the high address are written to the second register.

2. The flash memory controller according to claim 1, wherein: The flash memory controller further includes: a control module; The control module is used to generate a control signal according to the state of the state machine, and the control signal is used to control the flash memory controller to read data from the flash memory and / or output data to the bus.

3. The flash memory controller according to claim 1, wherein: N is an integer multiple of 4.

4. The flash memory controller according to claim 1, wherein: Also includes: An error correction code decoder is used to verify the data read from the flash memory.

5. A microcontroller, characterized in that: A flash memory controller comprising any one of claims 1 to 4.

6. The microcontroller according to claim 5, characterized in that: Also includes: The master device is used to send the data read request to the flash memory controller through the bus, and obtain the data in the target address through the bus.

7. The microcontroller according to claim 6, characterized in that: The bus is an AHB bus.

8. The microcontroller according to claim 6, characterized in that: The master device is a processor whose core is Cortex-M3, Cortex-M0 or Cortex-M4.

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