Method for accessing flash memory module and related flash memory controller and memory device

Abstract

The invention discloses a method for accessing a flash memory module and a related flash memory controller and memory device. The method for accessing the flash memory module comprises the following steps of: reading a first logical data page by using a first group of critical voltages, a first group of positively adjusted critical voltages and a first group of negatively adjusted critical voltages to respectively obtain first read information, second read information and third read information; selecting a second logic data page; reading the second logical data page by using a second set of threshold voltages to generate fourth read information; adjusting the first set of critical voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information to generate an adjusted first set of critical voltages; and reading the first logical data page in the flash memory module using the adjusted first set of threshold voltages.

Description

Technical Field

[0001] The invention relates to a flash memory controller. Background Art

[0002] Flash memory can be erased and written / programmed electronically to store data, and is widely used in memory cards, solid-state drives, portable multimedia players, etc. Since flash memory is non-volatile, no additional power is required to maintain the information stored in the flash memory. In addition, flash memory can provide fast data reading and better shock resistance, and these characteristics also explain why flash memory is so popular.

[0003] Flash memory can be divided into NOR flash memory and NAND flash memory. NAND flash memory has shorter erase and write time and each memory cell requires less chip area, so NAND flash memory allows higher storage density and lower cost per storage bit compared to NOR flash memory. Generally speaking, flash memory stores data in the form of a memory cell array, and the memory cell is implemented by a floating-gate transistor, and each memory cell can store a single bit of information or more than one bit of information by appropriately controlling the number of charges on the floating gate of the floating gate transistor to set the required threshold voltage for turning on the memory cell implemented by the floating gate transistor. In this way, when one or more predetermined gate control voltages are applied to the control gate of the floating gate transistor, the conduction state of the floating gate transistor will indicate one or more binary digits stored in the floating gate transistor.

[0004] However, due to certain factors, the number of charges originally stored in the memory cell may be affected / disturbed. For example, the disturbance in the flash memory may come from write disturbance (write / program disturbance), read disturbance (read disturbance) and / or retention disturbance (retention disturbance). Taking a NAND flash memory having memory cells each storing more than one bit of information as an example, a physical memory page (physical page) includes multiple logical data pages (logical page), and each logical data page is read using one or more gate control voltages. For example, for a memory cell for storing 4 bits of information, the memory cell will have one of 16 states (i.e., charge levels) corresponding to different numbers of charges (i.e., different threshold voltages). However, due to the program / erase count (P / E count) and / or data retention time, the threshold voltage distribution of the memory cell in the memory cell will change. Therefore, using the original gate control voltage setting (i.e., threshold voltage setting) to read the information stored in the memory cell may not correctly obtain the stored information due to the changed threshold voltage distribution.

[0005] In addition, US patent application US 8,760,929 proposes a threshold voltage tracking method to adjust the gate control voltage setting. However, this method cannot be effectively used in a memory cell storing 4 bits of information. Summary of the invention

[0006] Therefore, one of the objectives of the present invention is to provide a flash memory controller and a related control method, which can efficiently adjust the gate control voltage setting (threshold voltage setting) according to the read information of the flash memory to solve the above-mentioned problem.

[0007] In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, which includes: using a first set of critical voltages to read a first logical data page of a physical data page in the flash memory module to generate a readout information; decoding the readout information, and if the readout information cannot be successfully decoded, using the first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages to read the first logical data page to obtain a first readout information, a second readout information, and a third readout information respectively; selecting a second logical data page of the physical data page; using a second set of critical voltages to read the second logical data page to generate a fourth readout information; adjusting the first set of critical voltages according to the first readout information, the second readout information, the third readout information, and the fourth readout information to generate an adjusted first set of critical voltages; and using the adjusted first set of critical voltages to read the first logical data page in the flash memory module.

[0008] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller includes: a read-only memory for storing a program code; a buffer memory; and a microprocessor for executing the program code to control access to the flash memory module; wherein the microprocessor is used to perform the following operations: using a first set of threshold voltages to read a first logical data page of a physical data page in the flash memory module to generate a readout information; decoding the readout information, and if the readout information cannot be successfully decoded, respectively using the first set of threshold voltages to decode the first logical data page of a physical data page in the flash memory module; The invention relates to a method for reading a first logical data page by using a threshold voltage, a positively adjusted first set of critical voltages and a negatively adjusted first set of critical voltages to obtain a first readout information, a second readout information and a third readout information respectively; selecting a second logical data page of the physical data page; using a second set of critical voltages to read the second logical data page to generate a fourth readout information; adjusting the first set of critical voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information to generate an adjusted first set of critical voltages; and using the adjusted first set of critical voltages to read the first logical data page in the flash memory module.

[0009] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory controller performs the following operations: using a first set of critical voltages to read a first logical data page of a physical data page in the flash memory module to generate a readout information; decoding the readout information, and if the readout information cannot be successfully decoded, using the first set of critical voltages, a positively adjusted first set of critical voltages, and a negatively adjusted first set of critical voltages to read the first logical data page to obtain a first readout information, a second readout information, and a third readout information, respectively; selecting a second logical data page of the physical data page; using a second set of critical voltages to read the second logical data page to generate a fourth readout information; adjusting the first set of critical voltages according to the first readout information, the second readout information, the third readout information, and the fourth readout information to generate an adjusted first set of critical voltages; and using the adjusted first set of critical voltages to read the first logical data page in the flash memory module.

[0010] Description of the attached drawings

[0011] Figure 1 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0012] Figure 2 A schematic diagram of a block included in a flash memory module.

[0013] Figure 3 FIG. 4 is a schematic diagram showing that each memory unit is used to store 4 bits according to an embodiment of the present invention.

[0014] Figure 4 Schematic diagram showing that the distribution of each state of a memory cell is shifted or broadened.

[0015] Figure 5 FIG. 4 is a flow chart of a method for accessing a flash memory module according to an embodiment of the present invention.

[0016] Figure 6 FIG. 1 is a schematic diagram of using different threshold voltages to read data pages according to an embodiment of the present invention.

[0017] Figure 7 A schematic diagram for determining whether the second readout information is bit-inverted relative to the first readout information, and whether the third readout information is bit-inverted relative to the first readout information.

[0018]

Explanation of symbols

[0019] 100: Memory Device

[0020] 103: Memory Unit

[0021] 110: Flash memory controller

[0022] 112: Microprocessor

[0023] 112M: Read-only memory

[0024] 112C: Program code

[0025] 114: Control Logic

[0026] 116: Buffer memory

[0027] 118: Interface Logic

[0028] 120: Flash memory module

[0029] 130: Main device

[0030] 132: Encoder

[0031] 134:Decoder

[0032] 136: Control unit

[0033] 138: Counting unit

[0034] 139: Comparison Unit

[0035] 200: Block

[0036] 500~516: Steps

[0037] M_0~M_K: memory unit

[0038] P_0~P_N: Entity data page

[0039] VG_0~VG_N: Gate control voltage

[0040] B0~BK: bit value

[0041] S0~S15: Status

[0042] VT1~VT15: critical voltage

[0043] VT1', VT4', VT6', VT11': adjusted critical voltage DETAILED DESCRIPTION

[0044] Figure 11 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a control unit 136, a counting unit 138, and a comparing unit 139, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or Error Correction Code, ECC), and the decoder 134 is used to decode the data read from the flash memory module 120. In addition, the control unit 136, the counting unit 138, and the comparing unit 139 are implemented by circuit elements, and their specific operations will be described in the subsequent embodiments.

[0045] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a block. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.

[0046] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform a variety of control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.

[0047] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0048] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, no further explanation is given in the specification.

[0049] Figure 2 Schematic diagram of a block 200 included in a flash memory module 120, wherein the block 200 includes a plurality of physical data pages P_0, P_1, P_2, ..., P_N, and each of the physical data pages P_0-P_N includes a plurality of memory cells (e.g., floating gate transistors) 103. For example, for a target physical data page P_0 to be read, it includes memory cells M_0-M_K. In order to read the data stored in the memory cells M_0-M_K of the target physical data page P_0, the gate control voltages VG_0-VG_N should be appropriately set to read a plurality of bit values ​​B0-BK from the memory cells M_0-M_K, respectively. If each memory cell 103 is used to store N bits, that is, the target physical data page P_0 includes N logical data pages, the flash memory 102 sets the gate control voltage VG_0 to (2N-1) voltage levels to identify the N bits of each memory cell 103 in the target physical data page P_0.

[0050] Figure 3 FIG. 1 is a schematic diagram showing that each memory unit 103 is used to store 4 bits according to an embodiment of the present invention. Figure 3As shown, each memory cell can have sixteen states, and each state represents a different combination of four bits (named as top bit, upper bit, middle bit, and lower bit). Figure 3In the embodiment shown, when the memory cell is programmed to have state S0, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 1); when the memory cell is programmed to have state S1, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 1, 0); when the memory cell is programmed to have state S2, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 1, 0); when the memory cell is programmed to have state S3, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 0, 0, 0); ,0); when the memory cell is programmed to have state S4, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1,0,0,1); when the memory cell is programmed to have state S5, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,1); when the memory cell is programmed to have state S6, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,0,0); when the memory cell is programmed to have state S7, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0,0,1,0); When the memory cell is programmed to have state S8, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 1, 0); when the memory cell is programmed to have state S9, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (0, 1, 0, 0); when the memory cell is programmed to have state S10, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 0); when the memory cell is programmed to have state S11, the top bit, upper bit, middle bit and lower bit stored in the memory cell are (1, 1, 0, 1); The memory cell is programmed to have a state S12, and the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (0, 1, 0, 1); when the memory cell is programmed to have a state S13, the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (0, 1, 1, 1); when the memory cell is programmed to have a state S14, the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (0, 0, 1, 1); and when the memory cell is programmed to have a state S15, the top bit, the upper bit, the middle bit, and the lower bit stored in the memory cell are (1, 0, 1, 1).

[0051] In the related art, taking data page P_0 as an example, when the top bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 having four threshold voltages VT5, VT10, VT12 and VT15 to read the memory cell. If the memory cell is conductive when the critical voltage VT5 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT5 is applied and the memory cell is conductive when the critical voltage VT10 is applied, the top bit is determined to be "0"; if the memory cell is non-conductive when the critical voltage VT10 is applied and the memory cell is conductive when the critical voltage VT12 is applied, the top bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT12 is applied and the memory cell is conductive when the critical voltage VT15 is applied, the top bit is determined to be "0"; and if the memory cell is non-conductive when the critical voltage VT15 is applied, the top bit is determined to be "1". When the upper bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply the gate control voltage VG_0 having three threshold voltages VT2, VT8 and VT14 to read the memory cell. If the memory cell is conductive when the threshold voltage VT2 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the threshold voltage VT2 is applied and the memory cell is conductive when the threshold voltage VT8 is applied, the upper bit is determined to be "0"; if the memory cell is non-conductive when the threshold voltage VT8 is applied and the memory cell is conductive when the threshold voltage VT14 is applied, the upper bit is determined to be "1"; if the memory cell is non-conductive when the threshold voltage VT14 is applied, the upper bit is determined to be "0". When the middle bit needs to be read by the flash memory controller 110, the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 having four threshold voltages VT3, VT7, VT9 and VT13 to read the memory cell.If the memory cell is conductive when the critical voltage VT3 is applied, the intermediate bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT3 is applied and the memory cell is conductive when the critical voltage VT7 is applied, the intermediate bit is determined to be "0"; if the memory cell is non-conductive when the critical voltage VT7 is applied and the memory cell is conductive when the critical voltage VT9 is applied, the intermediate bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT9 is applied and the memory cell is conductive when the critical voltage VT13 is applied, the intermediate bit is determined to be "0"; and if the memory cell is non-conductive when the critical voltage VT13 is applied, the intermediate bit is determined to be "1". When the lower bit needs to be read by the flash memory controller 110 , the flash memory controller 110 can control the flash memory module 120 to apply a gate control voltage VG_0 having four threshold voltages VT1 , VT4 , VT6 , and VT11 to read the memory cell. If the memory cell is conductive when the critical voltage VT1 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT1 is applied and the memory cell is conductive when the critical voltage VT4 is applied, the lower bit is determined to be "0"; if the memory cell is non-conductive when the critical voltage VT4 is applied and the memory cell is conductive when the critical voltage VT6 is applied, the lower bit is determined to be "1"; if the memory cell is non-conductive when the critical voltage VT6 is applied and the memory cell is conductive when the critical voltage VT11 is applied, the lower bit is determined to be "0"; and if the memory cell is non-conductive when the critical voltage VT11 is applied, the lower bit is determined to be "1".

[0052] It should be noted that Figure 3 The gray code shown is for illustrative purposes only and is not intended to limit the present invention. Any suitable gray code can be used in the memory device 100, and the threshold voltages used to determine the top bit, the upper bit, the middle bit, and the lower bit can be changed accordingly.

[0053] However, the flash memory module 120 may be damaged due to certain factors, such as an increase in the number of write / read times and / or data retention time. Figure 3 The distribution of each state shown is shifted or widened, so that the threshold voltage used to read the memory cell is no longer the most suitable threshold voltage. Figure 4For example, due to the influence of the number of write / read times and / or data retention time of the flash memory module 120, the state S0 and the state S1 become wider and shift to the left, and the best threshold voltage should correspond to the intersection of the distribution of the state S0 and the state S1, that is, VT1' shown in the figure; at this time, if the original threshold voltage VT1 is used to read the memory cell, the read data will have a higher error, which may cause problems in the processing of the decoder 134. Similarly, due to the influence of the number of write / read times and / or data retention time of the flash memory module 120, the state S10 and the state S11 become wider and shift to the right, and the best threshold voltage should correspond to the intersection of the distribution of the state S10 and the state S11, that is, VT11' shown in the figure; at this time, if the original threshold voltage VT11 is used to read the memory cell, the read data will have a higher error, which may cause problems in the processing of the decoder 134. Therefore, in order to solve the above-mentioned problem of state distribution shift and / or widening of the memory cell, the present invention proposes a control method, which can efficiently determine the adjustment direction of the threshold voltage, especially for the situation where the bit to be read needs to use four threshold voltages, such as Figure 3 As shown, four threshold voltages VT1, VT4, VT6 and VT11 are required to read the memory cell to determine the bit value of the underlying bit.

[0054] Figure 5 FIG. 1 is a flow chart of a method for accessing a flash memory module 120 according to an embodiment of the present invention. At step 500, the process starts. At step 502, the microprocessor 112 in the flash memory controller 110 receives a read instruction, such as a read instruction from the host device 130, to start reading a first logical data page in a physical data page. For the convenience of the following description, the physical data page is represented by Figure 2 Taking the physical data page P_0 as an example, each memory cell in the physical data page P_0 can store 4 bits, that is, the physical data page P_0 includes four logical data pages, and the four logical data pages are used to store Figure 3 The top bit, upper bit, middle bit and lower bit are shown; in addition, in the following description, the first logical data page is a logical data page used to store the lower bit.

[0055] In step 504, the microprocessor 112 transmits a read request to the flash memory module 120 through the control logic 114 to request to read the first logical data page. After receiving the read request, the flash memory module 120 uses a first set of threshold voltages to read a segment of the first logical data page to obtain a readout information for the decoder 134 of the flash memory controller 110 to perform a decoding operation. In this embodiment, since the first logical data page is Figure 3 The first set of threshold voltages for reading the first logical data page includes Figure 3 The threshold voltages VT1, VT4, VT6, and VT11 are shown. In addition, the segment in the first logical data page read may be a coding unit, the size of which may be 4 kilobytes (KB) or other suitable sizes, and the decoding process of the segment by the decoder 134 may include a hard decoding and / or a soft decoding, wherein the hard decoding may be a decoding method of a BCH code (Bose-Chaudhuri-Hocquenghem code) or a low-density parity-check code (LDPC), and the soft decoding may be a decoding method of an LDPC. Since the decoding operation of the decoder 134 is well known to those having ordinary knowledge in the art, the details of the decoding operation are not repeated here.

[0056] In step 506 , the decoder 134 determines whether the read information of the segment of the first logical data page is decoded successfully. If so, the process proceeds to step 518 to end the read operation of the segment of the first logical data page; if not, the process proceeds to step 508 .

[0057] In step 508, the flash memory controller 110 obtains a first readout information, a second readout information, and a third readout information of the segment of the first logical data page, wherein the first readout information, the second readout information, and the third readout information are obtained by the flash memory module 120 using the first set of threshold voltages, the first set of threshold voltages adjusted positively, and the first set of threshold voltages adjusted negatively to read the segment of the first logical data page, respectively. Figure 6For example, the control unit 136 of the flash memory controller 110 may first send a first read request to the flash memory module 120 to use the first set of threshold voltages, i.e., the threshold voltages VT1, VT4, VT6, and VT11, to read the first logical data page to obtain the first read information. Then, the control unit 136 of the flash memory controller 110 may send a second read request to the flash memory module 120 to use the first set of threshold voltages after forward adjustment, i.e., the threshold voltages (VT1+Δ), (VT4+Δ), (VT6+Δ), and (VT11+Δ) to read the first logical data page to obtain the second read information, where "Δ" may be any suitable adjustment value (voltage value). Finally, the control unit 136 of the flash memory controller 110 may send a third read request to the flash memory module 120 to use the negatively adjusted first set of threshold voltages, i.e., the threshold voltages (VT1-Δ), (VT4-Δ), (VT6-Δ), (VT11-Δ) to read the first logical data page to obtain the third read information. In this embodiment, the first read information, the second read information, and the third read information are temporarily stored in a buffer area in the control logic 114.

[0058] In this embodiment, assuming that the size of the segment of the first logical data page is 4 KB (ie, 32768 bits), each of the first read information, the second read information, and the third read information also includes 32768 bits.

[0059] In step 510, the flash memory controller 110 selects a second logical data page in the physical data page P_0. In the present embodiment, the second logical data page is determined based on the first set of critical voltages used to read the first logical data page. Specifically, the two adjacent states of each critical voltage in the first set of critical voltages correspond to the same bit value in the second logical data page, and the four bit values ​​corresponding to the four critical voltages of the first set of critical voltages in the second logical data page include two "1"s and two "0". In addition, the two adjacent states of the four critical voltages included in the first set of critical voltages include (1,0), (0,1), (1,0), (0,1) in the first logical data page, and the two sets of states (1,0) correspond to the bit values ​​"1" and "0" of the second logical data page, respectively, and the other two sets of states (0,1) also correspond to the bit values ​​"1" and "0" of the second logical data page, respectively. Figure 3 For example, the second logical data page can be Figure 3A logical data page for storing upper bits, wherein two states S0 and S1 adjacent to a critical voltage VT1 in the first set of critical voltages correspond to the same bit value "1" in the second logical data page, two states S3 and S4 adjacent to a critical voltage VT4 in the first set of critical voltages correspond to the same bit value "0" in the second logical data page, two states S5 and S6 adjacent to a critical voltage VT6 in the first set of critical voltages correspond to the same bit value "0" in the second logical data page, and two states S10 and S11 adjacent to a critical voltage VT11 in the first set of critical voltages correspond to the same bit value "1" in the second logical data page.

[0060] In step 512, the control unit 136 of the microprocessor 112 sends a read request to the flash memory module 120 to request to read the second logical data page. After receiving the read request, the flash memory module 120 uses a second set of threshold voltages to read the segment of the second logical data page to obtain a fourth read information, wherein the fourth read information can be undecoded data or decoded data that has been decoded by the decoder 134. In this embodiment, since the second logical data page is Figure 3 The second set of threshold voltages for reading the second logical data page includes Figure 3 The threshold voltages VT2, VT8, and VT14 are shown. In addition, the segment in the second logical data page read and the segment in the second logical data page read in steps 504 and 508 correspond to the same memory cell.

[0061] In this embodiment, the fourth read-out information of the segment of the second logical data page has the same size as the first read-out information, the second read-out information and the third read-out information mentioned above, that is, assuming that the size of the segment of the first logical data page is 32768 bits, then each of the fourth read-out information of the segment of the second logical data page, the first read-out information, the second read-out information and the third read-out information of the first logical data page will also include 32768 bits.

[0062] In addition, in this process, it is assumed that the segment of the second logical data page can be successfully decoded. If the segment of the second logical data page cannot be successfully decoded, it can be decoded through other suitable decoding methods, such as redundant array of independent disks (RAID) decoding method.

[0063] In step 514, the control logic 114 determines the adjustment direction of the four threshold voltages in the first set of threshold voltages according to the fourth readout information of the segment of the second logical data page, the first readout information, the second readout information and the third readout information of the first logical data page, so as to determine an adjusted first set of threshold voltages. Figure 7 , wherein the fourth read information of the second logical data page, the first read information of the first logical data page, the second read information and the third read information are generated by reading the memory cells M_0-M_A of the physical data page P_0 shown in the second at different time points, wherein "A" in this embodiment may be "32767". To explain in detail, first, the comparison unit 139 compares the first read information of the first logical data page with the second read information when the fourth read information of the second logical data page is equal to a first logical value (e.g., "1"), and the counting unit 138 then counts the number of first bit flippings and second bit flippings occurring in the second read information relative to the first read information. In this embodiment, the first bit inversion may be a change from "1" to "0", that is, the bit value read from the same memory cell is "1" in the first read information, but "0" in the second read information; and the second bit inversion may be a change from "0" to "1", that is, the bit value read from the same memory cell is "0" in the first read information, but "1" in the second read information. Then, the comparison unit 139 compares the first read information and the second read information of the first logical data page when the fourth read information of the second logical data page is equal to a second logical value (e.g., "0"), and the counting unit 138 calculates the number of the first bit inversion and the second bit inversion that occur in the second read information relative to the first read information.

[0064] Next, the comparison unit 139 compares the first read information of the first logical data page with the third read information when the fourth read information of the second logical data page is equal to the first logical value (e.g., "1"), and the counting unit 138 calculates the number of first bit inversions and second bit inversions that occur in the third read information relative to the first read information. In this embodiment, the first bit inversion may be a change from "1" to "0", that is, the bit value read from the same memory cell is "1" in the first read information, but "0" in the third read information; and the second bit inversion may be a change from "0" to "1", that is, the bit value read from the same memory cell is "0" in the first read information, but "1" in the third read information. Finally, the comparison unit 139 compares the first read information and the third read information of the first logical data page when the fourth read information of the second logical data page is equal to the second logical value (e.g., "0"), and the counting unit 138 then calculates the number of first bit inversions and second bit inversions that occur in the third read information relative to the first read information.

[0065] In this embodiment, eight counting values ​​can be obtained by calculating the number of first bit inversions and second bit inversions of the second read information relative to the first read information when the fourth read information of the second logical data page is equal to "1" and "0" respectively, and the number of first bit inversions and second bit inversions of the third read information relative to the first read information. These eight counting values ​​can be used to correctly determine the adjustment directions of the four threshold voltages VT1, VT4, VT6, and VT11 in the first set of threshold voltages.

[0066] For example, assuming that when the fourth read information of the second logical data page is equal to "1", the number of second read information with respect to the first read information that has the second bit inversion ("0" becomes "1") is N1, and the number of third read information with respect to the first read information that has the first bit inversion ("1" becomes "0") is N2, then if N1 is greater than N2, it means that the number of newly added "1"s after using the critical voltage (VT1+Δ) to read the first logical data page will be greater than the number of newly added "0"s after using the critical voltage (VT1-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S0 and state S1 should be located on the left side of the critical voltage VT1, that is, the critical voltage VT1 should be reduced to obtain a better adjusted critical voltage VT1'. Similarly, if N1 is less than N2, it means that the number of newly added "1"s after using the critical voltage (VT1+Δ) to read the first logical data page will be less than the number of newly added "0"s after using the critical voltage (VT1-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S0 and state S1 should be located to the right of the critical voltage VT1, that is, the critical voltage VT1 should be increased to obtain a better adjusted critical voltage VT1'.

[0067] Assuming that when the fourth read information of the second logical data page is equal to "1", the number of the second read information that has the first bit inversion ("1" becomes "0") relative to the first read information is N3, and the number of the third read information that has the second bit inversion ("0" becomes "1") relative to the first read information is N4, then if N3 is greater than N4, it means that the number of "0"s added after using the critical voltage (VT11+Δ) to read the first logical data page will be greater than the number of "1"s added after using the critical voltage (VT11-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S10 and state S11 should be located on the left side of the critical voltage VT11, that is, the critical voltage VT11 should be reduced to obtain a better adjusted critical voltage VT11'. Similarly, if N3 is less than N4, it means that the number of newly added "0"s after using the critical voltage (VT11+Δ) to read the first logical data page will be less than the number of newly added "1"s after using the critical voltage (VT11-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S10 and state S11 should be located on the right side of the critical voltage VT11, that is, the critical voltage VT11 should be increased to obtain a better adjusted critical voltage VT11'.

[0068] Assuming that when the fourth read information of the second logical data page is equal to "0", the number of the second read information that has the first bit inversion ("1" becomes "0") relative to the first read information is N5, and the number of the third read information that has the second bit inversion ("0" becomes "1") relative to the first read information is N6, then if N5 is greater than N6, it means that the number of newly added "0"s after using the critical voltage (VT4+Δ) to read the first logical data page will be greater than the number of newly added "1"s after using the critical voltage (VT4-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S3 and state S4 should be located on the left side of the critical voltage VT4, that is, the critical voltage VT4 should be reduced to obtain a better adjusted critical voltage VT4'. Similarly, if N5 is less than N6, it means that the number of newly added "0"s after using the critical voltage (VT4+Δ) to read the first logical data page will be less than the number of newly added "1"s after using the critical voltage (VT4-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S3 and state S4 should be located to the right of the critical voltage VT4, that is, the critical voltage VT4 should be increased to obtain a better adjusted critical voltage VT4'.

[0069] Assuming that when the fourth read information of the second logical data page is equal to "0", the number of second read information with respect to the first read information that has the second bit inversion ("0" becomes "1") calculated is N7, and the number of third read information with respect to the first read information that has the first bit inversion ("1" becomes "0") is N8, then if N7 is greater than N8, it means that the number of newly added "1"s after using the critical voltage (VT6+Δ) to read the first logical data page will be greater than the number of newly added "0"s after using the critical voltage (VT6-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S5 and state S6 should be located on the left side of the critical voltage VT6, that is, the critical voltage VT6 should be reduced to obtain a better adjusted critical voltage VT6'. Similarly, if N7 is smaller than N8, it means that the number of newly added "1"s after using the critical voltage (VT6+Δ) to read the first logical data page will be smaller than the number of newly added "0"s after using the critical voltage (VT6-Δ) to read the first logical data page. Therefore, the intersection of the distribution of state S5 and state S6 should be located to the right of the critical voltage VT6, that is, the critical voltage VT6 should be increased to obtain a better adjusted critical voltage VT6'.

[0070] As described above, after determining the adjustment directions of the four threshold voltages VT1, VT4, VT6, and VT11, the control unit 136 can determine the adjusted first set of threshold voltages. Figure 6For example, the adjusted first set of critical voltages includes (VT1-Δ), (VT4-Δ), (VT6+Δ), and (VT11+Δ).

[0071] In step 516, the microprocessor 112 transmits a read request to the flash memory module 120 through the control logic 114 to request to read the first logical data page again, and controls the flash memory module 120 to use the adjusted first set of threshold voltages to read the segment of the first logical data page to obtain read information for the decoder 134 of the flash memory controller 110 to perform a decoding operation.

[0072] As described above, when the first logical data page cannot be successfully decoded, the present embodiment can read the contents of the second logical data page and the first logical data page to adjust the first set of critical voltages to generate an adjusted first set of critical voltages, and use the adjusted first set of critical voltages again to read the first logical data page, thereby greatly increasing the probability of successful reading / decoding.

[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for accessing a flash memory module, comprising: Using a first set of threshold voltages to read a first logical data page of a physical data page in the flash memory module to generate read information; Decoding the read information, if the read information cannot be successfully decoded, respectively using the first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read the first logic data page, to respectively obtain a first read information, a second read information, and a third read information; Selecting a second logical data page of the physical data page; Using a second set of threshold voltages to read the second logic data page to generate a fourth readout information; Adjusting the first set of threshold voltages according to the first readout information, the second readout information, the third readout information, and the fourth readout information to generate an adjusted first set of threshold voltages; and The first logic data page in the flash memory module is read using the adjusted first set of threshold voltages.

2. The method according to claim 1, characterized in that The first group of critical voltages includes a first critical voltage, a second critical voltage, a third critical voltage and a fourth critical voltage; the first group of critical voltages after positive adjustment includes the first critical voltage plus an adjustment value, a second critical voltage plus the adjustment value, the third critical voltage plus the adjustment value, and the fourth critical voltage plus the adjustment value; and the first group of critical voltages after negative adjustment includes the first critical voltage minus the adjustment value, the second critical voltage minus the adjustment value, the third critical voltage minus the adjustment value, and the fourth critical voltage minus the adjustment value.

3. The method according to claim 1, characterized in that The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; And two adjacent states of each threshold voltage in the first set of threshold voltages correspond to the same bit value in the second logical data page.

4. The method according to claim 3, characterized in that Each memory cell is used to store 4 bits, and each memory cell has 16 states; and the first set of critical voltages includes a first critical voltage, a second critical voltage, a third critical voltage and a fourth critical voltage, and the four bit values ​​corresponding to the second logical data page include two "1"s and two "0"s; and the two states adjacent to the first critical voltage, the second critical voltage, the third critical voltage and the fourth critical voltage include (1,0), (0,1), (1,0), (0,1) in the first logical data page, and the two sets of states (1,0) correspond to the bit values ​​"1" and "0" of the second logical data page, respectively, and the other two sets of states (0,1) also correspond to the bit values ​​"1" and "0" of the second logical data page, respectively.

5. The method according to claim 4, characterized in that The step of adjusting the first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information to generate the adjusted first set of threshold voltages comprises: When the fourth read information is equal to a first logic value, the first read information of the first logic data page is compared with the second read information, and a number of first bit inversions and a number of second bit inversions occurring in the second read information relative to the first read information are calculated to obtain a first count value and a second count value; When the fourth read information is equal to a second logic value, the first read information of the first logic data page is compared with the second read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the second read information relative to the first read information are calculated to obtain a third count value and a fourth count value; When the fourth read information is equal to the first logic value, the first read information of the first logic data page is compared with the second read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the second read information relative to the first read information are calculated to obtain a fifth count value and a sixth count value; as well as When the fourth read information is equal to the second logic value, the first read information of the first logic data page is compared with the third read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the third read information relative to the first read information are calculated to obtain a seventh count value and an eighth count value; and The adjustment directions of the first critical voltage, the second critical voltage, the third critical voltage and the fourth critical voltage are determined according to the first count value, the second count value, the third count value, the fourth count value, the fifth count value, the sixth count value, the seventh count value and the eighth count value to generate the adjusted first set of critical voltages.

6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, and the flash memory controller comprises: A read-only memory for storing a program code; a buffer memory; and a microprocessor for executing the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: Using a first set of threshold voltages to read a first logical data page of a physical data page in the flash memory module to generate read information; Decoding the read information, if the read information cannot be successfully decoded, respectively using the first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read the first logic data page, to respectively obtain a first read information, a second read information, and a third read information; Selecting a second logical data page of the physical data page; Using a second set of threshold voltages to read the second logic data page to generate a fourth readout information; Adjusting the first set of threshold voltages according to the first readout information, the second readout information, the third readout information, and the fourth readout information to generate an adjusted first set of threshold voltages; and The first logic data page in the flash memory module is read using the adjusted first set of threshold voltages.

7. The flash memory controller according to claim 6, wherein: The first group of critical voltages includes a first critical voltage, a second critical voltage, a third critical voltage and a fourth critical voltage; the first group of critical voltages after positive adjustment includes the first critical voltage plus an adjustment value, a second critical voltage plus the adjustment value, the third critical voltage plus the adjustment value, and the fourth critical voltage plus the adjustment value; and the first group of critical voltages after negative adjustment includes the first critical voltage minus the adjustment value, a second critical voltage minus the adjustment value, the third critical voltage minus the adjustment value, and the fourth critical voltage minus the adjustment value.

8. The flash memory controller according to claim 6, wherein: The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; And two adjacent states of each threshold voltage in the first set of threshold voltages correspond to the same bit value in the second logical data page.

9. The flash memory controller according to claim 8, wherein: Each memory cell is used to store 4 bits, and each memory cell has 16 states; and the first set of critical voltages includes a first critical voltage, a second critical voltage, a third critical voltage and a fourth critical voltage, and the four bit values ​​corresponding to the second logical data page include two "1"s and two "0"s; and the two states adjacent to the first critical voltage, the second critical voltage, the third critical voltage and the fourth critical voltage include (1,0), (0,1), (1,0), (0,1) in the first logical data page, and the two sets of states (1,0) correspond to the bit values ​​"1" and "0" of the second logical data page, respectively, and the other two sets of states (0,1) also correspond to the bit values ​​"1" and "0" of the second logical data page, respectively.

10. The flash memory controller according to claim 9, wherein: The step of adjusting the first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information to generate the adjusted first set of threshold voltages comprises: When the fourth read information is equal to a first logic value, the first read information of the first logic data page is compared with the second read information, and a number of first bit inversions and a number of second bit inversions occurring in the second read information relative to the first read information are calculated to obtain a first count value and a second count value; When the fourth read information is equal to a second logic value, the first read information of the first logic data page is compared with the second read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the second read information relative to the first read information are calculated to obtain a third count value and a fourth count value; When the fourth read information is equal to the first logic value, the first read information of the first logic data page is compared with the second read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the second read information relative to the first read information are calculated to obtain a fifth count value and a sixth count value; as well as When the fourth read information is equal to the second logic value, the first read information of the first logic data page is compared with the third read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the third read information relative to the first read information are calculated to obtain a seventh count value and an eighth count value; and The adjustment directions of the first critical voltage, the second critical voltage, the third critical voltage and the fourth critical voltage are determined according to the first count value, the second count value, the third count value, the fourth count value, the fifth count value, the sixth count value, the seventh count value and the eighth count value to generate the adjusted first set of critical voltages.

11. A memory device comprising: a flash memory module; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: Using a first set of threshold voltages to read a first logical data page of a physical data page in the flash memory module to generate read information; Decoding the read information, if the read information cannot be successfully decoded, respectively using the first set of threshold voltages, a first set of threshold voltages adjusted positively, and a first set of threshold voltages adjusted negatively to read the first logic data page, to respectively obtain a first read information, a second read information, and a third read information; Selecting a second logical data page of the physical data page; Using a second set of threshold voltages to read the second logic data page to generate a fourth readout information; Adjusting the first set of threshold voltages according to the first readout information, the second readout information, the third readout information, and the fourth readout information to generate an adjusted first set of threshold voltages; and The first logic data page in the flash memory module is read using the adjusted first set of threshold voltages.

12. The memory device according to claim 11, characterized in that The first group of critical voltages includes a first critical voltage, a second critical voltage, a third critical voltage and a fourth critical voltage; the first group of critical voltages after positive adjustment includes the first critical voltage plus an adjustment value, a second critical voltage plus the adjustment value, the third critical voltage plus the adjustment value, and the fourth critical voltage plus the adjustment value; and the first group of critical voltages after negative adjustment includes the first critical voltage minus the adjustment value, a second critical voltage minus the adjustment value, the third critical voltage minus the adjustment value, and the fourth critical voltage minus the adjustment value.

13. The memory device according to claim 11, characterized in that The physical data page includes a plurality of memory cells, each memory cell is used to store a plurality of bits, each memory cell has a plurality of states, and the plurality of states are used to indicate different combinations of the plurality of bits; And two adjacent states of each threshold voltage in the first set of threshold voltages correspond to the same bit value in the second logical data page.

14. The memory device according to claim 13, characterized in that Each memory cell is used to store 4 bits, and each memory cell has 16 states; and the first set of critical voltages includes a first critical voltage, a second critical voltage, a third critical voltage and a fourth critical voltage, and the four bit values ​​corresponding to the second logical data page include two "1"s and two "0"s; and the two states adjacent to the first critical voltage, the second critical voltage, the third critical voltage and the fourth critical voltage include (1,0), (0,1), (1,0), (0,1) in the first logical data page, and the two sets of states (1,0) correspond to the bit values ​​"1" and "0" of the second logical data page, respectively, and the other two sets of states (0,1) also correspond to the bit values ​​"1" and "0" of the second logical data page, respectively.

15. The memory device according to claim 14, characterized in that The step of adjusting the first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information to generate the adjusted first set of threshold voltages comprises: When the fourth read information is equal to a first logic value, the first read information of the first logic data page is compared with the second read information, and a number of first bit inversions and a number of second bit inversions occurring in the second read information relative to the first read information are calculated to obtain a first count value and a second count value; When the fourth read information is equal to a second logic value, the first read information of the first logic data page is compared with the second read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the second read information relative to the first read information are calculated to obtain a third count value and a fourth count value; When the fourth read information is equal to the first logic value, the first read information of the first logic data page is compared with the second read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the second read information relative to the first read information are calculated to obtain a fifth count value and a sixth count value; as well as When the fourth read information is equal to the second logic value, the first read information of the first logic data page is compared with the third read information, and the number of the first bit inversion and the number of the second bit inversion occurring in the third read information relative to the first read information are calculated to obtain a seventh count value and an eighth count value; and The adjustment directions of the first critical voltage, the second critical voltage, the third critical voltage and the fourth critical voltage are determined according to the first count value, the second count value, the third count value, the fourth count value, the fifth count value, the sixth count value, the seventh count value and the eighth count value to generate the adjusted first set of critical voltages.

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