Methods, apparatus, equipment and media for testing the randomization effect of flash memory controllers

Abstract

The present invention proposes a method, device, equipment and medium for testing the randomization effect of a flash memory controller, and relates to the field of storage technology. The method for testing the randomization effect of a flash memory controller includes: randomizing different original data and writing them into different types of data pages of a flash memory device, and then reading and caching them from different types of data pages to obtain cache data of different types of data pages; combining and processing different cache data according to preset state data generation rules and bit reading order to obtain multiple types of state data; performing statistical calculations on the number of each type of state data to obtain a number ratio value of each type of state data; finally, calculating and comparing the number ratio values ​​to determine the randomization effect of the flash memory controller; the method can provide a reliable reference for evaluating the randomization effect of the flash memory controller by directly counting the number ratio value of each type of state data in the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a method, device, equipment and medium for testing the randomization effect of a flash memory controller. Background Art

[0002] Data randomization is an important indicator that affects the evaluation of flash memory characteristics, and it is directly related to the security of data stored in the flash memory. At present, the method commonly used to test the randomization effect of the flash memory controller is: the controller first randomizes the data, encodes it with an error correction code, and then writes the data into the flash memory. Finally, the data is read from the flash memory, decoded by the error correction method, and the effectiveness of the randomization is indirectly reflected by observing the number of errors generated during the error correction process. However, since the error correction capability of the error correction module has an upper limit, once the error exceeds its correction range, accurate evaluation results cannot be obtained. Therefore, this method is difficult to directly observe the actual effect of randomization, and it is also difficult to intuitively understand the proportion of the storage unit state distribution. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a method, device, equipment and medium for testing the randomization effect of a flash memory controller, which can provide a reliable reference for evaluating the randomization effect of a flash memory controller by directly counting the number of proportions of each type of status data in a flash memory device.

[0004] In a first aspect, an embodiment of the present invention provides a method for testing a randomization effect of a flash memory controller, which is applied to a flash memory controller, wherein the flash memory controller is electrically connected to a flash memory device, and the method comprises:

[0005] Perform random processing on different original data information respectively to obtain different randomized data;

[0006] Writing different randomized data into different types of data pages of the flash memory device respectively to obtain different storage data;

[0007] Reading and caching the stored data from different types of data pages respectively to obtain different cache data of different types of data pages;

[0008] According to a preset state data generation rule and a bit reading order, data combination processing is performed on different cache data read from different types of data pages to obtain multiple types of state data; the preset state data generation rule is determined by the type of the flash memory device;

[0009] Perform statistical calculations based on the number of status data of each type to obtain the percentage of each type of status data;

[0010] The number proportion values ​​are calculated and compared to determine the randomization effect of the randomization process performed by the flash memory controller.

[0011] In some embodiments of the present invention, when the type of the flash memory device is a three-layer storage unit flash memory, the different types of data pages include: a most significant bit data page, an intermediate significant bit data page, and a least significant bit data page; the preset state data generation rule is a first generation rule; according to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are subjected to data combination processing to obtain multiple types of state data, including:

[0012] When the flash memory device is a three-layer storage unit flash memory, determining a bit to be read currently from the bit reading sequence;

[0013] Based on the current bit to be read, obtaining a first state value for the cache data read from the most significant bit data page, obtaining a second state value for the cache data read from the middle significant bit data page, and obtaining a third state value for the cache data read from the least significant bit data page;

[0014] According to the first generation rule, the first state value is determined as the high value of the state data, the second state value is determined as the median value of the state data, and the third state value is determined as the low value of the state data, and the high value, the median value, and the low value are sequentially concatenated to obtain the state data corresponding to the bit currently to be read;

[0015] The next bit to be read is determined from the bit reading sequence, and the status data corresponding to the next bit to be read is determined, until the status data corresponding to all bits indicated by the bit reading sequence are obtained.

[0016] In some embodiments of the present invention, when the type of the flash memory device is a multi-layer storage unit flash memory, the different types of data pages include: a most significant bit data page and a least significant bit data page; the preset state data generation rule is a second generation rule; according to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are subjected to data combination processing to obtain multiple types of state data, including:

[0017] When the flash memory device is a multi-layer storage unit flash memory, determining a bit to be read currently from the bit reading sequence;

[0018] Based on the current bit to be read, obtaining a first state value for the cache data read from the most significant bit data page, and obtaining a second state value for the cache data read from the least significant bit data page;

[0019] According to the second generation rule, the first state value is determined as the high-order value of the state data, and the second state value is determined as the low-order value of the state data, and the high-order value and the low-order value are sequentially concatenated to obtain the state data corresponding to the bit to be read currently;

[0020] The next bit to be read is determined from the bit reading sequence, and the status data corresponding to the next bit to be read is determined, until the status data corresponding to all bits indicated by the bit reading sequence are obtained.

[0021] In some embodiments of the present invention, when the type of the flash memory device is a four-layer storage unit flash memory, the different types of data pages include: a most significant bit data page, a second most significant bit data page, a second least significant bit data page and a least significant bit data page; the preset state data generation rule is a third generation rule; according to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are subjected to data combination processing to obtain multiple types of state data, including:

[0022] When the flash memory device is a four-layer storage unit flash memory, determining a bit to be read currently from the bit reading sequence;

[0023] Based on the bit currently to be read, a first state value is obtained for the cache data read from the most significant bit data page, a second state value is obtained for the cache data read from the second most significant bit data page, a third state value is obtained for the cache data read from the second least significant bit data page, and a fourth state value is obtained for the cache data read from the least significant bit data page;

[0024] According to the third generation rule, the first state value is determined as the high-order value of the state data, the second state value is determined as the second-highest-order value of the state data, the third state value is determined as the second-lowest-order value of the state data, and the fourth state value is determined as the low-order value of the state data, and the high-order value, the second-highest-order value, the second-lowest-order value, and the low-order value are sequentially concatenated to obtain the state data corresponding to the bit to be currently read;

[0025] The next bit to be read is determined from the bit reading sequence, and the status data corresponding to the next bit to be read is determined, until the status data corresponding to all bits indicated by the bit reading sequence are obtained.

[0026] In some embodiments of the present invention, the statistical calculation process is performed according to the quantity of each type of status data to obtain the quantity ratio of each type of status data, including:

[0027] Counting a first quantity of each type of status data;

[0028] The total number of statistical status data;

[0029] The first quantity of each type of status data is compared with the total quantity to obtain a quantity ratio of each type of status data.

[0030] In some embodiments of the present invention, calculating and comparing the number proportion values ​​to determine the randomization effect of the randomization process performed by the flash memory controller includes:

[0031] Calculate the variance of the quantity proportion of all types of status data to obtain the variance value;

[0032] Comparing the variance value with a variance threshold, wherein the variance threshold is determined by the type of the flash memory device;

[0033] When the variance value is less than or equal to the variance threshold, the randomization effect is judged to be qualified;

[0034] When the variance value is greater than the variance threshold, it is determined that the randomization effect is unqualified.

[0035] In some embodiments of the present invention, the calculating and comparing the quantity proportion values ​​to determine the randomization effect of the randomization process performed by the flash memory controller includes:

[0036] Calculating an error value between a quantity ratio value of each type of status data and an ideal ratio value, wherein the ideal ratio value is determined by the type of the flash memory device, and the error value is expressed as a ratio of a difference between the quantity ratio value of the status data and the ideal ratio value relative to the ideal ratio value;

[0037] comparing the absolute value of the error value of each type of status data with the error threshold;

[0038] When the absolute values ​​of the error values ​​of all types of status data are less than or equal to the error threshold, the randomization effect is judged to be qualified;

[0039] When there is at least one type of state data whose absolute value of the error value is greater than the error threshold, it is determined that the randomization effect is unqualified.

[0040] In a second aspect, an embodiment of the present invention provides an apparatus for testing a randomization effect of a flash memory controller, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the method for testing the randomization effect of a flash memory controller as described in the first aspect above.

[0041] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the device for testing the randomization effect of a flash memory controller as described in the second aspect above.

[0042] In a fourth aspect, an embodiment of the present invention provides a computer-readable medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the method for testing the randomization effect of a flash memory controller as described in the first aspect above.

[0043] The method for testing the randomization effect of a flash memory controller according to an embodiment of the present invention has at least the following beneficial effects:

[0044] Different original data information are randomly processed to obtain different randomized data; different randomized data are written into different types of data pages of the flash memory device to obtain different storage data; storage data are read from different types of data pages and cached to obtain different cache data of different types of data pages; different cache data read from different types of data pages are combined according to preset state data generation rules and bit reading order to obtain multiple types of state data; the preset state data generation rules are determined by the type of the flash memory device; statistical calculation is performed according to the number of each type of state data to obtain the number ratio of each type of state data; the number ratio is calculated and compared to determine the randomization effect of the randomization process performed by the flash memory controller. According to the technical solution of the embodiment of the present invention, different cache data read from different types of data pages are combined according to preset state data generation rules and bit reading order, and the number ratio of each type of state data in the flash memory device is directly counted, providing a reliable reference for evaluating the randomization effect of the flash memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a flow chart of a method for testing randomization effect of a flash memory controller provided by an embodiment of the present invention;

[0046] Figure 2It is a flow chart of a method for testing the randomization effect of a flash memory controller when the type of the flash memory device is a three-layer storage unit flash memory provided by an embodiment of the present invention;

[0047] Figure 3 It is a statistical diagram of different types of status data obtained when the type of the flash memory device is a three-layer storage unit flash memory provided by an embodiment of the present invention;

[0048] Figure 4 It is a flow chart of a method for testing the randomization effect of a flash memory controller when the type of the flash memory device is a multi-layer storage unit flash memory provided by an embodiment of the present invention;

[0049] Figure 5 It is a flow chart of a method for testing the randomization effect of a flash memory controller when the type of the flash memory device is a four-layer storage unit flash memory provided by an embodiment of the present invention;

[0050] Figure 6 yes Figure 1 Flow chart of step S15;

[0051] Figure 7 yes Figure 1 A flowchart of an embodiment of step S16;

[0052] Figure 8 yes Figure 1 A flowchart of another embodiment of step S16;

[0053] Fig. 9 It is a structural diagram of a device for testing randomization effect of a flash memory controller provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0055] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0056] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0057] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0058] The embodiment of the present invention provides a method for testing the randomization effect of a flash memory controller, a device for testing the randomization effect of a flash memory controller, an electronic device for testing the randomization effect of a flash memory controller, and a computer-readable storage medium. The method for testing the randomization effect of a flash memory controller includes: randomizing different original data and writing them into different types of data pages of a flash memory device, and then reading and caching them from different types of data pages to obtain different cache data of different types of data pages; combining and processing different cache data according to preset state data generation rules and bit reading order to obtain multiple types of state data; performing statistical calculations on the number of each type of state data to obtain the number ratio of each type of state data; finally, calculating and comparing the number ratio values ​​to determine the randomization effect of the flash memory controller; the method can provide a reliable reference for evaluating the randomization effect of the flash memory controller by directly counting the number ratio of each type of state data in the flash memory device.

[0059] The following further describes the method for testing the randomization effect of a flash memory controller according to an embodiment of the present invention based on the accompanying drawings.

[0060] Reference Figure 1 , Figure 1 A flowchart of a method for testing the randomization effect of a flash memory controller provided by an embodiment of the present invention, the method for testing the randomization effect of a flash memory controller includes but is not limited to the following steps:

[0061] S11, performing random processing on different original data information respectively to obtain different randomized data;

[0062] S12, writing different randomized data into different types of data pages of the flash memory device to obtain different storage data;

[0063] S13, reading and caching the stored data from different types of data pages respectively, to obtain different cache data of different types of data pages;

[0064] S14, performing data combination processing on different cache data read from different types of data pages according to a preset state data generation rule and a bit reading sequence to obtain multiple types of state data; the preset state data generation rule is determined by the type of the flash memory device;

[0065] S15, performing statistical calculations based on the quantity of each type of status data to obtain a percentage value of the quantity of each type of status data;

[0066] S16, calculating and comparing the quantity proportion values ​​to determine the randomization effect of the randomization process performed by the flash memory controller.

[0067] In step S11, different original data information is randomized respectively, wherein the number of original data is determined according to the type of device. Different flash memory devices have different numbers of original data. In some embodiments, the types of flash memory devices include triple-level cell flash memory (Triple-Level Cell, TLC), multi-level cell flash memory (Multi-Level Cell, MLC), and quad-level cell flash memory (Quad-Level Cell, QLC); in the triple-level cell flash memory, three different original data information are randomized respectively to obtain three different randomized data; in the multi-level cell flash memory, two different original data information are randomized respectively to obtain two different randomized data; in the quad-level cell flash memory, four different original data information are randomized respectively to obtain four different randomized data.

[0068] In step S12, different randomized data are written into different types of data pages of the flash memory device to obtain different storage data. In a three-layer storage unit flash memory, different types of data pages include: the most significant bit data page (Most Significant Bit, MSB), the middle significant bit data page (Central Significant Bit, CSB) and the least significant bit data page (Least Significant Bit, LSB). In a multi-layer storage unit flash memory, different types of data pages include: the most significant bit data page (Most Significant Bit, MSB) and the least significant bit data page (Least Significant Bit, LSB). In a four-layer storage unit flash memory, different types of data pages include: the most significant bit data page (Most Significant Bit, MSB), the second most significant bit data page (Second Most Significant Bit), the second least significant bit data page (Second Least Significant Bit) and the least significant bit data page (Least Significant Bit, LSB).

[0069] In step S13, storage data is read and cached from different types of data pages respectively. It is necessary to determine the data type of the data to be read, read the corresponding data from the flash memory device according to the determined data type and location, and then cache the read data into a temporary storage area. When caching data, it is necessary to clearly distinguish different types of data pages.

[0070] In step S14, the bit reading order refers to accessing each bit of the cache data in a specific order. The preset state data generation rule refers to a rule for determining the currently accessed bit, reading data at the bit according to different types of data pages, and then performing combined processing. The preset state data generation rule is determined by the type of flash memory device, and the state data generation rules of different flash memory devices are different.

[0071] In step S15, each type of status data refers to the data formed by reading data on different data pages from the cache data and combining them. On each bit, there are two states of 0 or 1, and the types of status data after different flash memory devices are combined are different. There are eight types of status data in the three-layer storage unit flash memory, which are 000, 001, 010, 011, 100, 101, 110, 111; there are four types of status data in the multi-layer storage unit flash memory, which are 00, 10, 01, 11; there are sixteen types of status data in the four-layer storage unit flash memory, which are 0000, 1000, 0100, 0010, 0001, 1100, 1010, 1001, 0110, 0101, 0011, 1110, 1101, 1011, 0111, 1111. Statistics are performed according to the number of each type of status data, that is, the number of each type of status data is counted. Taking a multi-layer storage unit flash memory as an example, the number of state data with a state of 00, the number of state data with a state of 10, the number of state data with a state of 01 and the number of state data with a state of 11 are counted.

[0072] In step S16, the calculation and comparison of the quantity proportion values ​​include two methods. One method is to judge the effect of the randomization of the flash memory controller by comparing the variance value of the quantity proportion values ​​of all types of status data with the size of the variance threshold; the other method is to judge the effect of the randomization of the flash memory controller by judging the size of the error value between the quantity proportion of each type of status data and the ideal proportion value.

[0073] It should be noted that the method for testing the randomization effect of the flash memory controller can be used to count the number of each type of status data in a wordline of a flash memory device, the number of each type of status data in a block of a flash memory device, and the number of each type of status data in the entire flash memory chip. The method and scope of use are flexible.

[0074] In step S11 to step S16, different original data information is randomized to obtain different randomized data; different randomized data are written into different types of data pages of the flash memory device to obtain different storage data; storage data is read from different types of data pages and cached to obtain different cache data of different types of data pages; according to the preset state data generation rule and the bit reading order, different cache data read from different types of data pages are combined to obtain multiple types of state data; the preset state data generation rule is determined by the type of the flash memory device; according to the number of each type of state data, statistical calculation is performed to obtain the number ratio of each type of state data; the number ratio is calculated and compared to determine the randomization effect of the randomization process performed by the flash memory controller. According to the technical solution of the embodiment of the present invention, different cache data read from different types of data pages are combined to obtain the number ratio of each type of state data in the flash memory device through the preset state data generation rule and the bit reading order, and the number ratio of each type of state data in the flash memory device is directly counted, providing a reliable reference for evaluating the randomization effect of the flash memory controller.

[0075] According to some embodiments of the present invention, referring to Figure 2 When the flash memory device is a three-layer storage unit flash memory, different types of data pages include: a most significant bit data page, a middle significant bit data page, and a least significant bit data page; the preset state data generation rule is a first generation rule; according to the preset state data generation rule and the bit reading order, different cache data read from different types of data pages are combined and processed to obtain multiple types of state data, including but not limited to the following steps:

[0076] S21, when the flash memory device is a three-layer storage unit flash memory, determining a current bit to be read from a bit reading sequence;

[0077] S22, based on the current bit to be read, obtaining a first state value for the cache data read from the most significant bit data page, obtaining a second state value for the cache data read from the middle significant bit data page, and obtaining a third state value for the cache data read from the least significant bit data page;

[0078] S23, according to the first generation rule, determine the first state value as the high value of the state data, determine the second state value as the median value of the state data, determine the third state value as the low value of the state data, and sequentially concatenate the high value, the median value, and the low value to obtain the state data corresponding to the bit to be read currently;

[0079] S24, determining the next bit to be read from the bit reading sequence, and determining the state data corresponding to the next bit to be read, until the state data corresponding to all the bits indicated by the bit reading sequence are obtained.

[0080] It should be noted that, refer to Figure 3 , the bit reading order refers to the bit column in the figure, starting from the 0th bit, reading each bit in the different cache data in sequence, and this process continues until each bit of cache data is completely read. When the currently read bit is determined, the cache data read from the most significant bit is used as the first state value, the cache data read from the middle significant bit is used as the second state value, and the cache data read from the least significant bit is used as the third state value. The first state value is determined as the high value, which is expressed as Figure 3 The second state value is determined as the median value, which is expressed as Figure 3 The third state value is determined as the low-order value, which is expressed as Figure 3 Finally, the high value, the middle value and the low value are combined in sequence to obtain eight different types of status data of the three-level storage unit flash memory, which is expressed as Figure 3 Status data in .

[0081] In step S21 to step S24, the currently read bit can be determined according to the bit reading order, and then according to the currently read bit and the first generation rule, the high value, median value and low value of the cache data of different page types are read and combined, so as to obtain the status data corresponding to each bit in the three-layer storage unit flash memory.

[0082] According to some embodiments of the present invention, referring to Figure 4 When the flash memory device is a multi-layer storage unit flash memory, different types of data pages include: a most significant bit data page and a least significant bit data page; the preset state data generation rule is a second generation rule; according to the preset state data generation rule and the bit reading order, different cache data read from different types of data pages are combined and processed to obtain multiple types of state data, including but not limited to the following steps:

[0083] S31, when the flash memory device is a multi-layer storage unit flash memory, determining a current bit to be read from a bit reading sequence;

[0084] S32, based on the current bit to be read, obtaining a first state value for the cache data read from the most significant bit data page, and obtaining a second state value for the cache data read from the least significant bit data page;

[0085] S33, according to the second generation rule, determining the first state value as the high-order value of the state data, determining the second state value as the low-order value of the state data, and sequentially concatenating the high-order value and the low-order value to obtain the state data corresponding to the bit to be read currently;

[0086] S34, determining the next bit to be read from the bit reading sequence, and determining the state data corresponding to the next bit to be read, until the state data corresponding to all the bits indicated by the bit reading sequence are obtained.

[0087] It should be noted that the principle of the bit reading order of the multi-layer storage unit flash memory is similar to that of the bit reading order of the three-layer storage unit flash memory, both of which start reading from the 0th bit of the cache data until all bits are read. Since the data page type is determined by the type of flash memory device, the page type of the multi-layer storage unit flash memory includes the most significant bit data page and the least significant bit data page. When reading data, it is only necessary to read the most significant bit data as the first state value and the least significant bit data as the second state value. The first state value is used as the high value and the second state value is used as the low value to combine to obtain four different types of state data of the multi-layer storage unit flash memory.

[0088] In step S31 to step S34, the currently read bit can be determined according to the bit reading order, and then according to the currently read bit and the second generation rule, the high and low values ​​of the cache data of different page types are read and combined to obtain the status data corresponding to each bit in the multi-layer storage unit flash memory.

[0089] According to some embodiments of the present invention, referring to Figure 5 When the flash memory device is a four-layer storage unit flash memory, different types of data pages include: a most significant bit data page, a second most significant bit data page, a second least significant bit data page, and a least significant bit data page; the preset state data generation rule is a third generation rule; according to the preset state data generation rule and the bit reading order, different cache data read from different types of data pages are combined and processed to obtain multiple types of state data, including but not limited to the following steps:

[0090] S41, when the type of the flash memory device is a four-level storage unit flash memory, determining a current bit to be read from a bit reading sequence;

[0091] S42, based on the bit currently to be read, obtaining a first state value for the cache data read from the most significant bit data page, obtaining a second state value for the cache data read from the second most significant bit data page, obtaining a third state value for the cache data read from the second least significant bit data page, and obtaining a fourth state value for the cache data read from the least significant bit data page;

[0092] S43, according to the third generation rule, the first state value is determined as the high value of the state data, the second state value is determined as the second high value of the state data, the third state value is determined as the second low value of the state data, and the fourth state value is determined as the low value of the state data, and the high value, the second high value, the second low value, and the low value are sequentially concatenated to obtain the state data corresponding to the bit to be read currently;

[0093] S44, determining the next bit to be read from the bit reading sequence, and determining the status data corresponding to the next bit to be read, until the status data corresponding to all the bits indicated by the bit reading sequence are obtained.

[0094] It should be noted that, since the data page type is determined by the type of flash memory device, the page types of the four-layer storage unit flash memory include the most significant bit data page, the second most significant bit data page, the second least significant bit data page and the least significant bit data page. When reading data, it is only necessary to read the most significant bit data as the first state value, the second most significant bit data as the second state value, the second least significant bit data as the third state value, and the least significant bit data as the fourth state value. The first state value is used as the high value, the second state value is used as the second most significant bit value, the third state value is used as the second least significant bit value, and the fourth state value is used as the low value to obtain sixteen different types of state data of the four-layer storage unit flash memory.

[0095] In step S41 to step S44, the currently read bit can be determined according to the bit reading order, and then according to the currently read bit and the third generation rule, the high value, the second highest value, the second lowest value, and the low value of the cache data of different page types are read and combined to obtain the status data corresponding to each bit in the four-layer storage unit flash memory.

[0096] According to some embodiments of the present invention, referring to Figure 6 ,exist Figure 1 Step S15 of the illustrated embodiment also includes but is not limited to the following steps:

[0097] S51, counting a first quantity of each type of status data;

[0098] S52, counting the total number of status data;

[0099] S53, comparing the first quantity of each type of status data with the total quantity, to obtain a quantity ratio of each type of status data.

[0100] It should be noted that, in one embodiment, the type of flash memory device is a three-layer storage flash memory, that is, the number of each state data in the eight state data of 000, 001, 010, 011, 100, 101, 110, and 111 is counted, and then the total number of the eight state data is counted, and finally the ratio of each type of state data to the total number is calculated.

[0101] In step S51 to step S53, by calculating the ratio of the quantity of each type of status data to the total quantity of all status data, the distribution of each type of status data in the overall data can be intuitively understood.

[0102] According to some embodiments of the present invention, referring to Figure 7 ,exist Figure 1 In one embodiment of step S16, the steps include but are not limited to the following steps:

[0103] S61, calculating the variance of the quantity proportion of all types of status data to obtain a variance value;

[0104] S62, comparing the variance value with a variance threshold, wherein the variance threshold is determined by the type of the flash memory device;

[0105] S63, when the variance value is less than or equal to the variance threshold, it is judged that the randomization effect is qualified;

[0106] S64: When the variance value is greater than the variance threshold, it is determined that the randomization effect is unqualified.

[0107] It should be noted that the variance threshold refers to a standard value for judging whether the randomization effect of the flash memory controller is qualified by the variance, and the variance threshold is determined by the type of the flash memory device. In one embodiment, the variance threshold of the flash memory device is 0.003. When the variance value is greater than 0.003, the randomization effect of the flash memory controller is judged to be unqualified; when the variance value is less than or equal to 0.003, the randomization effect of the flash memory controller is qualified.

[0108] In step S61 to step S64, the variance value of the quantity proportion of all types of status data is calculated, and then the variance value is compared with the variance threshold. The variance value can reflect the discreteness of the data. When the variance value is larger, it indicates that the data distribution has a greater discreteness; when the variance value is smaller, it means that the quantity proportion of each status data is relatively close, the data distribution is relatively uniform, and the randomization effect of the flash memory controller can be intuitively judged.

[0109] According to some embodiments of the present invention, referring to Figure 8 ,exist Figure 1 In another embodiment of step S16, the steps include but are not limited to the following steps:

[0110] S71, calculating the error value between the quantity ratio value of each type of status data and the ideal ratio value, wherein the ideal ratio value is determined by the type of the flash memory device, and the error value is expressed as the ratio of the difference between the quantity ratio value of the status data and the ideal ratio value to the ideal ratio value;

[0111] S72, comparing the absolute value of the error value of each type of status data with the error threshold;

[0112] S73, when the absolute values ​​of the error values ​​of all types of state data are less than or equal to the error threshold, it is determined that the randomization effect is qualified;

[0113] S74: When the absolute value of the error value of at least one type of state data is greater than the error threshold, it is determined that the randomization effect is unqualified.

[0114] It should be noted that the error value between the quantity proportion of each type of status data and the ideal proportion is calculated. The error value here refers to the relative error, that is, the relative error calculated based on the ideal proportion, which is expressed as the ratio of the difference between the quantity proportion of the status data and the ideal proportion to the ideal proportion.

[0115] It should be noted that the ideal proportion value is determined by the type of flash memory device. In a three-layer storage unit flash memory, the ideal proportion of each type of status data is one-eighth, that is, 12.5%; in a multi-layer storage unit flash memory, the ideal proportion of each type of status data is one-quarter, that is, 25%; in a multi-layer storage unit flash memory, the ideal proportion of each type of status data is one-sixteenth, that is, 6.25%. In one embodiment, the error threshold is 0.5%. When the absolute value of the error value of at least one type of status data is greater than 0.5%, the randomization effect of the flash memory controller is judged to be unqualified; when the absolute value of the error value of all types of status data is less than or equal to 0.5%, the randomization effect of the flash memory controller is judged to be qualified.

[0116] In step S71 to step S74, by comparing the error values ​​of all types of status data with the error thresholds, the randomization effect of the flash memory controller can be intuitively determined.

[0117] like Fig. 9 As shown, Fig. 9 1 is a structural diagram of a device for testing the randomization effect of a flash memory controller provided by an embodiment of the present invention. The present invention also provides a device for testing the randomization effect of a flash memory controller, comprising:

[0118] The processor 901 may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0119] The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 902, and the processor 901 calls and executes the dark image enhancement method of the embodiment of the present application;

[0120] Input / output interface 903, used to implement information input and output;

[0121] Communication interface 904, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0122] A bus 905 that transmits information between various components of the device (e.g., the processor 901, the memory 902, the input / output interface 903, and the communication interface 904);

[0123] The processor 901 , the memory 902 , the input / output interface 903 and the communication interface 904 are connected to each other in communication within the device via a bus 905 .

[0124] An embodiment of the present application also provides an electronic device, including the device for testing the randomization effect of a flash memory controller as described above.

[0125] The embodiment of the present application further provides a computer-readable medium, which stores computer-executable instructions, and the computer-executable instructions are used to execute the method for testing the randomization effect of the flash memory controller as described above.

[0126] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0127] It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0128] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions under the shared conditions without violating the spirit of the present invention. These equivalent deformations or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A method for testing the randomization effect of a flash memory controller, characterized in that: Applied to a flash memory controller, the flash memory controller is electrically connected to a flash memory device, and the method comprises: Perform random processing on different original data information respectively to obtain different randomized data; Writing different randomized data into different types of data pages of the flash memory device respectively to obtain different storage data; Reading and caching the stored data from different types of data pages respectively to obtain different cache data of different types of data pages; According to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are subjected to data combination processing to obtain multiple types of state data; the preset state data generation rule is determined by the type of the flash memory device, wherein, when the type of the flash memory device is a three-layer storage unit flash memory, the different types of data pages include: the most significant bit data page, the middle significant bit data page and the least significant bit data page; the preset state data generation rule is a first generation rule; when the type of the flash memory device is a multi-layer storage unit flash memory, the different types of data pages include: the most significant bit data page and the least significant bit data page; the preset state data generation rule is a second generation rule; when the type of the flash memory device is a four-layer storage unit flash memory, the different types of data pages include: the most significant bit data page, the second most significant bit data page, the second least significant bit data page and the least significant bit data page; the preset state data generation rule is a third generation rule; Perform statistical calculations based on the number of status data of each type to obtain the percentage of each type of status data; The number proportion values ​​are calculated and compared to determine the randomization effect of the randomization process performed by the flash memory controller.

2. The method for testing the randomization effect of a flash memory controller according to claim 1, characterized in that: According to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are processed by data combination to obtain multiple types of state data, including: When the flash memory device is a three-layer storage unit flash memory, determining a bit to be read currently from the bit reading sequence; Based on the current bit to be read, obtaining a first state value for the cache data read from the most significant bit data page, obtaining a second state value for the cache data read from the middle significant bit data page, and obtaining a third state value for the cache data read from the least significant bit data page; According to the first generation rule, the first state value is determined as the high value of the state data, the second state value is determined as the median value of the state data, and the third state value is determined as the low value of the state data, and the high value, the median value, and the low value are sequentially concatenated to obtain the state data corresponding to the bit currently to be read; The next bit to be read is determined from the bit reading sequence, and the status data corresponding to the next bit to be read is determined, until the status data corresponding to all bits indicated by the bit reading sequence are obtained.

3. The method for testing the randomization effect of a flash memory controller according to claim 1, characterized in that: According to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are processed by data combination to obtain multiple types of state data, including: When the flash memory device is a multi-layer storage unit flash memory, determining a bit to be read currently from the bit reading sequence; Based on the current bit to be read, obtaining a first state value for the cache data read from the most significant bit data page, and obtaining a second state value for the cache data read from the least significant bit data page; According to the second generation rule, the first state value is determined as the high-order value of the state data, and the second state value is determined as the low-order value of the state data, and the high-order value and the low-order value are sequentially concatenated to obtain the state data corresponding to the bit to be read currently; The next bit to be read is determined from the bit reading sequence, and the status data corresponding to the next bit to be read is determined, until the status data corresponding to all bits indicated by the bit reading sequence are obtained.

4. The method for testing the randomization effect of a flash memory controller according to claim 1, characterized in that: According to the preset state data generation rule and the bit reading order, the different cache data read from different types of data pages are processed by data combination to obtain multiple types of state data, including: When the flash memory device is a four-layer storage unit flash memory, determining a bit to be read currently from the bit reading sequence; Based on the bit currently to be read, a first state value is obtained for the cache data read from the most significant bit data page, a second state value is obtained for the cache data read from the second most significant bit data page, a third state value is obtained for the cache data read from the second least significant bit data page, and a fourth state value is obtained for the cache data read from the least significant bit data page; According to the third generation rule, the first state value is determined as the high-order value of the state data, the second state value is determined as the second-highest-order value of the state data, the third state value is determined as the second-lowest-order value of the state data, and the fourth state value is determined as the low-order value of the state data, and the high-order value, the second-highest-order value, the second-lowest-order value, and the low-order value are sequentially concatenated to obtain the state data corresponding to the bit to be currently read; The next bit to be read is determined from the bit reading sequence, and the status data corresponding to the next bit to be read is determined, until the status data corresponding to all bits indicated by the bit reading sequence are obtained.

5. The method for testing the randomization effect of a flash memory controller according to any one of claims 1 to 4, wherein the step of performing statistical calculations based on the number of each type of status data to obtain a percentage value of the number of each type of status data comprises: Counting a first quantity of each type of status data; The total number of statistical status data; The first quantity of each type of status data is compared with the total quantity to obtain a quantity ratio of each type of status data.

6. The method for testing the randomization effect of a flash memory controller according to any one of claims 1 to 4, wherein the number proportion values ​​are calculated and compared to determine the randomization effect of the randomization process performed by the flash memory controller, comprising: Calculate the variance of the quantity proportion of all types of status data to obtain the variance value; Comparing the variance value with a variance threshold, wherein the variance threshold is determined by the type of the flash memory device; When the variance value is less than or equal to the variance threshold, the randomization effect is judged to be qualified; When the variance value is greater than the variance threshold, it is determined that the randomization effect is unqualified.

7. The method for testing the randomization effect of a flash memory controller according to any one of claims 1 to 4, wherein the calculating and comparing the number proportion values ​​to determine the randomization effect of the randomization process performed by the flash memory controller comprises: Calculating an error value between a quantity ratio value of each type of status data and an ideal ratio value, wherein the ideal ratio value is determined by the type of the flash memory device, and the error value is expressed as a ratio of a difference between the quantity ratio value of the status data and the ideal ratio value relative to the ideal ratio value; comparing the absolute value of the error value of each type of status data with the error threshold; When the absolute values ​​of the error values ​​of all types of status data are less than or equal to the error threshold, the randomization effect is judged to be qualified; When there is at least one type of state data whose absolute value of the error value is greater than the error threshold, it is determined that the randomization effect is unqualified.

8. A device for testing the randomization effect of a flash memory controller, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor to enable the at least one control processor to execute the method for testing the randomization effect of a flash memory controller as described in any one of claims 1 to 7.

9. An electronic device, characterized in that: The device for testing the randomization effect of a flash memory controller as claimed in claim 8.

10. A computer-readable medium, characterized in that The computer-readable medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for testing the randomization effect of a flash memory controller according to any one of claims 1 to 7.

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