A method for implementing a multi-stack flash memory package

Abstract

The present application relates to chip packaging technical field, specifically a kind of method for realizing multi-layer flash memory package. Including the following steps: S1, stack several chips on substrate or PCB board, and adjacent chip is bonded by wire bonding;S2, on the upside of the uppermost chip, cover water-soluble adhesive sheet, water-soluble adhesive sheet wraps the side surface of the uppermost chip, the wire of the uppermost chip;S3, plastic package, plastic package material wraps chip, wire, water-soluble adhesive sheet;S4, after plastic package, the surface of the formed package is ground, and the surface of water-soluble adhesive sheet is exposed;S5, through water washing, water-soluble adhesive sheet is dissolved, and cavity is formed on the surface of package;S6, continue to stack several chips on the exposed chip surface in cavity;S7, repeat step S2 to step S5, until the stacking of all chips is completed, and cavity is plastic packaged.Compared with prior art, 3D flash memory chip 16 layers or more layers are stacked, and more storage chips are integrated in single package.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, in particular to a method for implementing multi-layer flash memory packaging. Background Art

[0002] Currently, 3D flash memory packaging involves stacking multiple flash memory chips and bonding them to a substrate or PCB. Wirebonds are then used to establish electrical connections between the flash memory chips in each layer, as well as between the chips and the substrate or PCB pads. Finally, the chips are encapsulated in a plastic mold and then processed through subsequent manufacturing steps to complete the packaging process. The industry's typical stacking layer count is 16. Higher stacking levels can cause the chips to warp and collapse, and the current stacking capacity limits the ability to integrate higher storage capacities into a single package. Summary of the Invention

[0003] In order to overcome the deficiencies of the prior art, the present invention provides a method for implementing multi-layer flash memory packaging.

[0004] To achieve the above object, a method for implementing multi-layer flash memory packaging is designed, comprising the following steps:

[0005] S1, stacking several chips on a substrate or PCB, with adjacent chips bonded by wire bonding;

[0006] S2, applying a water-soluble film to the upper side of the top chip, the water-soluble film covering the surface of one side of the top chip and the bonding wires of the top chip;

[0007] S3, plastic packaging, plastic packaging material wraps the chip, bonding wire, and water-soluble film;

[0008] S4, after the plastic packaging is completed, the surface of the formed package body is ground to expose the surface of the water-soluble film;

[0009] S5, washing with water to dissolve the water-soluble film and form a cavity on the surface of the package;

[0010] S6, stacking a plurality of chips on the chip surface exposed in the cavity, and bonding adjacent chips by wire bonding;

[0011] S7, repeating steps S2 to S5 until all chips are stacked, and then performing plastic sealing on the cavity to obtain a final package.

[0012] The number of chip layers stacked each time is 1-16 layers.

[0013] The upper and lower adjacent chips are bonded together by DAF film.

[0014] The chip is a flash memory chip.

[0015] Compared with the prior art, the present invention realizes stacking of 3D flash memory chips with more than 16 layers, and integrates more memory chips into a single package. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of step S1 of an embodiment of the present invention.

[0017] Figure 2 Schematic diagram of step S2 of an embodiment of the present invention.

[0018] Figure 3 Schematic diagram of step S3 of an embodiment of the present invention.

[0019] Figure 4 Schematic diagram of step S4 in an embodiment of the present invention.

[0020] Figure 5 Schematic diagram of step S5 of an embodiment of the present invention.

[0021] Figure 6 Schematic diagram of step S6 in an embodiment of the present invention.

[0022] Figure 7 Schematic diagram of step S7 of an embodiment of the present invention.

[0023] Figure 8 Schematic diagram of step S8 in an embodiment of the present invention.

[0024] Figure 9 Schematic diagram of step S9 of an embodiment of the present invention.

[0025] Figure 10 Schematic diagram of step S10 in an embodiment of the present invention.

[0026] Figure 11 Schematic diagram of step S11 of an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further described below with reference to the accompanying drawings.

[0028] The method for implementing multi-layer flash memory packaging in this embodiment includes the following steps:

[0029] S1, such as Figure 1 As shown, several layers of chips 3 are stacked on a substrate or PCB board 1, and adjacent chips 3 are bonded by bonding wires 6;

[0030] S2, applying a water-soluble film 5 to the upper side of the top chip 3, the water-soluble film 5 covering one side surface of the top chip 3 and the bonding wire 6 of the top chip 3;

[0031] S3, plastic encapsulation, the plastic encapsulation material 4 wraps the chip 3, the bonding wire 6, and the water-soluble film 5;

[0032] S4, after the plastic packaging is completed, the surface of the formed package body is ground to expose the surface of the water-soluble film 5;

[0033] S5, washing with water to dissolve the water-soluble film 5 and form a cavity on the surface of the package;

[0034] S6, stacking several layers of chips 3 on the surface of the chip 3 exposed in the cavity, and bonding adjacent chips 3 by bonding wires 6;

[0035] S7, applying a water-soluble film 5 to the upper side of the top chip 3, the water-soluble film 5 covering one side surface of the top chip 3 and the bonding wire 6 of the top chip 3;

[0036] S8, plastic encapsulation, the plastic encapsulation material 4 wraps the chip 3, the bonding wire 6, and the water-soluble film 5;

[0037] S9, grinding the surface of the formed package body to expose the surface of the water-soluble film 5;

[0038] S10, washing with water to dissolve the water-soluble film 5 and form a cavity on the surface of the package;

[0039] S11 , after all chips 3 are stacked, the cavity is plastic-sealed to obtain a final package.

[0040] In practice, the number of chips 3 stacked each time ranges from 1 to 16 layers. In this embodiment, the final package is formed through two stacking steps. In practice, the number of stacking steps and the number of chip layers in each stack can be determined based on the number of chips to be stacked. After each stacking step, a plastic encapsulation step is performed. The plastic encapsulation material 4 is wrapped around the chips 3 and the bonding wires 6 to provide support and prevent chip bending and collapse, which can occur when a large number of chips are stacked.

[0041] In this embodiment, upper and lower adjacent chips 3 are bonded together by DAF films 2. The chips 3 are flash memory chips.

[0042] By leveraging the easy-to-remove property of water-soluble film, the present invention improves the existing process of single stacking and plastic sealing into multiple stacking and plastic sealing. Each plastic sealing wraps and supports the previously stacked chips, preventing the stacked chips from bending or collapsing, and ultimately achieving the maximum number of stacking layers in a single package and integrating the maximum number of memory chips.

Claims

1. A method for implementing multi-layer flash memory packaging, characterized in that: The steps include: S1, stacking a plurality of chips (3) on a substrate or a PCB (1), and bonding adjacent chips (3) via bonding wires (6); S2, applying a water-soluble film (5) to the upper side of the top chip (3), wherein the water-soluble film (5) covers the surface of one side of the top chip (3) and the bonding wire (6) of the top chip (3); S3, plastic encapsulation, the plastic encapsulation material (4) wraps the chip (3), the bonding wire (6), and the water-soluble film (5); S4, after the plastic packaging is completed, the surface of the formed package body is ground to expose the surface of the water-soluble film (5); S5, washing with water to dissolve the water-soluble film (5) and form a cavity on the surface of the package; S6, further stacking a plurality of chips (3) on the surface of the chip (3) exposed in the cavity, and bonding adjacent chips (3) via bonding wires (6); S7, repeating steps S2 to S5 until all chips (3) are stacked, and the cavity is plastic-sealed to obtain a final package.

2. The method for implementing multi-layer flash memory packaging according to claim 1, wherein: The number of chips (3) stacked each time is 1-16 layers.

3. The method for implementing multi-layer flash memory packaging according to claim 1, wherein: Upper and lower adjacent chips (3) are bonded together via a DAF film (2).

4. The method for implementing multi-layer flash memory packaging according to claim 1, wherein: The chip (3) is a flash memory chip.

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