Voltage converter with Dickson structure

Abstract

The invention relates to the technical field of voltage conversion, and discloses a voltage converter with a Dickson structure, which comprises a first femto capacitor, a switch branch formed by connecting four first switch tubes in series, a Dickson switch capacitor network unit and a switch inductor unit, the input end of the switch branch is used for inputting a voltage VIN, the input end of a second-stage first switch tube of the switch branch is electrically connected with one end of a first femto capacitor, and the output end of a third-stage first switch tube of the switch branch is electrically connected with the other end of the first femto capacitor; the Dickson switched capacitor network unit is electrically connected with the output end of the second-stage first switch tube of the switch branch, and the switch inductor unit is electrically connected with the Dickson switched capacitor network unit; compared with an existing DIH voltage converter, the DIH voltage converter has the advantages that the switch branch and the first femto capacitor are arranged, so that the voltage conversion ratio of the DIH voltage converter can be increased on the basis that only several switch tubes and one femto capacitor need to be added.

Description

Technical Field

[0001] The invention relates to the technical field of voltage conversion, and in particular to a voltage converter with a Dickson structure. Background Art

[0002] With the rapid development of artificial intelligence and big data, the power consumption of data centers is also growing rapidly. In order to save energy, the traditional 12V distributed power supply architecture is gradually being replaced by a higher voltage level (such as 48V) power supply architecture.

[0003] At present, the core operating voltage of CPU / GPU / DRAM / ASIC in data centers has been reduced to 0.5V with the advancement of chip process nodes, and there is a trend of further reduction. Taking 48V bus voltage as an example, considering the voltage fluctuation range of ±25%, the maximum input voltage is 60V. Therefore, in extreme cases, a higher voltage conversion ratio (120:1) is required, which poses a huge challenge to the design of the voltage converter for chip power supply.

[0004] The traditional BUCK converter topology is widely used in step-down converters due to its simple structure. However, if it is applied to the high voltage conversion ratio converter in the data center, the switch duty cycle is only about 0.83%. The extremely small duty cycle is not only not conducive to the precise control of the converter output voltage, but also leads to a large effective value of the current flowing through the rectifier switch tube, reducing the conversion efficiency.

[0005] like Figure 1 As shown, Figure 1 The circuit shown is a 6th-order dual-inductor hybrid Dickson (DIH) converter topology applied to high voltage conversion ratio, including a 6th-order Dickson switched capacitor converter and a BUCK converter. Figure 1 The circuit shown uses a Dickson switched capacitor grid to pre-step down the output voltage. With the DC isolation of capacitors C1-C5, the voltage swing of the switch node connected to the output inductor is 1 / 6 of the input voltage VIN, thereby achieving a 6-fold expansion of the switch duty cycle. Similarly, an N-order dual-inductor hybrid Dickson converter can achieve an N-fold duty cycle expansion.

[0006] Under the requirement of 60V to 0.5V conversion, the ideal duty cycle of the DIH converter is only 5%. Compared with the traditional BUCK converter, the accuracy of the converter output voltage control is improved to a certain extent, but further optimization is still needed. Increasing the order of the converter is a direct way to expand its duty cycle, but this will bring new problems. On the one hand, the number of power devices such as switches and capacitors will increase; on the other hand, the driving voltage of the high-side switch will decrease as the order increases, which will cause the conversion efficiency to deteriorate. Summary of the invention

[0007] In view of the shortcomings of the background technology, the present invention provides a Dickson structure voltage converter, and the technical problem to be solved is that the existing voltage converter used in data centers can only improve the voltage conversion ratio under the condition of greatly increasing the circuit area and the number of components.

[0008] To solve the above technical problems, the present invention provides the following technical solutions: a voltage converter with a Dickson structure, comprising a first femtoquard capacitor, a switch branch formed by four first switch tubes connected in series, a Dickson switch capacitor network unit and a switch inductor unit; The input terminal of the first switch tube of the first stage of the switch branch is used to input the voltage V IN , the input end of the first switch tube of the second stage of the switch branch is electrically connected to one end of the first femtoquard capacitor, and the output end of the first switch tube of the third stage of the switch branch is electrically connected to the other end of the first femtoquard capacitor; The Dickson switch capacitor network unit is electrically connected to the output end of the first switch tube of the second stage of the switch branch, and is used to IN To lower blood pressure; The switch inductor unit is electrically connected to the Dickson switch capacitor network unit and is used to adjust the voltage conversion ratio of the voltage converter.

[0009] In some implementations, the first switch tube is an NMOS tube.

[0010] In a certain embodiment, the Dickson switched capacitor network unit includes N-1 second switch tubes connected in series in sequence, N is a positive integer greater than 2, and the input end of the first-stage second switch tube is electrically connected to the output end of the second-stage first switch tube of the switch branch; When N is an even number, along the series connection direction of the second switch tubes, the input ends of the second switch tubes at odd positions are respectively electrically connected to the second femtoquard capacitors; the input ends of the second switch tubes at even positions are respectively electrically connected to the third femtoquard capacitors; the other ends of all the third femtoquard capacitors are electrically connected to the output ends of the final second switch tubes, and the other ends of the third femtoquard capacitors are electrically connected to each other; When N is an odd number, along the series connection direction of the second switching tubes, except for the second switching tube of the last stage, the input ends of the second switching tubes at odd positions are electrically connected to the fourth femtoquard capacitors; the input ends of the second switching tubes at even positions are electrically connected to the fifth femtoquard capacitors; the other ends of all fourth femtoquard capacitors are electrically connected to the output end of the second switching tube of the last stage, and the other ends of all fifth femtoquard capacitors are electrically connected to each other.

[0011] In some implementations, the second switch tube is an NMOS tube.

[0012] In a certain embodiment, the switching inductor unit includes an inductor L1, an inductor L2, a third switch tube and a fourth switch tube; When N is an even number, one end of the inductor L1 is electrically connected to the input end of the third switch tube and the output end of the second switch tube of the final stage, respectively, the other end of the inductor L2 is electrically connected to the input end of the fourth switch tube and the other end of the second femtoquard capacitor, respectively, the output end of the third switch tube and the output end of the fourth switch tube are both grounded, and the other end of the inductor L1 is electrically connected to the other end of the inductor L2; When N is an odd number, one end of the inductor L1 is electrically connected to the input end of the third switch tube and the other end of the fifth femtoquard capacitor respectively, the other end of the inductor L2 is electrically connected to the input end of the fourth switch tube and the output end of the final second switch tube respectively, the output end of the third switch tube and the output end of the fourth switch tube are both grounded, and the other end of the inductor L1 is electrically connected to the other end of the inductor L2.

[0013] In some implementations, the third switch tube and the fourth switch tube are both NMOS tubes.

[0014] In some implementations, the other end of the inductor L1 is further connected to a filter unit.

[0015] In some implementations, the filtering unit includes a resistor Ro and a capacitor Co, one end of the resistor Ro and one end of the capacitor Co are electrically connected to the other end of the inductor L1, and the other end of the resistor Ro and the other end of the capacitor Co are grounded.

[0016] In one embodiment, N is 6.

[0017] In a certain embodiment, all the second switch tubes are connected in series in the direction of S 1 , S 2 ……S N-1 , the third switch tube is denoted as S N , the fourth switch is denoted as S N+1 , the four first switch tubes are marked as S in the series direction N+2 , S N+3 , S N+4 and S N+5 ; One working cycle of the voltage converter includes four working phases. In the working phase Φ 1 When , the switch tube corresponding to the even-numbered S is turned on, and the switch tube corresponding to the odd-numbered S is turned off; In the working phase Φ 2 When S N and S N+1The corresponding switch tube is turned on, and the other switch tubes are turned off; In the working phase Φ 3 When , the switch tube corresponding to the even-numbered S is turned off, and the switch tube corresponding to the odd-numbered S is turned on; In the working phase Φ 2 When S N and S N+1 The corresponding switch tube is turned on, and the other switch tubes are turned off.

[0018] The beneficial effect of the present invention compared with the prior art is that compared with the existing DIH voltage converter, the present invention can increase the voltage conversion ratio of the present invention by setting a switch branch and a first femtoquard capacitor, while only adding a few switch tubes and a femtoquard capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of an existing dual-inductor hybrid Dickson converter; Figure 2 Schematic diagram of the structure of the present invention when N is an even number in the embodiment; Figure 3 Schematic diagram of the structure of the present invention when N is an odd number in the embodiment; Figure 4 This is a schematic diagram of the structure when N is 6 in the embodiment; Figure 5 for Figure 4 The circuit operates in the working phase Φ 1 The equivalent circuit diagram when ; Figure 6 for Figure 4 The circuit operates in the working phase Φ 2 and Φ 4 The equivalent circuit diagram when ; Figure 7 for Figure 4 The circuit operates in the working phase Φ 3 The equivalent circuit diagram when ; Figure 8 for Figure 4 Waveform diagram when the circuit is working. DETAILED DESCRIPTION

[0020] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0021] like Figure 2 and 3 As shown, a Dickson structure voltage converter includes a first femtoquard capacitor C F0, a switch branch 1 formed by four first switch tubes connected in series, a Dickson switch capacitor network unit 2 and a switch inductor unit 3; The input terminal of the first switch tube of the first stage of the switch branch 1 is used to input the voltage V IN The input end of the first switch tube of the second stage of the switch branch 1 is connected to the first femtoquard capacitor C F0 One end is electrically connected to the output end of the first switch tube of the third stage of the switch branch 1 and the first femtoquard capacitor C F0 The other end is electrically connected; The Dickson switched capacitor network unit 2 is electrically connected to the output end of the first switch tube of the second stage of the switch branch 1, and is used to IN To lower blood pressure; The switched inductor unit 3 is electrically connected to the Dickson switched capacitor network unit 2 and is used to adjust the voltage conversion ratio of the voltage converter.

[0022] Specifically, in this embodiment, the first switch tube is an NMOS tube, the drain of the first switch tube is its own input terminal, and the source of the first switch tube is its own output terminal.

[0023] In a certain implementation manner, the number of the first switch tubes in the switch branch 1 may be other integers greater than 4. Although this can also achieve the functions of the present invention, the overall structure becomes more complicated.

[0024] Specifically, in this embodiment, the Dickson switch capacitor network unit 2 includes N-1 second switch tubes connected in series in sequence, N is a positive integer greater than 2, and the input end of the first-stage second switch tube is electrically connected to the output end of the second-stage first switch tube of the switch branch 1; Reference Figure 2 , when N is an even number, along the series connection direction of the second switch tubes, the input ends of the second switch tubes at odd positions are respectively electrically connected to the second femtoquard capacitors; the input ends of the second switch tubes at even positions are respectively electrically connected to the third femtoquard capacitors; the other ends of all the third femtoquard capacitors are electrically connected to the output ends of the final second switch tubes, and the other ends of the third femtoquard capacitors are electrically connected to each other; Figure 2 In the figure, all capacitors located at the bottom are second-order femtoquard capacitors, which are labeled C F1 , C F3 and C F,N-1 The capacitors located above are the third femtoquard capacitors, which are labeled C F2 and C F,N-2 Capacitance; Reference Figure 3In this embodiment, when N is an odd number, along the series connection direction of the second switch tubes, except for the second switch tubes at the final stage, the input ends of the second switch tubes at odd positions are respectively electrically connected to the fourth femtoquard capacitors; the input ends of the second switch tubes at even positions are respectively electrically connected to the fifth femtoquard capacitors; the other ends of all the fourth femtoquard capacitors are electrically connected to the output end of the second switch tube at the final stage, and the other ends of all the fifth femtoquard capacitors are electrically connected to each other; Figure 3 In the figure, all capacitors located at the bottom are the fourth femtoquard capacitors, which are labeled C F1 and C F,N-2 The capacitors located above are the fifth femtoquard capacitors, which are labeled C F2 and C F,N-1 Capacitance.

[0025] Specifically, in this embodiment, the second switch tube is an NMOS tube, the drain of the second switch tube is its own input terminal, and the source of the second switch tube is its own output terminal.

[0026] Specifically, in this embodiment, Figure 2 and 3 As shown, the switch inductor unit 3 includes an inductor L1, an inductor L2, a third switch tube and a fourth switch tube; Reference Figure 2 , when N is an even number, one end of the inductor L1 is electrically connected to the input end of the third switch tube and the output end of the second switch tube of the final stage, respectively, the other end of the inductor L2 is electrically connected to the input end of the fourth switch tube and the other end of the second femtoquard capacitor, respectively, the output end of the third switch tube and the output end of the fourth switch tube are both grounded, and the other end of the inductor L1 is electrically connected to the other end of the inductor L2; Reference Figure 3 When N is an odd number, one end of the inductor L1 is electrically connected to the input end of the third switch tube and the other end of the fifth femtoquard capacitor respectively, the other end of the inductor L2 is electrically connected to the input end of the fourth switch tube and the output end of the final second switch tube respectively, the output end of the third switch tube and the output end of the fourth switch tube are both grounded, and the other end of the inductor L1 is electrically connected to the other end of the inductor L2.

[0027] Specifically, in this embodiment, the third switch tube and the fourth switch tube are both NMOS tubes, the drain of the third switch tube and the drain of the fourth switch tube are their own input terminals, and the source of the third switch tube and the source of the fourth switch tube are their own output terminals.

[0028] exist Figure 2 and Figure 3 In the embodiment, the other end of the inductor L1 is also connected to the filter unit 4.

[0029] The filter unit includes a resistor Ro and a capacitor Co, one end of the resistor Ro and one end of the capacitor Co are both electrically connected to the other end of the inductor L1, and the other end of the resistor Ro and the other end of the capacitor Co are both grounded.

[0030] In one embodiment, N is 6, and the corresponding voltage converter circuit is as follows Figure 4 As shown, Figure 4 The circuit is analyzed as follows: The voltage converter contains 11 switching tubes, denoted as S 1 -S 11 , 6 flying capacitors, denoted as C F0 -C F5 , and two inductors L1 and L2. In one working cycle TS, the voltage converter experiences a total of 4 working phases Φ1-Φ4, and the equivalent circuits corresponding to each phase are as follows Figure 4 , Figure 5 and Figure 6 shown.

[0031] In steady state, let the DC bias voltage of the flying capacitor CF0-CF5 be VCF0-VCF5, that is, the average voltage. Under the DC isolation effect of the flying capacitor, the voltage swing VSW1, VSW2 of the switching nodes SW1, SW2 of the voltage converter is greatly reduced, thereby improving the switching duty cycle of the converter. The ideal working waveform of the converter in each working phase is as follows: Figure 8 shown.

[0032] from Figure 8 It can be seen that in the Φ1 phase, all the even-numbered switches are turned on, forming three parallel capacitor branches, namely CF0-CF1, CF2-CF3, and CF4-CF5. The charge flows to the inductor L2 through these capacitors, CF0, CF1, CF3, and CF5 accumulate charge, while CF2 and CF4 release charge. Under the action of the forward excitation voltage, the current iL2 of the inductor L2 increases linearly, and the reverse excitation voltage -VO is applied to the inductor L1 when S6 is turned on, and its current iL1 decays linearly, where VO is the output voltage.

[0033] After the Φ1 phase of DTS, the converter enters Φ2. This working phase lasts for a period of time (0.5-D)TS. At this time, only the switch tubes S6 and S7 are working in the on state, and all other switch tubes are turned off. In this stage, the charge of the flying capacitor remains unchanged. The turned-on S6 and S7 cause the inductors L1 and L2 to be subjected to the reverse excitation voltage -VO, and they experience the demagnetization process together, and the currents iL1 and iL2 decrease linearly.

[0034] After going through Φ1 and Φ2 for a total of 1 / 2 working cycles, the voltage converter enters Φ3, and this working phase lasts for DTS. The odd-numbered switches are turned on, S6 is turned off, and three new parallel capacitor branches are formed, namely (CF0||CF1)-CF2, CF3-CF4, and CF5. The charges flowing through these capacitor branches are simultaneously injected into the inductor L1. Then, the inductor L1 enters the forward excitation process, and the current iL1 increases linearly. Since S7 is still in the on state, the inductor L2 is reversely excited, and its current iL2 decreases linearly.

[0035] After the Φ3 working phase ends, the voltage converter enters Φ4 which is the same as Φ2, and only the switches S6 and S7 are turned on again, with a duration of (0.5-D)TS.

[0036] In addition Figure 8 In the example, the signal PWM1A is input to the S 1 , S 3 , S 5 , S 9 and S 11 The corresponding gate control signal of the switch tube, signal PWM1B, is input to the signal labeled S 6 The corresponding gate control signal of the switch tube, signal PWM2A, is input to the signal labeled S 2 , S 4 , S 8 and S 101 The gate control signal of the corresponding switch tube, signal PWM2B, is input to the signal labeled S 7 The corresponding control signal of the gate of the switch tube. 6 and S 7 The corresponding switch tube conduction time.

[0037] In steady state, if Figure 4 The equivalent circuit diagram of the 6-stage voltage converter is shown in FIG. 1 . According to Kirchhoff's voltage law, the relationship between the average flying capacitor voltage VCF0-VCF5 and the voltage swing VSW1, VSW2 of the switch nodes SW1, SW2 can be obtained, as shown in equation (1), where VIN is the input voltage.

[0038] (1) Inductors L1 and L2 satisfy the volt-second balance principle in steady state, and the relationship between VSW1, VSW2 and output voltage VO can be deduced as shown in equation (2).

[0039] (2) Substituting equation (2) into equation (1), the average voltage of each flying capacitor and the node voltage swing can be derived as shown in equation (3).

[0040] (3) Substituting the node voltage swing obtained from equation (3) back into equation (2), the output voltage VO can be deduced as (4) As can be seen from equation (4), the switch duty cycle of the present invention is expanded by 11 times compared to the BUCK converter, which is about twice the 6-fold duty cycle ratio of the 6-order DIH converter.

[0041] Although the above analysis is based on an even 6-order TLAHD converter as an example, the derivation process can be extended to other even or odd-order (N>2) TLAHD converter applications. Using the same analysis process, the flying capacitor voltage VCF,j and the voltage conversion ratio M of the N-order TLAHD converter can be derived as shown in equations (5) and (6), respectively.

[0042] (5) (6) From formula (5), it can be seen that the average voltage of all flying capacitors has a steady-state value, that is, the converter can achieve capacitor self-balancing; in addition, from formula (6), it can be found that the N-order voltage converter of the present invention has a duty cycle expansion of (2N-1) times compared to the BUCK converter, and has an advantage of nearly double the N-fold duty cycle expansion of the traditional N-order DIH converter.

[0043] In summary, the circuit structure of the voltage converter of the present invention is based on the flying capacitor V CF,j Under the DC isolation effect, the switch node voltage swing V SW1 , VSW2 The switching duty cycle is greatly reduced, and the switch duty cycle is expanded by (2N-1) times, which improves the output voltage control accuracy; In addition, all flying capacitors C F,j It has a fixed steady-state average voltage value, which is only related to the input voltage and the converter order, and realizes capacitor self-balancing. It does not require additional control circuits or control methods to achieve capacitor charge balance, thus simplifying the system control complexity.

[0044] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A Dickson structure voltage converter, characterized in that: It includes a first femtoquard capacitor, a switch branch formed by four first switch tubes connected in series, a Dickson switch capacitor network unit and a switch inductor unit; The input terminal of the first switch tube of the first stage of the switch branch is used to input the voltage V IN , the input end of the first switch tube of the second stage of the switch branch is electrically connected to one end of the first femtoquard capacitor, and the output end of the first switch tube of the third stage of the switch branch is electrically connected to the other end of the first femtoquard capacitor; The Dickson switch capacitor network unit is electrically connected to the output end of the first switch tube of the second stage of the switch branch, and is used to IN To lower blood pressure; The switch inductor unit is electrically connected to the Dickson switch capacitor network unit and is used to adjust the voltage conversion ratio of the voltage converter.

2. The Dickson structure voltage converter according to claim 1, characterized in that: The first switch tube is an NMOS tube.

3. The Dickson structure voltage converter according to claim 1, characterized in that: The Dickson switched capacitor network unit comprises N-1 second switch tubes connected in series in sequence, N is a positive integer greater than 2, and the input end of the first-stage second switch tube is electrically connected to the output end of the second-stage first switch tube of the switch branch; When N is an even number, along the series connection direction of the second switch tubes, the input ends of the second switch tubes at odd positions are respectively electrically connected to the second femtoquard capacitors; the input ends of the second switch tubes at even positions are respectively electrically connected to the third femtoquard capacitors; the other ends of all the third femtoquard capacitors are electrically connected to the output ends of the final second switch tubes, and the other ends of the third femtoquard capacitors are electrically connected to each other; When N is an odd number, along the series connection direction of the second switching tubes, except for the second switching tube of the last stage, the input ends of the second switching tubes at odd positions are electrically connected to the fourth femtoquard capacitors; the input ends of the second switching tubes at even positions are electrically connected to the fifth femtoquard capacitors; the other ends of all fourth femtoquard capacitors are electrically connected to the output end of the second switching tube of the last stage, and the other ends of all fifth femtoquard capacitors are electrically connected to each other.

4. The Dickson structure voltage converter according to claim 3, characterized in that: The second switch tube is an NMOS tube.

5. The Dickson structure voltage converter according to claim 3, characterized in that: The switch inductor unit includes an inductor L1, an inductor L2, a third switch tube and a fourth switch tube; When N is an even number, one end of the inductor L1 is electrically connected to the input end of the third switch tube and the output end of the second switch tube of the final stage, respectively, the other end of the inductor L2 is electrically connected to the input end of the fourth switch tube and the other end of the second femtoquard capacitor, respectively, the output end of the third switch tube and the output end of the fourth switch tube are both grounded, and the other end of the inductor L1 is electrically connected to the other end of the inductor L2; When N is an odd number, one end of the inductor L1 is electrically connected to the input end of the third switch tube and the other end of the fifth femtoquard capacitor respectively, the other end of the inductor L2 is electrically connected to the input end of the fourth switch tube and the output end of the final second switch tube respectively, the output end of the third switch tube and the output end of the fourth switch tube are both grounded, and the other end of the inductor L1 is electrically connected to the other end of the inductor L2.

6. The Dickson structure voltage converter according to claim 5, characterized in that: The third switch tube and the fourth switch tube are both NMOS tubes.

7. The Dickson structure voltage converter according to claim 6, characterized in that: The other end of the inductor L1 is also connected to a filter unit.

8. The Dickson structure voltage converter according to claim 7, characterized in that: The filtering unit comprises a resistor Ro and a capacitor Co. One end of the resistor Ro and one end of the capacitor Co are both electrically connected to the other end of the inductor L1 , and the other end of the resistor Ro and the other end of the capacitor Co are both grounded.

9. The Dickson structure voltage converter according to claim 5, characterized in that: N is 6.

10. The voltage converter of Dickson structure according to claim 5, characterized in that: All the second switch tubes are marked as S1, S2, ... S in the series direction. N-1 , the third switch tube is denoted as S N , the fourth switch is denoted as S N+1 , the four first switch tubes are marked as S in the series direction N+2 , S N+3 , S N+4 and S N+5 ; One working cycle of the voltage converter includes four working phases. In the working phase Φ1, the switch tube corresponding to the even-numbered S is turned on, and the switch tube corresponding to the odd-numbered S is turned off; In the working phase Φ2, S N and S N+1 The corresponding switch tube is turned on, and the other switch tubes are turned off; In the working phase Φ3, the switch tube corresponding to the even-numbered S is turned off, and the switch tube corresponding to the odd-numbered S is turned on; In the working phase Φ2, S N and S N+1 The corresponding switch tube is turned on, and the other switch tubes are turned off.

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