Clock signal generation device and integrated circuit

Abstract

The present application relates to a clock signal generation device and an integrated circuit, the device comprising: an oscillation module configured to provide a plurality of clock signals in response to an enable signal, the oscillation module comprising: a first oscillation unit including a resistance device exhibiting a negative temperature characteristic, configured to generate a first clock signal having a first phase, and configured to generate a second clock signal having a second phase; and a second oscillation unit including a resistance device having a positive temperature characteristic and configured to generate a second clock signal having a second phase, the first oscillation unit generating a third clock signal under the influence of the second clock signal, the second oscillation unit generating a fourth clock signal under the influence of the first clock signal, and the third clock signal generating a fourth clock signal under the influence of the fourth clock signal. The first to fourth clock signals have the same temperature characteristic; and the clock output module is coupled to the oscillation module and is configured to generate corresponding clock signal groups based on the plurality of clock signals. According to the scheme, the zero-temperature-coefficient frequency can be generated, the temperature stability is good, the frequency is adjustable, and the temperature characteristic is adjustable.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design, and specifically relates to a clock signal generating device and an integrated circuit. Background Art

[0002] In integrated circuits, multi-phase clocks are widely used and can be used to control the on / off of circuit switches and to allocate the sampling and integration time of sigma-delta modulators. Traditional multi-phase clock generation circuits often use inverter delay generation, but the inverter delay will change with temperature, thus affecting the accuracy, and there is also the disadvantage of a single duty cycle. In integrated circuits, clock signals are an indispensable part. Common circuits for generating clock signals include crystal oscillators, ring oscillators, and RC oscillators. RC oscillators have low cost, low power consumption, and simple structure and have been widely used. However, due to the influence of process, power supply voltage and temperature, there are accuracy issues when using RC oscillators. In actual circuit use, multi-phase clocks are widely used and can be used to control the on / off of circuit switches and to allocate the sampling and integration time of sigma-delta modulators.

[0003] In a common RC oscillator circuit, if a resistor with a positive temperature coefficient Rpos or a resistor with a negative temperature coefficient Rneg is used alone, the obtained frequency will change at different temperatures. This changing frequency can easily generate incorrect timing when applied to an actual circuit. Therefore, in response to this situation, a conventional circuit uses Rpos and Rneg in series to obtain a resistor that does not change with temperature, thereby obtaining a frequency that does not change with temperature. However, this circuit can only generate a single phase, and the generated clock needs to be processed additionally to obtain clocks of other phases.

[0004] Therefore, there is an urgent need for a low-temperature drift RC oscillator for generating a multi-phase clock with low temperature drift. Summary of the invention

[0005] In view of the technical problems existing in the prior art, the present application proposes a multi-phase clock generation device capable of adjusting temperature characteristics.

[0006] On the one hand, the present application proposes a clock signal generating device, comprising: an oscillation module, configured to provide multiple clock signals in response to an enable signal, wherein the oscillation module comprises: a first oscillation unit, the resistance device included in the first oscillation unit exhibits a negative temperature characteristic, configured to generate a first clock signal with a first phase, a second oscillation unit, the resistance device included in the first oscillation unit exhibits a positive temperature characteristic, configured to generate a second clock signal with a second phase, wherein the first oscillation unit generates a third clock signal under the influence of the second clock signal, and the second oscillation unit generates a fourth clock signal under the influence of the first clock signal, and the first to fourth clock signals have the same temperature characteristic; and a clock output module, coupled to the oscillation module, configured to generate a corresponding clock signal group based on the multiple clock signals.

[0007] In one embodiment, the clock output module includes: a clock driving unit configured to enhance the driving capabilities of the third clock signal and the fourth clock signal.

[0008] In one embodiment, the clock driving unit includes driving branches respectively used to enhance driving capabilities of the third and fourth clock signals, and the driving branches include a plurality of inverters connected in series.

[0009] In one embodiment, the clock output module further includes: a clock adjustment unit configured to generate a clock signal group with a preset duty cycle based on the first and / or second clock signal.

[0010] In one embodiment, the clock adjustment unit includes at least one variable capacitor for adjusting the duty cycle.

[0011] In one embodiment, the first and second oscillation units further include variable capacitors coupled to the resistor device to form an RC oscillation structure.

[0012] In one embodiment, the variable capacitor includes capacitor branches connected in parallel, wherein the capacitor branches include a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate.

[0013] In one embodiment, the first NAND gate in the first oscillation unit and the second NAND gate in the second oscillation unit constitute an RS trigger, wherein the first NAND gate receives the first clock signal and the fourth clock signal, and the second NAND gate receives the second clock signal and the third clock signal.

[0014] In one embodiment, the resistor device is implemented by a resistor array, which includes a plurality of resistor adjustment units, wherein the resistor adjustment unit includes: a first resistor branch, which includes a first resistor; a second resistor branch, which includes a second resistor and a switch, wherein the second resistor branch is connected in parallel with the first resistor branch.

[0015] The present application also discloses an integrated circuit, which includes the clock signal generating device as described in any one of the above items.

[0016] Through the technical solution in the present application, a frequency with zero temperature coefficient can be generated, with good temperature stability, and the frequency and temperature characteristics are adjustable. In addition, the duty cycle of the clock can be adjusted independently, and three pairs of non-overlapping clocks can be generated using three phase clocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein: Figure 1 A diagram showing the architecture of a clock signal generating device according to an embodiment of the present application; Figure 2 is a schematic diagram of a clock generation circuit according to an embodiment of the present application; Figure 3 is a schematic diagram of the structure of a resistor array according to an embodiment of the present application; Figure 4 is a schematic diagram of the structure of a capacitor array according to an embodiment of the present application; Figure 5 is a waveform diagram of a multi-phase clock according to an embodiment of the present application; Figure 6 FIG. 1 is a schematic diagram of a frequency variation curve of a low temperature drift according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0020] The technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not configured to limit the two units to only communicate with each other through the signals shown in the figure.

[0021] Figure 1 is a diagram of the architecture of a clock signal generating device according to an embodiment of the present application.

[0022] like Figure 1 As shown, the clock signal generating device includes an oscillation module 1 and an output module 2, wherein the oscillation module 1 is used to generate a plurality of periodic oscillation signals with specified temperature characteristics, and the output module 2 obtains the oscillation signal to generate at least one group of clocks with different phases.

[0023] Specifically, the oscillation module 1 includes a negative temperature oscillation unit 11, a positive temperature oscillation unit 12, and a latch feedback unit 13, wherein the negative temperature oscillation unit 11 includes a resistor with a negative temperature coefficient, and can generate an oscillation signal of a first phase, and obtain a first group of clocks after adjustment by the clock output unit 21 in the output module 2. Similarly, the positive temperature oscillation unit 12 uses a resistor with a positive temperature coefficient, and can generate an oscillation signal of a second phase, and obtain a second group of clocks with different phases after adjustment by the clock output unit 22.

[0024] The oscillation module 1 also includes a latch feedback unit 13 to couple the output signals of the negative temperature oscillation unit 11 and the positive temperature oscillation unit 12 to the output module 2 to generate a third group of clocks different from the first two groups of clocks. Specifically, the latch feedback unit 13 generates a clock signal at the output end (Q, Q'), and generates and outputs the third group of clocks through the clock output unit 23. In addition, the latch unit is multiplexed by the feedback paths of the negative temperature oscillation unit 11 and the positive temperature oscillation unit 12 to complement the clock frequencies of the two different temperature coefficients to form a clock frequency that is not affected by temperature. Therefore, the three groups of clock frequencies with different phases output are the same and have the same temperature characteristics.

[0025] Figure 2 is a schematic diagram of a clock generation circuit according to an embodiment of the present application.

[0026] like Figure 2 As shown, the clock generating circuit includes a negative temperature oscillation unit 101 , a positive temperature oscillation unit 102 , clock adjustment units 103 , 104 and a clock driving unit 105 .

[0027] Specifically, the negative temperature oscillation unit 101 includes an RC oscillation structure, namely, a variable negative temperature resistor R_neg and a variable capacitor C1. The voltage of the capacitor reaches the node Q via the inverter INV1, the OR gate OR1, the inverter INV2 and the NAND gate NAND1. The voltage of the node Q is fed back to the buffer BUF1 and then reaches the variable capacitor C1 via the variable negative temperature resistor R_neg.

[0028] In terms of circuit structure, the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 are symmetrical circuits, and the difference between the two includes the difference in resistance temperature coefficient, and the positive temperature oscillation unit 102 includes an adjustable positive temperature coefficient resistor R_pos. The clock signals generated by the two resistors with different temperature coefficients also show opposite temperature coefficients, but the coupling of the latch is realized through the NAND gates NAND1 and NAND2, and is fed back to the input ends of the two oscillation units, thereby realizing a clock frequency with a zero temperature coefficient.

[0029] The working principles of the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 and the multi-phase clock generation principle are described in detail. In this embodiment, the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 are symmetrical circuits, so only the negative temperature oscillation unit 101 is described.

[0030] The external enable signal PD controls the opening and closing of the entire oscillation module. In the initial state, PD is high, en is low, the drain voltage of transistor M1 is pulled high, and the positive plate output of capacitor C1 is "1", that is, the plate voltage is high. The input of buffer BUF1 is high, and the entire circuit does not oscillate.

[0031] Discharge process: When the PD voltage is pulled low, the en voltage is pulled high, the transistor M1 is turned off, and the output of the buffer BUF1 is instantly flipped to a low level, so the capacitor C1 is discharged through the resistor R_neg. When the capacitor C1 is discharged, the positive plate output of the capacitor is "0", that is, the plate voltage is low. The voltage is pulled high by the inverter INV1, and the voltage is pulled low after passing through the OR gate OR1 and the inverter INV2. Since Q' is a high level in the initial state, the branch voltage is pulled high after passing through NAND1, and the node Q voltage flips from low to high.

[0032] Charging process: When the voltage of node Q becomes high, the capacitor C1 is charged through buffer BUF1 and resistor R_neg. When the capacitor C1 is fully charged, the output of the positive plate of capacitor C1 is "1", that is, the voltage of this plate is high. This voltage is pulled down by INV1 and pulled up by OR1 and INV2. At this time, the voltage of node Q' is low, so the branch voltage is pulled down after NAND1, and the voltage of node Q flips from high to low, entering the next round of discharge process. Such repeated charging and discharging can obtain a periodic oscillation waveform.

[0033] The SR latch composed of NAND gates NAND1 and NAND2 feeds back Q' and Q to the charge and discharge input terminals of the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102, respectively, to generate clock signals CK0 and CK1 with non-overlapping phases. At the same time, the reverse and non-overlapping master clock is output from the output terminal of the SR latch, and the driving capability of the clock signal is improved through the clock output buffer 105, forming the master clock signals CLK1 and CLK2 with non-overlapping phases.

[0034] The temperature compensation principle is described in detail below: Since the temperature coefficient of the resistor R_neg is negative (i.e., the resistance value decreases as the temperature increases), and the temperature coefficient of R_pos is positive, the frequencies generated by the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 will present opposite temperature coefficients when working alone. Since the signal CK0 generated by the negative temperature oscillation unit 101 is fed back to the positive temperature oscillation unit 102 through the NAND gate NAND2, the clock signal CK1 generated by the positive temperature oscillation unit 102 is fed back to the negative temperature oscillation unit 101 through the NAND gate NAND1, so that the signals (frequencies) of the positive and negative temperature coefficients are offset to generate a signal (frequency) of zero temperature coefficient. The temperature coefficient can be adjusted by adjusting the size of the resistors R_neg and R_pos, thereby achieving a frequency of zero temperature coefficient and obtaining better temperature drift characteristics. At the same time, since the outputs of the NAND gates NAND1 and NAND2 are fed back to the input ends of 101 and 102, the signal not only achieves the zero temperature coefficient of CK0 and CK1 after transmission, but also achieves the frequency of CK0 and CK1 to be the same as the frequency of Q and Q'.

[0035] In one embodiment, the adjustable resistors R_neg and R_pos can be Figure 3 This is accomplished with the resistor array shown.

[0036] like Figure 3 As shown, the exemplary resistor array includes 8 resistors R1-R8, wherein resistors R1-R4 are connected in series and in parallel with resistors R5-R8, respectively. In the branches of resistors R5-R8, switches S1-S4 are also connected in series to determine whether resistors R5-R8 are connected to the circuit. In other words, resistors R1, R5 and switch S1 constitute a resistance adjustment unit, and resistor R1 belongs to the first resistance branch, and resistor R5 and switch S1 belong to the second resistance branch. The range of the equivalent resistance value of each resistor unit is the parallel value of R1 and R5 or R1. It can be understood that the adjustable resistors R_neg and R_pos can have a variety of implementation forms, and it is only necessary to make the equivalent resistances in the corresponding circuit R_neg and R_pos.

[0037] In practical applications, if the size of the resistor is to be adjusted, it can be selectively determined whether to close any one or more of the switches S1~S4 according to the needs, so as to merge the corresponding resistor into the corresponding branch to reduce the resistance value of R_neg or R_pos, thereby adjusting the resistance size of R_neg and R_pos. It can be understood that the size of the resistors R1-R8 can be adjusted according to the actual application. For example, the resistance values ​​of the resistors R1-R4 can be equal, or in a proportional relationship, and can be N times that of the resistors R5-R8, where N is greater than or equal to 1. In one embodiment, the proportional relationship of the resistors R1-R4 is the same as the proportional relationship of R5-R8.

[0038] The control signals of switches S1~S4 can be generated through registers, and the control strategy can be adjusted according to the actual application, so there is no need to elaborate on it here. The size of the R_neg (R_pos) resistor determines the step size of the oscillation frequency adjustment and also determines the frequency accuracy. The target frequency can be found by accurately controlling R_pos, and the temperature coefficient of the frequency can be compensated by controlling the R_neg resistor.

[0039] After repeated adjustment and calibration, the low temperature drift characteristic is obtained. The frequency change curve of the low temperature drift achieved by the present invention is as follows: Figure 6 As shown, it can be seen that the temperature drift curve presents a parabolic characteristic and has good temperature characteristics. Figure 3 This is only used as an example of the present application, and the resistance adjustment unit may be determined according to the accuracy of the required target frequency and the accuracy of the target frequency temperature drift.

[0040] In this embodiment, the duty cycle of the non-overlapping clocks is adjusted as follows: The clock signal CK0 of the first phase is adjusted by the adjustable capacitors C3 and C4 of the clock adjustment unit 103 to obtain the phase non-overlapping clocks CLK3 and CLK4. Similarly, the clock CK1 generation circuit of the second phase is adjusted by the adjustable capacitors C5 and C6 of 104 to obtain the phase non-overlapping clocks CLK5 and CLK6. The adjustable capacitors C3-C6 determine the size of the duty cycle of the phase non-overlapping clocks. In this embodiment, the adjustable capacitors C3 and C4, C5 and C6 are respectively located in different clock generation circuits, so the sizes of C3 and C4, C5 and C6 can be adjusted independently to obtain different duty cycles. When the value of capacitor C3 (C5) decreases, the duty cycle of CLK3 (CLK5) and CLK4 (CLK6) increases; when the value of capacitor C4 (C6) decreases, the duty cycle of CLK4 (CLK6) increases, and the duty cycle of CLK3 (CLK5) remains basically unchanged. Therefore, the duty cycle of each clock signal can be adjusted according to application requirements.

[0041] For the adjustable capacitors C1-C6, you can use Figure 4 This is achieved using the capacitor array shown.

[0042] like Figure 4 As shown, the capacitor array includes capacitor branches connected in parallel, wherein each capacitor branch includes a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate. Specifically, the capacitor branch includes capacitors (Ca, Cb and Cc), and each capacitor is coupled to the ground GND through a transmission gate (TGa, TGb and TGc). Therefore, by controlling the on and off of each transmission gate, the size of the variable capacitor C1-C6 can be adjusted, and the control signal of each branch switch is generated by a register. It can be understood that the adjustable capacitor C3-C6 is not the only available delay option, and is only used as an example of the present application. In other embodiments, other delay units can also be inserted into the nodes that affect the duty cycle of the clock signal (CLK3-CLK6) to form a non-overlapping clock with adjustable duty cycle, for example, between inverters INV11 and INV12, between inverters INV14 and INV15, between inverters INV12 and AND gate AND2, and between inverters INV15 and AND gate AND4.

[0043] Figure 5 The waveform of the clock output for this structure. The frequencies of CLK1~CLK6 are the same, but the duty cycles are different. This result is only used for example and is not a fixed result. The duty cycle can be adjusted according to actual needs. In the output waveform, the phases of CLK1 and CLK2, CLK3 and CLK4, and CLK5 and CLK6 do not overlap.

[0044] The present application also discloses an integrated circuit, which includes the aforementioned clock generation device. It is understandable that the integrated circuit may be an integrated circuit that requires a clock signal, such as an ADC, a DAC, a CPU, a GPU, etc., and there is no need to list them one by one here.

[0045] Through the above technical solution, a clock signal with low temperature characteristics can be realized, and the duty cycle of the clock signal can be adjusted according to application requirements, which greatly improves the applicability of the technical solution.

[0046] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A clock signal generating device, characterized in that: include: An oscillation module is configured to provide a plurality of clock signals in response to an enable signal, wherein the oscillation module comprises: The first oscillation unit includes a resistor device having a negative temperature characteristic and is configured to generate a first clock signal having a first phase. The second oscillating unit includes a resistor device exhibiting a positive temperature characteristic and is configured to generate a second clock signal having a second phase. Wherein, the first oscillation unit generates a third clock signal under the influence of the second clock signal, the second oscillation unit generates a fourth clock signal under the influence of the first clock signal, and the first to fourth clock signals have the same temperature characteristics; and a clock output module, coupled to the oscillation module, configured to generate a corresponding clock signal group based on the multiple clock signals.

2. The clock signal generating device according to claim 1, characterized in that: The clock output module comprises: The clock driving unit is configured to enhance the driving capabilities of the third clock signal and the fourth clock signal.

3. The clock signal generating device according to claim 2, characterized in that: The clock driving unit includes driving branches respectively used to enhance the driving capabilities of the third and fourth clock signals, and the driving branches include a plurality of inverters connected in series.

4. The clock signal generating device according to claim 1, characterized in that: The clock output module also includes: The clock adjustment unit is configured to generate a clock signal group with a preset duty cycle based on the first and / or second clock signals.

5. The clock signal generating device according to claim 4, characterized in that: The clock adjustment unit includes at least one variable capacitor for adjusting a duty cycle.

6. The clock signal generating device according to claim 5, characterized in that: The first and second oscillation units also respectively include variable capacitors coupled to the resistor device to form an RC oscillation structure.

7. The clock signal generating device according to claim 6, characterized in that: The variable capacitor includes capacitor branches connected in parallel, wherein the capacitor branch includes a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate.

8. The clock signal generating device according to claim 1, characterized in that: The first NAND gate in the first oscillation unit and the second NAND gate in the second oscillation unit constitute an RS trigger, Wherein, the first NAND gate receives the first clock signal and the fourth clock signal, The second NAND gate receives the second clock signal and the third clock signal.

9. The clock signal generating device according to claim 1, characterized in that: The resistor device is implemented by a resistor array, and the resistor array includes a plurality of resistor adjustment units, wherein the resistor adjustment unit includes: A first resistance branch, comprising a first resistor; The second resistance branch includes a second resistor and a switch, wherein the second resistance branch is connected in parallel with the first resistance branch.

10. An integrated circuit, characterized in that: The device comprises a clock signal generating device as claimed in any one of claims 1 to 9.

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