A clock signal generating device and an integrated circuit

Abstract

The present application relates to a clock signal generating device and an integrated circuit. The device includes: an oscillation module configured to provide a plurality of clock signals in response to an enable signal. The oscillation module includes: a first oscillation unit including a resistor device having a negative temperature characteristic and configured to generate a first clock signal having a first phase, and a second oscillation unit including a resistor device having a positive temperature characteristic and configured to generate a second clock signal having a second phase. The first oscillation unit generates a third clock signal under the influence of the second clock signal, and the second oscillation unit generates a fourth clock signal under the influence of the first clock signal. The first to fourth clock signals have the same temperature characteristic; a clock output module coupled to the oscillation module and configured to generate a corresponding clock signal group based on the plurality of clock signals. The solution of the present application can generate a frequency with zero temperature coefficient, has good temperature stability, and at the same time the frequency is adjustable and the temperature characteristic is adjustable.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit design, and particularly relates to a clock signal generating device and an integrated circuit. Background Art

[0002] In integrated circuits, multi-phase clocks are widely used and can be used to control the on / off of circuit switches and allocate the sampling and integration times of sigma-delta modulators, etc. Traditional multi-phase clock generation circuits often use inverter delays for generation. However, the inverter delay changes continuously with temperature, thus affecting the accuracy, and there is also the disadvantage of a single duty cycle. In integrated circuits, clock signals are an essential part. Common circuits for generating clock signals include crystal oscillators, ring oscillators, and RC oscillators. RC oscillators have been widely used due to their low cost, low power consumption, and simple structure. However, due to the influence of process, power supply voltage, and temperature, there are accuracy problems when using RC oscillators. In actual circuit use, multi-phase clocks are widely used and can be used to control the on / off of circuit switches and allocate the sampling and integration times of sigma-delta modulators, etc.

[0003] In a typical RC oscillator circuit, if only a positive temperature coefficient resistor Rpos or a negative temperature coefficient resistor Rneg is used alone, the resulting frequency will change at different temperatures. Applying this changing frequency to an actual circuit is likely to generate incorrect timings. Therefore, in response to this situation, in a conventional circuit, Rpos and Rneg are used in series to obtain a resistor that does not change with temperature, thereby obtaining a frequency that does not change with temperature. However, this circuit can only generate a single phase, and additional processing of the generated clock is required to obtain clocks of other phases.

[0004] Therefore, there is an urgent need for a low-temperature drift RC oscillator that generates multi-phase clocks with low temperature drift. Summary of the Invention

[0005] In view of the technical problems existing in the prior art, this application proposes a multi-phase clock generating device capable of adjusting temperature characteristics.

[0006] On the one hand, the present application provides a clock signal generation device, including: an oscillation module configured to provide a plurality of clock signals in response to an enable signal, wherein the oscillation module includes: a first oscillation unit including a resistor device having a negative temperature characteristic and configured to generate a first clock signal with a first phase, and a second oscillation unit including a resistor device having a positive temperature characteristic and configured to generate a second clock signal with a second phase. The first oscillation unit generates a third clock signal under the influence of the second clock signal, and the second oscillation unit generates a fourth clock signal under the influence of the first clock signal. Moreover, the first to fourth clock signals have the same temperature characteristic; and a clock output module coupled to the oscillation module and configured to generate a corresponding clock signal group based on the plurality of clock signals.

[0007] In one embodiment, the clock output module includes: a clock driving unit configured to enhance the driving capabilities of the third clock signal and the fourth clock signal.

[0008] In one embodiment, the clock driving unit includes driving branches respectively for enhancing the driving capabilities of the third and fourth clock signals, and each driving branch includes a plurality of serially connected inverters.

[0009] In one embodiment, the clock output module further includes: a clock adjusting unit configured to generate a clock signal group with a preset duty cycle based on the first and / or second clock signals.

[0010] In one embodiment, the clock adjusting unit includes at least one variable capacitor for adjusting the duty cycle.

[0011] In one embodiment, the first and second oscillation units further respectively include variable capacitors coupled to the resistor devices to form RC oscillation structures.

[0012] In one embodiment, the variable capacitor includes capacitor branches connected in parallel with each other. Each capacitor branch includes a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate.

[0013] In one embodiment, the first NAND gate in the first oscillation unit and the second NAND gate in the second oscillation unit form an RS flip-flop. The first NAND gate receives the first clock signal and the fourth clock signal, and the second NAND gate receives the second clock signal and the third clock signal.

[0014] In one embodiment, the resistance device is implemented by a resistance array, and the resistance array includes a plurality of resistance adjustment units. Among them, the resistance adjustment unit includes: a first resistance branch including a first resistor; a second resistance branch including a second resistor and a switch, where the second resistance branch is connected in parallel with the first resistance branch.

[0015] The present application also discloses an integrated circuit, which includes the clock signal generating device as described in any one of the above.

[0016] Through the technical solution in the present application, a frequency with zero temperature coefficient can be generated, the temperature stability is good, and at the same time the frequency is adjustable and the temperature characteristics are adjustable; in addition, the duty cycle of the clock can be independently adjusted, and three pairs of non-overlapping clocks are generated by using clocks of three phases. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Next, the preferred embodiments of the present application will be further described in detail with reference to the drawings, where:

[0018] Figure 1 is the architecture diagram of the clock signal generating device according to the embodiment of the present application;

[0019] Figure 2 is the schematic diagram of the clock generation circuit according to the embodiment of the present application;

[0020] Figure 3 is the structural schematic diagram of the resistance array according to the embodiment of the present application;

[0021] Figure 4 is the structural schematic diagram of the capacitor array according to the embodiment of the present application;

[0022] Figure 5 is the waveform diagram of the multi-phase clock according to the embodiment of the present application;

[0023] Figure 6 is the schematic diagram of the low-temperature drift frequency change curve according to the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0025] In the following detailed description, reference is made to the various specification drawings that form a part of the present application and illustrate specific embodiments of the present application. In the drawings, like reference numerals generally describe substantially similar components in different figures. The specific embodiments of the present application are described in sufficient detail below to enable those of ordinary skill in the relevant art and technology to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0026] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered as part of the specification. Regarding the connections between the units in the drawings, it is only for the convenience of illustration. It indicates that at least the units at both ends of the connection communicate with each other, and it is not intended to limit that the unconnected units cannot communicate. Additionally, the number of lines between two units is intended to represent at least the number of signals involved in the communication between the two units or at least the number of output terminals they have, and it is not configured to limit that the two units can only communicate with the signals shown in the figure.

[0027] Figure 1 It is an architecture diagram of a clock signal generation device according to an embodiment of the present application.

[0028] As Figure 1 shown, the clock signal generation device includes an oscillation module 1 and an output module 2. Among them, the oscillation module 1 is used to generate multiple periodic oscillation signals with specified temperature characteristics, and the output module 2 obtains the oscillation signals and generates at least one set of clocks with different phases.

[0029] Specifically, the oscillation module 1 includes a negative-temperature oscillation unit 11, a positive-temperature oscillation unit 12, and a latch feedback unit 13. Among them, the negative-temperature oscillation unit 11 includes a resistor with a negative temperature coefficient and can generate an oscillation signal of the first phase, which is adjusted by the clock output unit 21 in the output module 2 to obtain the first set of clocks. Similarly, the positive-temperature oscillation unit 12 uses a resistor with a positive temperature coefficient and can generate an oscillation signal of the second phase, which is adjusted by the clock output unit 22 to obtain the second set of clocks with different phases.

[0030] The oscillation module 1 further includes a latch feedback unit 13 to couple the output signals of the negative temperature oscillation unit 11 and the positive temperature oscillation unit 12 to the output module 2 respectively to generate a third set of clocks different from the first two sets of clocks. Specifically, the latch feedback unit 13 generates a clock signal at the output terminals (Q, Q'), and generates and outputs the third set of clocks through the clock output unit 23. In addition, the latch units are respectively multiplexed by the feedback paths of the negative temperature oscillation unit 11 and the positive temperature oscillation unit 12 to complement the clock frequencies with two different temperature coefficients to form a clock frequency that is not affected by temperature. Therefore, the three sets of clocks with different phases output have the same frequency and the same temperature characteristics.

[0031] Figure 2 It is a schematic diagram of the clock generation circuit according to the embodiment of the present application.

[0032] As Figure 2 shown, the clock generation circuit includes a negative temperature oscillation unit 101, a positive temperature oscillation unit 102, and clock adjustment units 103, 104, and a clock drive unit 105.

[0033] Specifically, the negative temperature oscillation unit 101 includes an RC oscillation structure, that is, a variable negative temperature resistor R_neg and a variable capacitor C1. The voltage of this capacitor reaches the node Q via the inverter INV1, the OR gate OR1, the inverter INV2, and the NAND gate NAND1. The voltage of the node Q is fed back to the buffer BUF1 and then reaches the variable capacitor C1 via the variable negative temperature resistor R_neg.

[0034] In terms of circuit structure, the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 are symmetric circuits. The differences between the two include the differences in the temperature coefficients of the resistors. The positive temperature oscillation unit 102 includes an adjustable positive temperature coefficient resistor R_pos. The clock signals separately generated by the two resistors with different temperature coefficients also exhibit opposite temperature coefficients, but the coupling of the latch is realized through the NAND gates NAND1 and NAND2 and fed back to the input terminals of the two oscillation units, thereby realizing a clock frequency with zero temperature coefficient.

[0035] The working principles of the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 and the multi-phase clock generation principle are elaborated in detail. In this embodiment, the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 are symmetric circuits, so only the negative temperature oscillation unit 101 is described.

[0036] The external enable signal PD controls the on and off of the entire oscillation module. In the initial state, PD is at a high level, en is at a low level, the drain voltage of the transistor M1 is pulled high, and the output of the positive electrode plate of the capacitor C1 is "1", that is, the voltage of this electrode plate is at a high level. The input of the buffer BUF1 is at a high level, and the entire circuit does not oscillate at this time.

[0037] Discharge process: When the PD voltage is pulled low, the en voltage is pulled high, the transistor M1 is turned off, and the output of the buffer BUF1 instantaneously flips to a low level. Therefore, the capacitor C1 discharges through the resistor R_neg. When the capacitor C1 finishes discharging, the output of the positive plate of the capacitor is "0", that is, the voltage of this plate is at a low level. This voltage is pulled high through the inverter INV1, and then pulled low after passing through the OR gate OR1 and the inverter INV2. Since Q' is at a high level in the initial state, the branch voltage is pulled high after passing through the NAND1, and the voltage of the node Q flips from low to high.

[0038] Charging process: After the voltage of the node Q becomes high, it charges the capacitor C1 through the buffer BUF1 and the resistor R_neg. When the capacitor C1 finishes charging, the output of the positive plate of the capacitor C1 is "1", that is, the voltage of this plate is at a high level. This voltage is pulled low through the INV1, and then pulled high after passing through the OR1 and the INV2. At this time, the voltage of the node Q' is at a low level. Therefore, the branch voltage is pulled low after passing through the NAND1, and the voltage of the node Q flips from high to low, entering the next round of the discharge process. Repeated charging and discharging like this can obtain a periodically oscillating waveform.

[0039] The SR latch composed of the NAND gates NAND1 and NAND2 respectively feeds back Q' and Q to the charging and discharging input terminals of the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102, generating non-overlapping clock signals CK0 and CK1 in phase. At the same time, a reverse and non-overlapping master clock is output from the output terminal of the SR latch. After passing through the clock output buffer 105, the driving ability of the clock signal is improved, forming non-overlapping master clock signals CLK1 and CLK2.

[0040] The following elaborates on the temperature compensation principle in detail:

[0041] Since the temperature coefficient of the resistor R_neg is negative (i.e., the resistance value decreases as the temperature increases), and the temperature coefficient of R_pos is positive, therefore, the frequencies generated by the negative temperature oscillation unit 101 and the positive temperature oscillation unit 102 when working alone will show opposite temperature coefficients. Since the signal CK0 generated by the negative temperature oscillation unit 101 is fed back to the positive temperature oscillation unit 102 through the NAND gate NAND2, therefore, the clock signal CK1 generated by the positive temperature oscillation unit 102 is fed back to the negative temperature oscillation unit 101 through the NAND gate NAND1, so that the signals (frequencies) with positive and negative temperature coefficients cancel each other out to generate a signal (frequency) with a zero temperature coefficient. By adjusting the magnitudes of the resistors R_neg and R_pos, the temperature coefficient can be adjusted, thereby achieving a frequency with a zero temperature coefficient and obtaining better temperature drift characteristics. At the same time, since the outputs of the NAND gates NAND1 and NAND2 are also fed back to the input terminals of 101 and 102, the signals not only achieve a zero temperature coefficient for CK0 and CK1 after transmission, but also make the frequencies of CK0 and CK1 the same as those of Q and Q'.

[0042] In one embodiment, both the adjustable resistors R_neg and R_pos can be implemented using Figure 3 the resistor arrays shown.

[0043] As Figure 3 shown, an exemplary resistor array includes eight resistors R1 - R8. Among them, resistors R1 - R4 are in series and are respectively in parallel with resistors R5 - R8. On the branches of resistors R5 - R8, switches S1 - S4 are respectively connected in series to determine whether resistors R5 - R8 are connected to the circuit. In other words, resistor R1, resistor R5, and switch S1 constitute a resistance adjustment unit, and resistor R1 belongs to the first resistor branch, while resistor R5 and switch S1 belong to the second resistor branch. The range of the equivalent resistance value of each resistor unit is the parallel value of R1 and R5 or R1. It can be understood that the adjustable resistors R_neg and R_pos can have various implementation forms, as long as the equivalent resistances in the corresponding circuits are R_neg and R_pos.

[0044] In practical applications, if the resistance needs to be adjusted, one or more of switches S1~S4 can be selectively determined to be closed according to requirements, so as to incorporate the corresponding resistors into the corresponding branches, thereby reducing the resistance values of R_neg or R_pos, and thus realizing the adjustment of the resistance sizes of R_neg and R_pos. It can be understood that the sizes of resistors R1 - R8 can be adjusted according to actual applications. For example, the resistance values of resistors R1 - R4 can be equal or in a proportional relationship, and can be N times that of resistors R5 - R8, where N is greater than or equal to 1. In one embodiment, the proportional relationships of resistors R1 - R4 and R5 - R8 are the same.

[0045] The control signals of switches S1~S4 can be generated by a register, and the control strategy can be adjusted according to actual applications, which will not be elaborated here. The size of the R_neg (R_pos) resistor determines the step size of the oscillation frequency adjustment and also determines the accuracy of the frequency. By precisely controlling R_pos, the target frequency can be found, and by controlling the R_neg resistor, the temperature coefficient of the frequency can be compensated.

[0046] After repeated adjustment and calibration, a low temperature drift characteristic is obtained. The frequency change curve with low temperature drift implemented by the present invention is as Figure 6 shown. It can be seen that the temperature drift curve presents the characteristics of a parabola and has good temperature characteristics. It should be noted that Figure 3 this is only used as an example of this application, and the resistance adjustment unit can be determined according to the accuracy of the required target frequency and the accuracy of the temperature drift of the target frequency.

[0047] In this embodiment, the implementation method for adjusting the duty cycle of the non-overlapping clock is as follows:

[0048] The clock signal CK0 of the first phase is adjusted by the adjustable capacitors C3 and C4 of the clock adjustment unit 103 to obtain non-overlapping clocks CLK3 and CLK4. Similarly, the clock CK1 generation circuit of the second phase is adjusted by the adjustable capacitors C5 and C6 of 104 to obtain non-overlapping clocks CLK5 and CLK6. The adjustable capacitors C3-C6 determine the duty cycle of the non-overlapping clocks. In this embodiment, the adjustable capacitors C3 and C4, and C5 and C6 are respectively located in different clock generation circuits, so the sizes of C3 and C4, and C5 and C6 can be adjusted independently to obtain different duty cycles. When the value of capacitor C3 (C5) decreases, the duty cycles of CLK3 (CLK5) and CLK4 (CLK6) increase; when the value of capacitor C4 (C6) decreases, the duty cycle of CLK4 (CLK6) increases, and the duty cycle of CLK3 (CLK5) remains basically unchanged. Thus, the duty cycle of each clock signal can be adjusted according to application requirements.

[0049] For the adjustable capacitors C1-C6, they can be implemented by Figure 4 the capacitor array shown.

[0050] As Figure 4 shown, the capacitor array includes capacitor branches connected in parallel. Among them, each capacitor branch includes a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate. Specifically, the capacitor branch includes capacitors (Ca, Cb, and Cc), and each capacitor is respectively coupled to the ground GND through a transmission gate (TGa, TGb, and TGc). Therefore, by controlling the on / off of each transmission gate, the sizes of the variable capacitors C1-C6 can be adjusted, and the control signals of each branch switch are generated by a register. It can be understood that the adjustable capacitors C3-C6 are not the only available delay options. Here, they are only used as examples of this application. In other embodiments, other delay units can also be inserted at the nodes affecting the duty cycle of the clock signals (CLK3-CLK6) to form non-overlapping clocks with adjustable duty cycles. For example, between the inverters INV11 and INV12, between the inverters INV14 and INV15, between the inverter INV12 and the AND gate AND2, and between the inverter INV15 and the AND gate AND4.

[0051] Figure 5 is the waveform of the output clock of this structure. The frequencies of CLK1~CLK6 are all the same, but the duty cycles are all different. This result is only for illustrative purposes and is not a fixed result. The duty cycle can be adjusted according to actual needs. In the output waveform, the phases of CLK1 and CLK2, CLK3 and CLK4, and CLK5 and CLK6 are all non-overlapping.

[0052] The present application also discloses an integrated circuit, which includes the clock generation device as described above. It can be understood that the integrated circuit may be an integrated circuit that requires a clock signal, such as an ADC, a DAC, a CPU, a GPU, etc., and will not be enumerated one by one here.

[0053] Through the above technical solution, a clock signal with low temperature characteristics can be achieved, and the duty cycle of the clock signal can be adjusted according to application requirements, greatly improving the applicability of the present technical solution.

[0054] The above embodiments are only for illustrating the present application, rather than limiting the present application. Those of ordinary skill in the relevant technical field can also make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope of the disclosure of the present application.

Claims

1. A clock signal generation device, characterized in that, Comprising: An oscillation module configured to provide a plurality of clock signals in response to an enable signal, wherein the oscillation module includes: A first oscillation unit including a resistive device that only exhibits a negative temperature characteristic and configured to generate a first clock signal having a first phase, A second oscillation unit including a resistive device that only exhibits a positive temperature characteristic and configured to generate a second clock signal having a second phase, The first and second oscillation units further respectively include a first variable capacitor and a second variable capacitor connected in series between ground and the resistive device to form an RC oscillation structure; Wherein, the first oscillation unit generates a third clock signal under the influence of the second clock signal, the second oscillation unit generates a fourth clock signal under the influence of the first clock signal, and the first to fourth clock signals have the same temperature characteristic, The first NAND gate in the first oscillation unit and the second NAND gate in the second oscillation unit form an RS flip-flop. The first NAND gate receives the first clock signal and the fourth clock signal, and the second NAND gate receives the second clock signal and the third clock signal. Wherein the third clock signal is fed back to the input end of the first oscillation unit, and the fourth clock signal is fed back to the input end of the second oscillation unit; and A clock output module coupled to the oscillation module and configured to generate a corresponding clock signal group based on the plurality of clock signals.

2. The clock signal generating device according to claim 1, wherein The clock output module includes: A clock driving unit configured to enhance the driving capabilities of the third clock signal and the fourth clock signal.

3. The clock signal generating device according to claim 2, wherein The clock driving unit includes driving branches respectively for enhancing the driving capabilities of the third and fourth clock signals, and the driving branches include a plurality of inverters connected in series.

4. The clock signal generating device according to claim 1, wherein The clock output module further includes: A clock adjusting unit configured to generate a clock signal group having a preset duty cycle based on the first and / or second clock signals.

5. The clock signal generating device according to claim 4, wherein The clock adjusting unit includes at least one variable capacitor for adjusting the duty cycle.

6. The clock signal generating device according to claim 5, wherein The first variable capacitor and the second variable capacitor respectively include capacitor branches connected in parallel, wherein the capacitor branch includes a capacitor and a capacitor transmission gate, and the capacitor is coupled to a low potential via the capacitor transmission gate.

7. The clock signal generating device according to claim 1, wherein The first oscillation unit further includes a first NOT gate and a second NOT gate connected in series between the node between the resistive device having a negative temperature characteristic and the first variable capacitor and the input end of the first NAND gate, and the output of the second NOT gate is used as the first clock signal; The second oscillation unit further includes a third NOT gate and a fourth NOT gate connected in series between the node between the resistive device having a positive temperature characteristic and the second variable capacitor and the input end of the second NAND gate, and the output of the fourth NOT gate is used as the second clock signal.

8. The clock signal generating device according to claim 1, wherein The resistive device is implemented by a resistor array, and the resistor array includes a plurality of resistor adjusting units, wherein the resistor adjusting unit includes: A first resistor branch including a first resistor; A second resistor branch, which includes a second resistor and a switch, wherein the second resistor branch is connected in parallel with the first resistor branch.

9. An integrated circuit, characterized in that, Comprising the clock signal generating device according to any one of claims 1 to 8.

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