Buffer circuit for suppressing turn-off overshoot voltage and oscillation of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and parameter calculation method

Abstract

The invention discloses a buffer circuit for suppressing turn-off overshoot voltage and oscillation of a SiC MOSFET and a parameter calculation method, the buffer circuit is connected in a double-buffer circuit, the buffer circuit comprises a buffer capacitor Csnub and a buffer resistor Rsnub, the buffer capacitor Csnub and the buffer resistor Rsnub are connected in series, the buffer capacitor Csnub and the buffer resistor Rsnub are connected in parallel, and the buffer capacitor Csnub and the buffer resistor Rsnub are connected in parallel. And two ends of the buffer capacitor Csnub and the buffer resistor Rsnub which are connected in series are respectively connected between the bus capacitor and the half-bridge module. According to the invention, the buffer circuit is utilized to suppress overshoot voltage and oscillation when the SiC MOSFET is turned off, and the advantage of high-speed switching of the SiC MOSFET is not sacrificed.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a buffer circuit and a parameter calculation method for suppressing turn-off overshoot voltage and oscillation of a SiC MOSFET. Background Art

[0002] The semiconductor power devices commonly used in power electronic systems mainly include silicon (Si) devices and SiC devices. SiCMOSFET has gradually become the preferred power device for high power density and high frequency applications due to its high switching speed, low on-resistance and high operating temperature.

[0003] As attached Figure 1 The double buffer circuit diagram of SiC MOSFET in the prior art is shown. The double buffer circuit includes a half-bridge module composed of an upper bridge SiC MOSFET tube Q1 and a lower bridge SiC MOSFET tube Q2, an input DC voltage V DC , bus capacitance C BUS , load inductance L lood , upper bridge drive voltage V gs_H and the lower bridge drive voltage V gs_L . Bus capacitance C BUS Connect the input DC voltage V DC Both ends; the half-bridge module is connected to the bus capacitor C BUS Two ends; load inductance L lood One end is connected to the drain of the upper bridge SiC MOSFET tube Q1 of the half-bridge module, and the other end is connected to the source of the lower bridge SiC MOSFET tube Q1 of the half-bridge module; the upper bridge drive voltage V gs_H and the lower bridge drive voltage V gs_L They are respectively connected to the upper and lower half-bridge driving voltage input ports of the half-bridge module.

[0004] However, SiC MOSFET is sensitive to parasitic parameters and is prone to severe switching oscillation, which not only affects the stability and reliability of the system, but also causes electromagnetic interference problems and even damages the device. In the prior art, this voltage oscillation can be suppressed by selecting a larger gate resistor, but this will reduce the switching speed of the SiC MOSFET and increase the loss, thereby reducing the advantages of the SiC MOSFET. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is: how to provide a buffer circuit and parameter calculation method for suppressing the overshoot voltage and oscillation when the SiCMOSFET is turned off, which can effectively suppress the overshoot voltage and oscillation when the device is turned off without reducing the switching speed.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] A buffer circuit for suppressing SiC MOSFET turn-off overshoot voltage and oscillation, the buffer circuit is connected in a double buffer circuit, and the buffer circuit includes a buffer capacitor C snub and snubber resistor R snub , the buffer capacitor C snub and the snubber resistor R snub connected in series, and the buffer capacitor C snub and the snubber resistor R snub The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module.

[0008] Preferably, the buffer circuit further includes a decoupling capacitor C dec and series damping resistor R dec , the decoupling capacitor C dec and the series damping resistor R dec connected in series, and the decoupling capacitor C dec and the series damping resistor R dec The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module.

[0009] A parameter calculation method for a buffer circuit for suppressing SiC MOSFET turn-off overshoot voltage and oscillation as described above comprises the following steps:

[0010] Step 1) According to the partial curve of drain-source voltage and junction capacitance in the SiC MOSFET device manual, the junction capacitance under any drain-source voltage is calculated;

[0011] Step 2) simulating and obtaining the original turn-off voltage oscillation waveform of the SiC MOSFET in the double buffer circuit when no buffer circuit is added, and calculating and obtaining the oscillation frequency according to the original turn-off voltage oscillation waveform;

[0012] Step 3) establishing an oscillation equivalent circuit model of the double buffer circuit when no buffer circuit is added, and calculating the total parasitic inductance of the power loop according to the oscillation frequency calculated in step 2);

[0013] Step 4) Create a buffer capacitor C snub and snubber resistor R snub The oscillation equivalent circuit model of the double buffer circuit at this time is obtained, and the damping coefficient ζ expression of the double buffer circuit at this time is obtained, and the buffer capacitance C is calculated snub The capacitance value and snubber resistor R snub resistance value.

[0014] Preferably, the method further comprises step 5) establishing a series damping resistor R decand decoupling capacitor C dec The oscillation equivalent circuit model of the double buffer circuit is calculated, and the series damping resistance R dec The resistance value and decoupling capacitor C dec Capacitance value.

[0015] Preferably, the calculation formula of the junction capacitance in step 1) is:

[0016]

[0017] Where: C V0 is the junction capacitance corresponding to the drain-source voltage of 0V in the SiC MOSFET device manual, C hv is the junction capacitance corresponding to the set value of the drain-source voltage in the SiC MOSFET device manual, V is the drain-source voltage of the SiC MOSFET, and a and b are coefficients.

[0018] Preferably, the calculation formula of the junction capacitance in step 1) is:

[0019]

[0020] Preferably, the calculation formula of the total parasitic inductance in step 3) is:

[0021]

[0022] Where: f r is the oscillation frequency.

[0023] Preferably, in step 4), the buffer resistor R snub The calculation formula is:

[0024]

[0025] Snubber capacitor C snub The calculation formula is:

[0026]

[0027] Preferably, in step 5), the decoupling capacitor C dec The capacitance is 50 to 100 times the junction capacitance;

[0028] Series damping resistor R dec The resistance value satisfies the following formula:

[0029] R2≤R dec ≤kR1

[0030]

[0031] Where: L loopis the parasitic inductance between the buffer circuit and the bus capacitor, L P1 is the parasitic inductance between the snubber circuit and the half-bridge module, k is the coefficient, C ds is the SiC MOSFET drain-source voltage.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] 1. The present invention utilizes a buffer circuit to suppress overshoot voltage and oscillation when the SiC MOSFET is turned off, without sacrificing the high-speed switching advantage of the SiC MOSFET.

[0034] 2. The calculation process of the buffer circuit parameters of the present invention is simple.

[0035] 3. The present invention verifies the suppression effect of the buffer circuit through a double-pulse simulation circuit. After adopting the buffer circuit, the oscillation of the turn-off voltage is significantly suppressed, which significantly improves the stability and efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a circuit diagram of a double buffer circuit in the prior art;

[0037] Figure 2 A circuit diagram of a double buffer circuit having a buffer circuit for suppressing SiC MOSFET turn-off overshoot voltage and oscillation according to the present invention;

[0038] Figure 3 The junction capacitance C in the parameter technical method of the buffer circuit for suppressing the overshoot voltage and oscillation of SiC MOSFET turn-off in the present invention is oss The fitting curve diagram of

[0039] Figure 4 is a simulation circuit diagram of a double buffer circuit without adding the buffer circuit of the present invention;

[0040] Figure 5 for Figure 4 The original turn-off voltage oscillation waveform obtained by the simulation circuit;

[0041] Figure 6 is an oscillation equivalent circuit model diagram of a double buffer circuit without adding the buffer circuit of the present invention;

[0042] Figure 7 It is an equivalent circuit diagram of the lower bridge of the double buffer circuit when the buffer capacitor and the buffer resistor in the buffer circuit of the present invention are added and the lower bridge is turned off;

[0043] Figure 8 It is an equivalent circuit diagram of the lower bridge of the double buffer circuit when the decoupling capacitor and the series damping resistor in the buffer circuit of the present invention are added and the lower bridge is turned off;

[0044] Fig. 9 The diagrams are overshoot voltage and oscillation suppression effect diagrams of the decoupling capacitor without the buffer circuit of the present invention, with the buffer capacitor and the buffer resistor, and with the series damping resistor. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0046] It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In the description of the present invention, it should be noted that the orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the invention product is usually placed when used, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance. In addition, the terms "horizontal", "vertical", etc. do not mean that the components are absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly tilted. In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0047] As attached Figure 2As shown, in this specific embodiment, a buffer circuit for suppressing the overshoot voltage and oscillation of SiC MOSFET turn-off is provided. The buffer circuit is connected in a double buffer circuit. The buffer circuit includes a buffer capacitor C snub , buffer resistor R snub , decoupling capacitor C dec and series damping resistor R dec , the buffer capacitor C snub and the snubber resistor R snub connected in series, and the buffer capacitor C snub and the snubber resistor R snub The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module. dec and the series damping resistor R dec connected in series, and the decoupling capacitor C dec and the series damping resistor R dec The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module.

[0048] In this specific embodiment, in order to verify this solution, a double buffer circuit is simulated using Wolfspeed's SiC MOSFET half-bridge module, model WAS310M17BM3. The simulation conditions are V DC =400V, I D =110A, load inductance L lood The bus capacitance C is 150μH. BUS is 400μF.

[0049] The parameter calculation method of the buffer circuit in this specific embodiment includes the following steps:

[0050] Step 1) According to the partial curves of drain-source voltage and junction capacitance in the SiC MOSFET device manual, the junction capacitance under any drain-source voltage is calculated.

[0051] The SiC MOSFET device manual provides junction capacitance curves under some drain-source voltages. In order to obtain the junction capacitance value under any drain-source voltage, the junction capacitance curve in the SiC MOSFET device manual is fitted using the formula. The fitting formula is as follows:

[0052]

[0053] Where: C V0 is the junction capacitance corresponding to the drain-source voltage of 0V in the SiC MOSFET device manual, C hv is the junction capacitance corresponding to the set value of the drain-source voltage in the SiC MOSFET device manual, V is the drain-source voltage of S, and a and b are coefficients.

[0054] In order to obtain better results, segmented fitting can be used:

[0055]

[0056] In this specific embodiment, the fitting results are as follows: Figure 3 As shown in the fitting results, it can be seen that when V DC =400V, C oss =2.6nH.

[0057] Step 2) The original turn-off voltage oscillation waveform of the SiC MOSFET in the double buffer circuit when no buffer circuit is added is simulated, and the oscillation frequency is calculated based on the original turn-off voltage oscillation waveform.

[0058] like Figure 4 The double pulse simulation circuit is shown without any buffer circuit, where the parasitic inductance L loop Set to 235nH; the original turn-off voltage oscillation waveform is obtained by simulation, such as Figure 5 As shown, the overshoot voltage is about 700V, which exceeds the rated voltage by approximately 300V. The voltage overshoot is severe, and the oscillation is also severe. The oscillation time is 1.23μs, there are about 6 oscillation cycles, and the oscillation frequency is 5.91MHz.

[0059] Step 3) establishing an oscillation equivalent circuit model of the double buffer circuit when no buffer circuit is added, and calculating the total parasitic inductance of the power loop according to the oscillation frequency calculated in step 2).

[0060] As attached Figure 6 This is the oscillation equivalent circuit model of the double buffer circuit when no buffer circuit is added. When the SiC MOSFET is turned off and oscillation occurs, it is completely turned off and can be equivalent to the junction capacitance Coss of the SiC MOSFET and the total parasitic inductance L of the power circuit. P Series resonance occurs, at which point the circuit's oscillation frequency f r It can be expressed as:

[0061]

[0062] According to the inverse solution of formula (3), the total parasitic inductance L is obtained P The expression is shown in formula (4).

[0063]

[0064] In this specific embodiment, when f r 5.91MHz, C oss When the total parasitic inductance L is 2.6nH, the calculated total parasitic inductance L P It is 279nH.

[0065] Step 4) Create a buffer capacitor C snub and snubber resistor R snub The oscillation equivalent circuit model of the double buffer circuit is shown in the attached figure. Figure 7 As shown, the damping coefficient ζ expression of the double buffer circuit is obtained, and the buffer capacitance C is calculated snub The capacitance value and snubber resistor R snub resistance value.

[0066] The damping coefficient ζ of this circuit can be expressed as:

[0067]

[0068] By setting the appropriate damping coefficient ζ, the buffer resistance R can be calculated according to formula (5): snub :

[0069]

[0070] When the damping coefficient ζ is set to 1, in the critical damping state, the buffer resistor R snub It is 5.18Ω.

[0071] Snubber capacitor C snub It can be expressed as:

[0072]

[0073] When the buffer resistor R snub is 5.18Ω, oscillation frequency f r When the buffer capacitor C is 5.91MHz, snub The calculated result is 5.2nF.

[0074] Step 5) Add series damping resistor R dec and decoupling capacitor C dec The oscillation equivalent circuit model of the double buffer circuit is shown in the attached figure. Figure 8 As shown, the series damping resistance R is calculated dec The resistance value and decoupling capacitor C dec Capacitance value.

[0075] In the attached Figure 8 In the power circuit, the total parasitic inductance L P It is divided into two parts: the parasitic inductance L between the half-bridge module and P1 The parasitic inductance L between the bus capacitor and loop At this time, the decoupling capacitor C dec Mainly for L loop For decoupling, decoupling capacitor C dec The value is generally the device junction capacitance Coss 50 to 100 times, here we take 55 times.

[0076] Attached Figure 8 The oscillation frequency f of the circuit shown r ' can be expressed as:

[0077]

[0078] To realize the parasitic inductance L loop Decoupling, parasitic inductance L loop With series damping resistor R dec and decoupling capacitor C dec The parallel impedance Z L At high frequency resonant frequency, it is much smaller than the parasitic inductance L P1 , as shown in formula (10).

[0079]

[0080] ω′=2πf r ′(11)

[0081] Right now

[0082]

[0083] Where n represents the position of the decoupling capacitor. Different positions have different effects on L loop The decoupling effect is different, here we take 0.2

[0084] Times R1.

[0085] At the same time, according to the impedance Z L The characteristic root equation root discriminant, damping resistance R dec When the formula (15) is exceeded, the parasitic inductance L can be eliminated. loop and decoupling capacitor C dec resonance.

[0086]

[0087] Finally, the decoupling capacitor C dec The series damping resistor R dec It should satisfy formula (16).

[0088] R2≤R dec ≤0.2R1(16)

[0089] According to the above inequality, when n = 5.3, m = 55, R dec It should be less than 8.2Ω and greater than 2.6Ω. Here, R dec is 3Ω.

[0090] After the above analysis and calculation, the parameters of the proposed turn-off overshoot voltage and oscillation suppression circuit have been determined. Fig. 9 The simulation effect of the suppression circuit proposed by the present invention is shown in the figure. Curve 1 is the drain-source voltage waveform when the lower bridge is turned off without adding the buffer circuit; Curve 2 is the drain-source voltage waveform when the device is turned off when the buffer capacitor and the buffer resistor are added. The oscillation is suppressed to a certain extent, but the effect is limited. There are still 2 oscillation cycles, and the overshoot voltage cannot be suppressed; Curve 3 is the turn-off drain-source voltage waveform after adding the buffer capacitor, buffer resistor, decoupling capacitor and series damping resistor of the present invention. The turn-off voltage overshoot and oscillation are significantly suppressed, and the overshoot voltage is reduced from nearly 700V to 577V, and no oscillation cycle occurs. It shows that the buffer circuit proposed by the present invention and the parameters determined by calculation can effectively suppress the turn-off overshoot voltage and oscillation of SiC MOSFET.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit the technical solution. Those skilled in the art should understand that those modifications or equivalent substitutions of the technical solution of the present invention that do not depart from the purpose and scope of the technical solution should be included in the scope of the claims of the present invention.

Claims

1. A buffer circuit for suppressing SiC MOSFET turn-off overshoot voltage and oscillation, characterized in that: The buffer circuit is connected in a double buffer circuit, and the buffer circuit includes a buffer capacitor C snub and snubber resistor R snub , the buffer capacitor C snub and the snubber resistor R snub connected in series, and the buffer capacitor C snub and the snubber resistor R snub The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module.

2. The buffer circuit for suppressing SiC MOSFET turn-off overshoot voltage and oscillation according to claim 1, characterized in that: The buffer circuit also includes a decoupling capacitor C dec and series damping resistor R dec , the decoupling capacitor C dec and the series damping resistor R dec connected in series, and the decoupling capacitor C dec and the series damping resistor R dec The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module.

3. A parameter calculation method for a buffer circuit for suppressing SiC MOSFET turn-off overshoot voltage and oscillation according to claim 1, characterized in that: The following steps are involved: Step 1) According to the partial curve of drain-source voltage and junction capacitance in the SiC MOSFET device manual, the junction capacitance under any drain-source voltage is calculated; Step 2) simulating and obtaining the original turn-off voltage oscillation waveform of the SiC MOSFET in the double buffer circuit when no buffer circuit is added, and calculating and obtaining the oscillation frequency according to the original turn-off voltage oscillation waveform; Step 3) establishing an oscillation equivalent circuit model of the double buffer circuit when no buffer circuit is added, and calculating the total parasitic inductance of the power loop according to the oscillation frequency calculated in step 2); Step 4) Create a buffer capacitor C snub and snubber resistor R snub The oscillation equivalent circuit model of the double buffer circuit at this time is obtained, and the damping coefficient ζ expression of the double buffer circuit at this time is obtained, and the buffer capacitance C is calculated snub The capacitance value and snubber resistor R snub resistance value.

4. The parameter calculation method of the buffer circuit for suppressing the turn-off overshoot voltage and oscillation of SiC MOSFET according to claim 3, characterized in that: The buffer circuit also includes a decoupling capacitor C dec and series damping resistor R dec , the decoupling capacitor C dec and the series damping resistor R dec connected in series, and the decoupling capacitor C dec and the series damping resistor R dec The two ends of the series connection are respectively connected between the bus capacitor and the half-bridge module; Also includes step 5) establishing a series damping resistor R dec and decoupling capacitor C dec The oscillation equivalent circuit model of the double buffer circuit is calculated, and the series damping resistance R dec The resistance value and decoupling capacitor C dec Capacitance value.

5. The parameter calculation method of the buffer circuit for suppressing the turn-off overshoot voltage and oscillation of SiC MOSFET according to claim 4, characterized in that: The calculation formula for the junction capacitance in step 1) is: Where: C V0 is the junction capacitance corresponding to the drain-source voltage of 0V in the SiC MOSFET device manual, C hv is the junction capacitance corresponding to the set value of the drain-source voltage in the SiC MOSFET device manual, V is the drain-source voltage of the SiC MOSFET, and a and b are coefficients.

6. The parameter calculation method of the buffer circuit for suppressing the turn-off overshoot voltage and oscillation of SiC MOSFET according to claim 5, characterized in that: The calculation formula for the junction capacitance in step 1) is:

7. The parameter calculation method of the buffer circuit for suppressing the overshoot voltage and oscillation of SiC MOSFET turn-off according to claim 6, characterized in that: The calculation formula for the total parasitic inductance in step 3) is: Where: f r is the oscillation frequency.

8. The parameter calculation method of the buffer circuit for suppressing the overshoot voltage and oscillation of SiC MOSFET turn-off according to claim 7, characterized in that: In step 4), the buffer resistor R snub The calculation formula is: Snubber capacitor C snub The calculation formula is:

9. The parameter calculation method of the buffer circuit for suppressing the turn-off overshoot voltage and oscillation of SiC MOSFET according to claim 8, characterized in that: In step 5), the decoupling capacitor C dec The capacitance is 50 to 100 times the junction capacitance; Series damping resistor R dec The resistance value satisfies the following formula: R2≤R dec ≤kR1 Where: L loop is the parasitic inductance between the snubber circuit and the bus capacitor, L P1 is the parasitic inductance between the snubber circuit and the half-bridge module, k is the coefficient, C ds is the SiC MOSFET drain-source voltage.

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