SOT-based digital AND gate and OR gate realization device

Abstract

The invention discloses an SOT-based digital AND gate and OR gate implementation device. The SOT-based digital AND gate and OR gate implementation device comprises two magnetic tunnel junctions, an SOT coupling layer, four MOS transistors and a read control circuit, one end of the SOT coupling layer is connected with the source electrode of the first MOS tube and the source electrode of the second MOS tube, and the other end of the SOT coupling layer is grounded; two magnetic tunnel junctions MTJ1 and MTJ2 with different sizes are fixed on the surface of the SOT coupling layer, each magnetic tunnel junction sequentially comprises a free layer, an oxide isolation layer and a fixed layer from bottom to top, and the fixed layers of the magnetic tunnel junctions are respectively connected with the source electrode of the third MOS tube and the source electrode of the fourth MOS tube; drain electrodes and grid electrodes of the third MOS tube and the fourth MOS tube are connected with the read control circuit. Current data measured by the current sensor cannot be lost due to power failure, and the current sensor has a storage function, is small in structure size and area, and is suitable for a high-density storage and calculation integrated structure.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit design, and relates to a device for realizing a digital AND gate and an OR gate based on a SOT. Background Art

[0002] Magnetic tunnel junction (MTJ) is a device affected by the spin-orbit torque (SOT) effect, with high resistance and low resistance states. Its resistance state is determined by the polarization direction of the reference layer and the free layer. The SOT coupling layer uses strong spin-orbit interaction to convert the charge flow into spin flow injected into the free layer through the spin Hall effect or the Rashba effect, exerting spin-orbit torque to drive the magnetic moment flip or the magnetic domain wall to move and change the polarization direction. When the polarization directions are parallel, the probability of electron tunneling is high and the resistance is low; when they are anti-parallel, the probability of tunneling is low and the resistance is high. Under the action of an external current, the MTJ can switch between the two resistance states. As a new storage technology, more and more semiconductor manufacturers are increasing their research and development and investment in MRAM technology to seek more cost-effective, faster and more efficient storage solutions.

[0003] Today, digital and analog integrated circuits based on von Neumann architecture are developing rapidly and have become an important force driving the Internet, and are an indispensable cornerstone of information processing in modern society. However, with the advancement of technology, the demand for information processing and storage for complex tasks is increasing, and the traditional von Neumann architecture has become a limiting factor, forcing people to explore new architectures.

[0004] To overcome the von Neumann bottleneck, researchers have proposed a memory-based in-memory computing architecture. This new computer architecture performs logical operations directly in the memory, eliminating the need to move data between the memory and the processor, thereby significantly improving data processing efficiency and reducing device power consumption.

[0005] In order to develop in-memory computing, a device with both storage and computing capabilities is needed. Magnetic tunnel junctions (MTJs) can represent logical states through resistance states. For MTJs with different threshold currents, some will flip and some will not under the same constant current. This feature can be used to build a variety of logic circuits. In addition, MTJs maintain their state after power failure, and have the advantages of non-volatility, radiation resistance, erasure resistance, high speed, etc. They are suitable for harsh environments, extend life, and improve efficiency. Due to the small size of MTJs, they are easy to integrate into chips.

[0006] Compared with the proposed STT-MTJ as the core device of the integrated storage and computing circuit, the SOT-MTJ has a lower write delay, reduces data transmission delay, and is more suitable for high-performance computing needs; and the read and write circuits are separated, which reduces read and write interference and improves parallel processing capabilities. Summary of the invention

[0007] In view of the deficiencies in existing research, the present invention proposes an implementation device of digital AND gates and OR gates based on SOT to reliably and stably implement "AND" and "OR" operations, which can be widely used in in-memory operations.

[0008] A device for realizing a digital AND gate and an OR gate based on SOT comprises two magnetic tunnel junctions, a SOT coupling layer, four MOS tubes and a read control circuit.

[0009] The SOT-based digital AND gate and OR gate implementation device specifically includes: one end of the SOT coupling layer is connected to the source of the first MOS tube and the source of the second MOS tube, and the other end is grounded; two magnetic tunnel junctions of different sizes are fixed on the surface of the SOT coupling layer, the two magnetic tunnel junctions are MTJ1 and MTJ2, the magnetic tunnel junctions are a free layer, an oxide isolation layer and a fixed layer from bottom to top, and the two magnetic tunnel junctions require different flip threshold currents, the fixed layers of the magnetic tunnel junctions are respectively connected to the third MOS tube and the fourth MOS tube, wherein the source of the third MOS tube is connected to the fixed layer of MTJ1, and the source of the fourth MOS tube is connected to the fixed layer of MTJ2; the drains and gates of the third MOS tube and the fourth MOS tube are both connected to the read control circuit.

[0010] The read control circuit is used to select whether to perform an "AND" operation or an "OR" operation. If the "AND" operation is performed, the third MOS tube is turned on, the remaining MOS tubes are turned off, and the "AND" operation result is output through the sensitive amplifier; if the "OR" operation is performed, the fourth MOS tube is turned on, the remaining MOS tubes are turned off, and the "OR" operation result is output through the sensitive amplifier; the gate of the first MOS tube is connected to the first input voltage, and the gate of the second MOS tube is connected to the second input voltage; the drain of the first MOS tube is connected to the fixed voltage VIN1, and the drain of the second MOS tube is connected to the fixed voltage VIN2; the resistance value of the magnetic tunnel junction is adjusted according to the input voltage.

[0011] Preferably, the SOT coupling layer conductor may be one of platinum, tantalum, tungsten or a combination thereof.

[0012] Preferably, the two magnetic tunnel junctions are made of the same material and diameter but have different heights.

[0013] Preferably, the two magnetic tunnel junctions are made of the same material and height but have different diameters.

[0014] As a preferred embodiment, the read control circuit is specifically: one end of the sensitive amplifier SA1 is connected to the drain of the third MOS tube, and the other end is connected to the reference resistor R ref1 Ground; one end of the sensitive amplifier SA2 is connected to the drain of the fourth MOS tube, and the other end is connected to the reference resistor R ref2 The third MOS tube gate and the fourth MOS tube gate are connected to the fixed voltage C and D respectively.

[0015] The magnetic tunnel junction is composed of a free layer, an oxide isolation layer and a fixed layer from bottom to top, wherein the fixed layer and the free layer are ferromagnetic materials, and the magnetization direction of the fixed layer is fixed and unchanged, and the magnetization direction of the free layer is affected by the SOT effect. When the magnetization directions of the two are the same, the magnetic tunnel junction exhibits a low resistance state, and when the magnetization directions are opposite, it exhibits a high resistance state. The oxide isolation layer is a non-magnetic insulating material.

[0016] Assume that the equivalent resistance value of the magnetic tunnel junction MTJ1 when it is low resistance is R1, the equivalent resistance value of MTJ2 when it is low resistance is R2, the equivalent resistance value of MTJ1 when it is high resistance is R3, and the equivalent resistance value of MTJ2 when it is high resistance is R4; wherein the equivalent resistance values ​​are R1<R2<R3<R4.

[0017] The implementation principle of the digital AND gate and OR gate implementation device based on SOT of the present invention is as follows:

[0018] Initialize the two magnetic tunnel junctions, pass a flip current into the SOT coupling layer, flip the magnetic tunnel junctions on the surface to a low resistance state, and then remove the flip current.

[0019] The gate voltages of the first MOS tube and the second MOS tube are controlled, and currents of different magnitudes are applied to the current input end of the SOT coupling layer to change the state of the magnetic tunnel junction.

[0020] Remove the input current, disconnect the coupling layer between the MOS tube and the SOT, and read the control circuit to collect the resistance of the magnetic tunnel junction.

[0021] Define different Rs as different logic outputs, establish a logical relationship table between input voltage and output voltage, and construct "AND" logic and "OR" logic according to the input and output control of different MOS tubes.

[0022] The present invention has the following beneficial effects:

[0023] 1. Two magnetic tunnel junctions of different sizes are used to form a logic gate circuit.

[0024] 2. Due to the non-volatile characteristics of the magnetic tunnel junction, the measured current data will not be lost due to power failure and has storage function.

[0025] 3. The device has a small structural size and is suitable for high-density storage and computing integrated structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a device for implementing a digital AND gate and an OR gate based on SOT in an embodiment;

[0027] Figure 2It is a flow chart of the implementation device of digital AND gate and OR gate based on SOT;

[0028] Figure 3 This is a schematic diagram of a circuit for measuring MTJ resistance state in an embodiment;

[0029] Figure 4 The structural diagram of a single MTJ and the schematic diagram of the magnetic moment direction of the MTJ;

[0030] In the figure: 01-SOT coupling layer, 02-MTJ1, 03-MTJ2, 04-third MOS tube, 05-fourth MOS tube, 06-first MOS tube, 07-second MOS tube. DETAILED DESCRIPTION

[0031] In summary, in order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the examples of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Of course, the described embodiments are embodiments of a part of the present invention, not all embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents an embodiment of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0032] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0033] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0034] A digital AND gate and OR gate implementation device based on SOT, such as Figure 1As shown, it is a structural block diagram of the implementation device of the digital AND gate and OR gate based on SOT in the first embodiment. In the block diagram, the SOT coupling layer 01 and two MTJs of different sizes are connected through two necessary input signals. The whole logic unit can be equivalent to a 2T2M (two MTJs and two MOS tubes) structure, wherein the MTJ is used to store non-volatile resistance values, and the read control circuit is used to read the state of the MTJ; two MOS tubes are connected between the read control circuit and the MTJ, each MOS tube represents a different logic operation, the third MOS tube 04 is turned on, representing the result of the "AND" operation, and the fourth MOS tube 05 is turned on, representing the result of the "OR" operation; the two MOS tubes connected to the SOT coupling layer 01 are responsible for the resistance state flipping control of the MTJ.

[0035] When the first MOS tube 06 or the second MOS tube 07 is turned on, the input current causes MTJ1 02 to flip, and MTJ2 03 does not flip; when both the first MOS tube 06 and the second MOS tube 07 are turned on, the input current causes both MTJ1 02 and MTJ2 03 to flip.

[0036] like Figure 2 As shown in the figure, it is a flow chart of the implementation device of digital AND gate and OR gate based on SOT. The implementation principle is as follows:

[0037] The above logic device is constructed, in which MTJ1 02 is smaller in size and has a smaller flip threshold current, while MTJ2 03 is larger in size and has a larger flip threshold current. When either the first input voltage or the second input voltage is turned on, MTJ1 02 can reach its flip threshold current, while MTJ2 03 does not reach its flip threshold current, and the resistance of MTJ1 02 is flipped while the resistance of MTJ2 03 remains unchanged. When the first input voltage and the second input voltage are turned on at the same time, both MTJ1 02 and MTJ2 03 can reach their flip threshold currents, and the resistance of both MTJ1 02 and MTJ2 03 are flipped.

[0038] Initialization: Input a sufficiently large initialization current into the SOT layer to make both MTJ1 02 and MTJ2 03 in a low resistance state.

[0039] The first input voltage (A) is fixed to control the opening and closing of the gate of the first MOS transistor 06, and the second input voltage (B) is fixed to control the opening and closing of the gate of the second MOS transistor 07. Currents of different magnitudes are applied to the current input end of the SOT coupling layer 01 to change the state of the magnetic tunnel junction.

[0040] according to Figure 3As shown, the input current is removed, the gate voltage (A) of the first MOS tube 06 and the gate voltage (B) of the second MOS tube 07 are disconnected; when the "AND" operation is performed, the gate of the third MOS tube 04 is controlled by a fixed voltage (C), the third MOS tube 04 and the sensitive amplifier SA1 are turned on, one end of SA1 is connected to the third MOS tube 04, and the other end is connected to the reference resistor R ref1 , its resistance is (R1+R3) / 2. When the resistance of MTJ1 02 is low resistance R1, the output OUT1=0; when the resistance of MTJ1 02 is high resistance R3, the output OUT1=1; when the "OR" operation is performed, the gate of the fourth MOS tube 05 is controlled by a fixed voltage (D), the fourth MOS tube 05 and the sensitive amplifier SA2 are turned on, one end of SA2 is connected to the fourth MOS tube 05, and the other end is connected to the reference resistor R ref2 , its resistance is (R2+R4) / 2. When the resistance of MTJ203 is low resistance R2, the output OUT2=0; when the resistance of MTJ203 is high resistance R4, the output OUT2=1.

[0041] like Figure 4 As shown, the magnetic tunnel junction (MTJ) has a multi-layer film structure, including a free layer and a fixed layer composed of magnetic materials, and an oxide isolation layer between the two. When the current flowing from the fixed layer to the free layer exceeds a certain critical value for a certain period of time, the magnetic moment direction of the free layer is parallel to the magnetic moment direction of the fixed layer, and the MTJ presents a low resistance "0" state; conversely, when the current flowing from the free layer to the fixed layer exceeds a certain critical value for a certain period of time, the magnetic moment direction of the free layer is anti-parallel to the magnetic moment direction of the fixed layer, and the MTJ presents a high resistance "1" state. The corresponding truth tables are shown in Tables 1 and 2 below:

[0042] Table 1: Truth table of logical "AND" operation

[0043]

[0044] Table 2: Logical OR operation truth table

[0045]

[0046] The above is only a specific implementation of a part of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A digital AND gate and OR gate implementation device based on SOT, characterized in that: It includes two magnetic tunnel junctions, a SOT coupling layer, four MOS tubes and a read control circuit; One end of the SOT coupling layer is connected to the source of the first MOS tube and the source of the second MOS tube, and the other end is grounded; two magnetic tunnel junctions MTJ1 and MTJ2 of different sizes are fixed on the surface of the SOT coupling layer, and the magnetic tunnel junctions are a free layer, an oxide isolation layer and a fixed layer from bottom to top, and the fixed layers of the magnetic tunnel junctions are respectively connected to the source of the third MOS tube and the source of the fourth MOS tube; the drains and gates of the third MOS tube and the fourth MOS tube are both connected to the read control circuit.

2. The implementation device of digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The gate of the first MOS tube is connected to the first input voltage, the gate of the second MOS tube is connected to the second input voltage, the drain of the first MOS tube is connected to the fixed voltage VIN1, and the drain of the second MOS tube is connected to the fixed voltage VIN2; the resistance of the magnetic tunnel junction is adjusted according to the input voltage.

3. The implementation device of digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The SOT coupling layer conductor is one of platinum, tantalum, and tungsten, or a combination thereof.

4. The implementation device of digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The two magnetic tunnel junctions require different switching threshold currents.

5. The implementation device of digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The two magnetic tunnel junctions have the same material and diameter but different heights.

6. The implementation device of digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The two magnetic tunnel junctions have the same material and height but different diameters.

7. The device for realizing digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The fixed layer and the free layer in the magnetic tunnel junction are made of ferromagnetic materials, the magnetization direction of the fixed layer is fixed, and the magnetization direction of the free layer is affected by the SOT effect; the oxide isolation layer is made of non-magnetic insulating material.

8. The device for realizing digital AND gate and OR gate based on SOT according to claim 1, characterized in that: The read control circuit is specifically: one end of the sensitive amplifier SA1 is connected to the drain of the third MOS tube, and the other end is connected to the reference resistor R ref1 Ground; one end of the sensitive amplifier SA2 is connected to the drain of the fourth MOS tube, and the other end is connected to the reference resistor R ref2 The third MOS tube gate and the fourth MOS tube gate are connected to the fixed voltage C and D respectively.

9. The device for realizing digital AND gate and OR gate based on SOT according to claim 8, characterized in that: The implementation device of the digital AND gate and OR gate turns on the third MOS tube and turns off the remaining MOS tubes when performing an AND operation, and outputs the AND operation result through the sensitive amplifier SA1; when performing an OR operation, turns on the fourth MOS tube, turns off the remaining MOS tubes, and outputs the OR operation result through the sensitive amplifier SA2.

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