Reconfigurable high-precision multipath time delay simulation method and device

Abstract

The invention relates to the technical field of wireless information transmission, and provides a reconfigurable high-precision multipath time delay simulation method and device. Group time delay and relative time delay are graded for three times, fine time delay with the time delay amount within a decimal range is realized by using a reduced farrow filter structure, the precision can reach 0.1 ns, coarse time delay with the time delay amount being integral multiple of a system clock is realized by using ram resources, and large-range time delay of signals is realized by using ping-pong operation through a dislocation address control technology. And finally, large-range and high-precision multipath time delay simulation is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless information transmission, and in particular to a reconfigurable high-precision multipath delay simulation method and device. Background Art

[0002] With the rapid development of global communication technology, satellite communication, as an important means of communication, has been widely used in military, civil, scientific research and other fields. However, the satellite communication channel environment is complex and changeable, including atmospheric interference, multipath delay, ionospheric influence and other factors, which have a serious impact on signal transmission quality and system performance. In the development of satellite communication systems, accurate simulation of the channel environment is crucial, especially accurate simulation of delay.

[0003] Existing solutions often use the internal storage unit of the FPGA chip to simulate the signal's delay by an integer multiple of the system clock cycle. When using a large memory, it is often necessary to pre-store some data to achieve simultaneous reading and writing. Although this can achieve a large delay, it will sacrifice accuracy. The existing technical solutions cannot meet the requirements of both accuracy and large delay at the same time. Summary of the invention

[0004] In order to solve the problems existing in the prior art, the present invention provides a reconfigurable high-precision multipath delay simulation method and device thereof, so as to solve the problem that the prior art cannot simultaneously meet the requirements of high precision and large delay.

[0005] To achieve the above object, the present invention provides a reconfigurable high-precision multipath delay simulation method, comprising:

[0006] S1, select the signal input and output mode, add the number of channel paths for each link, and set the delay parameters, fading type and Doppler frequency shift for each path;

[0007] S2, the host computer converts the delay parameters input by the user into group delay and relative delay, and classifies them into three levels according to the delay amount, namely fine delay, coarse delay and large-scale delay. The host computer calculates the delay amount corresponding to each level and converts it into a fixed-point number and sends it to the FPGA chip;

[0008] S3, the FPGA chip obtains the group delay sent by the host computer, uses RAM resources for coarse delay, uses the Lagrange interpolation algorithm to achieve fine delay for the output result, uses the random access memory to use ping-pong operation, and achieves a large range of signal delay through the staggered address control technology;

[0009] S4: The FPGA chip obtains the relative delay sent by the host computer, uses RAM resources to perform coarse delay, and uses the Lagrange interpolation algorithm to achieve fine delay for the output result;

[0010] S5: Add fading to the delayed result, superimpose and output the multipath signal.

[0011] Specifically, the host computer calculates the minimum delay as the group delay according to the delay parameters, and the co-path is converted into the relative delay with the minimum delay path as a reference.

[0012] Specifically, the fine delay is a delay that is a decimal multiple of the system clock, and the coarse delay is a delay that is an integer multiple of the system clock.

[0013] Specifically, the group delay includes fine delay, coarse delay and large-scale delay, and the relative delay includes fine delay and coarse delay.

[0014] Specifically, in step S3, the large-scale delay control operation is:

[0015] S3.1, the large-range delay module receives the delay start working flag sent by the host computer, and the read start address corresponding to the signal delay amount of each link;

[0016] S3.2, splice the data of each link and start writing data into the write FIFO;

[0017] S3.3, determine whether the write FIFO is half full. If it is, enter the write DDR4 operation. If it is not, go to S3.4.

[0018] S3.4, sequentially determine whether the read FIFO corresponding to each current link is half full. If not, read the data in the random access memory according to the read address corresponding to the read FIFO of the link, and then determine the state of the read FIFO corresponding to the next link. If it is half full, proceed to determine the state of the read FIFO corresponding to the next link, until the read FIFO of the last link is reached.

[0019] S3.5, repeat steps S3.3 and S3.4 until data reception is completed.

[0020] Specifically, the Lagrangian interpolation algorithm is a 4-point piecewise parabola reduced-order farrow filter.

[0021] Specifically, the interpolation polynomial of the farrow filter is:

[0022] ,

[0023] In the formula is the Lagrange interpolation factor, and its calculation formula is:

[0024]

[0025] Calculate the number between the four interpolation points as,

[0026] ,

[0027] With (t0, x k ), (t -0.5 , x k+0.5 ), (t -1 , x k+1 ) are used as interpolation points for secondary interpolation, and the Lagrange coefficient is obtained as follows:

[0028] ,

[0029] ,

[0030] ,

[0031] The interpolation polynomial is,

[0032] ,

[0033] By simplifying the above three equations, the 4-point segmented parabola interpolation coefficients are obtained as follows:

[0034] ;

[0035] ;

[0036] ;

[0037] .

[0038] Specifically, the farrow filter includes 2 multipliers and 8 adders.

[0039] The present invention also provides a reconfigurable high-precision multipath delay simulation device, which is characterized by comprising: a host computer and an FPGA chip, wherein:

[0040] The host computer is configured to select input and output modes according to the communication scenario, add the number of channel paths to each link, set different delay parameters, fading types and Doppler frequency shifts, convert the delay parameters into group delay and relative delay, and perform three classifications to divide the delay into fine delay, coarse delay and large-scale delay, calculate the delay amount corresponding to each level and convert it into a fixed-point number and output it to the FPGA chip;

[0041] The FPGA chip is configured to obtain the group delay and relative delay sent by the host computer, use random access memory to achieve large-scale delay, use RAM resources to achieve coarse delay, use Lagrange interpolation algorithm to achieve fine delay, add fading to the delayed result, and superimpose and output multipath signals.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] 1. The present invention classifies the delay into three levels, uses a reduced-order farrow filter structure to achieve a fine delay in the decimal range with an accuracy of up to 0.1ns, uses RAM resources to achieve a coarse delay with an integer multiple of the system clock, uses a random access memory to utilize ping-pong operations, and achieves a large range of signal delays through staggered address control technology, ultimately achieving a large-scale, high-precision multipath delay simulation.

[0044] 2. The present invention uses a reduced-order farrow filter, which only requires 2 multipliers and 8 adders without reducing the interpolation quality, effectively reducing the consumption of DSP computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is the overall block diagram of the multipath delay simulation device;

[0046] Figure 2 is a random access memory state control diagram;

[0047] Figure 3 is a structural diagram of a down-order farrow filter in the present invention;

[0048] Figure 4 This is a structural diagram of a farrow filter in the prior art. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0050] The present invention provides a reconfigurable high-precision multipath delay method:

[0051] S1, select the signal input and output mode, add the number of channel paths for each link, and set the delay parameters, fading type and Doppler frequency shift for each path.

[0052] Users can set the signal input mode by themselves. The input mode includes external source input or internal source input. If an external source is used, set the signal source. If an internal source is used, set the data type and corresponding parameters. Users select SISO and MIMO modes according to the standard channel model. A unit supports up to 8 inputs and 8 outputs and supports multiple unit cascades. The signal can be single tone, digital modulation and other signals. Add the number of channel paths for each link, and set different delay parameters, fading types, Doppler frequency shift and other parameters for each path.

[0053] S2: The host computer converts the delay parameters input by the user into group delay and relative delay, and classifies them into three levels according to the delay amount, namely fine delay, coarse delay and large-scale delay. The host computer calculates the delay amount corresponding to each level and converts it into a fixed-point number and sends it to the FPGA.

[0054] The host computer calculates the minimum delay as the group delay based on the delay parameters set by the user, and the rest of the paths use the minimum delay path as a reference for relative delay. The delay is graded three times according to the delay amount, which is divided into fine delay with a delay amount that is a decimal multiple of the system clock, coarse delay with a delay amount that is an integer multiple of the system clock, and large-scale delay. The group delay includes decimal delay, delay that is an integer multiple of the system clock, and large-scale delay, and the relative delay includes decimal delay and delay that is an integer multiple of the system clock. The host computer calculates the delay amount corresponding to each level and converts it into a fixed-point number and sends it to the FPGA.

[0055] S3, the FPGA chip obtains the group delay sent by the host computer, uses RAM resources for coarse delay, uses the Lagrange interpolation algorithm to output the result to achieve fine delay, uses random access memory to utilize ping-pong operation, and achieves large-scale signal delay through staggered address control technology.

[0056] The FPGA chip first performs group delay on the input signal, supporting up to 8 channels. In the signal delay processing part of the FPGA, the input signal is firstly subjected to group delay, supporting up to 8 channels. The FPGA obtains the group delay sent by the host computer, first uses RAM resources for coarse delay, and then uses the Lagrange interpolation algorithm to perform fine delay on the output result, with an accuracy of up to 0.1ns. Finally, the ping-pong operation is used to use DDR4 through the staggered address control technology to achieve a delay within 1s for 8 inputs.

[0057] Large-scale latency is achieved using DDR4 SDRAM, providing ultra-fast reading and writing using DDR4. By reasonably switching the read and write states, ping-pong operations are used to achieve simultaneous reading and writing of 8 signals under the system clock, and staggered address control technology is used to achieve large-scale latency for 8-channel data.

[0058] S3.1, the large-range delay module receives the delay start working flag sent by the host computer, and the read start address corresponding to the signal delay amount of each link;

[0059] S3.2, splice the data of each link and start writing data into the write FIFO;

[0060] S3.3, determine whether the write FIFO is half full. If it is, enter the write DDR4 operation. If it is not, go to S3.4.

[0061] S3.4, sequentially determine whether the read FIFO corresponding to each current link is half full. If not, read the data in the random access memory according to the read address corresponding to the read FIFO of the link, and then determine the state of the read FIFO corresponding to the next link. If it is half full, proceed to determine the state of the read FIFO corresponding to the next link, until the read FIFO of the last link is reached.

[0062] S3.5, repeat steps S3.3 and S3.4 until data reception is completed.

[0063] like Figure 2 As shown, the specific operation of the random access memory is:

[0064] Step (1): The user sets the group delay, and the host computer sends the group delay start flag and the read start address corresponding to the 8-channel signal delay;

[0065] Step (2): splice the 8-way data and start writing data into the write FIFO;

[0066] Step (3): Determine the state of the write FIFO. If it reaches half full, enter the write DDR4 operation. If it does not reach half full, enter step (4).

[0067] Step (4): Determine whether FIFO0 is half full. If it is half full, proceed to step (5). If it is not half full, start reading data in DDR according to the first read address, read 128 memory cells and proceed to step (5).

[0068] Step (5): Determine whether FIFO1 is half full. If it is half full, proceed to step (6). If it is not half full, start reading data in DDR according to the second read address, read 128 memory cells and proceed to step (6).

[0069] Step (6): Determine whether FIFO2 is half full. If it is half full, proceed to step (7). If it is not half full, start reading data in DDR according to the third read address, read 128 memory cells and proceed to step (7).

[0070] Step (7): Determine whether FIFO3 is half full. If it is half full, proceed to step (8). If it is not half full, start reading data in DDR according to the third read address, read 128 memory cells and proceed to step (8).

[0071] Step (8): Determine whether FIFO4 is half full. If it is half full, proceed to step (9). If it is not half full, start reading data in DDR according to the third read address, read 128 memory cells and proceed to step (9).

[0072] Step (9): Determine whether FIFO5 is half full. If it is half full, proceed to step (10). If it is not half full, start reading data in DDR according to the third read address, read 128 memory cells and proceed to step (10).

[0073] Step (10): Determine whether FIFO6 is half full. If it is half full, proceed to step (11). If it is not half full, start reading data in DDR according to the third read address, read 128 memory cells and proceed to step (11).

[0074] Step (11): Determine whether FIFO7 is half full. If it is half full, proceed to step (3). If it is not half full, start reading data in DDR according to the first read address. Read 128 memory cells and proceed to step (3).

[0075] S4: The FPGA chip obtains the relative delay sent by the host computer, uses RAM resources for coarse delay, and uses the Lagrange interpolation algorithm to achieve fine delay for the output result.

[0076] The signal after group delay is relatively delayed, supporting up to 64 paths. According to the relative delay sent by the host computer, the FPGA chip performs 64-path relative delay on the result after group delay, that is, uses RAM resources to delay integer multiples of the system clock, and then uses the Lagrange interpolation algorithm to achieve a delay with an accuracy of 0.1ns for the output result.

[0077] S5: Add fading to the delayed result, superimpose and output the multipath signal.

[0078] Finally, fading is added to the delayed results and aggregated into 8 outputs.

[0079] The Lagrange interpolation algorithm specifically uses a farrow filter to interpolate the original signal to achieve precise delay. Conventional farrow filters such as Figure 4 As shown, 3 multipliers and 11 adders are needed, which consumes a lot of DSP resources. Therefore, the present invention simplifies the farrow filter.

[0080] The Lagrange interpolation formula is as follows:

[0081] ,

[0082] In the formula, C i is the Lagrange interpolation factor, which is the impulse response coefficient of the interpolation filter. Its calculation formula is:

[0083]

[0084] The impulse response coefficient of the farrow filter is a function of the delay control word u. The direct structure with fixed coefficients cannot achieve dynamic delay variation. The filter coefficients in the farrow filter are independent of the delay control word u, which can achieve dynamic delay adjustment. The farrow filter uses a P-order polynomial of u to approximate the ideal impulse response h d (n), its impulse response is expressed as:

[0085]

[0086] Where n=0, 1, 2…N, g m (n) is the impulse response of the m-th group of sub-FIR filters, P is the order, and μ is the interpolation coefficient.

[0087] The coefficients of the sub-FIR filter are fixed. The coefficient function of the Farrow filter is:

[0088]

[0089]

[0090] In the farrow structure filter constructed by cubic Lagrange interpolation polynomial, each sub-FIR filter coefficient is fixed and has a small dynamic range. The filter coefficient multiplication can be conveniently realized by shift addition, so that the entire fine delay filter uses three multipliers.

[0091] The number of multipliers used can be further reduced by interpolation reduction, that is, by using the 4-point piecewise parabola interpolation method to approximate the cubic interpolation with quadratic interpolation. For the 4-point cubic Lagrange interpolation, the interpolation polynomial is:

[0092] ,

[0093] Calculate the number between the four interpolation points as,

[0094] ,

[0095] With (t0, x k ), (t -0.5 , x k+0.5 ), (t -1 , x k+1 ) are used as interpolation points for secondary interpolation, and the Lagrange coefficient is obtained as follows:

[0096] ,

[0097] ,

[0098] ,

[0099] The interpolation polynomial is,

[0100] ,

[0101] By simplifying the above three equations, the 4-point segmented parabola interpolation coefficients are obtained as follows:

[0102] ;

[0103] ;

[0104] ;

[0105] .

[0106] Based on the above interpolation coefficients, the simplified farrow structure filter is obtained as Figure 3 As shown, only 2 multipliers and 8 adders are needed without reducing the interpolation quality, which effectively reduces the consumption of DSP computing resources.

[0107] like Figure 1 As shown, the present invention also provides a reconfigurable high-precision multipath delay simulation device, including a host computer and an FPGA chip, the host computer is configured to select an input and output mode according to the communication scenario, and add the number of paths of the channel to each link, set different delay parameters, fading types and Doppler frequency shift, the host computer converts the delay parameters into group delay and relative delay, and performs three classifications, divides the delay into fine delay, coarse delay and large-scale delay, calculates the delay amount corresponding to each level and converts it into a fixed-point number and outputs it to the FPGA chip. The FPGA chip obtains the delay sent by the host computer, uses a random access memory to realize a large-scale delay, uses RAM resources to realize a coarse delay, uses a Lagrange interpolation algorithm to realize a fine delay, adds fading to the delayed result, and superimposes and outputs the multipath signal.

[0108] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A reconfigurable high-precision multipath delay simulation method, characterized in that: include: S1, select the signal input and output mode, add the number of channel paths for each link, and set the delay parameters, fading type and Doppler frequency shift for each path; S2, the host computer converts the delay parameters input by the user into group delay and relative delay, and classifies them into three levels according to the delay amount, namely fine delay, coarse delay and large-scale delay. The host computer calculates the delay amount corresponding to each level and converts it into a fixed-point number and sends it to the FPGA chip; S3, the FPGA chip obtains the group delay sent by the host computer, uses RAM resources for coarse delay, uses the Lagrange interpolation algorithm to achieve fine delay for the output result, uses the random access memory to use ping-pong operation, and achieves a large range of signal delay through the staggered address control technology; S4: The FPGA chip obtains the relative delay sent by the host computer, uses RAM resources to perform coarse delay, and uses the Lagrange interpolation algorithm to achieve fine delay for the output result; S5: Add fading to the delayed result, superimpose and output the multipath signal.

2. According to the reconfigurable high-precision multipath delay simulation method described in claim 1: the host computer calculates the minimum delay as the group delay based on the delay parameters, and the residual path is converted into a relative delay using the minimum delay path as a reference.

3. According to the reconfigurable high-precision multipath delay simulation method of claim 1: the fine delay is a delay that is a decimal multiple of the system clock, and the coarse delay is a delay that is an integer multiple of the system clock.

4. According to the reconfigurable high-precision multipath delay simulation method of claim 1: the group delay includes fine delay, coarse delay and large-scale delay, and the relative delay includes fine delay and coarse delay.

5. The reconfigurable high-precision multipath delay simulation method according to claim 1: in step S3, the large-scale delay control operation is: S3.1, the large-range delay module receives the delay start working flag sent by the host computer, and the read start address corresponding to the signal delay amount of each link; S3.2, splice the data of each link and start writing data into the write FIFO; S3.3, determine whether the write FIFO is half full. If it is, enter the write DDR4 operation. If it is not, go to S3.

4. S3.4, sequentially determine whether the read FIFO corresponding to each current link is half full. If not, read the data in the random access memory according to the read address corresponding to the read FIFO of the link, and then determine the state of the read FIFO corresponding to the next link. If it is half full, proceed to determine the state of the read FIFO corresponding to the next link, until the read FIFO of the last link is reached. S3.5, repeat steps S3.3 and S3.4 until data reception is completed.

6. The reconfigurable high-precision multipath delay simulation method according to claim 1, characterized in that: The Lagrangian interpolation algorithm is a 4-point piecewise parabola descending farrow filter.

7. The reconfigurable high-precision multipath delay simulation method according to claim 6, characterized in that: The interpolation polynomial of the farrow filter is, ， In the formula is the Lagrange interpolation factor, and its calculation formula is: Calculate the number between the four interpolation points as, ， With (t0, x k ), (t -0.5 , x k+0.5 ), (t -1 , x k+1 ) are used as interpolation points for secondary interpolation, and the Lagrange coefficient is obtained as follows: ， ， ， The interpolation polynomial is, ， By simplifying the above three equations, the 4-point segmented parabola interpolation coefficients are obtained as follows: ； ； ； 。 8. The reconfigurable high-precision multipath delay simulation device according to claim 6, characterized in that: The farrow filter includes 2 multipliers and 8 adders.

9. A reconfigurable high-precision multipath delay simulation device, characterized in that: include: Host computer and FPGA chip, among which, The host computer is configured to select input and output modes according to the communication scenario, add the number of channel paths to each link, set different delay parameters, fading types and Doppler frequency shifts, convert the delay parameters into group delay and relative delay, and perform three classifications to divide the delay into fine delay, coarse delay and large-scale delay, calculate the delay amount corresponding to each level and convert it into a fixed-point number and output it to the FPGA chip; The FPGA chip is configured to obtain the group delay and relative delay sent by the host computer, use random access memory to achieve large-scale delay, use RAM resources to achieve coarse delay, use Lagrange interpolation algorithm to achieve fine delay, add fading to the delayed result, and superimpose and output multipath signals.

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